Generic-memory module

From book V. Carl Hamacher

Fundamental of Computer Architecture

2019-20 EVEN SEMESTER Dr. Bhargav Goradiya

BVM Engineering College
 Chapter 5
The Memory System

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 Connection of the memory to the CPU

Processor k-bit address bus Memory

MAR

k
n-bit data bus Up to 2 addressable
MDR locations

Control lines word length= n bits

CU

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 Organization of bit cells in a memory chip

From Figure 5.2 Page 296 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.
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 Organization of a 1Kx1 memory chip

From Figure 5.3 Page 297 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.

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 Semiconductor Memories
 Nonvolatile memory  Volatile memory
ROM SRAM

PROM DRAM

EPROM Asynchronous
 DRAM
EEPROM
 FPM DRAM
Flash memory
Synchronous
 SDRAM

 DDR SDRAM

 RDRAM

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 ROM
ROM : Read Only Memory
Programmed when manufacturing is in process.

PROM : Programmable Read Only Memory

 Programmable by user only once
 Flexible and convenient compared to ROM

 Programmed by burning the fuse using high current pulse

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 A simple 4-word ROM

From Figure 11-12 Page 298 of “Microprocessors: principles and applications”, Charles M.Gilmore, McGraw Hill pub.
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 A simple 4-word ROM using MOS

From Figure 11-13 Page 299 of “Microprocessors: principles and applications”, Charles M.Gilmore, McGraw Hill pub.
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 EEPROM
Electrically Erasable PROM

No requirement of physically removed from the

circuit for reprogramming
 Use special voltage level to erase data
 Any cell contents can be delete selectively

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 EPROM
Reprogrammable

Erased by UV light
 Example EPROM chips
 27C64 : 8KB
 27C128 : 16KB

 27C256 : 32KB

 27C512 : 64KB

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 EPROM 2764, 27128, 27256

From Figure 11-15, Page 301 of “Microprocessor : Principle and Application”, Charles M. Gilmore, McGraw Hill pub.

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 Flash Memory
Electrically erasable

Single cell can be read but can be written only an

entire block of cells.
 Prior to writing, the previous of the block are erased.
 Suitable for used as solid state disk such as CompactFlash,
MemoryStick, SD, MD etc.

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 SRAM cell
b b'
Vsupply

word line

bit line bit line

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 DRAM cell

word line

bit line

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 SRAM VS DRAM
SRAM DRAM
 Very fast  Slower than SRAM

 Very Expensive  Cheaper than SRAM

 Used in Cache memory  Used in most computer

and CPU register as main memory
 Need to be refreshed periodically

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 DRAM: Multiplexed Row-Column addressing

From Figure 11-7, Page 291 of “Microprocessor : Principle and Application”, Charles M. Gilmore, McGraw Hill pub.

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 DRAM: Multiplexed Row-Column addressing
Reducing Address pins of IC chip

RAS = Row Address Strobe

CAS = Column Address Strobe

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 Static RAM

 2Kx8  8Kx8

From Figure 11-5, Page 289 of “Microprocessor : Principle and Application”, Charles M. Gilmore, McGraw Hill pub.

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 Dynamic RAM chip: Example

From Figure 11-6, Page 290 of “Microprocessor : Principle and Application”, Charles M. Gilmore, McGraw Hill pub.

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 Memory Module

From www.oamao.com/Matos/ ordi/guide.htm

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 3 Types of RAM modules

FROM http://www.buycomputermemory.com/computer-memory-types-and-memory-technology.html
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 Internal organization of a 2Mx8 DRAM

From Figure 5.7 Page 300 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.
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 SDRAM
Synchronous DRAM

Need clock signal for synchronize operation

Can be used with clock speed 100 and 133 MHz

Built in refresh circuitry

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 Structure of Synchronous DRAM

From Figure 5.8 Page 302 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.
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 Burst read of length 4 in an SDRAM

Row Col

D0
From Figure 5.9 Page 303 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.
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 The use of Memory controller

Row/Column
Address address

RAS
R/W
CAS
Memory
Request Controller R/W

Processor Clock
CS Memory
Clock

data

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 The role of Memory controller
Is the North-bridge chip in typical PC

Activate/Deactivate signal RAS and CAS timing

for DRAM
Interposed between Processor and Memory

Refresh DRAM if required

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 Memory organization in typical PC

From http://www.via.com.tw/en/p4-series/pt800.jsp

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 Memory organization in typical PC

From http://www.via.com.tw/en/p4-series/pt880.jsp

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 Memory hierarchy
Processor
increasing increasing increasing
size Registers speed cost per bit

Cache L1

Cache L2

Main
memory

secondary
storage
memory

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 Thanks

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