Welcome

Paul Colestock

RF-MS Product Manager

George Estep

RF-MS Application
Development Engineer

© 2011 Agilent Technologies

1 February 7, 2011
Opening Comments
Transient, Harmonic Balance, and ?
• Transient Analysis (sinusoidal)

DC f0 2.f0 3.f0 DC f0 2.f0 3.f0

• Harmonic Balance and Carrier Analysis (multi-tone)

DC f0 2.f0 3.f0 DC f0 2.f0 3.f0

• ? (modulated carrier)
Communication channel
(WCDMA, WiMedia, etc.)

DC f0 2.f0 3.f0 DC f0 2.f0 3.f0

February 3, 2011
Page 2
Agenda

Opening Comments
Definition of Memory Effects
Manifestations of Memory Effects in Circuits
Simulation Challenges Posed by Circuit Memory
Simulation Techniques for Modulated Waveforms
Circuit Simulation Examples
• Power Amplifier
• Receiver
Summary and Conclusion

3 February 3, 2011
Memory Effects Defined

Memory effects are non-noise circuit characteristics which

cannot be described by the steady-state nonlinear transfer
function of the circuit.
• Filtering effects
Vout
• Delay effects
• Hysteretic effects
Vin

Memory effects make it difficult to predict circuit response to

modulated waveforms based upon steady-state characteristics.
We will group memory effects by time-constant magnitude:
• “Baseband” memory effects tend to have long time constants
• “Inband” memory effects tend to have short time constants

4 February 3, 2011
Manifestations of Memory Effects in Circuits
Some examples
• Multiple time-constant memory effects

 Transistors
 Thermal effects (transit time)
 Trapping effects

 Matching networks
(group delay)
 Biasing circuits
 Band filtering
 AGC loops
 DC offset correction
Long time- Short time-
constant constant
memory memory
~µs to ms ~ns

Baseband Inband
Memory Effects Memory Effects
Nonlinear Coupling

February 3, 2011
Page 5
Manifestations of Memory Effects in Circuits
Low Noise Amplifiers
Many Low Noise Amplifiers (LNAs)
are typically wideband structures
having little or no memory effects.
However, some LNAs will exhibit
strong memory effects.
• Automatic Gain-Control (AGC) circuitry
can have important memory
characteristics.
• Some LNA circuits use complex biasing
schemes which add memory effects to
the function of the LNA.

6 February 3, 2011
Manifestations of Memory Effects in Circuits
Power Amplifiers
Power amplifiers are often
intentionally DESIGNED to have
strong memory effects in order to
improve output power and linearity
and limit out-of-band emissions.
• Matching networks can perform
functions at harmonic frequencies
which result in memory effects.
• Baseband circuits are typically strongly
band-limited to minimize
intermodulation distortion.

7 February 3, 2011
Manifestations of Memory Effects in Circuits
Receivers
Receivers typically include baseband
circuitry which produce strong
memory effects.
• DC offset correction (DCOC) circuitry
are used in zero- and low-IF structures
to help take full advantage of the
dynamic range of the A/D converter.
This circuit has strong memory effects.
• Baseband filtering often strongly limits
the bandwidth of the baseband circuits.
• Automatic Gain- and/or Level-Control
(AGC and/or ALC) circuitry can also
have important memory characteristics.

8 February 3, 2011
Manifestations of Memory Effects in Circuits
Transmitters
With the exception of the PA portion,
many transmitters do not contain
strong memory effects. However,
some do:
• Baseband filtering is included in some
transmitters to reduce the emission of
noise or other spurious signals.
• Automatic Level-Control (ALC) circuitry
may introduce memory effects.

9 February 3, 2011
Manifestations of Memory Effects in Circuits
How can you detect them with a steady-state solver?
• You typically need to sweep frequency to see these effects.
• Here is an example of what you might see for an amplifier:

Some inband effects can be seen by Some baseband effects can be seen by
sweeping a single tone in a steady-state sweeping the difference between two tones
simulation in a steady-state simulation
Lower IM3 Upper IM3
18 50
1.86GHz

)
17 1.90GHZ
45
1.95GHZ

(
Pin=-10dBm

C/IM3 ratio (dB)

1.99GHZ
2.03GHZ
16 40
Gain (dB)

15 35
)

Pin=-6dBm
(

14 30

p
13 25
resonance
12 20 Pin=-2dBm
wrapping
pp
Pin=2dBm
11 15

10 10
-10 -8 -6 -4 -2 0 2 4 0 1 2 3 4 5 6 7 8 9 10

Input power (dBm) Tone spacing (MHz)

February 3, 2011
Page 10
Simulation Challenges Posed by Circuit Memory
Why are we here?
Most radio circuit design analysis Communication is not possible using
today is performed using sinusoidal steady-state signals.
or other steady-state stimuli.
• Most modern radios use complex
Periodic stimulus such digitally-modulated waveforms to carry
as a sine wave information.
Communication signal
(LTE, WiMax, etc.)

DC f0 2.f0 3.f0

• Measurement equipment also often DC f0 2.f0 3.f0

uses periodic waveforms to

characterize circuitry.

11 February 3, 2011
Simulation Techniques for Modulated Waveforms
So How are Circuits Characterized with Modulation?
Transient simulation techniques can Envelope transient techniques can
be used to analyze any circuit with offer significant speedups over
any type of modulation. transient.
• Transient simulation times are too long • Through an approach which combines
for this approach to be useful except for transient and harmonic balance
the simplest cases. techniques, envelop transient can
– Amplifiers? Maybe greatly speed simulation with
modulated waveforms.
– Receivers? Not likely
• Improving accuracy in transient Communication signal
(LTE, WiMax, etc.)
simulation often entails a significant
slowdown in performance.

DC f0 2.f0 3.f0

12 February 3, 2011
Simulation Techniques for Modulated Waveforms
Some Target Figures-of-Merit for Envelope Transient
Prediction of ACPR EVM
power in
power in adjacent Q
channel channel

Real decision
∆E
EVM
∆φ Ideal decision

Trajectories / Constellations

And more…

Eye Diagram
Bit Error Rate

February 3, 2011
Page 13
Simulation Techniques for Modulated Waveforms
But there are STILL a couple of problems…
Envelope transient, though faster Sometimes it is necessary to use
than transient, is still often too slow to behavioral models for portions of the
meet the needs of designers. circuit.
• Fast envelope transient techniques • Parts of the circuit may come from a
have been developed in order to help third party who is unwilling or unable to
resolve this situation. share design details.
– These techniques typically involve • Various parts of the circuit may be
characterizing the entire circuit using descibed using incompatible formats.
a steady-state solver. • The circuit may be too large to fit on a
– This characterization is then used to computer using transistor-level views of
quickly analyze the circuit with all components.
modulated waveforms.

But circuit memory effects make creation of accurate

models using steady-state analysis VERY DIFFICULT!

14 February 3, 2011
Simulation Techniques for Modulated Waveforms
Two Main Types of Envelope Behavioral Models
Memoryless model: Model with memory effects:
Inband memory model
Input Output

Vout
Baseband memory model

Vin
• Use a steady-state solver to calculate
AM-AM and AM-PM characteristics for • Modeling memory effects requires more
the circuit for the fundamental and and different types of characterization
harmonics at the center of the band and of the circuit than creating a
at various power levels. memoryless model.
• Interpolate within this result to estimate • Inband and baseband effects are
the response of the circuit to a time- handled differently due to the fact that
varying stimulus. they are quite different phenomena.

15 February 3, 2011
Simulation Techniques for Modulated Waveforms
Memoryless Fast Envelope Limitation
• Each AM/AM AM/PM is identified at the center fCENTER of the modulation
bandwidth

BW = 1 BW = 1
TimeStep TimeStep
Memoryless
models will
provide a signal
Pass-band Filter
which did not have
undergoes any
f CENTER f f CENTER f filtering effects

Real Behavior Interpretation made by memoryless models

Memory effects not taken into account.

Please note that MANY circuits CAN be accurately modeled without memory!!

February 3, 2011
Page 16
Circuit Simulation Examples
Power Amplifier
Circuit Description:
• 20 MOS devices
• Contains 25-port S-
parameter block
• Linear gain: 31 dB

17 February 3, 2011
Circuit Simulation Examples
Power Amplifier - “Memory Effects Map”

Inband Memory Effects Plot Baseband Memory Effects Plot

18 February 3, 2011
Circuit Simulation Examples
Power Amplifier – Output Spectrum Comparison

RED – Normal Envelop Transient GREEN – Memoryless Model BLUE – Model with Memory

19 February 3, 2011
Circuit Simulation Examples
Power Amplifier – Power Gain Comparison

RED – Normal Envelop Transient GREEN – Memoryless Model BLUE – Model with Memory

20 February 3, 2011
Circuit Simulation Examples
Power Amplifier – ACPR Comparison

RED – Normal Envelop Transient GREEN – Memoryless Model BLUE – Model with Memory

21 February 3, 2011
Circuit Simulation Examples
Power Amplifier – Performance Comparison
Method Used Accurate? Model Sim Time Sim
Time Speedup
Envelope Transient  0 sec 1133 sec 1X
Envelope w/ Memoryless Model  <1 sec 7 sec 162X
Envelope w/ Memory Model  40 sec 101 sec 11X

• For a memoryless circuits, ALL envelope transient approaches covered

give correct results.
– It is important to verify that the circuit is memoryless by verifying the
results against normal envelope simulation.
• In this case, the memoryless model is the most efficient since it requires
the fewest simulations to complete.

22 February 3, 2011
Circuit Simulation Examples
Receiver
Circuit Description:
• 946 MOS devices
• Contains 12-port S-
parameter block
• Frequency: 2.4 GHz
• Output: Zero-IF
• Linear gain: 40 dB

23 February 3, 2011
Circuit Simulation Examples
Receiver “Memory Effects Map”

Inband Memory Effects Plot Baseband Memory Effects Plot

Due to the fact that this is a zero-IF
receiver, there is no map for the
“Inband” response.

24 February 3, 2011
Circuit Simulation Examples
Receiver – Output Spectrum Comparison

RED – Normal Envelop Transient GREEN – Memoryless Model BLUE – Model with Memory

25 February 3, 2011
Circuit Simulation Examples
Receiver – Performance Comparison
Method Used Accurate? Model Sim Time Sim
Time Speedup
Envelope Transient  0 sec 1560 sec 1X
Envelope w/ Memoryless Model X 58 sec 14 sec 111X
Envelope w/ Memory Model  17985 sec 37 sec 42X

• For circuits with memory, a memoryless model can give very poor results.
– It is important to verify that the results using the model with memory
using normal envelope simulation.
• In this case, the behavioral model with memory is accurate but it is slower
than regular envelope transient simulation. In many cases, it will be faster.
Many factors will impact the speed.

26 February 3, 2011
Summary and Conclusion

Memory effects are circuit behaviors that defy modeling through

standard steady-state characterization techniques.
• Inband memory effects have been differentiated from baseband memory
effects based on their widely-differing time constants.
– Different modeling techniques are used to characterize these two effects.
• Several examples of memory effects for various types of circuitry have been
presented.
• Techniques for spotting circuit memory effects using a steady-state solver have
been provided.
• Example simulations showing the limitations of memoryless models in the
presence of memory effects have been given.

Conclusion: Proper understanding of these behaviors can help

designers to understand when memoryless models can or cannot be
used to evaluate the response of circuitry to modulated stimuli.

27 February 3, 2011
Questions and Answers

Questions?

28 February 3, 2011
 http://www.agilent.com/find/eesof-goldengate

Where do you go from here?

• Visit GoldenGate on the Web to sign up for a

demonstration or evaluation.

• Download the GoldenGate Workshop and go through

the example based on this Webcast.

• Contact your local Agilent EEsof field representative or

George Estep, RF-MS Application Specialist

[email protected]

Paul Colestock, RF-MS Product Manager

[email protected]

Attend other RFIC Webcasts from Agilent EEsof EDA:

• Understanding Cross Modulation Effects in LTE Transceivers
• A Practical Approach to Verifying RFICs with Fast Mismatch Analysis

29 February 3, 2011
You are invited

Joe Civello
Advanced Design System Product Manager

Confidentiality Label
30 February 7, 2011