Digital Signal Processing: Discrete-Time Systems Lecture - 4
Digital Signal Processing: Discrete-Time Systems Lecture - 4
Chapter 1
Discrete-Time Systems
Lecture - 4
DSP-II 2p. 2
Block Diagram Representation of Discrete-Time
Systems
DSP-II 3p. 3
x(n)
𝑦(𝑛)=x(n)+r(n)
r(n)
DSP-II 4p. 4
Block Diagram Representation of Discrete-Time
Systems
c
X(n) Y(n)=c.X(n)
• OR
X(n) c Y(n)=c.X(n)
DSP-II 5p. 5
x1(n) Y(n)=x1(n).x2(n)
x2(n)
DSP-II 6p. 6
Block Diagram Representation of Discrete-Time
Systems
4) unit delay element: The unit delay is a special system
that simply delays
• the signal passing through it by one sample.
• Figure below illustrates such a system.
• If the input signal is x ( n ) , the output is x(n - 1).
• In fact, the sample x(n - 1) is stored in memory at time n -
1 and it is recalled from memory at time n to form
• Thus this basic building block requires memory.
• The use of the symbol ,z-1 to denote the unit of delay will
become apparent when we discuss the Z transform
DSP-II 7p. 7
0.5
0.25
a
0.5
x(n) y(n)
0.25
b
10
DSP-II p. 10
Interconnection of Discrete-Time Systems
DSP-II p. 11
11
DSP-II p. 13
13
𝒙𝟏 (𝒏)=𝒙(𝒏) 𝒚𝟏 (𝒏)
𝑻𝟏
x(n) y(n)
𝑻𝟐
𝒙𝟐 (𝒏)= 𝒙(𝒏) 𝒚𝟐 (𝒏)
𝑻
DSP-II p. 15
15
𝒆𝟏 (𝒏)
x(n) 𝑻𝟏 y(n)
-
𝑻𝟐 𝒚(𝒏)
𝑻𝟐
DSP-II p. 17
17
END
DSP-II p. 18
18