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S.E. (Computer) (Second Semester) EXAMINATION, 2019
8 2 P0
MICROPROCESSOR
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CE

(2015 PATTERN)

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Time : Two Hours Maximum Marks : 50

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N.B. :— (i) Answer question Nos. 1 or 2, 3 or 4, 5 or 6, 7 or 8.

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(ii) Neat diagram must be drawn wherever necessary.
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(iii) Figures to the right indicate full marks.
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(iv) Assume suitable data, if necessary.

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1. (a) List and explain coprocessor interface instructions of

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80386. [2]

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(b) With the help of diagram explain 80386 applications register
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set. [4]
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(c) Explain how linear address 0080400A H will be translated into

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physical address using paging mechanism. Whether the address

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generated will be the same to linear address ? [6]

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2. (a) Explain LEA and XLAT instructions. [2]

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(b) Draw and explain EFLAGs register of 80386. [4]

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(c) With the help of diagram explain the 80386 mechanism to

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translate logical address to linear address and linear to physical

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address. [6]

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3. (a) List aspects of protection related to pages.
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(b) Write a short note on “Multitasking” feature of 80386. [4]

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(c) List different sources of interrupts and explain different ways

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by which 80386 can enable and disable interrupts. [6]

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4. (a) Define DPL, RPL and CPL. [2]

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(b) Write a short note on “Task Linking”. [4]
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(c) List mechanism which provide protection for I/O functions
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and explain the role of IOPL in providing protection for

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I/O functions. [6]

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5. (a) Write a short note on “Virtual 8086 mode”. [3]

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(b) Explain 80386 processor state after RESET. [4]
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(c) What all initializations required to start processor in real mode

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after reset ? [6]

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6. (a) Explain, how test registers are used in testing TLB ? [7]
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(b) What all initializations required to start processor in protected

mode after reset ? [6]
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7. (a) Explain HOLD and HLDA signals of 80386DX. [4]

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(b) Draw and explain 80387 register stack. [4]

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(c) Draw and explain bus states and transitions when address

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pipelining is not used. [5]

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8. (a) List various bus states when address pipelining is used. [4]
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(b) Which data types are supported by 80387 ? [4]

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(c) Draw write cycle with non-pipelined address timing. [5]

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