INDIAN INSTITUTE OF INFORMATION TECHNOLOGY,

DESIGN AND MANUFACTURING, KURNOOL

Department of Electronics and Communication Engineering

Digital Logic Design Practice Manual

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LIST OF EXPERIMENTS:

1. Verification and Interpretation of Truth Tables of Logic Gates.

2. Verification of De-morgan’s Theroems.
3. Design of Half Adder, Full adder, Half Subtractor and Full Subtracor.
4. Design of Code Converters.
5. Design of 4 bit Ripple Carry Adder and 4 bit Adder/Subtractor .
6. Design of a Magnitude comparator.
7. Design of BCD-7-Segment LED display decoder.
8. Design of Multiplexer and De Multiplexer.
9. Design of Flip-flops (SR, JK, D and T).
10. Design of shift Registers.
11. Design of counters.

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LAB INSTRUCTIONS:

1. Dress code has to be strictly followed in the Lab.

2.The lab is totally of 3 hours duration which the student is expected
finish the experiment.
3. Each and every student should submit their report of the previous
experiment.
4. Every student has to have an idea over the experiment that is to be
done in that session with
that he/she has to prepare a list of the equipment.

SAFETY PRECAUTIONS:

1. Switch OFF the power supply while leaving the Laboratory.

2. Submit all the Components while leaving the Laboratory.
3. Avoid loose connections.
4. Equipments must be handle properly.
5. Apply the specified voltage with proper ground.
6. Check the connections before switching on supply.

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The Breadboard
The breadboard consists of two terminal strips and two bus strips (often broken in the
centre). Each bus strip has two rows of contacts. Each of the two rows of contacts are a node.
That is, each contact along a row on a bus strip is connected together (inside the breadboard).
Bus strips are used primarily for power supply connections, but are also used for any node
requiring a large number of connections. Each terminal strip has 60 rows and 5 columns of
contacts on each side of the centre gap. Each row of 5 contacts is a node.

You will build your circuits on the terminal strips by inserting the leads of circuit components
into the contact receptacles and making connections with 22-26-gauge wire. There are wire
cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and 0V power
supply connections to separate bus strips.

Fig 1. The breadboard and he lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs (Integrated circuits)
used during the experiments. Incorrect connection of power to the ICs could result in them
exploding or becoming very hot - with the possible serious injury occurring to the people
working on the experiment! Ensure that the power supply polarity and all components and
connections are correct before switching on power.

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 Building the Circuit

Throughout these experiments we will use TTL chips to build circuits. The steps for wiring a
circuit should be completed in the order described below:

1. Turn the power (Trainer Kit) off before you build anything.
2. Make sure the power is off before you build anything.
3. Connect the +5V and ground (GND) leads of the power supply to the power and ground bus
strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the chips in the same direction
with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on
the chip package).
5. Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
6. Select a connection on your schematic and place a piece of hook-up wire between
corresponding pins of the chips on your breadboard. It is better to make the short connections
before the longer ones. Mark each connection on your schematic as you go, so as not to try to
make the same connection again at a later stage.
7. Get one of your group members to check the connections, before you turn the power on.
8. If an error is made and is not spotted before you turn the power on. Turn the power off
immediately before you begin to rewire the circuit.
9. At the end of the laboratory session, collect you hook-up wires, chips and all equipment and
return them to the demonstrator.
10. Tidy the area that you were working in and leave it in the same condition as it was before
you started.

Common Causes of Problems

1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates.

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6. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, components at the
start of the experiment and return them to their proper place after you have finished the
experiment. Please inform the demonstrator or technician if you locate faulty equipment. If you
damage a chip, inform a demonstrator, don't put it back in the box of chips for somebody else
to use.

IC Pin Configurations:

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Example Implementation of a Logic Circuit
Build a circuit to implement the Boolean function 𝐹 = 𝐴. 𝐵 .

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 Quad 2 Input 7400 Hex 7404 Inverter

Exp No-1: Verification and Interpretation of truth tables of logic gates.

Aim: To study and verify the logic gates.

Apparatus Required:

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S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 7400 NAND Gate 1
3 IC 7408 AND Gate 1
4 IC 7402 NOR Gate 1
5 IC 7432 OR Gate 1
6 IC 7404 NOT Gate 1
7 IC 7486 XOR Gate 1
8 Patch cords and Connecting wires As required

Theory:
AND Gate:

The output state of a digital logic AND gate only returns “LOW” again when ANY of
its inputs are at a logic level “0”. In other words for a logic AND gate, any LOW input will give a
LOW output. The logic or Boolean expression given for a digital logic AND gate is that for
Logical Multiplication which is denoted by a single dot or full stop symbol.

Truth table:

OR Gate:

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Our next gate to investigate is the OR gate, so-called because the output of this gate will be
"true" if either or both of the inputs are "true". If both inputs are "false", then the output is
"false". A plus (+) sign is used to show the OR operation.

Truth table:

NOT Gate:

A logical inverter, sometimes called a NOT gate to differentiate it from other types of electronic
inverter devices. It has only one input. It reverses the logic state. If the input is 1, then the
output is 0. If the input is 0, then the output is 1. This is also shown as (A').

Truth table:

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NAND Gate:

The NAND (Not – AND) gate has an output that is normally at logic level “1” and only goes
“LOW” to logic level “0” when ALL of its inputs are at logic level “1”. The Logic NAND Gate is the
reverse or “Complementary” form of the AND gate.

Truth table:

NOR Gate:

The inclusive NOR (Not-OR) gate has an output that is normally at logic level “1” and only goes
“LOW” to logic level “0” when ANY of its inputs are at logic level “1”. The Logic NOR Gate is
the reverse or “Complementary” form of the inclusive OR gate.

Truth Table:

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XOR Gate:

The previous gates are all fairly direct variations on three basic functions: AND,OR, and NOT. The
XOR gate, however, is something quite different. The XOR (Exclusive-OR) gate‟s output is "true"
if either, but not both, of the inputs are "true". The output is "false" if both inputs are "false"
or if both inputs are "true". Another way of looking at this circuit is to observe that the output is
"true" if the inputs are different and “false if the inputs are the same.

An encircled plus sign (⊕) is used to show the XOR operation.

Truth table:

Procedure:
1. Connect the trainer kit to the AC power supply.

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 2. Insert the IC (Integrated Circuit) on breadboard of trainer kit and ensure that AC power
supply is OFF.
3. Connect the IC Pin No.7 to Ground and Pin No.14 to Vcc (5V supply).
4. Connect the input pins of logic gates to input logic levels and output pin to output logic
level on trainer kit.
5. Switch ON the trainer kit power supply after verified by Instructor.
6. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Power supply should not exceed more than +5V.

Result:
Thus the logic gates are studied and their truth tables were verified.

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Exp No-2: Verification of De-Morgan's Laws.

Aim: To study and verify the De-Morgan's laws.

Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 7400 NAND Gate 1
3 IC 7408 AND Gate 1
4 IC 7402 NOR Gate 1
5 IC 7432 OR Gate 1
6 IC 7404 NOT Gate 1
7 Patch cords and connecting wires As required

Theory:
De-Morgan's Laws

Boolean algebra has postulates and identities. We can often use these laws to reduce
expressions or put expressions in to a more desirable form. One of these laws is the
De-Morgan's law.

De-Morgan's law has two conditions, or conversely, there are two laws called De-Morgan's
Laws.

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First Condition or First law: The compliment of the product of two variables is equal to the sum
of the compliment of each variable.

Thus according to De-Morgan's laws or De-Morgan's theorem if A and B are the two variables or
Boolean numbers. Then accordingly

(𝐴𝐵) = 𝐴. 𝐵

This means that NAND gate function is identical to OR gate function with complemented inputs.

Second Condition or Second law: The compliment of the sum of two variables is equal to the product
of the compliment of each variable. Thus according to De Morgan’s theorem if A and B are the two
variables then.

(𝐴 + 𝐵) = 𝐴. 𝐵

This means that NOR function is equal to the AND gate function with complemented inputs.

Logic Diagram:

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Procedure:

1. Patch the left hand side circuit for the first condition of De-Morgan's Law on the Digital
trainer Kit. Connect the inputs to the input switches and output to the LED and verify the truth
table for all the combinations.

2. Similarly, patch the right hand side circuit for the first condition of De-Morgan's Law on the
Digital trainer kit. Connect the inputs to the input switches and output to the LED and verify the
truth table for all the combinations. Both the truth tables should be similar.

3. Repeat steps 1 and 2 for the second condition of De-Morgan's Law.

4. Get it checked by the instructor.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Power supply should not exceed more than +5V.

Result:

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Thus the De Morgan’s laws are studied and their truth tables were verified.

Exp No-3: Basic Adders and Subtractors.

Aim: Design and verify the Half adder, Half subtractor, Full adder and Full subtractor circuits.

Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 7486 XOR Gate 1

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3 IC 7408 AND Gate 1
4 IC 7432 OR Gate 1
5 IC 7404 NOT Gate 1
6 Patch Cords and connecting wires As required

Theory:
Combinational logic: In digital circuit theory, combinational logic (sometimes also referred to as
time-independent logic) is a type of digital logic which is implemented by Boolean circuits,
where the output is a pure function of the present input only. This is in contrast to sequential
logic, in which the output depends not only on the present input but also on the history of the
input. In other words, sequential logic has memory while combinational logic does not.
Combinational logic is used in computer circuits to perform Boolean algebra on input signals
and on stored data. Practical computer circuits normally contain a mixture of combinational and
sequential logic. For example, the part of an arithmetic logic unit, or ALU, that does
mathematical calculations is constructed using combinational logic. Other circuits used in
computers, such as half adders, full adders, half subtractors, full subtractors, multiplexers,
Demultiplexers, encoders and decoders are also made by using combinational logic.

Half Adder: A Half Adder accepts two binary digits on its inputs and produces two binary digits on
its output, a sum bit and a carry bit.

Logic Diagram:

𝑆𝑢𝑚 = 𝐴𝐵 + 𝐴𝐵 = 𝐴⊕𝐵

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 𝐶𝑎𝑟𝑟𝑦 = 𝐴𝐵

Half Subtractor: A Half Subtractor is a combinational circuit that subtracts two bits and produces
two bits as output i.e. Difference and Borrow.

Logic Diagram:

𝐷𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑐𝑒 = 𝐴𝐵 + 𝐴𝐵 = 𝐴⊕𝐵

𝐵𝑜𝑟𝑟𝑜𝑤 = 𝐴𝐵

Full Adder:
A full adder is a logical circuit that performs an addition operation on three binary digits
and just like the half adder; it also generates a carry out to the next addition column. Then a

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Carry-in is a possible carry from a less significant digit, while a Carry-out represents a carry to a
more significant digit.

Logic Diagram:

𝑆𝑢𝑚 = ∑ 𝑚(1, 2, 4, 7)

𝐶𝑎𝑟𝑟𝑦 = ∑ 𝑚(3, 5, 6, 7)

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Full Subtractor:
The combinational circuits of a full subtractor performs the operation of subtraction on three
binary bits producing outputs as difference D and borrow B-out. Just like the binary adder
circuit, the full subtractor can also be thought of as two half subtractors connected together, with
the first half subtractor passing its borrow to the second half subtractor as follows.

Logic Diagram:

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 𝐷𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑐𝑒 = ∑ 𝑚(1, 2, 4, 7)

𝐵𝑜𝑟𝑟𝑜𝑤 = ∑ 𝑚(1, 2, 3, 7)

Procedure:
1. Connect the trainer kit to the AC power supply.
2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.
4. Verify the truth tables for each input/output combination.

Precautions:
5. All connections should be made neat and tight.
6. Digital lab kits and ICs should be handled with utmost care.
7. While making connections main voltage should be kept switched off.
8. Power supply should not exceed more than +5V.

Result:
Thus the basic Adders and Subtractors are designed and verified their truth tables.

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Exp No-4: Design of Code converters.

Aim: Design and verify the Binary to Gray and Gray to Binary code converters.

Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 7486 XOR Gate 1
6 Patch Cords and connecting wires As required

Theory:
The logical circuit which converts binary code to equivalent gray code is known as binary to gray
code converter. The gray code is a non-weighted code. The successive gray code differs in one
bit position only that means it is a unit distance code. It is also referred as cyclic code. It is not
suitable for arithmetic operations. It is the most popular of the unit distance codes. It is also a
reflective code. An n-bit Gray code can be obtained by reflecting an n-1 bit code about an axis
after 2n-1 rows, and putting the MSB of 0 above the axis and the MSB of 1 below the axis.

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Logic Diagram:

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Logic Diagram:

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Procedure:
1. Connect the trainer kit to the AC power supply.
2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.

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 4. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Power supply should not exceed more than +5V.

Result:
Thus the Binary to Gray and Gray to Binary code converters are designed and verified their truth
tables.

Exp No-5: Design of 4-bit Ripple Carry Adder and 4-bit Adder/ subtractor

Aim: - To realize the Design of 4-bit Ripple Carry Adder and4-bit Adder/ Subtractor.

Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 7408 AND Gate 1
3 IC 7486 XOR Gate 1
4 IC 7404 NOT Gate 1
5 IC 7432 OR Gate 1
6 IC 7483 Four Ripple adder 1
7 Patch Cords and connecting wires As required
Theory:
Ripple carry adder circuit:
Multiple full adder circuits can be cascaded in parallel to add an N-bit number. For an N-bit
parallel adder, there must be N number of full adder circuits. A ripple carry adder is a logic
circuit in which the carry-out of each full adder is the carry in of the succeeding next most
significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the
next stage. In a ripple carry adder the sum and carry out bits of any half adder stage is not valid
until the carry in of that stage occurs. Propagation delays inside the logic circuit are the reason
behind this.

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Propagation delay is time elapsed between the application of an input and occurrence of the
corresponding output. Consider a NOT gate, When the input is “0” the output will be “1”
and vice versa. The time taken for the NOT gate’s output to become “0” after the application of
logic “1” to the NOT gate’s input is the propagation delay here. Similarly the carry propagation
delay is the time elapsed between the application of the carry in signal and the occurrence of
the carry out (Cout) signal. Circuit diagram of a 4-bit ripple carry adder is shown below.

Sum out S0 and carry out Cout of the Full Adder-A is valid only after the propagation delay of
Full Adder-A. In the same way, Sum out S3 of the Full Adder-D is valid only after the joint
propagation delays of Full Adder-A to Full Adder-D. In simple words, the final result of the
ripple carry adder is valid only after the joint propagation delays of all full adder circuits inside
it.

Logic Diagram:

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Truth Table:

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4-bit Adder/Subtractor circuit:
The Arithmetic micro-operations like addition and subtraction can be combined into one
common circuit by including an exclusive-OR gate with each full adder.

The block diagram for a 4-bit adder/subtractor circuit can be represented as:

⮚ When the mode input (M) is at a low logic, i.e. '0', the circuit act as an adder and when
the mode input is at a high logic, i.e. '1', the circuit act as a subtractor.
⮚ The exclusive-OR gate connected in series receives input M and one of the inputs B.
⮚ When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry is 0, and the circuit performs A
plus B.
⮚ When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input carry. The circuit
performs the operation A plus the 2's complement of B.

Logic Diagram:

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Truth Table:
Control Input A B Sum/Differenc Carry/Borrow
e
M A3A2A1A0 B3B2B1B0 S3S2S1S0 Cout
0 1010 0101 1111 0
0 1111 1100 1011 1
1 1010 0101 1010 0
1 1111 1100 1100 0

Procedure:
1. Connect the trainer kit to the AC power supply.
2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.
4. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.

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 4. Power supply should not exceed more than +5V.

Result:
Thus the 4-bit Ripple Carry Adder and 4- bit Adder/Subtractor circuits are designed and verified
their truth tables.

Exp No-6: Design of Magnitude Comparator

Aim: - To realize the Design of magnitude comparator.

Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 7485 Four Bit Comparator 1
3 IC 7408 AND Gate 1
4 IC7411 AND Gate 1

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5 IC 7432 OR Gate 1
6 IC 7404 NOT Gate 1
7 IC 7486 XOR Gate 1
8 Patch cords and connecting wires As required

Theory:
A magnitude digital comparator is a combinational circuit that compares two digital or
binary numbers (consider A and B) and determines their relative magnitudes in order to find out
whether one number is equal, less than or greater than the other digital number.

Three binary variables are used to indicate the outcome of the comparison as A>B, A<B, or
A=B. The below figure shows the block diagram of a n-bit comparator which compares the two
numbers of n-bit length and generates their relation between themselves.

These comparators can compare 2-bit, 4-bit and 8-bit numbers depending on the application
requirement. These are available in TTL as well as CMOS logic family ICs and some of these ICs
include IC 7485 (4-bit comparator), IC 4585 (4-bit comparator in CMOS family) and IC 74AS885
(8-bit comparator).

1-Bit Magnitude Comparator:

A comparator used to compare two bits, i.e., two numbers each of single bit is called a single bit
comparator. It consists of two inputs for allowing two single bit numbers and three outputs to
generate less than, equal and greater than comparison outputs.

The figure below shows the block diagram of a single bit magnitude comparator. This
comparator compares the two bits and produces one of the 3 outputs as L (A<B), E (A=B) and G
(A>B).

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2-Bit Comparator:

A 2-bit comparator compares two binary numbers, each of two bits and produces their
relation such as one number is equal or greater than or less than the other. The figure below
shows the block diagram of a two-bit comparator which has four inputs and three outputs.

The first number A is designated as A = A1A0 and the second number is designated as B = B1B0.
This comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B) and L (L = 1 iA<B).

4-Bit Comparator:
It can be used to compare two four-bit words. The two 4-bit numbers are A = A3 A2 A1A0 and
B=B3 B2 B1 B0 where A3 and B3 are the most significant bits. It compares each of these bits in one
number with bits in that of other number and produces one of the following outputs as A = B,
A < B and A>B. The output logic statements of this converter are

● If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or

● If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
● If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B. Or
● If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1 and
B0 = 0, then A > B.
Logic Diagram:

1-Bit Comparator:

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2-Bit Comparator:

4-Bit Comparator:

Truth Table:

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1-Bit Comparator:

2-Bit Comparator:

4-Bit Comparator:

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Procedure:
1. Connect the trainer kit to the AC power supply.
2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.
4. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Power supply should not exceed more than +5V.

Result:
Thus the magnitude comparator circuits are designed and verified their truth tables.

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Exp No-7: Design of Multiplexer and Demultiplexer

Aim: - To realize the Design of multiplexer and demultiplexer.

Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 74153 Multiplexer 4x1 1
3 IC 7408 AND Gate 1
4 IC7411 AND Gate(3-Input) 1
5 IC 7432 OR Gate 1
6 IC CD4075 OR Gate(3-input) 1
7 IC 7404 NOT Gate 1
8 IC74151 Multiplexer(8X1) 1
9 Patch cords and connecting wires As required

Theory:
In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital
input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n
select lines, which are used to select which input line to send to the output.
A 2n -to-1 multiplexer sends one of 2n input lines to a single output line.

The Demultiplexer is combinational logic circuit that performs the reverse operation of
Multiplexer. It has only one input, n selectors and 2n outputs. Depending on the combination of
the select lines, one of the outputs will be selected to take the state of the input.

Logic Diagram:
2X1 MUX:

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4X1 MUX:

8X1 MUX:

Truth Table:
2X1 MUX:

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4X1 MUX:

8X1 MUX:

Logic Diagram:
1X2 DMUX:

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1X4 DMUX:

1X8 DMUX:

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Truth Table:
1X2 DMUX:

1X4 DMUX:

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1X8 DMUX:

Procedure:
1. Connect the trainer kit to the AC power supply.
2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.
4. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.

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 4. Power supply should not exceed more than +5V.

Result:
Thus the multiplexer and de-multiplexer circuits are designed and verified their truth tables.

Exp No-8: Design of Decoder, Encoder and Parity Generator/Checker

Aim: - To realize the Design of decoder, encoder and parity generator/checker.
Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 74138 decoder(3 to 8) 1
3 IC 7408 AND Gate 1
4 IC7411 AND Gate 1
5 IC 7432 OR Gate 1
6 IC 7404 NOT Gate 1

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7 IC 74180 Parity Generator/Checker 1
8 IC74147 Priority Encoder 1
9 Patch cords and connecting wires As required

Theory:
Encoder: Encoder takes all the data inputs one at a time and converts them to a single encoded
output, it is a multi-input data line, combinational logic circuit that converts the logic level 1
data at its input to an equivalent binary code at its output. Encoder has 2n input lines with
common types that include 4 to 2, 8 to 3 & 16 to 4 line configuration. Encoders are available to
encode either a decimal or hexadecimal input pattern to typically binary or BCD output code.

Decoder: A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs
into coded outputs, where the input and output codes are different; e.g. n-to-2n, BCD decoders.
Decoding is necessary in applications such as data multiplexing, 7-segment display and memory
address decoding. Any n-variable logic function, in canonical sum-of-minterms form can be
implemented using a single n-to-2n decoder to generate the minterms, and an OR gate to form
the sum. The output lines of the decoder corresponding to the minterms of the function are
used as inputs to the OR gate. Any combinational circuit with n inputs and m outputs can be
implemented with an n-to-2n decoder with m OR gates. Suitable when a circuit has many
outputs, and each output function is expressed with few minterms.

Priority Encoder:
IC 74147 is a digital encoder IC that encodes 9 inputs lines into 4 output lines. It is also known as
the Decimal to BCD priority encoder. The priority encoder term is used because it provides
encoding for highest order data lines as a first priority. It is made up using Transistor-Transistor
Logic(TTL) technology. It is a 10 to 4 encoder IC. Here Priority is give to the highest order active
low input.
Parity Generator:
The parity generator is a combination circuit at the transmitter, it takes an original message as
input and generates the parity bit for that message and the transmitter in this generator
transmits messages along with its parity bit.

The even parity generator maintains the binary data in even number of 1’s, for example, the
data taken is in odd number of 1’s, this even parity generator is going to maintain the data as
even number of 1’s by adding the extra 1 to the odd number of 1’s. This is also a combinational
circuit whose output is dependent upon the given input data, which means the input data is
binary data or binary code given for parity generator.

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The odd parity generator maintains the binary data in an odd number of 1’s, for example, the
data taken is in even number of 1’s, this odd parity generator is going to maintain the data as an
odd number of 1’s by adding the extra 1 to the even number of 1’s. This is the combinational
circuit whose output is always dependent upon the given input data.  If there is an even number
of 1’s then only parity bit is added to make the binary code into an odd number of 1’s.

The combinational circuit at the receiver is the parity checker. This checker takes the received
message including the parity bit as input. It gives output ‘1’ if there is some error found and
gives output ‘0’ if no error is found in the message including the parity bit.

Logic Diagram:

2 to 4 Decoder:

3 to 8 Decoder:

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Truth Tables:

2 to 4 Decoder:

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3 to 8 Decoder:

Logic Diagram:

4 to 2 Encoder:

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8 to 3 priority Encoder:

Truth Tables:

4 to 2 Encoder:

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8 to 3 Priority Encoder:

Logic Diagram:
Parity Generator/Checker:

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Procedure:
1. Connect the trainer kit to the AC power supply.
2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.
4. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Power supply should not exceed more than +5V.

Result:
Thus the decoder, encoder and parity generator/checker circuits are designed and verified their
truth tables.

52 Digital Logic Design Practice | IIITDM Kurnool

Exp No-9: Design of BCD to 7-Segment Display Decoder
Aim: - To realize the Design of BCD to 7-segment display decoder.
Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 Patch cords and connecting wires As required

Theory:
Seven segment display is the most common device used for displaying digits and alphabet. You
can see the Seven Segment Display devices in TV show counting down to “0‟. Use of LEDs in
seven segment displays made it more popular.

The binary information can be displayed in the form of decimal using this seven segment
display. Its wide range of applications is in microwave ovens, calculators, washing machines,
radios, digital clocks etc.

The CD4511 is a BCD to 7-segment decoder. It means it takes a number in binary form as an
input, then displays this number on a 7-segment display using its outputs. A 7-segment display
is a component with seven Light-Emitting Diodes (LED) arranged as shown below. By turning on
different combinations of the LEDs, a number between 0 and 9 is displayed.

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Logic Diagram:

Truth Table:

Inputs Outputs
LE 𝐵𝐿 𝐿𝑇 A B C D a b c d e f g
X X 0 X X X X 1 1 1 1 1 1 1
X 0 1 X X X X 0 0 0 0 0 0 0
0 1 1 0 0 0 0 1 1 1 1 1 1 0
0 1 1 0 0 0 1 0 1 1 0 0 0 0
0 1 1 0 0 1 0 1 1 0 1 1 0 1
0 1 1 0 0 1 1 1 1 1 1 0 0 1
0 1 1 0 1 0 0 0 1 1 0 0 1 1
0 1 1 0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 1 0 1 0 1 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1 1 1 1
Procedure:
1. Connect the trainer kit to the AC power supply.

54 Digital Logic Design Practice | IIITDM Kurnool

 2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.
4. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Power supply should not exceed more than +5V.

Result:
Thus the BCD to 7-segment display decoder is designed and verified their truth tables.

Exp No-10: Design of Latch and Flip flops.

Aim: - To realize the Design of Latch and Flip flops.

Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 7400 NAND Gate 1
3 IC 7402 NOR Gate 1
4 IC 7474 D flip flop 1
5 IC 7473 JK Flip flop 1
6 Patch cords and connecting wires As required

Theory:

A flip flop is an electronic circuit with two stable states that can be used to store binary data.
The stored data can be changed by applying varying inputs. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers, communications,
and many other types of systems.

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SR Flip-Flop:
The basic NAND gate RS flip flop circuit is used to store the data and thus provides feedback
from both of its outputs again back to its inputs. The RS flip flop actually has three inputs, SET,
RESET and clock pulse.
D Flip-Flop:
A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop by
connecting the R input through an inverter, and the S input is connected directly to data input.
The modified clocked SR flip-flop is known as D-flip-flop and is shown below. From the truth
table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when the
inputs are same and high. In many practical applications, these input conditions are not
required. These input conditions can be avoided by making them complement of each other.
JK Flip-Flop:
In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit may be
re-joined if both inputs are 1 than also the outputs are complement of each other.
T Flip-Flop:
T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop. Both the
JK inputs of the JK flip – flop are held at logic 1 and the clock signal continuous to change as
toggle.

Logic Diagram:
SR Latch:

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SR Flip flop:

JK Flip flop:

T Flip flop:

D Flip flop:

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Truth Tables:

SR Flip flop:
CLK S R Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Invali
d

JK Flip flop:
CLK J K Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 1
1 1 0 0
1 1 1 𝑄𝑛

T Flip flop:
CLK T Qn+1
0 X Qn
1 0 1
1 1 0

D Flip flop:
CLK T Qn+1
0 X Qn

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1 0 0
1 1 1

Procedure:
1. Connect the trainer kit to the AC power supply.
2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.
4. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Power supply should not exceed more than +5V.

Result:
Thus the Latch and flip flops are designed and verified their truth tables.

Exp No-11: Design of Shift Registers.

Aim: - To realize the Design of shift registers.

Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1

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2 IC 7474 D Flip flop 1
3 IC 7408 AND Gate 1
4 IC 7432 OR Gate 1
5 Patch cords and connecting wires As required

Theory:

Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store
multiple bits of data, we need multiple flip flops. N flip flops are to be connected in an order to
store n bits of data. A Register is a device which is used to store such information. It is a group
of flip flops connected in series used to store multiple bits of data.

The information stored within these registers can be transferred with the help of shift registers.
Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in such
registers can be made to move within the registers and in/out of the registers by applying clock
pulses. An n-bit shift register can be formed by connecting n flip-flops where each flip flop
stores a single bit of data. The registers which will shift the bits to left are called “Shift left
registers”.

The registers which will shift the bits to right are called “Shift right registers”. Shift registers are
basically of 4 types. These are:

1. Serial In Serial Out shift register

2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register

Logic Diagram:
SISO:

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SIPO:

PIPO:

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PISO:

Procedure:
1. Connect the trainer kit to the AC power supply.
2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.
4. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Power supply should not exceed more than +5V.

Result:
Thus the shift registers are designed and verified their truth tables.

62 Digital Logic Design Practice | IIITDM Kurnool

Exp No-12: Design of Counters.

Aim: - To realize the Design of counters.

Apparatus Required:
S.No Name of the Component/Equipment Quantity
1 Digital Trainer Kit 1
2 IC 7473 JK Flip flop 2
3 IC 7408 AND Gate 1
4 IC 7432 OR Gate 1
5 Patch cords and connecting wires As required

Theory:
A Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in digital
electronics for counting purpose, they can count specific event happening in the circuit. For
example, in UP counter a counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on our design like any random
sequence 0,1,3,2… .They can also be designed with the help of flip flops.
Counter Classification:
Counters are broadly divided into two categories

● Asynchronous counter
● Synchronous counter

Asynchronous Counter :
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock
and the clock input of rest of the following flip flop is driven by output of previous flip flops.

Synchronous Counter:
Unlike the asynchronous counter, synchronous counter has one global clock which drives each
flip flop so output changes in parallel. The one advantage of synchronous counter over
synchronous counter is, it can operate on higher frequency than asynchronous counter as it
does not have cumulative delay because of same clock is given to each flip flop.

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Logic Diagram:
3-bit Asynchronous counter:

3-bit Synchronous counter:

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Procedure:
1. Connect the trainer kit to the AC power supply.
2. Make the circuit connections on Digital trainer Kit as per logic diagram.
3. Switch ON the trainer kit power supply after verified by the Instructor.
4. Verify the truth tables for each input/output combination.

Precautions:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Power supply should not exceed more than +5V.

Result:
Thus the counters are designed and verified their truth tables.

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IC PIN CONFIGURATIONS:

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67 Digital Logic Design Practice | IIITDM Kurnool