November 2,1999

AN4104

Forward Converter Type PC SMPS with SPS

Sangtae-Im
PD division

Introduction
The purpose of this application note is to examine basic circuit characteristics, transformer and
secondary inductor design methods according to the circuit design, auxiliary power supply terminal
and optimum remote control circuit etc., based on the forward converter with SPS (Fairchild power
switch) as all related to the desk-top PC SMPS.

First of all, the basic concept of the SPS is to combine the existing MOSFET and its control IC,
which were previously separately conÞgured, into 1 package and to include external circuits for
conÞguring existing, various protection features in the internal control IC to execute self-protection.
By doing this, the SMPS can be easily designed with few components, enhancing set reliability
and production and reducing Þeld defects. These additional effects result in Total cost down, the
ultimate purpose to its development.

Various line-up of SPS supports everything from products for 5W auxiliary power supply product to
250W, large capacity SMPS, depending on the type of the internal MOSFET. Table 1 shows the
SPS product groups which can be applied to a 220V-input forward converter with different output
power.

Because the forward converter has high energy transfer efÞciency as compared to the ßyback
converter, it can obtain a large output using a relatively small transformer and has superior output
ripple noise characteristics. For these reasons, it is frequently used in above -150W PC SMPS.
Unlike the ßyback-type, the forward converter operates with the ON-ON method immediately
delivering energy to the secondary side when the transformer primary main switch turns on.

The next section describes the basic circuit operation of this type of forward converter

Table 1.
Device Freq. Power
KA5H0165R 100kHz 10 ~ 20W
KA1M0680 70kHz 90 ~ 150W
KA1H0680 100kHz
KA1L0880 50kHz 180 ~ 250W
KA1M0880 70kHz

Rev C, November 1999

1
 RECT
C6 R3 R4 D5 L2
+12V
RT1 FUSE
R5 +
C4 C12 + C11 +
D2
C1
R6 +
C5 D4
+5V
R1

R2 R10
D3 C14 +
C13 +
D1 R7
R10
VCC Dranin
SPS
R8 R11
GND SS FB

C8 R12
C7 + C10 +
OP1
C9 C17
OP1
C15 C16 IC3

Figure 1. Basic circuit of the Forward converter with SPS

1. FORWARD CONVERTER
1.1 Basic Operation
Figure 2 shows the basic topology of the forward converter. The transformer in the forward con-
verter acts to eliminate the concept of energy storage and acts purely as an energy transfer media.
Therefore, the most ideal transformer in the forward converter would be one that has an inÞnite
magnetizing inductor value (Lm) making the circuit an open circuit, essentially. In actuality, how-
ever, this magnetizing inductor value is Þnite. Therefore, a circuit (Figure A) which completely
resets the stored energy in the magnetizing inductor before the beginning of the next switching
cycle when the switch turns on at every cycle is absolutely needed. Though there are various tech-
niques to form this type of a reset circuit, the transformer reset winding or the RCD clamping circuit
etc. is more widely used. It can be said that the forward converter operates basically the same as
that of the Buck converter (or also called the Step-down converter). It is just that the desired output
voltage can be obtained suitable for off-line by Þrst using the transformer to down the hundreds of
DC volts to an appropriate tens of volts and then stepping down through, again, two manual
switches (Diode1,2) and the secondary inductor. At this time, D1 always switches the same as the
primary main switch (SW) and D2 switches opposite to D1.

Rev C, November 1999

2
The next section reviews the stages along with each waveform of the operation of this type of for-
ward converter.
D1

+ iLi

Lm Vm D2
−

VIN + sw
−
D3 isw

+
−
VC
A

Figure 2. Forward converter topology

N:1 Li

+
+ + VLi − +
ia
Lm Vm VS VO
− −
+
− iLm −

VIN
isw

Figure 2a. Equivalent circuit when SW is on (t1~t2)

N:1 Li

+ VLi − +
+

Vm Lm VO

− −
VIN +
−

+
− VC

Figure 2b. Equivalent circuit when SW is off (t2~t3)

N:1 Li

+ + VLi − +

Vm Lm VO

− −
VIN +
−
t3 ~ t4
Cos

Figure 2c. Equivalent circuit when SW is off (t3~t5)

Rev C, November 1999

3
 Vm

Vin

Sa Sa=Sb

(a)

Sb

Vc-Vi

iLM

ILp
(b)

VLi

Vs-Vo
Sc Sc=Sd
(c)
Sd
Vo

iLi

Ip Io

(d)

isw

Ip
N
ILp
(e)

Vsw

Vc

Vi

(f)

t1 t2 t3 t4 t5

Figure 3. Operating waveform of the forward converter

t1~t2 Interval
Between t1~t2 when the primary side main switch (SW) turns on Þgure 2 and Þgure 2a becomes
equivalent and the state of each switching element, voltage and current of each terminal can be
expressed through the following equations.

SW: on, D1: on, D2: off, D3: off

Vm = VIN
iLm = (VIN / Lm) á t
Rev C, November 1999

4
ia = iLi / N
isw = iLm+ia = [(VIN / Lm)t] + [iLi / N]
VS = VIN / N

As revealed above, the current shape of the primary switch in the forward converter is determined
by the magnetizing inductance current, iLm, and the secondary inductor current, iLi.

Looking at Þgure 2a, voltage Vm equals VIN when the main switch (SW) is on and, in addition, the
secondary side voltage, VS, is applied in one direction, turning on D1. The current delivered
through the transformer supplies the output current (Io) through the secondary side inductor (Li). It
is stored in Li as magnetic energy until the main switch turns off and then it free wheels through D2
to supply the output current continuously.

t2~t3 Interval
When the primary main switch turns off, reverse voltage is applied to the Vs and D1 turns off. At
this time, the energy which was stored in Li during t1~t2 free wheels through D2 to supply output
current continuously and D2 turns on. As D3 turns on, the energy stored in the Lm forms the path
through which iLm can continuously ßow. At this time, the voltage across Vm is applied with reverse
voltage of (Vc-VIN) based on Vc making iLm have a negative slope (Figure 3b) which slowly
reduces to become 0 at t3. Consequently, the energy stored in Lm completely resets. Once Vm
resets and becomes 0V, D3 turns off.

One item to note here is that the max duty of the forward converter is decided when designing
according to the value of Vc. This can be well understood through Þgure 3(a). As was mentioned
previously, D3 and Vc act to completely reset the energy, which was stored in Lm during the inter-
val the SW was on, before the next cycle. For example, if Vc is designed to be 2VIN, namely, when
the Vm reverse voltage is designed to become -VIN when the SW is off and max duty exceeds
50%, the energy stored in Lm does not reset completely before the next cycle and eventually the
transformer saturates and the max duty becomes limited to 50%. This is a very important design
point for a forward converter and should be especially, carefully considered during designing in
order to properly obtain the maximum output under minimum input voltage conditions. The state of
each switching element during this internal is as follows:

SW: off, D1: off, D2: on, D3: on

t3~t5 Interval
Once t3 is reached, the stored energy in Lm completely resets; Vm becomes 0V; D3 turns off. The
equivalent circuit is shown in Þgure 2c. The energy stored in the secondary inductor, Li, free
wheels through D2 with a slope -Vo / Li until the next main SW turns on and continues to supply
output current. [Refer to Þgures 3c, d]. In this interval, the output voltage determined below is the
same as the input/output condition of the Step-down converter

V O = D × V S [D: Duty]

= D × ( V IN ÷ N )

Rev C, November 1999

5
The voltage waveform of the primary main switch (SW) of the forward converter is a step waveform
as in Þgure 3f. During the interval between t3~t4, there is resonance between the transformer mag-
netizing inductor (Lm) and the parallel equivalent capacitor of the SW and its voltage decreases to
the input voltage.

1.2 Reset Circuit ConÞguration

The circuit which resets the stored energy in the magnetizing inductor (Lm) in the forward con-
verter, during the time the primary switch is on, is different from Figure 2 and actually conÞgured in
the manner shown below.

iLm
iLm

iR

(a) (b)

Figure 4. Actual configuration of the reset circuit

As representative reset circuits, Þgures 4 (a) and (b) have the following characteristics.

Reset Circuit using the RCD

In Þgure 4(a), the circuit consumes the energy, which was stored in Lm during on time, through the
resistor and completely resets the Lm energy before the next cycle. Its concept can be considered
the same as that of the RCD snubber circuit, which is used to clamp the ßyback leakage inductor's
reverse voltage.

The reverse voltage across Lm, which changes with duty, is a special feature of this type of a RCD
reset circuit. Even if the input voltage becomes low as the reverse voltage increases due to an
increase in duty, it still has beneÞcial features in normal operation.

Reset Circuit using the Reset Winding

The circuit in Þgure 4(b) uses a separate reset winding to return the energy stored in Lm to the
source to completely reset the energy before the beginning of the next cycle.

When the diode connected in series to the reset winding in Þgure 4(b) turns on, the voltage across
the reset winding equals the input voltage (Vin). Furthermore, a reverse voltage based on the
winding ratio of the two windings is applied across Lm and this reverse voltage completely resets
the energy. Unlike the concept associated with the above RCD circuit, which consumes the energy
stored in Lm, the reset method, which returns the stored energy in Lm to the input using the reset
winding, is more advantageous in terms of efÞciency. However, if the input voltage decreases, the
reverse voltage across Lm decreases and, ultimately, the max duty becomes limited. Therefore,
where normal operation is required even at low input voltage, the reset circuit based on the above
RCD circuit can be advantageous.

Rev C, November 1999

6
1.3 Coupled Inductor Circuit

D5 Va
+12V
i2

Io2
+ VL2 −
−VLe+
Vb 12V
D4 Le

N:1
Vb
+5V
Va 5V
i1
L1

Io1 + VL1 −

Figure 5. Coupled inductor Figure 5.1. Equivalent circuit

of the coupled inductor

The output of the forward converter applied in an actual PC SMPS is not simply one but multi-
outputs of 3.3V, 5V and ±12V, usually. Among these, the 5V and 12V outputs design the secondary
side inductor as a coupled inductor, which uses the same core, as shown in Þgure 5. The main
reason for using the coupled, 5V and 12V inductors is to raise the cross regulation between the
two voltages resulting from load ßuctuations. If the turn ratio between the two windings and the turn
ratio of the transformer do not match when designing this type of coupled inductor, a ripple current
increases toward one of the two outputs (Figure 6b/c). This is described well in the equivalent
circuit in Þgure 5.1. If the turn ratio of the coupled inductor is designed well to be 5:12 when the
duty is 50%, the transformer turn ratio should be determined such that Va and Vb become 10V and
24V, respectively, for normal operation. However, a case where Vb was designed low such that it
only outputs 22V because the transformer turn ratio was not appropriate will be examined.

In such a case, the voltage across L1(VL1) becomes 5V and, accordingly, voltage across L2 (VL2)
becomes 12V based on the turn ratio. In addition, the voltage across the leakage inductor has a
reverse voltage of -2V and the current shape is such that the ripple voltage at the 5V terminal
becomes much larger, as shown by Þgure 6(c).In order to optimize the ripple current
characteristics at the two output terminals, the turn ratio should be determined such that turn ratio
of transformer at the two output terminals and the turn ratio of the inductor match. In an actual
circuit, this type of turn ratio matching is quite tricky. This is because the diode drop voltage varies
according to the amount of output current and because it is difÞcult to obtain a positive turn
ratio.Therefore, an actual design should consider these points such that the output voltage and
turn ratio are best matched.

Rev C, November 1999

7
 i2
i2
Io2
Io2

i1 i1
Io1 Io1

i1+i2 i1+i2

a) When the winding ratio between the transformer inductor is well matched b) When the transformerÕs 12V terminal is high

i2
Io2

i1
Io1

i1+i2

c) When the transformers 5V terminal is high

Figure 6. Each waveform of the secondary output terminal

1.4 Hold up Time and Slope Compensation

Like the PC SMPS, a power supply which supplies power to the apparatus which records and
saves data requires a minimum hold-up time to safely record the former execution in the event of
an instantaneous power failure or off power. The PC SMPS above generally requires this type of
hold up time. Once the main power turns off, the energy stored in the DC link capacitor supplies
the output power. Furthermore, the input voltage drops as time passes and, therefore, duty must
gradually increase in order to supply continuous output power. That is, in order to supply smooth
output power when the input voltage drops, the max duty value must be sufÞcient such that the
desired hold - up time is satisÞed even when a relatively small input capacitor is used. It must be
designed to operate normally up to a Þxed duty in order to supply output power over a Þxed period
of time in the event of an instantaneous power cutoff. Smooth reset must be possible even when
the duty increases and input power limitation due to sub-harmonic when duty exceeds 50% in the
current mode -controlled PWM SMPS must be prevented. Slope compensation is used to improve
the sub-harmonic in this peak current control mode.

Slope Compensation
Sub-harmonic shows cyclic distortion at a frequency lower than the basic switching frequency and,
consequently, does not exceed the input power of 50% duty during normal operation. A subhar-
monic is generated when the duty is above 50% at continuous current mode (CCM) in the peak
current control mode. This sub-harmonic is created when the waveforms input to the two PWM
comparator inputs do not meet at the point where they are to supposed to coincide. This is
because the error amp output of the voltage loop phase lags behind the output voltage waveform.

Rev C, November 1999

8
 OSC

Vfb +
ERR Ve S Q
Σ −
AMP
Vref − Comp R
+
Vc

Slope
Compensation T
Indutor
Current
T

Figure 7. Block diagram of the peak current mode control

Figure 8 shows current waveform distortions according to duty when controlled as an open loop
with an ∆Io error. In Þgure 8a, when the duty is less than 50%, ∆Io converges after few cycles have
passed but, in Þgure 8b, when duty is over 50%, ∆Io gradually gets larger as cycles pass and
results in the generation of sub-harmonic oscillation. On the other hand, in Þgure 8c, even when
duty is over 50%, with slope compensation applied at the error amp output, ∆Io converges after
few cycles as in Þgure 8a and, consequently, shows normal operation. Even if duty exceeds 50%
due to the lowering of the input voltage, normal output can be supplied without input power limita-
tion from subharmonics by applying slope compensation. Consequently, the desired hold up time
requirement can be satisÞed even using a small input capacitor. The optimum compensation can
be obtained when using 1/2 the negative slope (M2) of the current waveform in Þgure 2 as the
slope, generally, for slope compensation.

Error amp. Output voltage

Ve Ve

M2
M1 M2
M1
∆IO
∆I1 Inductor ∆IO Inductor
D ∆I1
D

a) Duty cycl < 0.5

b) Duty cycl > 0.5

Ve

Compensating slope

M1 M2
∆IO
Inductor

D ∆I1

c) Duty cycl > 0.5 with slope compensation

Figure 8. Slope compensation

After having reviewed slope compensation for improving the subharmonic oscillation when control-
ling through the peak current mode, the application of slope compensation in a circuit with SPS will
Rev C, November 1999

9
be examined. With SPS, the application circuit for slope compensation can be formed more simply
than the existing 3842 series, as shown by Figure 9. It can be formed by using the voltage wave-
form of the VCC terminal winding of the transformer. A negative slope can be obtained when C1
discharges due to the negative voltage at the VCC terminal when the SW is on. This slope is deter-
mined by R1 and C1 time constants; the equation is presented below. C1 value should be ten
times the C2 value and R1 value can be calculated from equation 1. It can be then designed with
the desired slope.

SPS
FB

C2
R1
Ton Toff

Vs waveform + iC1
+
Vs C1
−

Figure 9. Slope compensation application circuit of the SPS

Vc1
R1 Linear slope

∆Vc
+
−
V + C1
Discharge
t
ton

Ð ton ⁄ R 1 C 1
∆V C 1 = V S ( e Ð 1 )………1

Figure 10. Equivalent circuit of the interval when the SW is ON and FB terminal actual waveform

2. Auxiliary Power Supply

The auxiliary power supply for the PC SMPS requires an output voltage of 5V-10Watt. Unlike the
main power supply, this auxiliary power supply is always operating as long as AC input is supplied.
The SMPS for the auxiliary power supply is low power -below 10W. It is a circuit with KA1H0165R/
KA1H0165RN ßyback conÞguration using the primary side regulation method to reduce cost.

Figure 11 shows the ßyback method auxiliary power supply circuit with KA1H0165R, controlled
through primary regulation. The next section reviews each stage of operation of this type of auxil-
iary power supply terminal.

Rev C, November 1999

10
 L201

R101
C101
D201
R102
+ +
EC201 R201 EC202

D103 D102
C104
+
1: SOURCE
2: DRAIN 3 2
3: VCC
4: Feedback 1H0165R

ZD101
C103 + 1 4

R104
C105
R103

Figure 11. Primary regulation method flyback converter using KA1H0165R

2.1 Start-up
Because the PC SMPS input terminal always uses the voltage doubler, it rectiÞes with the DC volt-
age of 220VAC even if 110VAC is input. Therefore, the start up condition for a auxiliary power sup-
ply can be calculated based on the 220V input power supply condition ßyback design. The start up
current consumed in the internal UVLO block before the SPS starts-up is deÞned to be Max
450µA. Furthermore, the start-up voltage to start internal blocks is 15V and the stop voltage to stop
them is 10V.

Furthermore, an appropriate start-up resistance for the auxiliary power supply is calculated such
that current over 450µA needed at the start can be supplied to the IC even at the lowest DC input
conditions.

The equation is presented below.

R102 = (240 Ð 15) Ö 450µA = 500kΩ

The time after the AC is input and before the auxiliary power supply starts is determined based on
the start-up resistance and capacitance (C103) connected in parallel to the VCC terminal.

2.2 Primary Regulation

VCC
1mA SPS
Vfb Vfb*

D1 D2
R1
−
Cfb
R2 +

Ids

*R1 + R2 = 3kΩ

Figure 12. SPS feedback regulation circuit

Rev C, November 1999

11
Figure 12 shows the block diagram of the SPS internal feedback terminal and the external applica-
tion circuit used for primary regulation.

When the feedback terminal in the Þgure is operating normally, Vfb voltage is set to always main-
tain a Þxed VCC voltage and compared to the transformer inductor sensing current (Ids) to deter-
mine the PWM duty.

Furthermore, the secondary side output voltage, proportional to the primary side voltage, is based
on the transformer turn ratio. To increase the load regulation of the output voltage due to load vari-
ations, the coupling coefÞcient between the primary and secondary side should be designed high
when making the transformer and an appropriate dummy resistance attached to the load terminal.
The advantage of primary regulation is the cost down effect, but its disadvantage is that precise
output voltage regulation is difÞcult when the load variation is wide.

However, it is useful in a system where the load variation is comparatively stable after power has
been applied.

Table 2 shows the parts list of Þgure 11 needed to form the auxiliary power supply

Table 2. Part list of Þgure 11

Part Value Part Value

R101 100kΩ D101 UF4007
R102 500kΩ D102 1N4937
R103 120Ω D103 1N4148
R104 1.2kΩ D201 Shottoky
C101 222 / 630V C202 470µF / 10V
C103 22µF R201 470µF / 10V
C103 22µF R201 500Ω
ZD101 12V / 0.5W L201 20µH

2.3 Remote ON-OFF Control

The above type of PC SMPS requires a remote control, which can cut off the main power supply
terminal operation, through an external or internal signal at stand by. The remote control applica-
tion circuit for the main power supply terminal with SPS easily controls by ÒdowningÓ the potentials
of the SPS soft-start terminal and the feedback terminal to ground level. The circuit can be formed
by adding external components, one TR, one diode and one photocoupler, excluding the existing
photo-coupler (OP1) for controlling feedback.

The operation of this remote control can be understood through the SPS internal block in Þgure
13(b). As shown by the Þgure, the current source controls the SPS internal feedback terminal. Fur-
thermore, all three, internal diodes are on from 0~3V in the initial state and their voltages are
almost equal. Consequently, Vfb, VSS and VCO have the same potentials. Furthermore, if TRs of
the photocouplers connected to feedback and soft -start terminals completely saturate in Figure 13

Rev C, November 1999

12
(b), all the current from the current source discharges through the feedback terminal and S/S termi-
nal paths and eventually VCO becomes lower than 0.2V, the transistor saturation voltage. Because
the positive terminal of the comparator in Þgure 13 (b) has a 0.1V offset, the negative terminal of
the internal comparator (Comp1) always has a voltage less than the positive terminal if VCO is less
than 0.2V and, as a result, the comparator output becomes high state. If the comparator output
maintains the high state, the SPS cannot switch any further and cuts off the main power supply ter-
minal operation. Again, to start the main power supply operation, the TR in the secondary side is
turned off and OP1 and OP2, which were held back in the primary side, are released. Because the
VCC voltage is normal at this time, soft start operation starts like the before and the main power
source terminal switches normally. The reason for making the feedback terminal and soft start ter-
minal GND level simultaneously for the remote control is as follows:

First, even if OP2 was eliminated and OP1 in the feedback terminal saturated, VCO drops below
0.2V as mentioned before and the main power supply terminal stops switching and its operation
stops. However, VSS remains at 5V because the diode connected to the soft start terminal has
been cut-off and, therefore, it cannot execute SPS soft start when the main power terminal is
restarted. Therefore, to make the initial state or equal conditions to turn on/ off the main power sup-
ply terminal using the remote control, the soft start terminal must be ÒdownedÓ to the GND level.

Furthermore, even when the soft start terminal OP2 is ÒdownedÓ to the GND level and the feed-
back terminal OP1 left as is, VCO drops below 0.2V and the main power supply terminal stops
operating. However, the problem that arises at this point is that Vfb gradually increases due to the
5µA current supply source connected to the feedback terminal. When the feedback voltage
reaches 7.5V, SPS latches -up due to the internal protection circuit and, once latched-up, the
latched-up state does not release until VCC falls below 5V. Therefore, even if the main power sup-
ply terminal is turned on by the remote control, the SPS remains latched-up and does not operate.

The feedback terminal potential is dropped to the GND level to prevent the feedback voltage from
rising to 7.5V by ßowing 5µA through OP1.

Though the method of cutting off the SPS VCC power of the main power supply exists for remote
control of the main power supply besides the above method, dropping the soft-start and feedback
terminal voltages to GND level is simpler and effective in terms of circuitry for faster control based
on the remote control signal. Figure 14 shows the application circuit of the PC SMPS, which
require the auxiliary power supply, with SPS, above examined slope compensation and possible
remote-On/ Off control.

The auxiliary power supply terminal has the ßyback conÞguration primary regulation method with
KA1H0165R and the main power supply terminal is designed to have the forward conÞguration
with KA1M0880 allowing 5V and 12V outputs. The auxiliary power supply VCC winding supplies the
DC input to the SPS VCC of the main power supply and, once the AC input power is supplied, the
auxiliary power supply always operate normally.

Rev C, November 1999

13
 VCC

5V(Output of Auxiliary SMPS)

VCC Drain

SPS
GND SS FB
+

OP2
+
OP1

OP1

Remote control signal

(a)

5µA 1mA

VCO
Comp1
Feedback
−
Vfb +

Soft start VSS

0.1V
5V offset

OP1
+
SPS

OP2

(b)

Figure 13. Application circuit for remote control(a) and SPS internal block diagram(b)

Rev C, November 1999

14
 C101 R101

R102
D101

D103 L201 +5V

D201

D102
3 2
+ +
EC202

ZD101
1H0165R EC201 R201

C103 1 4
+
R104
C102 R103

DC input
C6 R3 R4 D5 L2
+12V
+

D2 D4
+5V

R9
+ +
C13 C14 R10
3 1 R12 R13
R11
2 1M0880
R8
+ 5 4
C7
OP1 OP2
+ C8

C10 D6
C9 TR1
OP2 IC3
OP1
C15 C16

Remote on / off
signal

Figure 14. PC SMPS application circuit diagram with SPS

and auxiliary power supply terminal remote on/off function

Rev C, November 1999

15
3. KNOWN CAUTIONARY ITEMS WHEN DESIGNING TO APPLY THE SPS
Until now, the forward converter operation with SPS and SPS application circuit conÞguration
method according to the various, special conditions of the PC SMPS were examined. Next, the
known cautionary items when designing a circuit with SPS will be reviewed.

3.1 PCB Layout

Unlike the previous circuit which separated the switching element and the PWM control IC, the
SPS combines the switching element (MOSFET) and the PWM IC into one package so the follow-
ing items must be carefully considered when laying out the PCB.

One of the main items for caution when laying out the SMPS PCB is always the separation of the
power GND and the Signal GND. The SPS package internally has a common GND so the power
GND and Signal GND must be separated at the shortest possible point from the lead frame GND-
Pin and the GND pattern length made shortest possible when laying out the PCB. (Refer to Þgure
15 )

Sense
FET
IC

Drain GND V CC Vfb SS

DC link capacitor

Layout the PCB by separating the power

GND and signal GND at the shortest
Make power GND the shortest
and thickest possible

Figure 15. SPS lead frame and layout technique

3.2 Auxiliary Power Supply Switching Oscillation

The SPS PWM control is the Current Mode method. Though there are many advantages to the
Current Mode Control, switching oscillation can be generated due to the noise in the sensing
current if the output load decreases.

(Refer to Figure 16) The sensing current noise can greatly affect the PCB pattern, but, by using
slope compensation as shown in Figure 16, the PCB could be designed more prudently. The
standard values of the components used for slope compensation are presented in Figure 16. The
above values is applicable to all ßyback conÞgured SMPS.

Rev C, November 1999

16
 Vfb
isense (a) Ideal case

Noise (b) Real case

switching error

Slope
Compensation
(c) Slope Compensation

VCC
VCC
1H0165R
1H0165R
FB
FB

272
272

333 2.2k

(d) Application of slope compensation to improve switching oscillation

Figure 16. Origin for switching oscillation at no load and slope compensation application

Referance
[1] Switch Mode Power Supply Handbook, Keith H. Billings, McGraw-Hill, Inc., 1989

[2] ÒCoupled Filter Inductors in Multiple Output Buck Regulators Provide Dramatic Performance
Improvement,Ó L. H. Dixon, Unitrode Seminar Manual SEM500

[3] ÒModeling, Analysis and Compensation of the Current-Mode ConverterÓ, Unitrode Application
Note(U-97), Unitrode Linear Integrated Circuits Data Book and Applications Handbook

[4] Fairchild Semiconductor SPS Application Note, Fairchild Electronics, 1999

Author
Sangtae, Im is an application engineer in Power Device Division, Fairchild Electronics Co., LTD.

Tel. 82-32-680-1275
Fax. 82-32-680-1317
E-mail. [email protected]

Rev C, November 1999

17
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™ ISOPLANAR™ TinyLogic™

CoolFET™ MICROWIRE™ UHC™
CROSSVOLT™ POP™ VCX™
E2CMOSTM PowerTrench 
FACT™ QFET™
FACT Quiet Series™ QS™
FAST® Quiet Series™
FASTr™ SuperSOT™-3
GTO™ SuperSOT™-6
HiSeC™ SuperSOT™-8
DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.