TOSHIBA MOS MEMORY PRODUCTS

TC5565APL-10, TC5565APL-12, TC5565APL-15

TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
DESCRIPTION
The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and
operates from a single 5V supply. Advanced circuit techniques provide both high speed and low power features with a maximum
operating current of 5mA/MHz and maximum access time of 100ns/120ns/150ns.
When CE2 is a logical low or \CEl is a logical high, the device is placed in low power standby mode in which standby current is 2uA
typically. The TC5565APL/AFL has three control inputs. Two chip enable (\CE1, CE2) allow for device selection and data retention
control, and an output enable input (\OE) provides fast memory access. Thus the TC5565APL/AFL is suitable for use in various
microprocessor application systems where high speed, low power, and battery back up are required.
The TC5565APL also features pin compatibility with the 64K bit EPROM (TMM2764D).
RAM and EPROM are then interchangeable in the same socket, resulting in flexibility in the definition of the quantity of RAM versus
EPROM in microprocessor application systems. The TC5565APL is offered in a dual-in-line 28 pin standard plastic package. The
TC5565AFL is offered in 28 pin mini Flat Package.
FEATURES • Directly TTL Compatible
• Low Power Dissipation : All Inputs
and Outputs
27.5mW/MHz(Max.) operating • Pin Compatible with 2764 type EPROM
• Standby Current: 100uA(Max.) Ta=70°C • TC5565APL Family (Package Type)
• Access Time
TC5565APL/AFL-10 : 100ns(Max.) Package Type Device Name
TC5565APL/AFL-12 : 120ns(Max.) 600 mil DIP TC5565APL
TC5565APL/AFL-15 : 150ns(Max.) 300 mil DIP *TC5563APL
• 5V Single Power Supply - (Slim Package)
• Power Down Features: CE2, \CE1 Flat Package TC5565AFL
• Fully Static Operation (SOP)
Data Retention Supply Voltage: 2.0-5.5V * See TC5563APL Technical Data.
PIN CONNECTION (TOP VIEW) BLOCK DIAGRAM

AO-A12 Address Inputs

R/W Read/Write Control Input
\OE Output Enable Input
\CE1, CE2 Chip Enable Inputs
I/O1 – I/O8 Data Input/Output
VDD Power (+5V)
GND Ground
N.C. No Connection
 TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15

OPERATION MODE \CE1 CE2 \OE R/W 1/01-T/08 POWER

Read L H L H DOUT IDDO
Write L H * L DIN IDDO
Output Deselect L H H H High-Z IDDO
Standby H * * * High-Z IDDS
L * * High-Z IDDS

MAXIMUM RATINGS
SYMBOL ITEM RATING UNIT
VDD Power Supply Voltage -0.3~7.0 v
VIN Input Voltage *-0.3~7.0 v
VI/O Input and Output Voltage -0-5-VDD+0.5 v
PD Power Dissipation 1.0/0.6** W
Tsolder Soldering Temperature 260-10 °C sec
Tstg Storage Temperature -55~150 °C
Topr Operating Temperature 0-70 °C
* -3.0V at pulse width 50ns MAX. **Flat package

D.C RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER MIN. Typ. MAX. UNIT
VDD Power Supply Voltage 4.5 5.0 5.5 v
VIH Input High Voltage 2.2 - VDD+0.3 v
VIL Input Low Voltage -0.3 - 0.8 V
VDH Data-Retention Supply Voltage 2.0 - 5.5 V
 TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15

D.C and OPERATING CHARACTERISTICS (Ta=0~70°C, VDD = 5V±10%)

SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
Input Leakage
IIL VIN=O~VDD - - ±1.0 uA
Current
IOH Output High Current VOH-2-4V -1.0 - mA
IOL Output Low Current VOL-0.4V 4.0 - mA
VIH or CE2-VOL or
\CE1 = VIH or CE2=VOL 0r R/W = VIL
ILO Output Leakage Current - - ±1.0 uA
or \OE=VIH
VOUT=0~VDD
tcycle =1.0us 10 mA

TC5565APL-10 tcycle
- - 45 mA
TC556SAFL-10 =100ns

VDD =5.5V
\CE1=VIL
IDDO1 CE2=VIH TC5565APL-12 tcycle - - 40 mA
Other input= TC5565AFL-12 =120ns
VIH/VIL

TC5565A?L-15 tcycle
- - 35 mA
TC5565AFL-15 =150ns
Operating Current

tcycle=1.0us - - 5 mA

TC5565APL-10
tcycle =100ns - - 40 mA
VDD=5.5V TC5565AFL-10
\CEl=O.2V
IDD02 CE2=VDD –0.2V TC5565AFL-12
Other lnput= tcycle =120ns - - 35 mA
VDD - 0.2V/0.2V TC5565AFL-12

TC5565APL-15
tcycle =150ns - - 30 mA
TC5565AFL-15

IDDS1 \Cel = VIH or CE2 = VIL 3 mA

VDD = 5.5V - 2 100 uA
Standby Current \CE1 = VDD – 0.2V or
*IDDS2 VDD = 3.0V - 1 50 uA
CE2 = 0.2V

Note * In standby mode with \CE1>= VDD – 0.2V, these specification limits are guaranteed under the condition of
CE2 >= VDD – 0.2V or CE2 <= 0.2V.

CAPACITANCE (Ta=25°C)
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
CIN Input Capacitance VIN = GND - - 10 pF
COUT Output Capacitance VOUT = GND - - 10 pF
* This parameter periodically sampled is not 100% tested.
 TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15

A.C. CHARACTERISTICS (Ta=0~70°C, VDD = 5V±10%)

Read Cycle
SYMBOL PARAMETER TC5565APL-10 TC5565APL-12 TC5565APL-15
TC5565AFL-10 TC5565AFL-12 TC5565AFL-15
MIN. MAX. MIN. MAX. MIN. MAX
tRC Read Cycle Time 100 - 120 - 150 -
tACC Address Access Time - 100 - 120 - 150
tCOL \CE1 Access Time - 100 - 120 - 150
tC02 CE2 Access Time - 100 - 120 - 150
tOE Output Enable to Output Valid - 50 - 60 - 70
tCOE Chip Enable (\CE1, CE2) to
10 - 10 - 15 -
Output in Low-Z
tOEE Output Enable to Output in Low-Z 5 - 5 - 5 -
tOD Chip Enable (CE1, CE2) to
- 35 - 40 - 50
Output in High-Z
tODO Output Enable to Output in High-Z - 35 - 40 - 50
tOH Output Data Hold Time 20 - 20 - 20 -

Write Cycle
TC5565APL-10 TC5565APL-12 TC5565APL- 5
SYMBOL PARAMETER TC5565AFL-10 TC5565AFL-12 TC5565AFL- 5
MIN. MAX. MIN. MAX. MIN. MAX..
tWC Write Cycle Time 100 - 120 - 150 -
tWP Write Pulse Width 60 - 70 - 90 -
tCW Chip Selection to End of Write 80 - 85 - 100 -
tAS Address Set up Time 0 - 0 - 0 -
rWR Write Recovery Time 0 - 0 - 0 -
tODW R/W to Output High-Z - 35 0 40 - 50
rOEW R/W to Output Low-Z 5 - 5 - 10 -
tDS Data Set up Time 40 - 50 - 60 -
tDH Data Hold Time 0 - 0 - 0 -
A.C. TEST CONDITION

Output Load : 100pF + 1 TTL Gate

Input Pulse Level : 0.6V, 2.4V
Timing Measurement VIN : 0.8V, 2.2V
Reference Level VOUT : 0.8V, 2.2V
tr, tf : 5ns
 TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
TIMING WAVEFORMS
READ CYCLE (1)

WRITE CYCLE 1 (4) (R/W Controlled Write)

 TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15

WRITE CYCLE 2 (4) (\CE1 Controlled Write)

WRITE CYCLE 3 (4) (CE2 Controlled Write)

 TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
Note 1. R/W is High for Read Cycle.

2. Assuming that \CE1 Low transition of CE2 High transition occurs coincident with or after R/W Low transition, Outputs
remain in a high impedance state.

3. Assuming that \CEl High transition or CE2 Low transition occurs coincident with or prior to R/W High transition, Outputs
remain in a high impedance state.

4. Assuming that \OE is High for Write Cycle, Outputs are in high impedance state during this period.

DATA RETENTION CHARACTERISTICS (Ta=0~70°C)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT
VDH Data Retention Supply Voltage 2.0 - 5.5 V
Stand by Supply Current VDD=3.0V - - 50
IDDS2 uA
VDD=5.5V - - 100
tCDR Chip Deselection to Data Retention Mode 0 - - us
tR Recovery Mode tRC(1) - - us
Note (1) : Read cycle Time.

\CE1 Controlled Data Retention Mode (2)

CE2 Controlled Data Retention Mode (4)

 TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
Note 2 : In \CE1 controlled data retention mode, minimum standby current mode is achieved under the condition Of CE2<= O.2V Or
CE2>= VDD -0.2V.

3: If the VIH of \CE1 is 2.2V in operation, IDDS1 current flows during the period that the VDD voltage is going down from 4.5V to
2.4V,

4; In CE2 controlled data retention mode, minimum standby current mode is achieved under the condition of CE2 <= 0.2V.

DEVICE INFORMATION

The TC5565APL/AFL is an synchronous RAM using address activated circuit technology, thus the internal operation is synchronous.
Then once row address change occur, the precharge operation is executed by internal pulse generated from row address transient.
Therefore the peak current flows only after row address change, as shown in the following figure.
This peak current may induce the noise on VDD /GND lines. Thus the use of about 0.1uF decoupling capacitor for every device is
recommended to eliminate such noise.
 TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15

DIP 28 PIN OUTLINE DRAWING (6D28A-P) Unit in mm

Note) Lead pitch is 2.54 and tolerance is +\-0.25 against theoretical center of each
lead that is obtained on the basis of No.1 and No.28 leads.

MFP 28 PIN OUTLINE DRAWING (F28GC-P) Unit in mm

Note) Lead pitch is 1.27 and tolerance is +\-0.12 against theoretical center of each
lead that is obtained on the basis of No.1 and N0.28 leads