ALU Project Report

Submitted to Sir Noman

Project Question.
Design an Arithmetic Logic Unit that takes two four bit binary numbers A (A3A2A1A0) and B (B3B2B1B0) as inputs and do the following operations: It can add the two numbers. It can subtract the two numbers. It can multiply the two numbers. It can compare the two numbers. It can shift a number. It can rotate a number. Bit wise operation of AND, OR, X-OR, NOT.

The figure shown above is the schematic of our ALU having all the required operation. It uses registers to store the output values and for add, subtract and multiplication input registers have also been used. And these registers were made using simple D-Latches.

The Simple D-Latches:

These D-Latches have been used at the outputs except rotation. And secondly these were also used at the inputs for addition, subtraction and multiplication. They only work when the clock pulse is 1 and the outputs remain the same as the input D is. The Operation of ALU: Our ALU has two binary inputs A and B. Then there are corresponding control lines for rotating (that defines the rotating position of the bits). There is a control line for add/subtract i.e. if its 0 operation add will be selected and if its 1 operation subtraction will be selected. There is a common input clock pulse too. The inputs are being shown in the following figures:

Now discussing the particular operations performed by this ALU

Addition and Subtraction:

The first diagram shows the components used in the operation add/subtract. Lower figure shows that two inputs were taken A and B and were passed through the D-Latches so that it

can be stored. The outputs of these D-Latches were put into the full adders and then the outputs of these full adders were put into the output registers. And then the output was displayed in a five bit number. There is a control input that specifies addition or subtraction. That input is being exclusive ORed with the inputs. When this control input is 0, addition will take place and when it is 1, subtraction will take place. The figure at the right side on the last page shows the five bit output. One thing that should be kept in mind while subtraction is; A should be greater than B. There are four full adders that are used in this circuit. Each full adder consists of 2 XOR gates, 3 AND gates and an OR gate. The 3 AND gates are connected to the OR gate which gives the carry output. The sum output is achieved by the combination of two XOR gates. Each input of second four bit number i.e. B is connected to the XOR gate along with the input Control Input(CI).When CI is 0, the output of these XOR gates will be the same as that of the inputs of B and the circuit will perform addition. But when CI is 1, the outputs of these XOR gates will give the 1s complement of the inputs of B. CI acts as the carry input to the circuit i.e. it adds to the first bit of B i.e. B0, converting the 1s complement of B into 2s complement. Now we can add this 2s complement to the 1st four bit number A and achieve the subtraction operation. The functions used are: SUM = A (X-OR) B (X-OR) C CARRY = A.B+A.C+B.C Comparator:

The above figure shows a comparator, and the colored outputs shows three cases A>B,A<B and A=B. wires coming from the same two input D-Latches and then the corresponding bits passing through the two AND gates and so 8 AND gates were used. After that every two AND

gates were OR-ed. And the complete circuit can be seen in the above diagram. The functional operations used are following: A=B:

A>B:


A<B:
 

These functions were used in the form of gates..As shown in the figure. Bit wise Operation: These operations were very simple to perform. We used simple gates between the two bit, on which bitwise operation was to be performed (single bit in case of NOT). The outputs of these gates were given to the multiplexer. Then by changing the selection inputs of the multiplexer, the desired operation can be achieved.

Multiplication:

The main sequence followed by us can be seen in the figure above at the left side. We had to use 16 AND gates for making all the possible combinations between the bits of A and B. These 16 AND gates can be seen the figure at right, the inputs are coming from the input D-Latches. Since, in binary multiplication, the output is 1 when both the numbers are 1, whereas in all other cases it is 0. So this can be achieved by the use of AND gates. In the next step, both full and half adders are used to achieve the final output. Then first and give directly to output, while others use the full and half adders to complete the operation prescribed in the above left figure. And the carrys keep on going to the next stage. After these operations, the output passes through the output D-Latches and gives us the output in 8 bits as shown in the below figure:

Bit Shifting: Bit shifting is achieved by using shift registers. This shift register is known as parallel in-parallel out register. This is used due to the fact that we have to shift the bit from the left most side to the right side. There were two control inputs, when one of them is at 1, we can load it. When lower one is 1, the 1 starts to shift into the output and our initial bits start flushing out from the right side. For this function four positive edge triggered D-Latches were used and can be seen in the following figure:

Bit Rotating: Bit rotation means that the bits from the right side are shifted to the left side of the number or vice versa. The number of bits rotated depends on the type of bit rotation. In this circuit we have used left rotation. The bit shifting is achieved by using multiplexers. Each of the four multiplexers is given input from the same four bits but in different orders. For example, the first multiplexer is given input in the order A3A2A1A0 but the next is given A2A1A0A3 and so on. In this way, if both the select lines are OFF then we get normal output i.e. equal A3A2A1A0, but for S1=0 and S0=1, we get A2A1A0A3 and so on. The figure is shown below: