3D Electro-optical Simulations for Improving the

Photon Detection Probability of SPAD

Implemented in FD-SOI CMOS Technology
2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) | 978-1-6654-0685-7/21/$31.00 ©2021 IEEE | DOI: 10.1109/SISPAD54002.2021.9592555

S. Gao D. Issartel R. Orobtchouk

Univ Lyon Univ Lyon Univ Lyon
INSA Lyon, CNRS, INL, UMR5270 INSA Lyon, CNRS, INL, UMR5270 INSA Lyon, CNRS, INL, UMR5270
Villeurbanne, France Villeurbanne, France Villeurbanne, France
[email protected] [email protected] [email protected]
F. Mandorlo D. Golanski A. Cathelin
Univ Lyon STMicroelectronics STMicroelectronics
INSA Lyon, CNRS, INL, UMR5270 Crolles, France Crolles, France
Villeurbanne, France [email protected] [email protected]
[email protected]
F. Calmon
Univ Lyon
INSA Lyon, CNRS, INL, UMR5270
Villeurbanne, France
[email protected]

Abstract—In this article, a 3D electro-optical simulation incident photon to generate an avalanche event. is
method is presented in order to estimate the Photon Detection affected by several factors: wavelength, applied voltage,
Probability (PDP) of Single-Photon Avalanche Diodes photogeneration rate, electric field, doping levels. In order
(SPAD). The efficiency of the proposed simulation flow is
to improve the , authors in [7]-[9] respectively employ
demonstrated through a complete study aimed at improving
the PDP of a SPAD implemented in 28nm Fully Depleted the following approaches: i) an optimized SPAD
Silicon-On-Insulator (FD-SOI) CMOS technology using a architecture with charge-focusing, ii) an increase of light-
light-trapping approach (thanks to the patterning of Shallow material interaction thanks to nanostructuration, and iii) a
Trench Insolation – STI layer). Simulation shows an increase germanium cavity as an absorption layer. In this study, we
of PDP spectrum of over 50% at wavelengths of 400-550nm propose an efficient 3D electro-optical simulation method
and 750-1000nm and of 10-15% at the wavelengths of 550- to estimate the . Then, using the proposed electro-
750nm, compared to a reference SPAD without any optical simulation flow, we implement the light-trapping
nanostructuration. approach to improve the of SPAD devices
Keywords—SPAD; 28nm FD-SOI CMOS; Photon Detection implemented in 28nm FD-SOI CMOS technology.
Probability PDP; TCAD simulation; light-trapping
The method to optimize the PDP uses a simulation flow
I. INTRODUCTION described in section II where the electrical behaviour of
SPAD structure is also considered. In section III, the
Single-Photon Avalanche Diodes (SPAD) or Geiger- simulation methodology with the light-trapping approach
mode Avalanche Diodes have been a very active research is presented. Simulation results of proposed electro-optical
topic for the last few years due to their relatively simple simulation flow are reported and discussed in section IV.
structure making them easy to be implemented in CMOS
technologies and also due to their sub-nanosecond response II. PHOTON DETECTION PROBABILY SIMULATION
time and high light sensitivity [1]. SPAD devices are METHOD
frequently used for several purposes: Time-Of-Flight (TOF)
[2] for 3D imaging and LIDAR applications, charged In order to estimate the of SPAD devices, we
particle detection for medical and high energy physics integrated the product of the Avalanche Triggering
applications [3], Fluorescence Lifetime Imaging Probability ( ) and the electron-hole photogeneration
Microscopy (FLIM) for biological applications [4]. SPAD rate ( ) over the active volume ( ) of the SPAD. Then we
devices have been implemented in 28nm Fully Depleted divided by the incident photon flux (number per
Silicon-On-Insulator (FD-SOI) CMOS technology, which second) at the considered wavelength :
allows intrinsic 3D pixel [5] and indirect sensing of SPAD 1
, , ∗ , , , 1
avalanche events [6]. In this technology, SPAD devices are
implemented below the buried oxide (BOX) layer and the
electronic logic circuits are inserted in the thin silicon layer
on top of the BOX layer, which provides an intrinsic 3D
stack and a much higher fill-factor.
One of the key figures of merit of SPAD devices is the
Photon Detection Probability ( ) leading to important
research studies. represents the SPAD devices’
sensitivity and is defined as the probability of an absorbed Figure 1 Block diagram of Photon Detection Probability estimation

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 The simulation flow was then divided into two parts: drift velocity ( of holes in some areas and we
electrical part and optical part. We performed the electrical considered that when the ratio / was above 0.5,
and optical simulations with Synopsys Sentaurus and the n-type quasi-neutral region ended.
Lumerical FDTD respectively to obtain data for both the
electrical data ( , electric field , carrier mobility µ) The electrical simulations were 2D cylindrical symmetry
and optical data (photogeneration rate ). Data are whereas the optical simulations were 3D (with adapted
limit conditions linked to spatial period). The external
combined and postprocessed within an external Matlab
Matlab routine was able to extrapolate the 2D electrical
routine, as shown in Fig. 1.
data according to the cylindrical symmetry and to create 3D
We considered that the SPAD was composed of the matrix of electrical data. It was thus able to combine 2D
Space Charge Region – SCR (as multiplication region) and electrical and 3D optical data to calculate the .
two quasi-neutral regions, one p-type doped on top of the
SCR and the other n-type doped at the bottom of the SCR. III. SIMULATION METHODOLOGY
We calculated the limits of the active region (where
photogenerated carriers effectively lead to an avalanche A cross section of the investigated SPAD implemented in
event) by investigating the electric field distribution across 28nm FD-SOI CMOS technology is shown in Fig. 4. In the
the structure and also the ratio of drift and diffusion active region above the p-Well, design rules dictate the
velocities of minority carriers in each quasi-neutral region existence of Shallow Trench Isolation (STI) between
to consider the contribution of these regions to the . silicon regions. We artificially used these blocks of STI
Fig. 2 and 3 illustrate the profiles of electric field and ratio properly choosing their dimensions and positions, to realize
of drift and diffusion velocities of minority carriers a photonic crystal layer (diffraction grating) providing
respectively at the p-side and the n-side limits of SCR with light-trapping effects, in order to locate the maximum of
an excess voltage of 1.5V (15% of the breakdown voltage). interferences in the SCR.

Figure 4 Schematic of SPAD implemented in 28nm FD-SOI CMOS

technology (Scales are not respected and BEOL layers are not
Figure 2 Profiles of electric filed and ratio of drift and diffusion represented)
velocities of electrons at the p-side limit of SCR
From the optical point of view, the SPAD structure could
be simplified as shown in Fig. 5. Here the SiO2 region and
silicon substrate region are considered semi-infinite.

Figure 5 Simplified equivalent optical schematic of the SPAD

Figure 3 Profiles of electric filed and ratio of drift and diffusion structure
velocities of holes at the n-side limit of SCR
The problematic of improving the photon detection
We considered that the beginning of p-type quasi-neutral efficiency with a diffraction grating comes down to
region was given by the direction of electrical field that was maximizing the light intensity in the SCR (multiplication
favourable for electrons and the beginning of SCR (end of region). This optimisation is thus realised in two steps.
p-type quasi-neutral region) corresponded to the position Firstly, the pattern plays the role of an antireflection
where the electric field magnitude was below the threshold coating in the case of Front-Side Illumination (FSI) to
of -105V/cm. The end of SCR (beginning of n-type quasi- minimize the reflection coefficient "# at interface
neutral region) was where the electric filed surpassed the SiO2/diffraction grating. "# is function of the optical index
threshold. For the end of the n-type quasi-neutral region, n1, n2 and n3 and the diffraction grating thickness $% . The
the diffusion velocity ( of holes is dominant over the

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equivalent optical refractive index &%,'( in the case of FSI
follows an effective medium law [10]:
&%,'(
%
&)% *+ ∗ 1 , -- . &% / 0 ∗ -- 2
Here the Filling Factor (FF) is defined as the ratio
between the silicon area and the total area of one pattern
with square shape. The equivalent optical index of
diffraction grating layer is thus function of FF. The second
step consists of using the interferences of diffraction
grating to locate the maximum of light intensity in the SCR
where the ATP is the highest. The position of the
maximums of interferences is function of the pattern period.
Suitable pattern periods allow to improve the
photogeneration rate in the SCR and thus to improve the
general photon detection probability. Figure 7 Profiles of photogeneration rate of reference SPAD and
patterned SPAD with FF=0.15 and period=10nm
Our simulation methodology is to first find the optimal
FF of STI which allows the maximum light transmission electric field magnitude up to 30% and of photogeneration
by performing optical simulations with a small pattern rate up to 60%. Considering we didn’t fully control the
period (less than 100nm). Once the optimal -- is found, pattern dimensions, the antireflection effect could have
the second step is to extract the optimal spatial period been more significant.
allowing the constructive interferences in the SCR. The second step was dedicated to the optimisation of
pattern period in order to locate the maximums of
IV. SIMULATION RESULTS
interferences in the SCR. Several values of pattern period
The simulation methodology was applied to SPAD for each FF were performed in simulations. Fig. 8
implemented in 28nm FD-SOI CMOS technology (Fig. 4) illustrates a cartography of photogeneration rate at
in the case of FSI with several constrains. The first one is wavelength of 500nm with a pattern period of 0.48µm and
that the depth of STI blocks is fixed by the technological
process. Additionally, the process design rules impose
certain restrictions on width, length of STI areas and
distance between them. As the SPAD devices are
fabricated in standard process, the second constraint refers
to Back-end-of-Line (BEOL) layers, which are not
optimized for optical light transmission (moreover, their
optical properties are not fully characterized). Nevertheless,
the optimisation strategy still remains effective.
In the first step, several values of FF were simulated at
wavelengths of 500nm and 650nm. Fig. 6 and Fig. 7
respectively represent the profiles of electric field
magnitude and photogeneration rate with FF = 0.15 at
wavelength of 500nm and with a pattern period of 10nm.
These profiles were extracted near the centre of one pattern
and the incident light power was set to 1W/m². The curves
showed a significant antireflection effect of pattern with Figure 8 Cartography of photogeneration rate of patterned SPAD with
FF=0.15 and period=0.48µm
different values of FF compared to reference structure, with
a relative improvement of

Figure 6 Profiles of electric field magnitude of reference SPAD and Figure 9 PDP Profiles of reference SPAD and patterned SPAD with
patterned SPAD with FF=0.15 and period=10nm excess voltage Vex=0.6V

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 V. CONCLUSION
In this article, a 3D electro-optical simulation method for
SPAD Photon Detection Probability ( ) calculation is
presented. Then light-trapping concept thanks to the
patterning of STI layer is proposed to improve the of
a SPAD fabricated in 28nm FD-SOI CMOS technology
(with Front Side Illumination). The maximum relative gain
of 700% was reached at specific wavelengths and an
average gain of 100% in the range of wavelengths of 400-
1000nm was also obtained. These encouraging results have
permitted IC fabrication including several designs of FD-
SOI CMOS SPADs with different STI pattern sizes. Future
work will address the characterization of samples
with/without an STI pattern and improving the in the
Figure 10 PDP Profiles of reference SPAD and patterned SPAD with
excess voltage Vex=1.5V
case of Back-Side Illumination.
an FF of 0.15. The SCR was located 180nm away from the ACKNOWLEDGMENT
interface diffraction grating/silicon substrate. We could
observe the presence of a hot spot in the SCR, showing The authors would like to thank the Nano2022 research
clearly the diffracting effect of the pattern. program for the PhD Grand of Shaochen Gao, the French
national research agency ANR (ANR-18-CE24-0010) for
These period dimensions were then used in the the PhD Grand of Dylan Issartel and CMP (Grenoble) for
simulations with a larger range of wavelengths of 400- IC prototyping services.
1000nm in order to investigate the improvement for other
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