ECSE 222 – Digital Logic

Fall 2022 – Lecture 3

Boris Vaisband
 Agenda
• Canonical forms of Boolean functions
• VHDL

• Relevant book sections: 2.6, and 2.10

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 2
 Canonical Forms of Boolean Functions – Sum of Products
• Given n Boolean variables
• Minterm – product term where each of the n variables appears
▪ In non-complemented or complemented form
▪ Example: for 𝑥1 , 𝑥2 , 𝑥3 – 𝑥1 𝑥2 𝑥3 , 𝑥1ҧ 𝑥2 𝑥ҧ3 … → 2𝑛 minterms
• Sum of products
▪ The function y can be represented as a sum of minterms that correspond to all of the rows
in the truth table of the function where 𝑦 = 1
▪ Example: Row
x1 x2 y 𝑦 = ෍ 𝑚 0, 1, 3 = 𝑚 + 𝑚 + 𝑚 = 0 1 3
0 0 0 1 𝑚0 = 𝑥ҧ1 𝑥ҧ2 ∙ 𝑦(0)
1 0 1 1 𝑚1 = 𝑥ҧ1 𝑥2 ∙ 𝑦(1) 𝑥ҧ1 𝑥ҧ2 + 𝑥ҧ1 𝑥2 + 𝑥1 𝑥2
2𝑛 −1
2 1 0 0 𝑚2 = 𝑥1 𝑥ҧ2 ∙ 𝑦(2)
3 1 1 1 𝑚3 = 𝑥1 𝑥2 ∙ 𝑦(3)
General form ෍ 𝑚𝑖
𝑖=0
ECSE 222 – Digital Logic
(Fall 2022) B. Vaisband 3
 Canonical Forms of Boolean Functions – Product of Sums
• Given n Boolean variables
• Maxterm – sum term where each of the n variables appears
▪ In non-complemented or complemented form
▪ Example: for 𝑥1 , 𝑥2 , 𝑥3 – (𝑥1 + 𝑥2 + 𝑥3 ), (𝑥1ҧ + 𝑥2 + 𝑥ҧ3 )… → 2𝑛 maxterms
• Product of sums
▪ The function y can be represented as a product of maxterms that correspond to all of the
rows in the truth table of the function where y = 0
▪ Example: Row
x1 x2 y
0 0 0 1 𝑀0 = 𝑥1 + 𝑥2 + 𝑦(0) 𝑦 = ෑ 𝑀 2 = 𝑀2 = (𝑥ҧ1 + 𝑥2 )
1 0 1 1 𝑀1 = 𝑥1 + 𝑥ҧ2 + 𝑦(1)
2𝑛 −1
2 1 0 0 𝑀2 = 𝑥ҧ1 + 𝑥2 + 𝑦(2) General form ෑ 𝑀𝑖
3 1 1 1 𝑀3 = 𝑥ҧ1 + 𝑥ҧ2 + 𝑦(3) 𝑖=0

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 4
 Relation Between Sum of Products and Product of Sums
• Sum of products 𝑦 = 𝑥ҧ1 𝑥ҧ2 + 𝑥ҧ1 𝑥2 + 𝑥1 𝑥2 → use Boolean algebra →

𝑥ҧ1 𝑥ҧ2 + 𝑥ҧ1 𝑥2 + 𝑥1 𝑥2 = 𝑥ҧ1 (𝑥ҧ2 +𝑥2 ) + 𝑥1 𝑥2 = 𝑥ҧ1 + 𝑥1 𝑥2 = 𝑥ҧ1 + 𝑥2

• This process is called minimization

• We received the product of sums

2𝑛 −1 2𝑛 −1

෍ 𝑚𝑖 = ෑ 𝑀𝑖
𝑖=0 𝑖=0

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 5
 The World Before VHDL
• Polygon pushing
• Transistor-level design
• Boolean design
▪ One equation for each observable node
• Schematic design
▪ Use circuit blocks – impractical for large designs
• HDL – hardware design language

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 6
 What is VHDL?
• VHDL – VHSIC HDL – Very High Speed Integrated Circuit Hardware
Description Language
▪ Originally developed in 1983 by the US DoD
▪ First standard in 1987, revised in 1993
• VHDL is an industry standard language used to describe hardware from the
abstract to the concrete level
• Other common HDL languages: Verilog and SystemC
• VHDL is NOT a software programming language
• Where does it fit in the design flow?

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 7
 Typical Digital Design Flow
Design conception

Design Entry Physical design (layout)

Schematic capture VHDL

Timing simulation

Synthesis

No Timing
requirements
Functional simulation
met?

No Yes Yes
Design correct? Chip configuration
(implementation)
ECSE 222 – Digital Logic
(Fall 2022) B. Vaisband 8
 Before We Move Forward
• VHDL syntax is also covered in the first tutorial
• The book provides many good examples
• Google is your friend

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 9
 VHDL Design Units
• Entity
▪ Specifies the interface of the system with the environment
• Architecture
▪ Description of the internal part of the system, specifies how the inputs are transformed
into outputs
• Configuration
▪ Used to combine a component instance to an entity-architecture pair
• Package
▪ Encapsulate elements that can be shared globally among design units

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 10
 Entity
• Interface description
▪ Defines connections (ports)
▪ Transfer information to and from the system
• Port types
▪ IN, OUT, INOUT
• Example
ENTITY rsff IS set q
PORT (set, reset : IN BIT; rsff
q,qb : OUT BIT);
END rsff; reset qb

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 11
 Architecture
• All entities have one or more architectures
• Describes the functionality of the system
• Always connected with a specific entity
▪ Entity ports are available as signals within the architecture
• Description can be structural or behavioral
▪ Structural – specifies which sub-components are used and how they are connected
• A purely structural architecture does not describe any functionality and contains just a list of
components, their instantiation and the definition of their interconnections
▪ Behavioral – specifies what the system does, describes the response of the outputs to
changes of the inputs

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 12
 Architecture Syntax
• Declaration section architecture SYNTAX of EXAMPLE is
▪ Data types subtype DIGIT is integer range 0 to 9;
▪ Constants constant BASE: integer := 10;
signal DIGIT_A, DIGIT_B: DIGIT;
▪ Additional signals signal CARRY: DIGIT;
▪ Components begin
▪ More DIGIT_A <= 3;
SUM <= DIGIT_A + DIGIT_B;
• Definition section (after “begin”) DIGIT_B <= 7;
▪ Signal assignments CARRY <= 0 when SUM < BASE else 1;
▪ Processes end EXAMPLE ;
▪ Component instantiation
▪ Concurrent statements – order not important

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 13
 Structural Architecture entity FULLADDER is
port (A,B, CARRY_IN: in bit;
SUM, CARRY: out bit);
• A purely structural architecture does end FULLADDER;
not describe any functionality
architecture STRUCT of FULLADDER is
▪ Only a list of components signal W_SUM, W_CARRY1, W_CARRY2 : bit;
▪ Their instantiation component HALFADDER
port (A, B : in bit;
▪ Definition of their interconnections SUM, CARRY : out bit);
• Example end component;
component ORGATE
port (A, B : in bit;
RES : out bit);
end component;

begin
MODULE1: HALFADDER
Instantiation port map(A, B, W_SUM, W_CARRY1);

…
ECSE 222 – Digital Logic
(Fall 2022) B. Vaisband 14
 Port Association
• Two methods of port association are possible
▪ Positional port association
• E.g., port map(A,B,C,open,E);
• Order is critical
▪ Named port association
• E.g., port map(Sum=>S, Carry=>open, IN1=>X, IN2=>Y);
• Left side: formals – port names from component declaration
• Right side: actual – architecture signals
▪ Independent of order in component declaration

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 15
 Behavioral Architecture Example

entity compare is
port(A,B: in std_logic_vector(7 downto 0);
EQ: out std_logic);
end compare;

architecture compare1 of compare is

begin
EQ <= '1' when (A = B) else '0';
end compare1;

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 16
 Design Example – 2→1 MUX

x1 0
s f
f 0 x1
1 x2
x2 1

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 17
 2→1 MUX – Entity Declaration
• Entity construct describes how the outside world sees our MUX
• Effectively defines the inputs and outputs of a black box called MUX21
s Library definition
VHDL standard –
library IEEE; includes STD_LOGIC
use IEEE.STD_LOGIC_1164.all; data type
x1 0 Black box named
ENTITY MUX21 IS “MUX21” I/O
PORT ( s, x1, x2: IN STD_LOGIC; definition
f
f : OUT STD_LOGIC
“IN” and “OUT” ports
);
x2 1 (to black box)
END MUX21; description
End of black box
“MUX21” definition

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 18
 2→1 MUX – Architecture Declaration – Structural
• Architecture construct describes the functionality of the black box defined by
the Entity construct
▪ Functionality description enclosed by “BEGIN” and “END”

x1 ARCHITECTURE LogicFunc OF MUX21 IS

BEGIN
f <= (x2 AND s) OR ((NOT s) AND x1);
f END LogicFunc;

s
x2

• VHDL does not assume any precedence of operators!

▪ This is not what you think it is f <= x2 AND s OR NOT s AND x1; it is a compilation error
▪ Use parenthesis
ECSE 222 – Digital Logic
(Fall 2022) B. Vaisband 19
 2→1 MUX – Architecture Declaration – Behavioral
• Instead of describing the gates used to implement a MUX
• We can simply describe what the MUX does – its behavior

ARCHITECTURE Behavior OF MUX21 IS

s f BEGIN
WITH s SELECT
0 x1 f <= x1 WHEN ‘0’,
1 x2 x2 WHEN ‘1’,
‘X’ WHEN others;
END Behavior;

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 20
 STD_LOGIC Data Type
• There is more to life than ‘0’s and ‘1’s
• The STD_LOGIC data type includes
▪ ‘U’ – uninitialized signal
▪ ‘X’ – unknown value
▪ ‘0’ – logic zero
▪ ‘1’ – logic one
▪ ‘Z’ – high impedance
▪ ‘W’ – weak signal
▪ ‘L’ – weak signal that should probably go to ‘0’
▪ ‘H’ – weak signal that should probably go to ‘1’
▪ ‘-’ – don’t care

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 21
 2→1 MUX – Signals
• Signals describe physical wires in the circuit
▪ Ports describe the associated signals of the same name

sig1
x1 ARCHITECTURE LogicFunc OF MUX21 IS
SIGNAL sig1, sig2 : STD_LOGIC;
BEGIN
f sig1 <= x1 AND (NOT s);
sig2 <= s AND x2;
s f <= sig1 OR sig2;
x2 END LogicFunc;
sig2

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 22
 2→1 MUX – Signal Order
• The order of signal assignment does not matter
• Why?
• This is not programming
▪ VHDL describes hardware

ARCHITECTURE LogicFunc OF MUX21 IS ARCHITECTURE LogicFunc OF MUX21 IS

SIGNAL sig1, sig2 : STD_LOGIC; SIGNAL sig1, sig2 : STD_LOGIC;
BEGIN BEGIN
sig1 <= x1 AND (NOT s); f <= sig1 OR sig2;
sig2 <= s AND x2; sig1 <= x1 AND (NOT s);
f <= sig1 OR sig2; sig2 <= s AND x2;
END LogicFunc; END LogicFunc;

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 23
 Data Types
• Every signal has a type
▪ Type specifies possible values
▪ Type must be fixed at signal declaration
• In entity: port declaration, or
• In architecture: signal declaration
• Data types on both sides of the assignment operator '<= ‘ must match
• Two main data types
▪ Scalar types – integer, real, enumerated
▪ Composite types – arrays and records
• Arrays – collection of signals of the same type
▪ Predefined arrays
• std_logic_vector (array of std_logic)
• string (array of character)

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 24
 Assignment for “std_logic” Data Type
• Single bit values are enclosed in '.'
• Vector values are enclosed in "..."
• Values may be separated by underscores to improve readability

signal BUS_A : std_logic_vector (3 downto 0);

BUS_A(3) <= ‘1’;

BUS_A <= “0011”;

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 25
 Operators
• VHDL includes built-in support for the following operators/gates
▪ AND
▪ OR
▪ NOT
▪ NAND
▪ NOR
▪ XOR
▪ XNOR
• Signal assignment operator ‘<=’

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 26
 Concatenation Operator
• The concatenation operator '&' is allowed only on the right side of the signal
assignment operator '<=‘

architecture CLASS1 of CONCAT is

signal BYTE : bit_vector (7 downto 0);
signal A_BUS, B_BUS : bit_vector (3 downto 0);
begin
BYTE <= A_BUS & B_BUS;
end CLASS1;

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 27
 Design Example – 2x2 Crossbar Switch
If 𝑠 = 0 then 𝑦1 = 𝑥1 and 𝑦2 = 𝑥2
𝑠=0

𝑥1 𝑦1 = 𝑥1
𝑠
𝑥2 𝑦2 = 𝑥2
𝑥1 𝑦1

𝑥2 𝑦2
If 𝑠 = 1 then 𝑦1 = 𝑥2 and 𝑦2 = 𝑥1
𝑠=1

𝑥1 𝑦1 = 𝑥2

𝑥2 𝑦2 = 𝑥1

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 28
 2x2 Crossbar Switch – Entity Construct
s
ENTITY Xbar IS
x(0) y(0) PORT ( x : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s : IN STD_LOGIC;
x(1) y(1) y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
);
END Xbar;

• “Bundle” bits into STD_LOGIC_VECTOR of two bits

• Both for inputs and outputs

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 29
 2x2 Crossbar Switch – Architecture Construct
x(0)
M1 y(0)
s

x(0) y(0)
s
x(1) y(1)
x(1)
M2 y(1)

ARCHITECTURE Structure OF Xbar IS

COMPONENT MUX21
• Use MUX21 as a sub-circuit
PORT ( s, x1, x2: IN STD_LOGIC; • Described as a “COMPONENT” of the “Xbar”
f : OUT STD_LOGIC);
END COMPONENT; • Two instances of the component MUX21
BEGIN
M1: MUX21 PORT MAP (s, x(0), x(1), y(0));
M2: MUX21 PORT MAP (x1 => x(1), x2 => x(0), f => y(1), s => s);
END Structure;
ECSE 222 – Digital Logic
(Fall 2022) B. Vaisband 30
 2x2 Crossbar Switch – Architecture Construct
x(0)
M1 y(0)
s

x(0) y(0)
s
x(1) y(1)
x(1)
M2 y(1)

ARCHITECTURE Structure OF Xbar IS

COMPONENT MUX21
• Map the ports of the sub-circuits to signals in
PORT ( s, x1, x2: IN STD_LOGIC; the “ARCHITECTURE”
f : OUT STD_LOGIC); • M1 – order matters
END COMPONENT;
BEGIN • M2 – order does not matter
M1: MUX21 PORT MAP (s, x(0), x(1), y(0));
M2: MUX21 PORT MAP (x1 => x(1), x2 => x(0), f => y(1), s => s);
END Structure;
ECSE 222 – Digital Logic
(Fall 2022) B. Vaisband 31
 2x2 Crossbar Switch – Architecture Construct – Behavioral
s

x(0) y(0)

x(1) y(1)

ARCHITECTURE Behavior OF Xbar IS

BEGIN
WITH s SELECT
y <= x(1) & x(0) WHEN 0, & is the “concatenate” operator
x(0) & x(1) WHEN 1;
END Behavior;

ECSE 222 – Digital Logic

(Fall 2022) B. Vaisband 32