Logic Equivalence Check

Verifies equivalence of design at different stages of

the ASIC flow
Contents:
● What is Logic Equivalence Check (LEC)
● Importance of LEC
● LEC in ASIC flow
● LEC process flow
● Steps for Logic Equivalence Check
● Setup Mode
● Design constraints
● Modeling directives
● Switch to LEC mode
● LEC mode
● Mapping process
● Compare process
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What is Logic Equivalence Check (LEC):
Logic Equivalence Check makes sure that two different representation of design
are logically equal by comparing design to be verified against reference design.

STAGE A RTL netlist

Design
LEC tool Synthesis Conformal
process

Equivalent Equivalent
Yes/No Yes/No
STAGE B Gate level

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Importance of LEC:
● Design passes through various steps like synthesis, place and route,
sign-offs, ECOs and numerous optimizations before it reaches production. At
every stage, we need to make sure that the logical functionality is intact
and does not break because of any of the automated or manual changes.

● If the functionality changes at any point during the entire process, the
entire chip becomes useless. This is why LEC is one of the most important
checks in the entire chip design process.

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LEC in ASIC flow:
● After getting the RTL design next step is to go for the gate level
representation by synthesis.

Here the equivalent checking comes to play as it compares the functionality

of RTL & netlist generated after synthesis is compared & check that both
still work exactly same or not.

● If it is passed then it goes for place & route then again equivalent checking
check the pre ApR gate level netlist & post ApR netlist for its functionality.

Note: After each and every manual and automated changes LEC takes place to make sure Logic remains same.
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LEC in ASIC flow:
● Verifies equivalence of design at different stages
of ASIC flow. i,e. After writing an RTL if any
changes are made then LEC takes place to make
sure modified RTL and previous RTL logic is same.

● LEC doesn’t verify timing so timing has to

verified separately.

● LEC is technology independent.

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LEC process flow:
LEC comprises of three steps-

● Setup Mode
● Mapping Mode
LEC Mode
● Compare Mode

There are various tools for performing LEC-

Formality from Synopsys, Conformal from
Cadence.

We will use conformal for Logic Equivalence Check

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Steps for Logic Equivalence Check:
Setup Mode: Tool needs two designs and their associated libraries to perform
LEC. We designate the design types, which are Golden (which is verified, such as
RTL verified from Front-end) and Revised (which is modified).

● Saving LEC transcript to a log file

● Specifying black boxes
● Reading libraries and designs
● Specifying design constraints
● Specifying modeling directives
● Switching to LEC mode

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Setup Mode:
● Saving LEC transcript to a log file: Specify the name of the log file where
LEC session transcript is to be written.

set log file logfile -replace

● Specifying black boxes: Modules types RAM or any encrypted IP functions,

analog, behavioral or any module which user don’t want to verify are
specified as black box.
○ Execute black boxing command before module is read in
add notranslate modules *ram*
○ Check for unbalanced black boxes in the Golden and Revised (after generating report)

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Setup Mode:
● Reading libraries and designs: All the library files and design files are
defined in this section.
○ Library
■ Verilog (standard simulation libraries), Liberty

read library -Both -liberty /home/timing_libs/slow.lib

○ Design (Synthesizable RTL, gate, transistor)

■ Verilog, VHDL, SPICE

read design -verilog -Golden /files/mapped_syn_rtl.v

read design -verilog -Revised /files/mapped_syn_rtl.v

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Setup Mode:
● Specifying design constraints:
○ First of all what are the design constraints?
- User’s inputs to control part of a design’s logic
○ Purpose of constraints:
■ To disable test logic (for example; scan and JTAG)
■ To specify relationships between pins
■ To constrain undriven signals
○ Example of constraints:
■ Pin constraint
■ Instance constraint
■ Pin equivalence
■ Tied signal
■ Undriven signal

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Design constraints:
● Pin constraints: Specify the mode of circuit operation under which
comparison will take place (for example; functional vs. scan operation).

add pin constraints 0 scan_en -revised

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Design constraints:
● Instance constraint: Apply to any internal DFF or D-latch output to Logic-0
or logic-1 (for example; JTAG registers).

add instance constraint 0 U1 -revised

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Design constraints:
● Pin equivalence: Specify the relationship (equivalent or inverted equivalent)
between two or more primary input pins.

add pin equivalence CLK –invert CLK_n -revised

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Design constraints:
● Tied signal: Specify floating nets or pins to be tied to Logic-0 or Logic-1 (for
example; equate GND to 0 or VDD to 1).

add tied signal 0 GND -net -revised

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Design constraints:
● Undriven signals: Specify the global behavior of floating signals in the
designs (for example; ties all floating signals to a constant).

set undriven signal 0 -revised

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Setup Mode:
● Specifying modeling directives: In SETUP mode, user can specify directives
to influence the way LEC models the design.

○ Modeling directives are needed to handle modeling styles specific to

vendors’ libraries or synthesis tools.
○ Modeling options:
■ Latch folding
■ Gated-clock
■ Latch transparent

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Modeling directives:
● Latch folding: Tool might use 2 D-latches (master/slave) to model a DFF.
Which will create a mapping issue.

set flatten model -latch_fold

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Modeling directives:
● Gated-clock: Tools create latch-based gated clock circuit instead of using
specified cell, which causes aomparing problem.

set flatten model –gated_clock

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Modeling directives:
● Latch transparent: Designer’s choice to have a D-latch with its clock always
enabled as a buffer (transparent latch), causes comparing problem.

set flatten model –latch_transparent

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Setup Mode:
● Switching to LEC mode: After defining the black boxes, libraries, designs,
constraints and directives, setup is done. Now we will move to LEC mode for
further operations.

set log file logfile.log -replace

add notranslate module *sram*
read library -liberty /home/libs/slow.lib
read design cpu_rtl.v -verilog -golden
read design -file verilog.vc -verilog -revised
add pin constraint 0 scan_en -revised
set flatten model -latch_fold
set system mode lec 21
Switch to LEC mode:
● Flatten golden and revised designs
○ For both Golden and revised netlists Conformal flatten the hierarchy and makes flat netlists

● Perform circuit modeling

○ Conformal gets the functionality from the Golden netlist then it will read in the revised
verilog netlist and then reads in .libs and extracts the functionality from the .lib using the
functional statement in the .lib for each cell

● Map key points (automatic by default)

○ While switching to LEC mode from setup mode the tool automatically maps all the key
points.

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LEC mode:
After completing the setup we will check the logic equivalence in between of
our golden and revised design.

● LEC mode:
○ Mapping process
■ Resolving unmapped key points
○ Compare process
■ Debugging non-equivalent key points

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Mapping process:
Here, we are going to map the key points and as well as resolve the unmapped
key points.

Key points: primary inputs(PI), primary outputs(PO), DFFs, D-latches, black

boxes are considered as the key points.

● Design consists of combinational logic cones

bounded by the key points.

map key points

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Mapping process:
Conformal maps design in few processes.

Name-based: Mapping based strictly on instance pathnames (or net names) of

key points.

Function-based: Mapping based on function and structure of logic cones.

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Mapping process:
set mapping method <mapping_option>

● Can be applied in both SETUP and LEC modes

● Available mapping options:

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Mapping process:
Key point Mapping: Pairing corresponding key points PI’s, PO’s, DFFs, D-latches,
black boxes in between Golden and Revised netlists.

● While key points are mapped corresponding logic cones are also correctly
paired.

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Unmapped key points:
Warning: Key point mapping is incomplete

There could be some unmapped key points while mapping in between Golden
and Revised. There have several types of unmapped points:

Extra: Key point that exists in only the Golden design or in only the Revised
design, but does not affect the circuit functionality. Example: scan_in, scan_out

Unreachable: Key point that is not propagated to any observable point.

Example: spare flops

Not-mapped: Key point that has no correspondence on the other side.

report unmapped points

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Unmapped key points:
Solution: Add renaming rule
add renaming rule <rule_id> <search_string> \
<replacement_string> [-golden | -revised]

● Renaming rule structures

○ %d - matches 1 or more digits (0-9)
○ #(expr) - expr evaluates to a constant integer
○ %s - matches 1 or more alpha-numeric characters

● The escape character " \ "

○ You must prefix the following special characters with "\" if they are used in the
search_string as a normal character “ % . * ^ $ | ( ) [ ] / \ ”

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Compare Process:
Compare points are:

● Logic cones
● Primary outputs, DFFs, D-latches, and black boxes

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Compare Process:
● Corresponding combinational logic cones
● Two designs are equivalent when all corresponding cones are equivalent

add compare points -all

compare

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Compare Process:
● Comparison result: report compare data -class [...]

Equivalent: Key points proven to be equivalent (green-filled circle)

Inverted-Equivalent: Key points proven to be complementary (divided

green-filled circle)

Non-Equivalent: Key points proven to be different (red-filled circle)

Abort: Key points not yet proven equivalent or non-equivalent due to

timeout or other system parameters (yellow-filled circle)

Not-Compared: Key points not yet compared

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Debugging non-equivalent key points:
● Using the Mapping Manager to sort key points
● Concentrate on one logic cone at a time
● Debugging tools
○ Diagnosis Manager
○ Schematic Viewer

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Thank You

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