10th International Radar Symposium India - 2015 (IRSI - 15)

Bias Sequencing and Gate Pulsing Circuit for GaN

Amplifier
Apet Barsegyan, VinodhThangam, and Daniel Koyama
Integra Technologies, Inc., 321 Coral Circle, El Segundo, CA 90245, USA
[email protected]

Abstract:
This article explores the design and performance of a bias 2 Noise Blanking
sequencing and gate pulsing circuit used with a GaN HEMT For improved system performance, a noise blanking
power amplifier. With a focus on simple system integration, the circuit was integrated with the bias sequencer. In radar
circuit has been designed to enable the amplifier to operate from systems, noise blanking improves receiver sensitivity by
a single +50V supply.To make the amplifier fully autonomous, the reducing the inter-pulse noise leakage in receive-mode
gate pulsing circuit is designed to be triggered by RF input signal
instead of conventional TTL external control.
during the pulse-off period. The noise blanking function is
typically accomplished by switching the on/off bias of the
Keywords:GaN, HEMT, Transistor, Amplifier, Bias Sequencing, power amplifier in sync with the RF pulse, where the off-
Gate Pulsing state isolation of the amplifier provides the noise rejection
during the off period. For this demonstration a gate pulsing
I INTRODUCTION approach was used, where the gate bias voltage is switched
This paper describes a bias sequencing and gate pulsing alternately between normal bias and pinch-off in sync with
circuit integrated onto a RF power amplifier assembly with the RF pulse. Gate pulsing has the advantage of easier circuit
Integra GaN transistor IGN1214M500 [1]. Measurements implementation because of the low current and voltage
include pulse rise/fall time and delay, noise blanking. We switching requirement.
briefly investigate bias temperature compensation as an
option for enhancing performance. To facilitate system integration and demonstrate the
concept of a simple "drop-in" amplifier solution, the gate
II CIRCUIT REQUIREMENTS pulsing circuit is designed to trigger from the RF input signal
Gallium Nitride (GaN) is becoming the power amplifier thereby eliminating the need for external system control. A
technology of choice for radar system designersseeking detector/comparator circuit on the input side is used to sense
higher RF power densities, higher efficiency, and higher the RF signal and activate the gate pulsing function. This
voltage operationcompared tolegacytransistor technologies gate pulsing approach has been used successfully for an
such as silicon bipolar and Laterally Diffused MOS Integra customer's LDMOS pallet amplifier operating at 2
(LDMOS). In contrast to the more forgiving biasing ms pulse width and18% duty cycle.
requirements of enhancement-mode devices such as
LDMOS, GaN has special bias sequencing requirements All of the bias circuitry described above was
which system designers must accommodate to prevent incorporated onto the amplifier substrate assembly to make a
damage to the devices. “stand-alone” amplifier module (see figure 1).

1 Bias Sequencing
Depletion-mode devices such as GaNHigh Electron
Mobility Transistors (HEMTs)require positive drain voltage
with negative gate voltage to control the drain current. For
safe operation, the negative gate voltage should be present
before drain voltage is applied. During power-up, ideally one
should pinch off the GaN device gate during the initial drain
ramp-up. Likewise during power-down, the gate should be
pinched off again as drain voltage is decreased to zero.

The circuit described in this paper accomplishes this bias

sequencing function using a hot-swap controller IC [2] in Figure 1: IGN1214M500 Amplifier with bias sequencing and gate pulsing
combination with an N-Channel power MOSFET drain circuitry
switch. The circuit contains a voltage regulator and voltage
inverter to generate all internal voltages required by the
sequencer, thereby enabling single supply operation.

NIMHANS Convention Centre, Bangalore INDIA 1 of 5 15-19 December 2015

 10th International Radar Symposium India - 2015 (IRSI - 15)

Figure 2: Schematic of Bias Sequencing and Gate Pulsing Circuit

IIICIRCUIT DESCRIPTION Q4, allowing drain voltage to be applied to the GaN device.
Referring to the schematic in figure 2, an N-channel The supply voltage at which this occurs can be set by
power MOSFET Q4is used as a drain switch connecting the resistors R4 and R5. As an example, for R4=68KΩ and
positive supply to the drain of the GaN device. Q4 has low R5=10KΩ, the supply voltage will begin to turn the drain on
Rds,on = 8.5 mΩ to minimize voltage drop, and up to 80A of when it reaches 31V (31*10K/[10K+68K] = 4). The GATE
current handling. Q4 is switched on and off via the GATE pin (pin 6) of U1 utilizes a charge pump to provide a linear
pin (pin 6) of controller U1. ramp-up of the drain voltage. This ramp-up time can be
adjusted with capacitor C5.
At initial DC power-up, Q4 remains off while the +5V
voltage regulator U2 and voltage inverter U3 turn on. The For power-down, the process occurs in reverse except
output of U2 drives the input of U3 to produce the -5V that the threshold level is slightly offset due to built-in
needed for the GaN transistor gate biasing. When the hysteresis in controller U1 (high-to-low threshold, pin UV =
positive supply voltage reaches about +4 volts, U3 begins to 3.6V).For the example given above, the high-to-low
turn on and negative voltage appears at its output. When U3 threshold will be triggered when the supply voltage crosses
output voltage reaches about -4 volts, NPN transistor Q3 28V (28*10K/[10K+68K]=3.6) at which time Q4 turns off.
turns on, which turns on P-channel MOSFET Q1. With Q1 As described earlier, the negative voltage will not begin to
on, its source terminal goes to 0V, turning off N-channel shut down until the supply voltage has dropped below about
MOSFET Q2. The open-circuit at the drain of Q2 +4V.
disconnects it from the UV pin (pin1) of U1 and allows
normal operation of the controller U1 to proceed. Whenever The gate pulsing circuit is DC-poweredfrom the -5V
U3 is off or not fully on (i.e., is not outputting -4 volts or output of the voltage inverter U3, but otherwise operates
less), Q2 will be on, pulling the UV pin (pin 1) of the separately from the bias sequencer. In the off period of the
controller U1 down to 0V and forcing U1 to turn off Q4. RF pulse, the gate pulsing circuit is inactive and passes the -
This insures that no drain voltage is applied to the GaN 5V to the gate of the GaN transistor keeping it pinched off.
device when the voltage inverter is not outputting at least -4 In the pulse-on period, a Schottky diode detector circuit
volts, and that the GaN device will always be pinched off triggers a comparator/switch circuit which switches the gate
initially when drain voltage is being applied to it. voltage to the desired operating bias level. The bias can be
set in a voltage divider circuit formed by an adjustable
As power-up proceeds, U1 becomes active and assumes potentiometer. For fast switching time, a high-speed rail-to-
control of the remaining bias sequencing process. When the rail op-amp was used in the buffer amplifier. Also,
UV pin (pin 1) of U1 reaches the low-to-high threshold capacitance on the gate bias line following the switch was
voltage of 4V, the GATE pin (pin 6) of U1 begins to turn on minimized to maintain fast rise/fall time.

NIMHANS Convention Centre, Bangalore INDIA 2 of 5 15-19 December 2015

 10th International Radar Symposium India - 2015 (IRSI - 15)

The supply current draw of the sequencer/gate pulsing

circuit is 17 mA @ +50V supply.
IVAMPLIFIER MEASUREMENTS
An Integra IGN1214M500GaN HEMT amplifier with
on-board bias sequencing and gate pulsing circuitry was
assembled and tested. The amplifier has typical output power
of 500W and 13.5 dB RF gain at 60% efficiency over the 1.2
GHz to 1.4 GHz band.

The gate pulsing voltage waveform is shown in figure

3.The RF output pulse waveforms are shown in figure 4.
Measured rise/fall times are 100 nanoseconds and 16
nanoseconds respectively. For comparison, the same
transistor was tested in a fixture with normal gate biasing (no
gate pulsing); the RF pulse waveforms are shown below in
figure 5. With normal gate bias the rise time is 59
nanoseconds, and fall time is 15 nanoseconds.

Figure 6 showsdelay of the output pulse of approximately

10 nanoseconds relative to the input pulse.

Figure 4: Rise time and fall time (gate-pulsing)

Figure 3: Gate voltage waveform

Figure 5: Rise time and fall time (normal gate bias)

NIMHANS Convention Centre, Bangalore INDIA 3 of 5 15-19 December 2015

 10th International Radar Symposium India - 2015 (IRSI - 15)

Figure 8: Idq vs. temperature

Figure 6:

Frequency Input Output Noise Output Noise

(GHz) Noise Normal Gate Gate Pulsing
(dBm/Hz) Bias (dBm/Hz)
(dBm/Hz)
1.2 -126 -113 -147
1.3 -126 -113 -147
1.4 -126 -113 -148
Table 1: Amplifier noise power: normal gate bias vs. gate pulsing

Amplifier noise power was measured for normal gate

bias (Idq=200 mA) and compared to measurements taken Figure 9: Vgs vs. temperature (constant Idq)
with gate pulsing. Results are shown in table 1. An
improvement of about 34dB in noise rejection is achieved VICONCLUSION
with gate pulsing. An on-board bias sequencing and gate pulsing circuit has
been designed and demonstrated on a power amplifier using
IntegraGaN HEMT transistor IGN1214M500. With gate
VTEMPERATURE COMPENSATION pulsing, rise time of 100 nS and fall time of 16nS was
To achieve more consistent system performance over measured. Approximately 34dB improvement in noise
temperature, a temperature compensation circuit can be rejection was measured with the gate pulsing circuit. To
added to maintain a constant drain quiescent current. A improve system performance over temperature, a simple
typical implementation is shown in figure 7, wherethe temperature compensation circuit can be added to maintain
temperature-dependent base-emitter voltage of PNP constant bias for Integra GaN HEMT transistors with
transistor MMBT2907 is used to generate the compensating typically +0.6 mV/°C of compensation slope.
voltage. Figure 8 shows Idq vs. temperature and figure 9
shows gate voltage vs. temperature (for constant Idq) for
Integra GaN transistor IGN1214M500.Approximately+0.6 REFERENCES
mV/°Cgate voltage compensationis required for this [1] Integra datasheet IGN1214M500, www.integratech.com
transistor. [2] Linear Technology datasheet, www.linear.com/product/LT4256-1

Figure 7: Temperature Compensation circuit

NIMHANS Convention Centre, Bangalore INDIA 4 of 5 15-19 December 2015

 10th International Radar Symposium India - 2015 (IRSI - 15)

BIO DATA OF AUTHORS

VinodhThangam received his B.S. in Electronics and

Instrumentation from St. Peter’s Engineering College in
Chennai, India, and his M.S. in Electrical Engineering
from the University of Arkansas. He joined Integra
Technologies, Inc. in 2006 as an RF design engineer
and has been involved in developing high performance
RF power transistors and power amplifier modules for
radar and avionics systems.

Apet Barsegyan is Vice President and Chief Operating

Officer at Integra Technologies, Inc. A founding
employee of Integra in 1997,hecurrently serves as an
executive in technology development, sales, and
operations management for the company. He received
his Diploma Degree in Microwave Radiophysics from
Yerevan State University, Armenia, and his MSEE in
Microwave Engineering and Antennas from California
State University, Northridge.

Daniel Koyama has been an RF engineer at Integra

since 2013, supporting RF transistor and amplifier
pallet design. Previously he has worked at Boeing and
Raytheon, designing microwave circuits and modules
for space and airborne radar applications. He received
his B.S. inElectrical Engineering from UCLA.

NIMHANS Convention Centre, Bangalore INDIA 5 of 5 15-19 December 2015