Finite State Machine

Lesson 02
Chapter13
Dr. Mohammed Majid Al Khalidy

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Logic circuits: The classification of logic circuits is given below

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Q : Define the type of Sequential digital circuit (FSM) below
if it is synchronous or asynchronous digital circuit?

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 Finite State Machines
➢ Sequential circuits are also called Finite State Machines
(FSMs), because the functional behavior of these circuits
can be represented using a finite number of states (flip
flop outputs).
➢ Designing sequential circuits using the Finite State Machine
method is a powerful in Digital Logic Design.

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➢ Mealy machines are characterized by producing outputs
when a transition is taken.

➢ Moore machine, produces outputs when the machine is in a

state, rather than when a transition is taken. That is, the
output is defined by the current state rather than by the
current transition.

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Q : Define the type of FSM for each circuit below, is it
Moore or Mealy?

Figure. a

Figure. b
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Steps: Design of Sequential Circuits
In general to design a sequential circuits you have to go through
a certain steps:
Step 1:
Obtain a State reduction
state if necessary

diagram

Step 2: Use FF’s

State Choose type of excitation table
Obtain State Assignment flip-flops to complete the
Table table

Step 3: Obtain the FF

input equations
Derive state Use K-Maps
and the output
equations equations

Step 4:
Draw the
circuit
diagram
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Design a sequential circuit that detect 3 or more consecutive 1’s
in input.
001100011100011110101

• Draw the state

diagram from a
description

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Design a sequential circuit that detect 3 or more consecutive 1’s
in input.
001100011100011110101

• Draw the state

diagram from a
description

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▪ Obtain State Table

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▪ Obtain State Table

CS i/p NS o/p
A B X A+ B+ Y
0
1
0
1
0
1
0
1

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https://www.geogebra.org/scientific?lang=en

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A B
0 0
0 1
1 1 Moore depends on state only
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 CS i/p NS o/p
A B X A+ B+ Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1

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Example: Binary Adder
Use FSM to construct the state diagram and the state table for a
binary adder to add two numbers.
Design:
The input is two binary numbers, (xn…x1x0)2 and (yn…y1y0)2
At each step, we can compute (xi+yi) starting with (x0+y0).
– If (xi+yi)=0, we output 0.
– If (xi+yi)=1, we output 1.
– If (xi+yi)=2, we have a problem.
The problem is we need a carry bit.
In fact, our computation needs to know the carry bit at each step
(so we compute xi+yi+ci at each step), and be able to give it to
the next step.
We can take care of this by using states to represent the carry bit.
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We will use the following states
– State S0 occurs if the carry bit is 0
– State S1 occurs if the carry bit is 1
Since when we begin the computation, there is no carry, we
can use S0 as the start state,
So, how does which state we are in affect the output?
If we are in state S0 (we have a carry of 0)
– If (xi+yi)=0, we output 0, and stay in state S0
– If (xi+yi)=1, we output 1, and stay in state S0
– If (xi+yi)=2, we output 0, and go to state S1
If we are in state S1 (we have a carry of 1)
– If (xi+yi +1)=1, we output 1, and go to state S0
– If (xi+yi +1)=2, we output 0, and stay in state S1
– If (xi+yi +1)=3, we output 1, and stay in state S1

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▪ We will
choose Mealy
FSM

▪ The state
table is: Next State Output
Input Input
State 00 01 10 11 00 01 10 11
S0 S0 S0 S0 S1 0 1 1 0
S1 S0 S1 S1 S1 1 0 0 1
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Example: 2-bit gray-code counter with enable and ‘z’ output: 00, 01, 11,
10, 00, … The output ‘z’ is 1 when the present count is ‘10’. The count is the
same as the states encoded in binary.

First step: Draw the State Diagram and State Table. If we were to implement
the state machine in VHDL, this is the only step we need.

Second step: State Assignment. We assign unique flip flop states to our state
labels (S1, S2, S3, S4). Notice that this is arbitrary. However, we can save
resources if we assign each state to the count that we desire. Then, the output
‘count’ is just the flip flops’ outputs.

gray-code

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Third step: Excitation table. Here, we replace the state labels by the flip flop
states:

Fourth step: Excitation equations and minimization. 𝑄1(𝑡 + 1) and 𝑄0(𝑡 + 1) are
the next state of the flip flops, i.e. these signals are to be connected to the
inputs of the flip flops.

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Fifth step: Circuit implementation:

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FSM Vs. Counter
Example: 3-bit Binary Upcounter

Decide to implement with

Toggle Flipflops
What inputs must be
presented to the T FFs
to get them to change
to the desired state bit?

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K-maps for Toggle
Inputs:
C
CB
A 00 01 11 10
Resulting Logic Circuit:
0 1 1 1 1

1 1 1 1 1
+
B
TA = 1

C
CB
A 00 01 11 10 QA QB QC
TS Q T S Q T S Q
0 0 0 0 0
CLK Q CLK Q CLK Q
1 1 1 1 1 R R R
\Reset
B
Count
TB = A

C
CB
A 00 01 11 10

0 0 0 0 0

1 0 1 1 0

B
TC = A • B
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Timing Diagram:
100

\Reset

QC

QB

QA
Count

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More Count Sequence

Step 1: Derive the State Transition Diagram

Count sequence: 000, 010, 011, 101, 110

000 110

010 101

011

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Step 2: State Transition Table

Present Next
State State
C B A C + B + A+
0 0 0 0 1 0
0 0 1 X X X
0 1 0 0 1 1
0 1 1 1 0 1
1 0 0 X X X
1 0 1 1 1 0 Note the Don't Care conditions
1 1 0 0 0 0
1 1 1 X X X

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Step 3: K-Maps for Next State Functions

CB CB
A 00 01 11 10 A 00 01 11 10
0 0 0 0 X 0 1 1 0 X
1 X 1 X 1 1 X 0 X 1

C+ = A B+ = B + AC

CB
A 00 01 11 10
0 0 1 0 X

1 X 1 X 0
A+ = BC

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Step 4: Choose Flipflop Type for Implementation
Use Excitation Table to Remap Next State Functions

Present Toggle
Q Q+ T State Inputs

C B A TC TB TA
0 0 0
0 1 1 0 0 0 0 1 0
1 0 1 0 0 1 X X X
1 1 0 0 1 0 0 0 1
0 1 1 1 1 0
Toggle Excitation 1 0 0 X X X
Table 1 0 1 0 1 1
1 1 0 1 1 0
1 1 1 X X X
Remapped Next State
Functions

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Remapped K-Maps
CB CB
A 00 01 11 10 A 00 01 11 10
0 0 0 1 X 1 0 1 X
0
1 X 1 X 0 1 X 1 X 1
TC TB

CB
A 00 01 11 10
0 0 1 0 X

1 X 0 X 1
TA

TC = A C + A C = A  C
TB = A + B + C
TA = A B C + B C 36
 Resulting Logic:

Note:
T-FFs are
implemented
using JK-FFs
5 Gates
13 Input Literals +
Flipflop connections
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Timing Waveform:

100

Count
\Reset
0 0 0 0 1 1 0
C
B 0 0 1 1 0 1 0

A 0 0 0 1 1 0 0

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Solution:

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