Achieving a Common Chassis Worldwide

Y, C, and Synchronizing Signal Processing ICs

CXA2060AS
CXA2061S
Sony provides an extensive lineup of Y, C, and synchronizing signal ■ Reduced peripheral components
processing ICs (YCD). count
■ On-chip 1H delay line
These ICs take advantage of earlier TV ICs and in addition adopt new
■ On-chip SECAM decoder
technologies to incorporate even more peripheral components and ■ On-chip video switch
functionality in the same chip. ■ Three crystal oscillator pin sets
The CXA2060AS supports NTSC, PAL (including PAL-M and PAL-N), for PAL-M and PAL-N support
■ The CXA2060AS and CXA2061S
and SECAM, whereas the CXA2061S is a special-purpose NTSC YCD
are pin compatible.
chip.
Thus the pin compatible CXA2060AS and CXA2061S support all TV
broadcast regions and can achieve a common chassis worldwide.

Worldwide Horizontal Built-in 1H Delay Line and this single chip can completely support
Deployment SECAM Decoder all aspects of a color system.
The CXA2060AS is a single-chip Y,C, The CXA2060AS includes an on-chip Vertical Deployment
and synchronizing signal processing IC 1H delay line and an on-chip SECAM from the Low End to the
(YCD) that includes both a 1H delay decoder. While earlier products such as High End
line and a SECAM decoder on chip, and the CXA2000Q required an external 1H
the CXA2061S is a special-purpose delay line for PAL and an external Since these chips also provide Y and
NTSC YCD. While it goes without SECAM decoder for SECAM, by in- color difference signal input/output, a
saying that these chips are pin compat- cluding these circuits on chip, the feature block can be added. Since an fsc
ible, their I2C control registers are also CXA2060AS allows the same circuit to output is provided, a digital comb filter
identical, making them software provide the different types of signal pro- can be used. Thus these chips support
compatible as well. These two products cessing required by NTSC, PAL, and flexible deployment in higher grade
were designed to allow a common SECAM. This allows the same chassis television systems. The CXA2060AS
chassis to be used in all TV broadcast to be used for all reception areas, includ- and the CXA2061S not only aim for
regions. Figure 1 shows the block ing NTSC-only areas, PAL/SECAM extensive and complete television
diagram of the CXA2060AS. areas, and NTSC/PAL-M/PAL-N areas. functionality, but also promise the
achievement of a common chassis
Reduced Peripheral worldwide.
Components Count
Figure 2 presents a sample application
circuit. In addition to the components
used in this system, a video switch, a
V O I C E 1H delay line, and a SECAM decoder
would be required to construct the same
We are finally seeing the debut system using earlier products. The
of single-chip support for multi- CXA2060AS includes these devices on
format systems! We performed chip. (The CXA2061S only includes the
extensive field testing in devel- video switch on chip.) Since a high-per-
oping this IC, looking for signals formance sync separator system for the
that are difficult to receive in all input signal is fully included on chip,
corners of the world. As a result, no separate sync separator circuit input
this IC achieves the best signal is required. Additionally, the
SECAM discrimination perfor- sample-and-hold capacitor for the auto-
mance of the century! Sony’s cutoff circuit (AKB) is built in, and ca-
engineers strongly recommend pacitors and an oscillator element are
that you try this IC. not required for the H/V oscillator. Thus
 VMOUT/VPROT

G2IN (R-YOUT)
B2IN (B-YOUT)
R2IN (YOUT)
(FSC OUT)

Y CLAMP

YUVSW

YS2/YM
APCFIL

XTAL1

XTAL2
XTAL3

ERYIN
EBYIN
GND2

APED

EYIN

G1IN
R1IN

B1IN
VCC2

YSI
45 48 47 46 44 40 8 1 15 39 38 37 36 28 27 26 25 32 31 30 29

CVCO FSC OUT SW EYUV Clamp 42 ABLFIL

APC 4.433619MHz <FSC SW> PAL/NTSC PAL/NTSC NTSC, PAL/ YUV SW
3.579545MHz <Y SEL>
<HUE> 3.575611MHz Demod. SECAM YUVOUT 3 ABLIN
3.582056MHz <YUV OUT>
SECAM Killer Clamp ABL/Peak ABL AKB
<KILLER OFF> RGB 1/2
<ABL MODE>
<<IKR>>
21 IKIN
ACC Det. Color System Discriminator Color Amp. <ABL VTH>
<XTAL> <ID LEVEL> <COLOR>
Line BLK <C OFF>
<COL SYSTEM> Axis
<COL LOOP> <<KILLER ID OFF>> De- 1H

<R/G/B CUTOFF>
<AXIS PAL>

<R/G/B DRIVE>
<DYNAMIC C>
<NO COLOR> <<PAL>>

Dynamic Color
Chroma Delay Line 24 BOUT

Gamma Amp.
<AXIS NTSC>

Picture Amp.

<R/G/B ON>
emphasis

<PICTURE>
<RGB SEL>

Cutoff Cont.
Bright Cont.
<GAMMA>

<BRIGHT>
Drive Amp.

R/G/B BLK
Amp. <ID STOP> <<SECAM>>

YS2 SW
YSI SW

YM SW

<PON>
Clamp
<ID START> <<XTAL ID>>
DPIC
23 GOUT
<DPIC> Y/C Mix.
BPF Bell PLL SECAM 22 ROUT
PAL: 4.43MHz LIM VCO <AGING> RGB Clamp
Filter SECAM
NTSC: 3.58MHz
<BELL F0> Amp. CAL by
<C BPF> FM Demod. 4.43MHz
Clamp
Filter Alignment DC TRAN VPROT I2C bus
DAC <*1>
ACC Amp. (SECAM ACC Det.) CAL. by fxc <<VNG>> Decoder
<DC TRAN>
VM Amp. Status I/F
35 SDA
Chroma (OFF YS/YM) SW <*1>
<<*2>> 34 SCL
TV/C2IN 43 Chroma SW Trap DL Sharpness DL
PAL : 4.43MHz PAL/NTSC Sharpness Amp.
NTSC : 3.58MHz 300 ± 100ns
ATT <SHARPNESS> Wide Saw Func. VD SAW Func.
C1IN 2 SECAM : 4.2 + 4.43MHz SECAM
600 ± 200ns <SHP F0> <VON> <S CORRECTION>
14 VDN
<TRAP OFF> <Y DELAY> <PRE/OVER> <V SIZE> <V LINEARITY>
<ASPECT> 13 VDP
CVBS2/Y2IN 41 Y SW <SCROLL> <V POSITION> <EHT COMP>
Count Down Line Counter <UPPER VLIN>
V TIM Gen. VSAW Gen.
(50/60) <LOWER VLIN> EW Parabola Func.
CVBS1/Y1IN 4 Y V Sync Sep. <FIELD FREQ> <V UNDER SCAN> <H SIZE> <TRAPEZIUM>
<CD MODE> <<FIELD ID>> VTIM <V ZOOM> 11 EW
<VSS> <VTIM SEL> <V UNDER SCAN> <PIN AMP> <EW DC>
<INTERLACE> <<NO VSYNC>> <CORNERPIN>
COMB CIN 7 Monitor SW
H Sync Sep.
<HSS> AFC Phase Det.
COMB YIN 9 <AFC GAIN> H TIM Gen. <H POSITION>
<HMASK> HSAW Gen. <H BLK> HD Gen.
(Video SW) <FH HIGH> <AFC BOW>
<<RF LEVEL>> <LEFT HBLK> <AFC ANGLE> IREF REG
<VIDEO SEL> <<HLOCK>> <HOSC> <RIGHT HBLK> HPROT <HD W>
MON OUT 6 <S SEL> <<HCENT>> <<HNG>>

20 17 5 18 19 10 12 16 33
AFCFIL

SCP

VTIM

HP/HPROT

HD

GND1

IREF

REG

VCC1
*1: Including all control signals enclosed in single angle brackets ( <...> ).
*2: Including all status signals enclosed in double angle brackets ( <<...>> ).

■ Figure 1 CXA2060AS Block Diagram

1µ
18p PAL/SECAM/NTSC:
1 APED XTAL1 48
0.01µ 18p XTAL1: 4.43361875MHz
2 C1 IN XTAL2 47 XTAL2: 3.579545MHz
ABL Input 10k 18p
CVBS/S Input 1 3 ABL IN XTAL3 46 XTAL3: Open or FSC Output
0.1µ
4 CVBS1/Y1 IN
10k 0.22µ PAL-M/NTSC/PAL-N:
APC FIL 45
0.1µ 220p XTAL1: 3.57561149MHz
V Timing Output 5 VTIM VCC2 44 XTAL2: 3.579545MHz
0.1µ
Monitor Output 6 MON.OUT TV/C2 IN 43 XTAL3: 3.58205625MHz
1µ
CVBS from Tuner Input
7 COMB C IN ABL FIL 42 4.7µ
Glass 0.1µ CVBS/S 2 Input
1µ Note: In the CXA2061S, Pins 46
Comb 8 Y CLAMP CVBS2/Y2 IN 41
Filter 1µ and 48 are unused and must
9 COMB Y IN GND2 40
0.01µ be left open.
10 GND1 EB-Y IN 39
0.01µ
V Parabola Output 11 EW ER-Y IN 38
10k 0.01µ External YUV Input
12 I REF EY IN 37
13 VD+ YUV SW 36
V Drive Output
14 VD– SDA 35 2
I C
VM Output 15 VM OUT/VPROT SCL 34
10µ 47µ
V Protection Input 1k 16 REG VCC1 33 VCC + 9V
0.1µ
SCP Output 17 SCP R2 IN 32
Flyback Pulse Input 1µ 0.01µ
X-ray Protection Input 18 HP/PROTECT G2 IN 31 External RGB Input 2
0.01µ
H Drive Output 19 HD B2 IN 30 (for OSD/TEXT)
1µ 12k 0.01µ
2.2k 20 AFC FIL YS2/YM 29
4700p
21 IK IN R1 IN 28
Vth≈5V 0.01µ
22 R OUT G1 IN 27 External RGB Input 1
C Board 0.01µ
23 G OUT B1 IN 26 (for SCART)
0.01µ
24 B OUT YS1 25

■ Figure 2 CXA2060AS/CXA2061S Application Circuit Example