Chapter 2: Structural Modeling

Chapter 2: Structural Modeling

Prof. Soo-Ik Chae

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-1
 Chapter 2: Structural Modeling

Objectives

After completing this chapter, you will be able to:

 Describe what is the structural modeling
 Describe how to instantiate gate primitives
 Describe how to model a design in gate primitives
 Describe inertial and transport delays
 Describe how to specify delays in gates
 Describe hazards and their effects in gate networks

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-2
 Chapter 2: Structural Modeling

Structural Modeling

 Structural style: Modeled as a set of interconnected

components.
 Modules/UDPs
- Modules/UDPs may or may not be synthesized.
- A gate-level module is usually synthesizable.
 Gate primitives: There are 12 gate primitives.
- Gate primitives are synthesizable.
 Switch primitives: There are 16 switch primitives.
- Will not be covered
- They are usually used to model a new logic gate
circuit at switch level.
- They are not synthesizable, in general.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-3
 Chapter 2: Structural Modeling

Gate Primitives

 and/or gates
 have one scalar output and multiple scalar inputs
 are used to realize the basic logic operations
 include
and or xor nand nor xnor
 buf/not gates
 have one scalar input and one or multiple scalar outputs
 are used to realize the not operation,
 are used to buffer the output of an and/or gate,
 are used as controlled buffers
 include
buf not bufif0 notif0 bufif1 notif1
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 Chapter 2: Structural Modeling

and/nand Gates

i1 i1
i2 out i2 out

i2 i2
and nand
0 1 x z 0 1 x z
0 0 0 0 0 0 1 1 1 1
1 0 1 x x 1 1 0 x x
i1

i1
x 0 x x x x 1 x x x
z 0 x x x z 1 x x x

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-5
 Chapter 2: Structural Modeling

or/nor Gates

i1 i1
i2 out i2 out

i2 i2
or nor
0 1 x z 0 1 x z
0 0 1 x x 0 1 0 x x
1 1 1 1 1 1 0 0 0 0
i1

i1
x x 1 x x x x 0 x x
z x 1 x x z x 0 x x

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-6
 Chapter 2: Structural Modeling

xor/xnor Gates

i1 i1
i2 out i2 out

i2 i2
xor xnor
0 1 x z 0 1 x z
0 0 1 x x 0 1 0 x x
1 1 0 x x 1 0 1 x x
i1

i1
x x x x x x x x x x
z x x x x z x x x x

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-7
 Chapter 2: Structural Modeling

buf/not Gates

in out in out

in out in out

0 0 0 1
1 1 1 0
x x x x
z x z x

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-8
 Chapter 2: Structural Modeling

bufif0/notif0 Gates

in out in out
ctrl ctrl

ctrl ctrl
bufif0 notif0
0 1 x z 0 1 x z
0 0 z L L 0 1 z H H
1 1 z H H 1 0 z L L
in

in
x x z x x x x z x x
z x z x x z x z x x

Note that: L represents 0 or z and

H represents 1 or z.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-9
 Chapter 2: Structural Modeling

bufif1/notif1 Gates

in out in out
ctrl ctrl

ctrl ctrl
bufif1 notif1
0 1 x z 0 1 x z
0 z 0 L L 0 z 1 H H
1 z 1 H H 1 z 0 L L
in

in
x z x x x x z x x x
z z x x x z z x x x

Note that: L represents 0 or z and

H represents 1 or z.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-10
 Chapter 2: Structural Modeling

Instantiation of Basic Gates

 To instantiate and/or gates

gatename [instance_name](output, input1, input2, ..., inputn);
 instance_name is optional.

module basic_gates (x, y, z, f) ;

input x, y, z;
output f ;
wire a, b, c; // internal nets
// Structural modeling using basic gates. x b
nor g1 (b, x, y); y g1
g2 a g4 f
not g2 (a, x);
and g3 (c, a, z); g3 c
z
nor g4 (f, b, c);
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-11
 Chapter 2: Structural Modeling

Array of Instances

 Array instantiations may be a synthesizer dependent!

 Suggestion: you had better to check this feature before
using the synthesizer.

wire [3:0] out, in1, in2;

// basic array instantiations of nand gate.
nand n_gate[3:0] (out, in1, in2);

// this is equivalent to the following:

nand n_gate0 (out[0], in1[0], in2[0]);
nand n_gate1 (out[1], in1[1], in2[1]);
nand n_gate2 (out[2], in1[2], in2[2]);
nand n_gate3 (out[3], in1[3], in2[3]);

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-12
 Chapter 2: Structural Modeling

An Example --- A 1-Bit Full Adder

module full_adder_structural(x, y, c_in, s, c_out);
// I/O port declarations
input x, y, c_in;
output s, c_out;
wire s1, c1, c2, c3;
// Structural modeling of the 1-bit full adder.
xor xor_s1(s1, x, y); // compute sum.
xor xor_s2(s, s1, c_in);
and and_c1(c1, x, y); // compute carry out.
and and_c2(c2, x, c_in); x s1
and and_c3(c3, y, c_in); y
s
c_in
or or_cout(c_out, c1, c2, c3);
endmodule c1

c2
c_out

c3

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-13
 Chapter 2: Structural Modeling

An Example --- A 4-to-1 Multiplexer

i0 y0

i1 y1

out
i2 y2
module mux4_to_1_structural (i0, i1, i2, i3, s1, s0, out);
input i0, i1, i2, i3, s1, s0; i3 y3
output out;
wire s1n, s0n; // Internal wire declarations
wire y0, y1, y2, y3;
// Gate instantiations s1 s0
not (s1n, s1); // Create s1n and s0n signals.
not (s0n, s0);
and (y0, i0, s1n, s0n); // 3-input and gates instantiated
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3); // 4-input or gate instantiated
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-14
 Chapter 2: Structural Modeling

An Example --- A 9-Bit Parity Generator

x[0] c
x[1]
g
ep
x[2] d
x[3]
i

x[4] e
x[5]
h
op
x[6] f
x[7]

x[8]

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-15
 Chapter 2: Structural Modeling

An Example --- A 9-Bit Parity Generator

module parity_gen_9b_structural(x, ep, op);

// I/O port declarations
input [8:0] x;
output ep, op;
wire c, d, e, f, g, h, j;
xor xor_11(c, x[0], x[1]); // first level
xor xor_12(d, x[2], x[3]);
xor xor_13(e, x[4], x[5]);
xor xor_14(f, x[6], x[7]);
xor xor_21(g, c, d); // second level
xor xor_22(h, e, f);
xor xor_31(i, g, h); // third level
xor xor_ep(ep, i, x[8]); // fourth level
xnor xnor_op(op, i, x[8]);
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-16
 Chapter 2: Structural Modeling

Applications of Tristate Buffers

 To instantiate tristate buffers

buf_name[instance_name](output, input, control);
 The instance_name is optional.

// Data selector – 2-to-1 mux

module two_to_one_mux_tristate (x, y, s, f);
x input x, y, s;
output f;
f // internal declaration
y tri f;
// data selector body
bufif0 b1 (f, x, s); // enable if s = 0
S
bufif1 b2 (f, y, s); // enable if s = 1
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-17
 Chapter 2: Structural Modeling

Inertial and Transport Delay Models

 Inertial delay model

 The signal events do not persist long enough will not be
propagated to the output.
 It is used to model gate delays (RC delays).
 It is the default delay model for HDL (Verilog HDL and
VHDL).
 Transport delay model
 Any signal events will be propagated to the output.
 It is used to model net (i.e. wires) delays.
 The default delay of a net is zero.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-18
 Chapter 2: Structural Modeling

The Effects of Inertial Delays

x a x
f
y 2 4 6 8 10 12 14 16 18 20
y
b
2 4 6 8 10 12 14 16 18 20
b
wire a; 2 4 6 8 10 12 14 16 18 20
and #4 (b, x, y); // Inertial delay
a
and #4 (a, x, y);
not #1 (f, a); 2 4 6 8 10 12 14 16 18 20
f
Inertial delay 2 4 6 8 10 12 14 16 18 20

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-19
 Chapter 2: Structural Modeling

The Effects of Transport and Inertial Delays

x a
f
y
x

b 2 4 6 8 10 12 14 16 18 20
y
2 4 6 8 10 12 14 16 18 20
wire #2 a; // Transport delay b
and #4 (b, x, y); // Inertial delay 2 4 6 8 10 12 14 16 18 20
and #4 (a, x, y);
not #1 (f, a); a
2 4 6 8 10 12 14 16 18 20
Inertial delay f
Transport delay 2 4 6 8 10 12 14 16 18 20

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-20
 Chapter 2: Structural Modeling

Gate Delay Specifications

 Gate Delay Specifications

 Specify propagation delay only:
• gatename #(prop_delay) [instance_name](output, in_1, in_2,…);
 Specify both rise and fall times:
• gatename #(t_rise, t_fall) [instance_name](output, in_1, in_2,…);
 Specify rise, fall, and turn-off times:
• gatename #(t_rise, t_fall, t_off) [instance_name](output, in_1,
in_2,…);
• Turn-off time: transition to high-impedance value
• When a value changes to x, the delay is the smallest of the two or
three delays

Delay specifier: min:typ:max

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-21
 Chapter 2: Structural Modeling

Gate Delay Specifications

• gatename #(d1) [instance_name](output, in_1, in_2,…);

• gatename #(d1, d2) [instance_name](output, in_1, in_2,…);
• gatename #(d1, d2, d3) [instance_name](output, in_1, in_2,…);
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-22
 Chapter 2: Structural Modeling

Gate Delays Specifications

// Only specify one delay

and #(5) a1 (b, x, y);

// Only specify one delay using min:typ:max

not #(10:12:15) n1 (a, x);

// Specify two delays using min:typ:max

and #(10:12:15, 12:15:20) a2 (c, a, z);

// Specify three delays using min:typ:max

or #(10:12:15, 12:15:20, 12:13:16) o2 (f, b, c);

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-23
 Chapter 2: Structural Modeling

Hazards and Their Effects

 A hazard is an unwanted short-width output signal when the

inputs to a combinational circuit changes.
 These unwanted signals are generated when different paths
from input to output have different propagation delays.
 Static hazard
 Dynamic hazard

1 0 1 0 1 0 0 1 0 1 1 0 1 0

(a) static-1 hazard (b)static-0 hazard (c) dynamic hazard

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-24
 Chapter 2: Structural Modeling

A Static Hazard Example

x a
y
f
c
b
z

x
module hazard_static (x, y, z, f); t pd
input x, y, z; y t pd
output f;
x'
// internal declaration
wire a, b, c; // internal net
z t pd
// logic circuit body
and #5 a1 (a, x, y); t pd
not #5 n1 (c, x); a
t pd t pd
and #5 a2 (b, c, z); t pd t pd
b
or #5 o2 (f, b, a); t pd
t pd t pd
endmodule f
Hazard
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-25
 Chapter 2: Structural Modeling

A Dynamic Hazard Example

x b
3
d
2 a
c
y f
1 e
w
z

x=y=z=1

e
dynamic hazard
f

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 2-26