Scribd
Upload
60 views2 pages

Be Summer 2021

This document is an exam for a Computer Organization and Architecture course. It contains 5 questions assessing various topics related to computer organization: 1. Question 1 covers differences between hardwired and microprogrammed control units, register stack and memory stack contents, and evaluating arithmetic expressions using accumulator and stack computers. 2. Question 2 defines pipelining and asks about pipeline configurations, fetch and decode operations, and speedup from pipelining. 3. Question 3 lists characteristics of RISC processors, explains complement calculations, and elaborates on CPU-IOP communication and content addressable memory. 4. Question 4 explains memory hierarchy, assembler passes, and microprogram control unit address selection.

Uploaded by

Chandresh Kanzariya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
60 views2 pages

Be Summer 2021

This document is an exam for a Computer Organization and Architecture course. It contains 5 questions assessing various topics related to computer organization: 1. Question 1 covers differences between hardwired and microprogrammed control units, register stack and memory stack contents, and evaluating arithmetic expressions using accumulator and stack computers. 2. Question 2 defines pipelining and asks about pipeline configurations, fetch and decode operations, and speedup from pipelining. 3. Question 3 lists characteristics of RISC processors, explains complement calculations, and elaborates on CPU-IOP communication and content addressable memory. 4. Question 4 explains memory hierarchy, assembler passes, and microprogram control unit address selection.

Uploaded by

Chandresh Kanzariya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Seat No.: ________ Enrolment No.

___________

GUJARAT TECHNOLOGICAL UNIVERSITY


BE - SEMESTER–IV (NEW) EXAMINATION – SUMMER 2021
Subject Code:3140707 Date:06/09/2021
Subject Name:Computer Organization & Architecture
Time:02:30 PM TO 05:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

Marks
Q.1 (a) State differences between hardwired control unit and 03
microprogrammed control unit.
(b) Explain register stack and memory stack. 04
(c) Show the contents of registers E, AC, BR, QR and SC during the 07
process of multiplying 11111 with 10101.

Q.2 (a) Write down RTL statements for the fetch and decode operation 03
of basic computer.
(b) Define pipelining. For arithmetic operation (Ai *Bi + Ci) with a 04
stream of seven numbers (i=1 to 7). Specify a pipeline
configuration to carry out this task.
(c) Write a program to evaluate the arithmetic statement: 07
A*B+C*D+E
i. Using an accumulator type computer.
ii. Using a stack organized computer.
OR
(c) A non-pipeline system takes to process a task. The same task 07
can be processed in a six segment pipeline with a clock cycle of
10ns. Determine the speedup ratio of the pipeline for 100 tasks.
What is the maximum speed up that can be achieved?
Q.3 (a) List down six major characteristics of RISC processors. 03
(b) Explain how (r-1)’s complement is calculated. Calculate 9’s 04
complement of 546700.
(c) Elaborate CPU-IOP communication. 07
OR
Q.3 (a) List and explain major instruction pipeline conflicts. 03
(b) Define RTL. Give block diagram and timing diagram of transfer 04
of R1 to R2 when P=1.
(c) Elaborate content addressable memory (CAM). 07
Q.4 (a) Explain memory hierarchy in brief. 03
(b) Draw and explain flowchart for first pass of assembler. 04
(c) Explain using a flowchart how address of control memory is 07
selected in microprogrammed control unit.
OR
Q.4 (a) Briefly explain DMA. 03
(b) Write assembly level program to subtract two given numbers. 04
(c) Write the symbolic microprogram routine for the BSA 07
instruction. Use the microinstruction format of basic
microprogrammed control unit.

1
Q.5 (a) How many AND gates and Adders will be required to multiply a 03
5 bit number with a 3 bit number? Also say size of adder (bits).
How many bits will be there in the result?
(b) What do you mean by cache memory? Justify the need of cache 04
memory in computer systems.
(c) Discuss multistage switching network with neat diagrams. 07
OR
Q.5 (a) Explain the non-restoring methods for dividing two numbers. 03
(b) Discuss source-initiated transfer using handshaking in 04
asynchronous data transfer.
(c) Elaborate cache coherence problem with its solutions. 07

*******************

You might also like