Exam

Name___________________________________

TRUE/FALSE. Write 'T' if the statement is true and 'F' if the statement is false.
1) A LOW input to an inverter produces a HIGH output. 1) _______

2) The OR gate performs a function similar to series-connected switches. 2) _______

3) The output of an AND gate is HIGH only when all inputs are HIGH. 3) _______

4) The output of an AND gate is LOW only when all inputs are LOW. 4) _______

5) When the inputs to a 3-input AND gate are 001, the output is HIGH. 5) _______

6) When the inputs to a 3-input OR gate are 001, the output is HIGH. 6) _______

7) The output of an OR gate is HIGH when at least one input is HIGH. 7) _______

8) The output of an OR gate is LOW when at least one input is LOW. 8) _______

9) The output of a NAND gate is HIGH only when one or more inputs are HIGH. 9) _______

10) The output of a NAND gate is LOW only when all inputs are HIGH. 10) ______

11) The output of a NOR gate is LOW only when all inputs are HIGH. 11) ______

12) The output of a NOR gate is HIGH only when all inputs are HIGH. 12) ______

13) When the inputs to a 3-input NAND gate are 001, the output is HIGH. 13) ______

14) When the inputs to a 3-input NOR gate are 001, the output is LOW. 14) ______

15) The output of a 2-input Exclusive-OR gate is HIGH when the inputs are equal, or identical. 15) ______

16) The output of a 2-input Exclusive-NOR gate is HIGH when the inputs are equal, or identical. 16) ______

17) A circle, or "bubble," on a distinctive-shape logic symbol indicates a logic inversion. 17) ______

MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
18) The symbol below represents a(n) ________. 18) ______

A) NAND gate B) AND gate

C) OR gate D) none of the above

19) The symbol below represents a(n) ________. 19) ______

A) NAND gate B) AND gate

 C) OR gate D) none of the above

20) The symbol below represents a(n) ________. 20) ______

A) OR gate B) AND gate

C) Inverter D) none of the above

21) The symbol below represents a(n) ________. 21) ______

A) OR gate B) AND gate

C) Inverter D) none of the above

22) The symbol below represents a(n) ________. 22) ______

A) AND gate B) Inverter C) OR gate D) NAND gate

23) The symbol below represents a(n) ________. 23) ______

A) inverter B) NOR gate

C) NAND gate D) Exclusive-NOR gate

24) The symbol below represents a(n) ________. 24) ______

A) NOR gate B) NAND gate

C) inverter D) Exclusive-NOR gate

25) The symbol below represents a(n) ________. 25) ______

A) NAND gate B) NOR gate C) AND gate D) OR gate

26) The symbol below represents a(n) ________. 26) ______

 A) AND gate B) NAND gate
C) OR gate D) Exclusive-OR gate

27) The symbol below represents a(n) ________. 27) ______

A) NAND gate B) NOR gate

C) Exclusive-NOR gate D) Exclusive-OR gate

28) The symbol below represents a(n) ________. 28) ______

A) OR gate B) AND gate C) Inverter D) NAND gate

29) The truth table below describes a(n) ________. 29) ______

A) AND gate B) OR gate C) NOR gate D) NAND gate

30) The truth table below describes a(n) ________. 30) ______

A) AND gate B) OR gate C) NOR gate D) NAND gate

31) The truth table below describes a(n) ________. 31) ______

A) AND gate B) OR gate C) NOR gate D) NAND gate

32) The truth table below describes a(n) ________. 32) ______

A) AND gate B) OR gate C) NOR gate D) NAND gate

33) Which of the truth tables below describes the Exclusive-NOR gate? 33) ______

A) (A) B) (B) C) (C) D) (D)

34) The timing diagram below is correct for a 2-input ________ gate. 34) ______

A) AND B) OR C) NAND D) Exclusive-OR

35) The timing diagram below is correct for a 2-input ________ gate. 35) ______

A) AND B) OR C) NAND D) Exclusive-OR

36) The timing diagram below is correct for a 2-input ________ gate. 36) ______

A) AND B) OR C) NAND D) Exclusive-OR

37) The timing diagram below is correct for a 2-input ________ gate. 37) ______

A) OR B) NOR
C) Exclusive-NOR D) AND

38) The timing diagram below is correct for a 2-input ________ gate.
 38) ___
___

A) Exclusive-NOR B) Exclusive-OR
C) NAND D) AND

39) The timing diagram below is correct for a 2-input ________ gate. 39) ______

A) AND B) NAND
C) Exclusive-OR D) Exclusive-NOR

40) IC's with a ________ prefix have a broad operating temperature range and are generally used by 40) ______
the military.
A) TTL B) 54 C) 74 D) 2N

41) The ________ series of IC's are pin, function and voltage-level compatible with the 74 series IC's. 41) ______
A) HCT B) 2N C) CMOS D) ALS

42) A logic gate draws 10mA when its output is HIGH and 20mA when its output is LOW. When 42) ______
operating from a 12V supply with a 10% duty cycle the average power dissipation will be
________.
A) 228mW B) 360mW C) 324mW D) 180mW

43) The fanout for standard bipolar logic devices is ________. 43) ______
A) 2 B) 5 C) 10 D) 1

44) The term "hex inverter" refers to ________. 44) ______

A) an inverter that has a history of failure B) six inverters in a single package
C) a six-input symbolic logic device D) an inverter which has six inputs

45) Which type of gate can be used to add two bits? 45) ______
A) XNAND B) NOR C) XOR D) NAND

46) An AND gate is checked for operation and the following readings are taken on the gate: input A 46) ______
= 0.2 V, input B = 4.5 V, input C = 0.4 V, output = 4.9 V. What might be wrong with the gate?
A) Input C is too high. B) The output is too low: it should be 5 V.
C) Nothing is wrong with the gate. D) The output is stuck high; the chip is bad.

47) When an open occurs on the input to a bipolar logic device, the output will ________. 47) ______
A) react to the open input as if it were a HIGH input
B) go HIGH, since full voltage appears across an open
C) go LOW, because there is no current in an open circuit
 D) still be good, if only the good inputs are used

48) When an open occurs on the input of a CMOS gate, the output will ________. 48) ______
A) go HIGH, since full voltage appears across an open
B) be treated as if the open input were a HIGH
C) go LOW, because there is no current in an open circuit
D) be unpredictable; it may go HIGH or LOW

49) What technology allows a GAL to be reprogrammed again and again? 49) ______
A) CMOS B) NMOS C) TTL D) E2CMOS

50) What programmable arrays are in PLD's? 50) ______

A) NOR arrays B) OR arrays and AND arrays
C) AND arrays only D) OR arrays only

51) Which of the following is not a type of SPLD? 51) ______

A) PLA B) RAM C) PROM D) GAL

52) The difference between a PLA and a PAL is ________. 52) ______
A) the PAL has a programmable OR plane and a programmable AND plane while the PLA
only has a programmable AND plane
B) the PLA has a programmable OR plane and a programmable AND plane while the PAL
only has a programmable AND plane
C) the PAL has more possible product terms than the PLA
D) PALs and PLAs are the same thing.

53) HDL stands for ________. 53) ______

A) hardwired digital logic B) hardware description language
C) hardwire descriptive logic D) none of the above

54) HDLs differ from ________ in that they include ways of describing propagation times and other 54) ______
logic characteristics.
A) software digital logic B) software programming languages
C) software description languages D) none of the above

55) The ________ in a VHDL program defines the logic element and its inputs/outputs or ports. 55) ______
A) hardware B) architecture C) entity D) source

56) The ________ in a VHDL program describes its logic operation. 56) ______
A) entity B) architecture C) source D) hardware

57) A ________ IC comes with logic functions that are not programmed in and cannot be altered. 57) ______
A) fixed-function B) VHDL C) HDL D) microcontroller
 1) TRUE
2) FALSE
3) TRUE
4) FALSE
5) FALSE
6) TRUE
7) TRUE
8) FALSE
9) FALSE
10) TRUE
11) FALSE
12) FALSE
13) TRUE
14) TRUE
15) FALSE
16) TRUE
17) TRUE
18) B
19) B
20) A
21) A
22) D
23) B
24) B
25) B
26) D
27) C
28) C
29) A
30) B
31) D
32) C
33) A
34) A
35) C
36) B
37) B
38) B
39) D
40) B
41) A
42) A
43) C
44) B
45) C
46) D
47) A
48) D
49) D
50) B
51) B
52) B
53) B
54) C
55) C
56) B
57) A