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Lab 4

The summary provides the key information from the document in 3 sentences: Virtual memory pages 0, 2, 3, and 6 are mapped to physical frames 1, 0, 3, and 2 respectively based on the valid bits in the page table entries. The document then provides examples of calculating the number of virtual memory pages, physical memory page frames, and page table entries for given virtual and physical memory sizes and page size. It also works through examples of virtual to physical address translations using the given page table entries.
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0% found this document useful (0 votes)
15K views

Lab 4

The summary provides the key information from the document in 3 sentences: Virtual memory pages 0, 2, 3, and 6 are mapped to physical frames 1, 0, 3, and 2 respectively based on the valid bits in the page table entries. The document then provides examples of calculating the number of virtual memory pages, physical memory page frames, and page table entries for given virtual and physical memory sizes and page size. It also works through examples of virtual to physical address translations using the given page table entries.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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CSIT212

LAB 4

1. Suppose a process page table contains the entries shown below. Using the format shown in
Figure 6.17a, indicate where the process pages are located in memory.

Virtual page Frame Valid bit

0 1 1
1 * 0
2 0 1
3 3 1
4 * 0
5 * 0
6 2 1
7 * 0

0
1 0
2
1
3
4 2
5 3
6
7
 The virtual page 0 is mapped to frame 1 in the physical memory, as illustrated in the
preceding picture, since the valid bit is 1.
 Because the valid bit for virtual page 1 is zero, the process's page is now not in
physical memory.

 The page is mapped to frame 0 in the physical memory since the valid bit for virtual
page 2 is 1.

 The page is mapped to frame 3 in physical memory because the valid bit
corresponds to virtual page 3.
 The pages of the processes are now not in physical memory since the valid bits
correspond to virtual pages 4 and 5.
 The page is mapped to frame 2 in the physical memory since the valid bit for virtual
page 6 is 1.
 Because the valid bit for virtual page 7 is zero, the process's page is now not in
physical memory

2. Suppose we have 210 bytes of virtual memory and 28 bytes of physical main memory.
Suppose the page size is 24 bytes.
a) How many pages are there in virtual memory?
Size of virtual memory / size of page = the number of pages in virtual memory
= 210 / 24 = 26
b) How many page frames are there in main memory?
Size of physical memory / Size of page = Number of pages in physical memory
= 28 / 24
= 2(8-4)= 24 page frames
c) How many entries are in the page table for a process that uses all of virtual memory?
Page offset = 4 bits
Number of virtual memory needed = 10 bits
10-4 = 6
26 entries

3. A system implements a paged virtual address space for each process using a one-level page
table. The maximum size of virtual address space is 16MB. The page table for the running
process includes the following valid entries (the → notation indicates that a virtual page maps to
the given page frame, that is, it is located in that frame):

Virtual page 2 → page frame 4 Virtual page 4 → page frame 9


Virtual page 1 → page frame 2 Virtual page 3 → page frame 16
Virtual page 0 → page frame 1

The page size is 1024 bytes and the maximum physical memory size of the machine is 2MB.
a) How many bits are required for each virtual address?
virtual address space=16 MB (220 . 24)
There are 24 address lines and 24 bits in use.
b) How many bits are required for each physical address?
virtual address space=2 MB (220. 21)
There are 21 address lines and 21 bits in use.
c) What is the maximum number of entries in a page table?
maximum number of entries in a page table = (virtual m space /page size)
                                    =224/210      
 = 214 entries

d) To which physical address will the virtual address 0x5F4 translate?


page 0 contains 0-1023 addresses
      page 1 contains 1024-2047 addresses
     =>phy addr 1524 is in frame1(offset=(1524-1024)=500 )
        page 1 maps toframe 2
     => corresponding physical addr =2548 (2048+500)

e) Which virtual address will translate to physical address 0x400?


 physical addr 1024 is in frame 1(offset=0 ;starting addr inframe 1)
   since virtual page 0 maps to frame 1
     corresponding virtual address =0

4. Under What circumstances is it desirable to collect groups of processes and programs into
subsystems running on a large computer? What advantages would there be to creating logical
partitions on this system?
 If the processes share a set of resources, it may be beneficial to organize them
together as a subsystem.
 It's a good idea to group processes and programs into subsystems because if a certain
set of processes is used to test the system and anything strange happens, such as a
system crash, only the subsystem in which the processes are executing would be
affected.
 If a certain set of individuals is granted restricted access to limited resources for a
short period of time, it may be useful to organize the user processes as a subsystem as
well.
Advantages include:

• Subsystems cannot offer low-level segmentation of the machine and its resources. This is
accomplished by adding LPARs to a subsystem.
• Each subsystem creates a logically different environment that can be handled and
adjusted independently.
5. Discuss the following questions relative to compilers:
a. Which phase a compiler would give you syntax error?
The exical analyzer phase complains about variables that aren't specified.

A lexical analyzer is a computer program that divides a string of letters into lexemes
and generates a list of tokens. These tokens include language-specific reserve words,
literals, operators, and programmer-defined variables. A symbol table for variables
and procedure names is built in this step. It raises an error if any of the variables are
undefined.
b. Which phase complains about undefined variables?
Undefined variables are a problem at the lexical analyzer phase.
A lexical analyzer is a computer program that divides a string of letters into lexemes
and generates a list of tokens. These tokens include language-specific reserve words,
literals, operators, and programmer-defined variables. A symbol table for variables
and procedure names is built in this step. It raises an error if any of the variables are
undefined.
c. If you try to add an integer to character string, which compiler would emit the error
message?
When a programmer tries to add an integer to a character string, the semantic
analyzer phase generates an error message.

A syntax tree is supplied to a semantic analyzer as input from the syntactic analysis
phase.
This step examines the program for semantic flaws and type checking. When a type
mismatch occurs, this phase displays an error message.

6. Java is called an interpreted language, yet Java is a compiled language that produces a binary
output stream. Explain how this language can be both compiled and interpreted.

( complete the answer from the slides)


Java is a compiled and interpretable programming language.

Java is a high-level object-oriented language that may be compiled or interpreted.


The steps for running a Java program are as follows:

• First, the java source file is compiled, resulting in a class file with byte code.
• This is not an executable byte code.
• The Java virtual machine loads this byte code (class file) (JVM).
• It checks the class file format in the Java virtual machine. • After that, the interpreter
analyzes the class files and generates the target machine code.
• When the target machine code is created, the execution begins.

7. Answer the following with respect to database processing:


a. What is a race condition? Give an example.
The ultimate state of the database in a transaction is determined not by the accuracy
of the updates, but by which transaction finishes last, which is known as a race
situation.Network system (where two users on separate servers or locations share the
same network) and fle system are examples of race conditions.
b. How can race conditions be prevented?
Transaction managers enforce the atomicity and isolation properties, which avoid race
situations.
c. What are the risks in race condition prevention?
Risks in race condition prevention are
It's difficult to keep data synchronized when two transactions are using the same
resources, and the user has no control over the sequence in which transactions are
executed.

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