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Verification Test Question Paper - Maven

1. This document contains a verification test with 4 multiple choice questions in Part A and 4 long answer questions in Part B related to UVM concepts such as transactions, sequences, virtual sequences, coverage, assertions, and UVM component connections. 2. Part A involves writing code to copy a transaction object, generating read and write addresses in a virtual sequence, calculating coverage from a covergroup, and writing an assertion. 3. Part B involves identifying UVM component ports and connections, defining a transaction with constraints, generating transactions without extending the transaction class, and drawing a UVM TB architecture with interface for a FIFO.

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aman nigam
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2K views

Verification Test Question Paper - Maven

1. This document contains a verification test with 4 multiple choice questions in Part A and 4 long answer questions in Part B related to UVM concepts such as transactions, sequences, virtual sequences, coverage, assertions, and UVM component connections. 2. Part A involves writing code to copy a transaction object, generating read and write addresses in a virtual sequence, calculating coverage from a covergroup, and writing an assertion. 3. Part B involves identifying UVM component ports and connections, defining a transaction with constraints, generating transactions without extending the transaction class, and drawing a UVM TB architecture with interface for a FIFO.

Uploaded by

aman nigam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Verification Test

50 Marks

PART -A
20 Marks
1. Complete the following code based on the instructions given in the comments
-- 5 Marks

Class transaction;
rand bit[2:0] addr;
rand bit[3:0] data;

// Implement user defined copy method

endclass

transaction t1, t2;


initial
begin
t1 = new();
assert(t1.randomize());
//copy the object t1 to t2 using user defined copy method
end

2. Write code to generate both waddr and raddr values in between 10 to 20 for the below transaction
class and start both the sequences inside virtual sequence by showing all connections between
sub sequencer & virtual sequencer. (Note: both write and read drivers should drive the data at the
same time) -- 6 Marks

class write_xtn extends uvm_sequence_item;


`uvm_object_utils(write_xtn)
function new(string name);
super.new(name);
endfunction
rand int waddr;
endclass

class read_xtn extends uvm_sequence_item;


`uvm_object_utils(read_xtn)
function new(string name);
super.new(name);
endfunction
rand int raddr;
endclass
3. In the below code, how many bins will be created? Calculate the coverage?
-- 4 Marks
module test;
class example;
bit [0:2] y;
bit z;
covergroup cg;
CP_Y : coverpoint y
{ option.auto_bin_max = 4 ; }
CP_Z : coverpoint z;
Y X Z : cross CP_Y, CP_Z;
endgroup
function new();
cg=new();
endfunction
endclass

example e_h=new();
initial
begin
for( int i=0; i< 5; i++)
begin
e_h.y= i;
e_h.z= ~e_h.z;
e_h. cg.sample;
end
end

4. Write an assertion for the following. -- 5 Marks


Once enable goes high in the next cycle, one pulse on signal “a” (whose width is equal to
one clock cycle) should be generated and from there it should be generated for every ten
clock cycles.
PART -B
30 Marks
1. For the following UVM components, identify the proper ports with respect to following configurations
and write a snippet of code to make connections in the concerned connect phases. Data flow is from
producer to consumer. -- 8 Marks
a. In-between DIV1 & DIV2, DIV1 is initiator & DIV2 is target
b. In-between DIV2 & DIV3, DIV2 & DIV3 are initiators

2. Define transaction for the minute counter with valid constraints.(When one_min is high the
inputs get loaded & when low the counter should start counting and counter works in 12
hour format)
-- 6 Marks
3. Generate the transactions without extending the Transaction class and creating new objects.
-- 6 Marks
class Transaction;
rand bit [31:0] addr, data;
constraint c1 {addr inside{[0:100],[1000:2000]};}
endclass
transaction t;
initial
begin
t = new();

//Generate the transaction with address range [50-100], [1000-1500] and data < 10
//Sending transaction to DUT
driveBus(t);

//Generate the transaction by forcing addr as 2000 and data > 10


//Sending transaction to DUT
driveBus(t);

end

4. Draw the UVM TB architecture to verify FIFO of depth 16 bytes, showing the connections
between the components properly and also write the interface block for the same.
-- 10 Marks

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