1

Final Revision (CSE111s)

TABLE OF CONTENTS:
➢ Number System – 1
➢ Number System – 2
➢ Arithmetic Operation
➢ 1’s, 2’s, 9’s & 10’s Complements
➢ Binary Coded Decimal (BCD)
➢ Boolean Logic Operations
➢ Sum of Products
➢ Logic Gates
➢ Half Adder & Full Adder
➢ Combinational Circuits
➢ Multiplexers (Data Selectors)
➢ Code Converters
➢ Flip Flops
➢ Combinational Circuits VS sequential Circuits
➢ Counters
➢ Registers
➢ Shift Registers
➢ Introduction of Memory Devices
➢ Read Only Memory (ROM)
➢ sequential circuits
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Number System – 1
1) Any signed negative binary number is recognized by its ________
a) MSB
b) LSB
c) Byte
d) Nibble

Answer: a

2) The representation of octal number (532.2)8 in decimal is ________

a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10

Answer: a

3) The decimal equivalent of the binary number (1011.011)2 is ________

a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10

Answer: a

4) The decimal equivalent of the octal number (645)8 is ______

a) (450)10
b) (451)10
c) (421)10
d) (501)10

Answer: c

5) The largest two-digit hexadecimal number is ________

a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16

Answer: c
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6) Representation of hexadecimal number (6DE) H in decimal:

a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160

Answer: a

Number System – 2
1) The given hexadecimal number (1E.53)16 is equivalent to ____________
a) (35.684)8
b) (36.246)8
c) (34.340)8
d) (35.599)8

Answer: b

2) The octal number (651.124)8 is equivalent to ______

a) (1A9.2A)16
b) (1B0.10)16
c) (1A8.A3)16
d) (1B0.B0)16

Answer: a

3) The octal equivalent of the decimal number (417)10 is _____

a) (641)8
b) (619)8
c) (640)8
d) (598)8

Answer: a

4) Convert the hexadecimal number (1E2)16 to decimal.

a) 480
b) 483
c) 482
d) 484

Answer: c
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5) (170)10 is equivalent to ____________

a) (FD)16
b) (DF)16
c) (AA)16
d) (AF)16

Answer: c

6) Convert (214)8 into decimal.

a) (140)10
b) (141)10
c) (142)10
d) (130)10

Answer: a

7) Convert (0.345)10 into an octal number.

a) (0.16050)8
b) (0.26050)8
c) (0.19450)8
d) (0.24040)8

Answer: b

8) Convert the binary number (01011.1011)2 into decimal.

a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.7893)10

Answer: a

9) Octal to binary conversion: (24)8 =?

a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2

Answer: b
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10) Convert binary to octal: (110110001010)2 =?

a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8

Answer: b

Arithmetic Operation
1) What is the addition of the binary numbers 11011011010 and 010100101?
a) 0111001000
b) 1100110110
c) 11101111111
d) 10011010011

Answer: c

2) Perform binary addition: 101101 + 011011 =?

a) 011010
b) 1010100
c) 101110
d) 1001000

Answer: d

3) Perform binary subtraction: 101111 – 010101 =?

a) 100100
b) 010101
c) 011010
d) 011001

Answer: c

4) Binary subtraction of 100101 – 011110 is?

a) 000111
b) 111000
c) 010101
d) 101010

Answer: a
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5) Binary subtraction of 101101 – 001011 =?

a) 100010
b) 010110
c) 110101
d) 101100

Answer: a

1’s, 2’s, 9’s & 10’s Complements

1) 1’s complement of 1011101 is ____________

a) 0101110
b) 1001101
c) 0100010
d) 1100101

Answer: c

2) 2’s complement of 11001011 is ____________

a) 01010111
b) 11010100
c) 00110101
d) 11100010

Answer: c

3) On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________

a) 01001
b) 11010
c) 10101
d) 10100

Answer: d
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4) On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ____________

a) 0111001
b) 1100101
c) 0110110
d) 1000011

Answer: d

5) On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________

a) 1101100
b) 011101
c) 11010101
d) 11010111

Answer: b

6) On addition of 28 and 18 using 2’s complement, we get ____________

a) 00101110
b) 0101110
c) 00101111
d) 1001111

Answer: b

7) On addition of +38 and -20 using 2’s complement, we get ____________

a) 11110001
b) 100001110
c) 010010
d) 110101011

Answer: c

8) On addition of -46 and +28 using 2’s complement, we get ____________

a) -10010
b) -00101
c) 01011
d) 0100101

Answer: a
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9) On addition of -33 and -40 using 2’s complement, we get ____________

a) 1001110
b) -110101
c) 0110001
d) -1001001

Answer: d

10) On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1

Answer: d

11) The addition of +19 and +43 results as _________ in 2’s complement system.
a) 11001010
b) 101011010
c) 00101010
d) 0111110

Answer: d

12) 1’s complement can be easily obtained by using _________

a) Comparator
b) Inverter
c) Adder
d) Subtractor

Answer: b

13) The 1’s complements require _________

a) One operation
b) Two operations
c) Three operations
d) Combined Operations

Answer: a
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14) For arithmetic operations only _________

a) 1’s complement is used
b) 2’s complement
c) 10’s complement
d) 9’s complement

Answer: b

Binary Coded Decimal (BCD)

1) Binary coded decimal is a combination of __________

a) Two binary digits
b) Three binary digits
c) Four binary digits
d) Five binary digits

Answer: c

2) The decimal number 10 is represented in its BCD form as __________

a) 10100000
b) 01010111
c) 00010000
d) 00101011

Answer: c

3) Add the two BCD numbers: 1001 + 0100 =?

a) 10101111
b) 01010000
c) 00010011
d) 00101011

Answer: c

Explanation: Firstly, Add the 1001 and 0100. We get 1101 as output but it’s not in
BCD form. So, we add 0110 (i.e., 6) with 1101. As a result, we get 10011 and it’s BCD
form is 0001 0011.
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4) A three-digit decimal number requires ________ for representation in the

conventional BCD format.
a) 3 bits
b) 6 bits
c) 12 bits
d) 24 bits

Answer: c

5) The excess-3 code for 597 is given by __________

a) 100011001010
b) 100010100111
c) 010110010111
d) 010110101101

Answer: a

Explanation: The addition of ‘3’ to each digit yields the three new digits ‘8’, ’12’
and ’10’. Hence, the corresponding four-bit binary equivalents are 100011001010,
in accordance to 8421 format.

Boolean Logic Operations

1) The expression for Absorption law is given by _________
a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A

Answer: a

2) Complement of the expression A’B + CD’ is _________

a) (A’ + B) (C’ + D)
b) (A + B’) (C’ + D)
c) (A’ + B) (C’ + D)
d) (A + B’) (C + D’)

Answer: b
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3) DeMorgan’s theorem states that _________

a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B

Answer: a

4) The involution of A is equal to _________

a) A
b) A’
c) 1
d) 0

Answer: a

Explanation: The involution of A means double inversion of A (i.e., A”)

5) A (A + B) =?
a) AB
b) 1
c) (1 + AB)
d) A

Answer: d

6) (A + B) (A’ * B’) =?
a) 1
b) 0
c) AB
d) AB’

Answer: b

7) Simplify Y = AB’ + (A’ + B) C.

a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A

Answer: b
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8) The Boolean function A + BC is a reduced form of ____________

a) AB + BC
b) (A + B) (A + C)
c) A’B + AB’C
d) (A + C) B

Answer: b

9) According to boolean law: A + 1 = ?

a) 1
b) A
c) 0
d) A’

Answer: a

Sum of Products
1) The logical sum of two or more logical product terms is called __________
a) SOP
b) POS
c) OR operation
d) NAND operation

Answer: a

2) The canonical sum of product form of the function y(A,B) = A + B is __________

a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’

Answer: b

3) There are _____________ Minterms for 3 variables (a, b, c).

a) 0
b) 2
c) 8
d) 1

Answer: c
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4) _____________ expressions can be implemented using either (1) 2-level AND-OR logic
circuits or (2) 2-level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS

Answer: c

5) The expression Y=AB+BC+AC shows the _________ operation.

a) EX-OR
b) SOP
c) POS
d) NOR

Answer: b

Logic Gates
1) The output of a logic gate is 1 when all the input are at logic 0 as shown below:

INPUT OUTPUT

A B C

0 0 1

0 1 0

1 0 0

1 1 0

INPUT OUTPUT

A B C

0 0 1

0 1 0

1 0 0
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1 1 1

The gate is either _________

a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR

Answer: d

Hint: EX-OR = XNOR

2) The code where all successive numbers differ from their preceding number by
single bit is __________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray

Answer: d

3) The following switching functions are to be implemented using a decoder:

f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line

Answer: c

4) How many AND gates are required to realize Y = CD + EF + G?

a) 4
b) 5
c) 3
d) 2

Answer: d
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5) The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11

Answer: a

6) A universal logic gate is one which can be used to generate any logic function.
Which of the following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND

Answer: d

7) A full adder logic circuit will have __________

a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs

Answer: d

8) Which of the following are known as universal gates?

a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR

Answer: a

9) The gates required to build a half adder are __________

a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate

Answer: c
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Hint: EX-OR gate = XOR gate

10) Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates

Answer: c

Explanation: Expression for XOR is: A.(B’)+(A’).B

So in the above expression, the following logic gates are used: AND, OR, NOT.
Thus, 2 AND gates with two-inputs and 1 OR gate with two-inputs will be required
for constructing a XOR gate.

11) How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2

Answer: a

12) How many two input AND gates and two input OR gates are required to realize
Y = BD + CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3

Answer: a

13) If we use an AND gate to inhibit a signal from passing one of the inputs must be
___________
a) LOW
b) HIGH
c) Inverted
d) Floating

Answer: a
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14) The AND function can be used to ___________ and the OR function can be used to
_____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert

Answer: a

Half Adder & Full Adder

1) In parts of the processor, adders are used to calculate ____________

a) Addresses
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned

Answer: d
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2) Total number of inputs in a half adder is __________

a) 2
b) 3
c) 4
d) 1

Answer: a

3) In which operation carry is obtained?

a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction

Answer: b

4) If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B

Answer: c

5) If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B

Answer: a

6) Half-adders have a major limitation in that they cannot __________

a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages

Answer: c
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7) The difference between half adder and full adder is __________

a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned

Answer: c

8) If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C

Answer: c

9) If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C

Answer: a

10) How many AND, OR and EX-OR gates are required for the configuration of full
adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1

Answer: b

11) Half subtractor is used to perform subtraction of ___________

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
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Answer: a

12) Full subtractor is used to perform subtraction of ___________

a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits

Answer: b

Combinational Circuits
1) Which of the circuits in figure (a to d) is the sum-of-products implementation of
figure (e)?
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a) a
b) b
c) c
d) d

Answer: d

2) Which of the following logic expressions represents the logic diagram shown?

a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB

Answer: d

3) What type of logic circuit is represented by the figure shown below?

a) XOR
b) XNOR
c) AND
d) XAND

Answer: b
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4) Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate
b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one OR gate
d) One 4-input NAND gate, one inverter

Answer: b

5) For a two-input XNOR gate, with the input waveforms as shown below, which
output waveform is correct?

a) d
b) a
c) c
d) b

Answer: a

6) 3 bits full adder contains ________

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs

Answer: d
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7) What is the indication of a short to ground in the output of a driving gate?

a) Only the output of the defective gate is affected
b) There is a signal loss to all load gates
c) The node may be stuck in either the HIGH or the LOW state
d) The affected node will be stuck in the HIGH state

Answer: b

Multiplexers (Data Selectors)

1) What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output

Answer: b

2) Which combinational circuit is renowned for selecting a single input from

multiple inputs & directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) DeMultiplexer

Answer: a

3) It is possible for an enable or strobe input to undergo an expansion of two or

more MUX ICs to the digital multiplexer with the proficiency of large number of
___________
a) Inputs
b) Outputs
c) Selection lines
d) Enable lines

Answer: a
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4) One multiplexer can take the place of ___________

a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits

Answer: d

5) A digital multiplexer is a combinational circuit that selects ___________

a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one
c) Many decimal inputs and transmits the selected information
d) Many decimal outputs and accepts the selected information

Answer: a

6) If the number of n selected input lines is equal to 2^m then it requires _____
select lines.
a) 2
b) m
c) n
d) 2n

Answer: b

7) How many select lines would be required for an 8-line-to-1-line multiplexer?

a) 2
b) 4
c) 8
d) 3

Answer: d
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8) In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is ___________

a) X0
b) X1
c) X2
d) X3

Answer: b

Explanation: The output will be X1, because c1 = 0 and c0 = 1 results into 1 which
further results as X1. And rest of the AND gates gives output as 0.

9) 4 to 1 MUX would have ____________

a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs

Answer: c

10) The two input MUX would have ____________

a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines

Answer: a

11) A combinational circuit that selects one from many inputs are ____________
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
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Answer: d

12) Which of the following circuit can be used as parallel to serial converter?
a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter

Answer: a

Explanation: A combinational circuit that selects one from many inputs is known
as Multiplexer. In multiplexer, different inputs are inserted parallely and then it
gives one output which is in serial form.

13) Without any additional circuitry an 8:1 MUX can be used to obtain ____________
a) Some but not all Boolean functions of 3 variables
b) All function of 3 variables but none of 4 variables
c) All functions of 3 variables and some but not all of 4 variables
d) All functions of 4 variables

Answer: d

Explanation: A 2^n:1 MUX can implement all logic functions of (n+1) variables
without any additional circuitry. Thus 8:1 MUX can implement all logic functions
of (3+1) variables, for 4 variables there are 16 possible combinations. So to use 8:1
MUX use 3 inputs as select lines of MUX and the 4th input as input of MUX.

Code Converters
1) Use the weighting factors to convert the following BCD numbers to binary
___________

0101 0011 & 0010 0110 1000

a) 01010011 & 001001101000

b) 11010100 & 100001100000
c) 110101 & 100001100
d) 101011 & 001100001

Answer: c
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Explanation: Firstly, convert every 4 sets of binary to decimal from the given:
0101=5, 0011=3. Then convert 53 to binary, which will give 110101. Again, do the
same with the next 4 set of binary digits.

2) The binary representation of BCD number 00101001 (decimal 29) is ___________

a) 0011101
b) 0110101
c) 1101001
d) 0101011

Answer: a

3) Convert binary number into gray code: 100101.

a) 101101
b) 001110
c) 110111
d) 111001

Answer: c

Explanation: Conversion from Binary To Gray Code:

b6 = g6

b5 = g6 (XOR) g5

b4 = g6 (XOR) g5 (XOR) g4

b3 = g6 (XOR) g5 (XOR) g 4 (XOR) g3

.
.
.
b1 = g6 (XOR) g5 (XOR) g4 (XOR) g3 (XOR) g2 (XOR) g1

Flip Flops
1) When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle

Answer: c
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Hint: after one cycle both J and K become 0

2) Which of the following is correct for a gated D-type flip-flop?

a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH

Answer: a

3) The sequential circuit is also called ___________

a) Flip-flop
b) Latch
c) Strobe
d) Adder

Answer: b

4) In S-R flip-flop, if Q = 0 the output is said to be ___________

a) Set
b) Reset
c) Previous state
d) Current state

Answer: b

Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.

5) The output of latches will remain in set/reset untill ___________

a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
Answer: a

6) What is a trigger pulse?

a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation

Answer: a
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Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.

7) The characteristic equation of S-R latch is ____________

a) Q(n+1) = (S + Q(n)) R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R

Answer: a

8) The characteristic equation of J-K flip-flop is ______________

a) Q(n+1) = JQ(n)+K’Q(n)
b) Q(n+1) = J’Q(n)+KQ'(n)
c) Q(n+1) = JQ'(n)+KQ(n)
d) Q(n+1) = JQ'(n)+K’Q(n)

Answer: d

9) The characteristic equation of D-flip-flop implies that ___________

a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state

Answer: d

Explanation: A characteristic equation is needed when a specific gate requires a

specific output in order to satisfy the truth table. The characteristic equation of
D flip-flop is given by Q(n+1) = D; which indicates that the next state is
independent of the present state.

10) The characteristic equation of a T flip-flop is:

(A) Q(n+1) = TQ’(n) + T’ Q(n)
(B) Q(n+1) = T+Q(n)
(C) Q(n+1) = TQ(n)
(D) Q(n+1) = T’Q’(n)

Answer: A
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11) What is one disadvantage of an S-R flip-flop?

a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State

Answer: d

12) The characteristic of J-K flip-flop is similar to _____________

a) S-R flip-flop
b) D flip-flop
c) T flip-flop
d) Gated T flip-flop

Answer: a

13) A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting
___________
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates

Answer: a

14) A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave

Answer: d

Explanation: The flip flop is sensitive only to the positive or negative edge of the
clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge.
This triggering of flip-flop during the transition state, is known as Edge-triggered
flip-flop. Thus, the output curve has a time period twice that of the clock.
Frequency is inversely related to time period and hence frequency gets halved.
 31

15) Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as
counters. After four input clock pulses, the binary count is ________
a) 00
b) 11
c) 01
d) 10

Answer: a

Explanation: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops
are used. So, mod = 22 = 4). So, after 4 clock pulses the O/P repeats i.e., 00.

16) Four J-K flip-flops are cascaded (‫ )متتالية‬with their J-K inputs tied HIGH. If the input
frequency (fin) to the first flip-flop is 32 kHz, the output frequency (four) is ________
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz

Answer: b

Explanation: 32/2=16: -first flip-flop, 16/2=8: - second flip-flop, 8/2=4: - third flip-
flop, 4/2=2: - fourth flip-flop. Since the output frequency is determined on basis of
the 4th flip-flop.

17) Determine the output frequency for a frequency division circuit that contains 12
flip-flops with an input clock frequency of 20.48 MHz
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz

Answer: b

Explanation: 12 flip flops = 212 = 4096

Input Clock frequency = 20.48*106 = 20480000
Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.
 32

18) In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________

a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop

Answer: c

Explanation: In J-K flip-flop, if both the inputs are same then it behaves like T flip-
flop.

19) In J-K flip-flop, the function K=J is used to realize _____________

a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop

Answer: c

20) The flip-flop is only activated by _____________

a) Positive edge trigger
b) Negative edge trigger
c) Either positive or Negative edge trigger
d) Sinusoidal trigger

Answer: c

21) The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T

Answer: d

22) On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition
when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
 33

Answer: c

23) How is a J-K flip-flop made to toggle?

a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1

Answer: d

24) In J-K flip-flop, “no change” condition appears when ___________

a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0

Answer: d

25) On a J-K flip-flop, when is the flip-flop in a hold condition?

a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1

Answer: a

26) The D flip-flop has _______ input.

a) 1
b) 2
c) 3
d) 4

Answer: a

27) The D flip-flop has ______ output/outputs.

a) 2
b) 3
c) 4
d) 1

Answer: a
 34

Explanation: The D flip-flop has two outputs: Q and Q complement. The D flip-flop
has one input. The D of D-flip-flop stands for “data”. It stores the value on the
data line.

28) A D flip-flop can be constructed from an ______ flip-flop.

a) S-R
b) J-K
c) T
d) S-K

Answer: a

Explanation: A D flip-flop can be constructed from an S-R flip-flop by inserting an

inverter between S and R and assigning the symbol D to the S input.

29) In D flip-flop, if clock input is HIGH & D=1, then output is ___________
a) 0
b) 1
c) Forbidden
d) Toggle

Answer: a

30) Which of the following is correct for a gated D flip-flop?

a) The output toggles if one of the inputs is held HIGH
b) Only one of the inputs can be HIGH at a time
c) The output complement follows the input when enabled
d) Q output follows the input D when the enable is HIGH

Answer: d

31) A positive edge-triggered D flip-flop will store a 1 when ________

a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH

Answer: b
 35

Combinational Circuits VS sequential Circuits

1) In a combinational circuit, the output at any time depends only on the _______ at
that time.
a) Voltage
b) Intermediate values
c) Input values
d) Clock pulses

Answer: c

2) In a sequential circuit, the output at any time depends only on the input values at
that time.
a) Past output values
b) Intermediate values
c) Both past output and present input
d) Present input values

Answer: c

3) A combinational circuit is one in which the output depends on the ____________

a) Input combination at the time
b) Input combination and the previous output
c) Input combination at that time and the previous input combination
d) Present output and the previous output

Answer: a

4) The only difference between a combinational circuit and a flip-flop is that

_____________
a) The flip-flop requires previous state
b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) The flip-flop depends on the past as well as present states

Answer: c
 36

5)How many stable states combinational circuits have?

a) 3
b) 4
c) 2
d) 5

Answer: c

Explanation: The two stable states of combinational circuits are 1 and 0.

Whereas, in flip-flops there is an additional state known as Forbidden State.

Counters
1)What is the maximum possible range of bit-count specifically in n-bit binary
counter consisting of ‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2(n+1)/2

Answer: c

Explanation: The maximum possible range of bit-count specifically in n-bit binary

counter consisting of ‘n’ number of flip-flops is 0 to 2n-1. For say, there is a 2-bit
counter, then it will count till 22-1 = 3. Thus, it will count from 0 to 3.

2) A decimal counter has ______ states.

a) 5
b) 10
c) 15
d) 20

Answer: b

Explanation: Decimal counter is also known as 10 stage counter. So, it has 10

states. It is also known as Decade Counter counting from 0 to 9.

3) A binary counter has ______ states.

a) 16
b) 10
c) 15
d) 20
 37

Answer: a

4) The parallel outputs of a counter circuit represent the _____________

a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count

Answer: d

Explanation: The parallel outputs of a counter circuit represent the clock count. A
counter counts the number of times an event takes place in accordance to the
clock pulse.

Registers
1) The register is a type of ___________
a) Sequential circuit
b) Combinational circuit
c) CPU
d) Latches

Answer: a

2) The main difference between a register and a counter is ___________

a) A register has no specific sequence of states
b) A counter has no specific sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) A register counts data

Answer: a

3) A shift register is defined as ___________

a) The register capable of shifting information to another register
b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only

Answer: b
 38

Shift Registers
1)The full form of SIPO is ___________
a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out

Answer: a

2) A shift register that will accept a parallel input or a bidirectional serial load and
internal shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion

Answer: c

3) How can parallel data be taken out of a shift register simultaneously?

a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF

Answer: d

Explanation: Because no other flip-flops are connected with the output Q,

therefore one can use the Q out of each FF to take out parallel data.

4) What is meant by the parallel load of a shift register?

a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data

Answer: a

5) The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel
output shift register with an initial state 01110. After three clock pulses, the register
contains ________
a) 01110
 39

b) 00001
c) 00101
d) 00110

Answer: c

Explanation: LSB bit is inverted and feed back to MSB:

01110->initial
10111->first clock pulse
01011->second
00101->third.

6) Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to
store the nibble 1100. What will be the 4-bit pattern after the second clock pulse?
(Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111

Answer: c

Explanation: In Serial-In/Serial-Out shift register, data will be shifted one at a

time with every clock pulse. Therefore,
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.

7) A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble
0111 is waiting to enter. After four clock pulses, the register contains ________
a) 0000
b) 1111
c) 0111
d) 1000

Answer: c

8) With a 200 kHz clock frequency, eight bits can be serially entered into a shift register
in ________
a) 4 μs
b) 40 μs
 40

c) 400 μs
d) 40 ms

Answer: b

Explanation: f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;

In serial transmission, data enters one bit at a time. After 8 clock cycles only 8
bits will be loaded = 8 * 5 = 40 micro-sec.

9) An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz
to achieve a time delay (td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us

Answer: c

Explanation: One clock period is = ( 𝟏⁄𝟐)micro-s = 0.5 microseconds. In serial

transmission, data enters one bit at a time. So, the total delay = 0.5*8 = 4
microseconds time is required to transmit information of 8 bits.

10) A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH.
The nibble 1011 is waiting to be entered on the serial data-input line. After three
clock pulses, the shift register is storing ________
a) 1101
b) 0111
c) 0001
d) 1110

Answer: b

11) A 4-bit shift register that receives 4 bits of parallel data will shift to the ________
by ________ position for each clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three

Answer: a
 41

Explanation: If register shifts towards left then it shift by a bit to the left and if
register shifts right then it shift to the right by one bit. Since, it receives parallel
data, then by default, it will shift to right by one position.

12) How many clock pulses will be required to completely load serially a 5-bit shift
register?
a) 2
b) 3
c) 4
d) 5

Answer: d

13) An 8-bit serial in/serial out shift register is used with a clock frequency of 150
kHz. What is the time delay between the serial input and the Q3 output?
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms

Answer: b

Explanation: In serial-sifting, one bit of data is shifted one at a time. From Q0 to

Q3 total of 4-bit shifting takes place. Therefore, 4/150kHz = 26.67 microseconds.

14) When is it important to use a three-state buffer?

a) When two or more outputs are connected to the same input
b) When all outputs are normally HIGH
c) When all outputs are normally LOW
d) When two or more outputs are connected to two or more inputs

Answer: a

15) What are the three output conditions of a three-state buffer?

a) HIGH, LOW, float
 42

b) High-Z, 0, float
c) Negative, positive, 0
d) 1, Low-Z, float

Answer: a

16) In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After

three clock pulses, the data outputs are ________
a) 1110
b) 0001
c) 1100
d) 1000

Answer: b

Explanation: Parallel in parallel out gives the same output as input. Thus, after
three clock pulses, the data outputs are 0001.

17) How much storage capacity does each stage in a shift register represent?
a) One bit
b) Two bits
c) Four bits
d) Eight bits

Answer: a

Explanation: A register is made of flip-flops. And each flip-flop stores 1 bit of data.
Thus, a shift register has the capability to store one bit and if another bit is to
store, in such a situation it deletes the previous data and stores them.

Introduction of Memory Devices

1) Memory is a/an ___________
a) Device to collect data from other computer
b) Block of data to keep data separately
c) Indispensable part of computer
d) Device to connect through all over the world

Answer: c

2) The instruction used in a program for executing them is stored in the __________
a) CPU
b) Control Unit
 43

c) Memory
d) Microprocessor

Answer: c

3) A flip flop stores __________

a) 10 bits of information
b) 1 bit of information
c) 2 bit of information
d) 3-bit information

Answer: b

4) A register is able to hold __________

a) Data
b) Word
c) Nibble
d) Both data and word

Answer: b

5) A register file holds __________

a) A large number of word of information
b) A small number of word of information
c) A large number of programs
d) A modest number of words of information

Answer: d

Explanation: A register file is different from a simple register because of

capability to hold a modest number of words of information. A word is a group of
16-bits or 2-bytes.

6) A large memory is compressed into a small one by using __________

a) LSI semiconductor
b) VLSI semiconductor
c) CDR semiconductor
d) SSI semiconductor

Answer: b

Explanation: VLSI (Very Large-Scale Integration) semiconductor is used in modern

computers to short the size of memory.
 44

7) VLSI chip utilizes __________

a) NMOS
b) CMOS
c) BJT
d) All of the Mentioned

Answer: d

Explanation: VLSI (Very Large-Scale Integration) is a memory chip which is made

up of NMOS, CMOS, BJT, and BiCMOS. It can include 10,000 to 100,000 gates per IC.

8) CD-ROM refers to __________

a) Floppy disk
b) Compact Disk-Read Only Memory
c) Compressed Disk-Read Only Memory
d) Compressed Disk- Random Access Memory

Answer: b

9) Data stored in an electronic memory cell can be accessed at random and on

demand using __________
a) Memory addressing
b) Direct addressing
c) Indirect addressing
d) Control Unit

Answer: b

10) The full form of PLD is __________

a) Programmable Large Device
b) Programmable Long Device
c) Programmable Logic Device
d) Programmable Lengthy Device

Answer: c

11) The evolution of PLD began with __________

a) EROM
b) RAM
 45

c) PROM
d) EEPROM

Answer: a

Explanation: The evolution of PLD (Programmable Logic Device) began with

Programmable Read Only Memory (i.e., PROM). Here, the ROM can be externally
programmed as per the user.

12) A ROM is defined as __________

a) Read Out Memory
b) Read Once Memory
c) Read Only Memory
d) Read One Memory

Answer: c

13) The full form of PROM is __________

a) Previous Read Only Memory
b) Programmable Read Out Memory
c) Programmable Read Only Memory
d) Previous Read Out Memory

Answer: c

14) The full form of EPROM is __________

a) Easy Programmable Read Only Memory
b) Erasable Programmable Read Only Memory
c) Eradicate Programmable Read Only Memory
d) Easy Programmable Read Out Memory

Answer: b

15) ASIC stands for __________

a) Application Special Integrated Circuits
b) Applied Special Integrated Circuits
c) Application Specific Integrated Circuits
d) Applied Specific Integrated Circuits

Answer: c
 46

16) In a computer, registers are present __________

a) Within control unit
b) Within RAM
c) Within ROM
d) Within CPU

Answer: d

17) A sequential access memory is one in which __________

a) A particular memory location is accessed rapidly
b) A particular memory location is accessed sequentially
c) A particular memory location is accessed serially
d) A particular memory location is accessed parallely

Answer: b

18) A Random-Access Memory is one in which __________

a) Any location can be accessed sequentially
b) Any location can be accessed randomly
c) Any location can be accessed serially
d) Any location can be accessed parallely

Answer: b

19) Memories are classified into _____ categories.

a) 3
b) 4
c) 5
d) 6

Answer: c

Explanation: Memory is typically classified of 2 types: Primary and Secondary.

These are further classified into 5 types of memories, and these are Secondary,
RAM, Dynamic/Static, Volatile/Non-volatile, Magnetic/Semiconductor Memory.

20) Secondary memory is also known as ___________

a) Registers
b) Main Memory
c) RAM
d) Both registers and main memory
 47

Answer: d

21) In a computer, registers are present __________

a) Within control unit
b) Within RAM
c) Within ROM
d) Within CPU

Answer: d

22) Which of the following has the capability to store the information permanently?
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM

Answer: b

23) CD-ROM refers to __________

a) Floppy disk
b) Compact Disk-Read Only Memory
c) Compressed Disk-Read Only Memory
d) Compressed Disk- Random Access Memory

Answer: b

Read Only Memory (ROM)

1) ROM has the capability to perform _____________
a) Write operation only
b) Read operation only
c) Both write and read operation
d) Erase operation

Answer: b

2) The ROM is a ___________

a) Sequential circuit
b) Combinational circuit
c) Magnetic circuit
d) Static circuit
 48

Answer: b

Explanation: ROM is made up of Decoder and OR gates

3) In ROM, each bit combination that comes out of the output lines is called ___________
a) Memory unit
b) Storage class
c) Data word
d) Address

Answer: c

Explanation: In ROM, each bit combination that comes out of the output lines is
called data word. Usually, a word consists of 16-bits or 2-bytes.

4) The full form of EEPROM is __________

a) Erasable Electrically Programmable ROMs
b) Electrically Erasable Programmable ROMs
c) Electrically Erasable Programming ROMs
d) Electrically Erasable Programmed ROMs

Answer: b

5) Which bus is used for input and output in case of microprocessor operation?
a) Address bus
b) System bus
c) Control bus
d) Data bus

Answer: c
 49

sequential circuits

1) If the initial state QA QB QC = 110, after how many clocks it get back same
value

• A) 2

• B) 6

• C) 7

• D) 8

Solution:

Correct answer is option 'A'

 50

2) What will be the current state after two clock pulses further from the
number of pulses obtained from the above question?

• A) 011

• B) 100

• C) 101

• D) 110

Solution:

Correct answer is option 'D'

 51

3) The divide by N counter as shown in figure. If initially Q0 = 0, Q1 = 1, Q2 = 0.

What is the value of N?

A) 5

B) 6

C) 3

D) 4

Solution:

So, 5-mod counter.

 52

4) Consider the circuit given below with initial state Q0 = 1; Q1 = Q2 = 0. The

state of the circuit is given by the value 4Q2 + 2Q1 + Q0

Which one of the following is the. correct state sequence of the circuit?

A) 1,3,4,6,7,5,2

B) 1,2,5,3,7,6,4

C) 1,2,7,3,5,6,4

D) 1,6,5,7,2,3,4

Solution:

Therefore, the correct state sequence of the circuit is 1, 2, 5, 3, 7, 6, 4.

 53

5) The following diagram represents a finite state machine which takes as

input a binary number from the least significant bit

Which one of the following is TRUE?

A) It computes 1’s complement of the input number.

B) It computes 2's complement of the input number.

C) It increments the input number.

D) It decrements the input number.

Solution:

Here, for state Q0

When input is 0 output is 0 and it remains in state Q0.
When input is 1 output is 1 and goes to state Q1.
For state Q1.
When input is 0 output is 1, when input is 1 output is 0.
Here state changes from Q0 to Q1 when there is a 1 as input, in state Q1 every
input is complemented.
Hence, the given circuit computes 2’s complement of the input number.
Hence (b) is correct answer.
 54

6) Consider the following circuit

The flip-flops are positive edge triggered DFFs. Each state is designated as a two-bit
string Q0Q1 Let the initial state be 00. The state transition sequence is:

A.

B.

C.

D.

Solution:

The state transitions sequence is

 55

7) The functional difference between SR flip-flop and JK flip-flop is that JK flip-

flop

A) Is faster than SR flip-flop

B) Has a feedback path

C) Accepts both inputs 1

D) Does not require external clock

Solution:

S-R flip flop gives invalid output when both inputs are 1 while JK flip-flop toggle the
previous output when both inputs are 1. Hence it accepts both inputs 1.

8) The number of flip-flops required in a modulo N counter is

A)

B)

C)

D)

Solution:
 56

The number of flip-flops required for modulo N counter is [ log2(N)].

9) Consider the figure given below:

Initially all flip-flops are cleared. How many docks pulse have to be applied to the
system before the output from FF3 becomes a HIGH level?

A) 2

B) 4

C) 6

D) 8

Solution:

So, 4 clock pulses are needed.

 57

10) The logic circuit shown below is a 3-bit

A) Shift register

B) Asynchronous binary up-counter

C) Asynchronous binary down-counter

D) Synchronous binary up counter

Solution:

If input initially is QAQBQC = 000

So after 1st clock pulse QAQBQC = 100
Since, values is incremented so a binary up counter, synchronous since clock
provided to all at same time.
 58

11) The inputs of the J-K flip-flop, shown below are:

PRESET = CLEAR = 1; J = K = 0
If a single clock pulse is applied the device will

A) Toggle

B) Set

C) Reset

D) Not change states

Solution:

To make flip-flop working both preset = apart = 1 Since J = K = 0, so it does not

change its state i.e., remains in same state.
 59

12) ‘n’ flip-flop will divide the clock frequency by a factor of

A) n2

B) n

C) 2n

D) log(n)

Solution:
n
n-flip-flop divide the clock frequency by a factor of 2 .

13) If a clock with time period 'T' is used with n stage shift register, the output
of final stage will be delayed by

A) nT sec

B) (n -1) T (sec)

C) n/T (sec)

D) (2n-1) T (sec)

Solution:

N stage shift register will take (n - 1) x clock time to show the output of final stage.
 60

14) For which of the following flip-flops, the output is clearly defined for all
combinations of two inputs?

A) R-S flip-flop

B) J-K flip-flop

C) D flip-flop

D) None of these

Solution:

For J-K flip-flop, the output is clearly defined for all combinations of two inputs. For
S-R flip-flop output is not defined when S = R = 1. A D flip-flop has only one input.

15) In a J-K flip-flop, toggle means

A) set Q = 0 and

B) set 0 = 1 and

C) change the output to the opposite state

D) no change in the output

Solution:
In a J-K flip-flop, toggle means change the output to the opposite state. A J-K flip-flop toggles
when
 61

16) What J-K input condition will always set ‘Q+ upon the occurrence of the
active clock transition?

A) J = 1, K = 0

B) J = 1, K = 1

C) J = 0, K = 1

D) J = 0, K = 0

Solution:

Truth table for J-K flip-flop is shown below.

When J = 1 and K = 0, output (Q+) is always set upon the occurrence of the active
clock transition.
 62

17) The output of S-R flip-flop when S = 1, R = 0 is

A) low

B) high

C) no change

D) high impedance

Solution:

18) The output of a J-K flip-flop with asynchronous preset and clear inputs if
‘1’. The output can be changed to ‘0’ with which one of the following
conditions?

A) By applying J = 1, K= 0 and using the clock

B) By applying a synchronous preset input

C) By applying J = 1, K = 1 and using the clock

D) By applying J = 0, K = 0 and using the clock

Solution:

When J = 1, K = 1 and the clock, next state will be complemented of the present
state. Thus,
 63

19) An eight-stage ripple counter uses a flip-flop with propagation delay of 75

nanoseconds. The pulse width of the strobe is 50 nanoseconds. The frequency
of the input signal which can be used for proper operation of the counter is
approximately equal to

A) 500 MHz

B) 2 MHz

C) 4 MHz

D) 1.5 MHz

Solution:

Maximum time taken for all flip-flops to stabilize is (75 ns x 8) + 50 ns = 650 ns.
Frequency of operation must be less than

Thus, option (d) is correct.

 64

20) A J-K flip-flop can be implemented using D flip- flop connected such that

A)

B)

C)

D)

Solution:

Correct answer is option 'D'

 65

21) Assertion (A): In general, asynchronous circuits are considerably faster

than synchronous circuits.
Reason (R): In an asynchronous circuit, events can occur after one event is
completed and there is no need to wait for a clock pulse.

A) Both A and R are true, and R is the correct explanation of A

B) Both A and R are true, but R is not the correct explanation of A

C) A is true but R is false

D) A is false but R is true

Solution:

Correct answer is option 'A'

22) Consider the following statements:

1. Sequential circuits are always faster than combination circuits.
2. In an asynchronous circuit there is no problem of stability.
3. The logic circuits whose outputs at any instant of time depend only on the
input signals present at that time are known as combinational circuits.
4. In a combinational circuit, for a change in the input, the output appears
immediately.
5. In a sequential circuit, the output signals are fed back to the input side.

Which of the statement given above are correct?

A) 2, 3 and 4

B) 1. and 5 only

C) 3 and 5 only
 66

D) 1,2 and 4

Solution:

• Combinational circuits are often faster than sequential circuits since the
combination’s circuits do not require memory whereas the sequential circuits need
memory devices to perform their operations in sequence. Hence statement - 1 is
not correct.
• in an asynchronous circuit, events are allowed to occur without any
synchronization In such a case, the system become: unstable which results in
difficulties. Hence statement-2 is not correct.
• Statement-3 is correct which is the definition of a combinational circuit.
• in a combinational circuit, for a change if the input, the output appears
immediately except for the propagation delay through circuit gates. Thus,
statement-4 is no correct.
• In a sequential circuit, an output signal is e function of the present input signals
and e sequence of the past input signals i.e., the past output signals since the
output signals are fed back to the input side. Hence, statement-5 is correct.
Thus, statements 3 and 5 are only correct.

The end of Revision, Best Wishes

Mahmoud Abdelraoof Mahmoud
13/1/2021