MTW20N50E

Preferred Device

Power MOSFET
20 Amps, 500 Volts
N–Channel TO–247
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage–blocking capability without degrading http://onsemi.com
performance over time. In addition, this advanced Power MOSFET is
designed to withstand high energy in the avalanche and commutation 20 AMPERES
modes. The new energy efficient design also offers a drain–to–source
diode with a fast recovery time. Designed for high voltage, high speed
500 VOLTS
switching applications in power supplies, converters and PWM motor RDS(on) = 240 mΩ
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical N–Channel
and offer additional safety margin against unexpected voltage D
transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
G
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
S
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature 4
• Isolated Mounting Hole Reduces Mounting Hardware
TO–247AE
CASE 340K
MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Style 1
1
Rating Symbol Value Unit 2
3 MARKING DIAGRAM
Drain–Source Voltage VDSS 500 Vdc
& PIN ASSIGNMENT
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc 4
Gate–Source Voltage Drain
– Continuous VGS ± 20 Vdc
– Non–Repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk
Drain Current – Continuous ID 20 Adc MTW20N50E
Drain Current – Continuous @ 100°C ID 14.1 LLYWW
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 60 Apk
Total Power Dissipation PD 250 Watts
Derate above 25°C 2.0 W/°C
Operating and Storage Temperature Range TJ, Tstg –55 to °C 1 3
150 Gate Source

Single Pulse Drain–to–Source Avalanche EAS 2000 mJ 2

Energy – Starting TJ = 25°C Drain
(VDD = 100 Vdc, VGS = 10 Vdc,
LL = Location Code
IL = 20 Apk, L = 10 mH, RG = 25 Ω)
Y = Year
Thermal Resistance – Junction to Case RθJC 0.50 °C/W WW = Work Week
Thermal Resistance – Junction to Ambient RθJA 40
Maximum Lead Temperature for Soldering TL 260 °C ORDERING INFORMATION
Purposes, 1/8″ from case for 10 seconds
Device Package Shipping

MTW20N50E TO–247 30 Units/Rail

Preferred devices are recommended choices for future use

and best overall value.

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

November, 2000 – Rev. 5 MTW20N50E/D
 MTW20N50E

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 250 µAdc) 500 – – Vdc
Temperature Coefficient (Positive) – 583 – mV/°C
Zero Gate Voltage Drain Current IDSS µAdc
(VDS = 500 Vdc, VGS = 0 Vdc) – – 10
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C) – – 100
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – – 100 nAdc
ON CHARACTERISTICS (Note 1.)
Gate Threshold Voltage VGS(th)
(VDS = VGS, ID = 250 µAdc) 2.0 3.0 4.0 Vdc
Temperature Coefficient (Negative) – 7.0 – mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 10 Adc) RDS(on) – 0.20 0.24 Ohm
Drain–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 20 Adc) – 5.75 6.0
(ID = 10 Adc, TJ = 125°C) – – 6.0
Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) gFS 11 16.2 – mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss – 3880 6950 pF
Output Capacitance (VDS = 25 Vd
Vdc, VGS = 0 Vdc,
Vd
Coss – 452 920
f = 1.0 MHz)
Reverse Transfer Capacitance Crss – 96 140

SWITCHING CHARACTERISTICS (Note 2.)

Turn–On Delay Time td(on) – 29 55 ns
Rise Time (VDD = 250 Vdc, ID = 20 Adc, tr – 90 165
VGS = 10 Vdc,
Vdc
Turn–Off Delay Time RG = 9.1 Ω) td(off) – 97 190
Fall Time tf – 84 170
Gate Charge QT – 100 132 nC
(See Figure 8)
(VDS = 400 Vdc, ID = 20 Adc, Q1 – 20 –
VGS = 10 Vdc)
Q2 – 44 –
Q3 – 36 –

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (Note 1.) VSD Vdc
(IS = 20 Adc, VGS = 0 Vdc)
– 0.916 1.1
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
– 0.81 –
Reverse Recovery Time trr – 431 – ns
(S Figure
(See Fi 14)
ta – 272 –
(IS = 20 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) tb – 159 –
Reverse Recovery Stored QRR – 6.67 – µC
Charge

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance LD – 5.0 – nH
(Measured from the drain lead 0.25″ from package to center of die)

Internal Source Inductance LS – 13 – nH

(Measured from the source lead 0.25″ from package to source bond pad)
1. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.

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 MTW20N50E

TYPICAL ELECTRICAL CHARACTERISTICS

40 40
TJ = 25°C VGS = 10 V 9V VDS ≥ 10 V
8V
32 32
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

24 24
7V

16 16 100°C
6V
25°C
8 8

5V TJ = -55°C
0 0
0 2 4 6 8 10 12 14 16 18 20 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

0.6 0.34
VGS = 10 V TJ = 25°C
0.5 TJ = 100°C 0.32

0.4
0.30
25°C
0.3
VGS = 10 V
0.28
0.2
-55°C
0.26 15 V
0.1

0 0.24
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Temperature and Gate Voltage

2.4 10000
R DS(on) , DRAIN-TO-SOURCE RESISTANCE

VGS = 10 V VGS = 0 V
ID = 10 A TJ = 125°C
2.0
1000
100°C
I DSS , LEAKAGE (nA)

1.6
(NORMALIZED)

1.2 100

0.8
10
0.4 25°C

0 1
-50 -25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 450 500
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage

Temperature Current versus Voltage

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 MTW20N50E

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the off–state condition when
controlled. The lengths of various switching intervals (∆t) calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can on–state when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain–gate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
t = Q/IG(AV) complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG – VGSP) resistance (Figure 9) shows how typical switching
tf = Q2 x RG/VGSP performance is affected by the parasitic circuit elements. If
where the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG
The circuit used to obtain the data is constructed to minimize
RG = the gate drive resistance
common inductance in the drain and gate circuit loops and
and Q2 and VGSP are read from the gate charge curve.
is believed readily achievable with board mounted
During the turn–on and turn–off delay times, gate current is components. Most power electronic loads are inductive; the
not constant. The simplest calculation uses appropriate data in the figure is taken with a resistive load, which
values from the capacitance curves in a standard equation for approximates an optimally snubbed inductive load. Power
voltage change in an RC network. The equations are: MOSFETs may be safely operated into an inductive load;
td(on) = RG Ciss In [VGG/(VGG – VGSP)] however, snubbing reduces switching losses.
td(off) = RG Ciss In (VGG/VGSP)

9000 10000
VDS = 0 V VGS = 0 V TJ = 25°C VGS = 0 V TJ = 25°C
8000
Ciss Ciss
7000
C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

6000 1000

5000
Crss Ciss
4000
Coss
3000 100

2000
Crss
1000 Crss Coss
0 10
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Figure 7a. Capacitance Variation Variation

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 MTW20N50E

10 500 1000
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) td(off)

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

QT VDD = 250 V
ID = 20 A tr
8 VGS 400 VGS = 10 V
TJ = 25°C
Q1 Q2 tf
6 300

t, TIME (ns)
100
td(on)
4 200
ID = 20 A
TJ = 25°C
2 100

Q3 VDS
0 0 10
0 10 20 30 40 50 60 70 80 90 100 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

20
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)

16

12

0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82 0.86 0.90 0.94
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous drain–to–source voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and adjusted for operating conditions
forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is
junction temperature and a case temperature (TC) of 25°C. to rate in terms of energy, avalanche energy capability is not
Peak repetitive pulsed power limits are determined by using a constant. The energy rating decreases non–linearly with an
the thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal temperature.
Resistance–General Data and Its Use.” Although many E–FETs can withstand the stress of
Switching between the off–state and the on–state may drain–to–source avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded and the continuous current (ID), in accordance with industry
transition time (tr,tf) do not exceed 10 µs. In addition the total custom. The energy rating must be derated for temperature
power averaged over a complete switching cycle must not as shown in the accompanying graph (Figure 12). Maximum
exceed (TJ(MAX) – TC)/(RθJC). energy at currents below rated continuous ID can safely be
A Power MOSFET designated E–FET can be safely used assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For

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 MTW20N50E

SAFE OPERATING AREA

100 2000
VGS = 20 V

EAS, SINGLE PULSE DRAIN-TO-SOURCE

10 µs 1800 ID = 20 A
SINGLE PULSE
TC = 25°C 1600
I D , DRAIN CURRENT (AMPS)

AVALANCHE ENERGY (mJ)

10
1400
100 µs
1200
1 ms
1.0 1000
10 ms 800
dc 600
0.1 RDS(on) LIMIT
THERMAL LIMIT 400
PACKAGE LIMIT 200
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE

0.2
r(t), NORMALIZED EFFECTIVE

0.1
0.1
0.05 P(pk)
RθJC(t) = r(t) RθJC
0.02
D CURVES APPLY FOR POWER
0.01 0.01
PULSE TRAIN SHOWN
t1 READ TIME AT t1
SINGLE PULSE t2 TJ(pk) - TC = P(pk) RθJC(t)
DUTY CYCLE, D = t1/t2
0.001
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

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 MTW20N50E

PACKAGE DIMENSIONS

TO–247
CASE 340K–01
ISSUE C

–T–
–Q–
E NOTES:
0.25 (0.010) M T B M –B– 1. DIMENSIONING AND TOLERANCING PER ANSI
C Y14.5M, 1982.
4 2. CONTROLLING DIMENSION: MILLIMETER.

U L MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 19.7 20.3 0.776 0.799
A R B 15.3 15.9 0.602 0.626
C 4.7 5.3 0.185 0.209
D 1.0 1.4 0.039 0.055
1 2 3
E 1.27 REF 0.050 REF
F 2.0 2.4 0.079 0.094
G 5.5 BSC 0.216 BSC
–Y– H 2.2 2.6 0.087 0.102
P J 0.4 0.8 0.016 0.031
K
K 14.2 14.8 0.559 0.583
L 5.5 NOM 0.217 NOM
P 3.7 4.3 0.146 0.169
Q 3.55 3.65 0.140 0.144
V H R 5.0 NOM 0.197 NOM
F J U 5.5 BSC 0.217 BSC
G V 3.0 3.4 0.118 0.134
D
STYLE 1:
0.25 (0.010) M Y Q S
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN

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 MTW20N50E

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