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Computer Architecture

This document describes a 4x4 register file module implemented using Verilog code. It contains modules for a 1-bit register, 4-bit register, and the top-level 4x4 register file module. The register file allows writing to one of four 4-bit registers using a 2-bit selection signal and reading from two registers using another 2-bit selection signal. A testbench is provided to test the register file functionality.

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zeeshan shaukat
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31 views

Computer Architecture

This document describes a 4x4 register file module implemented using Verilog code. It contains modules for a 1-bit register, 4-bit register, and the top-level 4x4 register file module. The register file allows writing to one of four 4-bit registers using a 2-bit selection signal and reading from two registers using another 2-bit selection signal. A testbench is provided to test the register file functionality.

Uploaded by

zeeshan shaukat
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Muhammad Usman CA Lab 12-ENC-17

4 bit register file:


module D_ff (out, in, rst, clk);

output out; input in; input rst; input clk; reg out;

always @(posedge clk)

begin

if (rst)

out = 0;

else

out = in;

end

endmodule

//module for 1bit register

module onebitreg(y1,load1,x1,rst1,clk1);

input x1,rst1,clk1,load1;

output y1; wire w1,w2,w3,w4;

not(w1,load1); and(w2,y1,w1); and(w3,x1,load1); or(w4,w3,w2);

D_ff f1(y1, w4, rst1, clk1);

endmodule

//module for 4bit register

module fourbitreg(y,load,x,rst2,clk2);

input [3:0]x; input load,rst2,clk2; output [3:0]y;

onebitreg f2(y[0],load,x[0],rst2,clk2); onebitreg f3(y[1],load,x[1],rst2,clk2);

onebitreg f5(y[2],load,x[2],rst2,clk2); onebitreg f6(y[3],load,x[3],rst2,clk2);

endmodule

//module for 4*4 register

module register(dataoutreg1,dataoutreg2,datain,load2,rst3,clk3,s,s1);

input [3:0]datain; input [1:0]s,s1; input load2,rst3,clk3;

wire [3:0]dataout1,dataout2,dataout3,dataout4,loadi;
Muhammad Usman CA Lab 12-ENC-17

//selection of load enable for “ write” cycle

output [3:0]dataoutreg1,dataoutreg2;

assign loadi=(load2==0)?4'b0000:(s==2'b00)?4'b0001:(s==2'b01)?4'b0010:(s==2'b10)?4'b0100:4'b1000;

fourbitreg g1(dataout1,loadi[0],datain,rst3,clk3); fourbitreg g2(dataout2,loadi[1],datain,rst3,clk3);

fourbitreg g3(dataout3,loadi[2],datain,rst3,clk3); fourbitreg g4(dataout4,loadi[3],datain,rst3,clk3);

//assignment statement for assigning values for 1st read cycle

assign dataoutreg1=(s1==2'b00)?dataout1:(s1==2'b01)?dataout2:(s1==2'b10)?dataout3:dataout4 ;

//assignment statement for assigning values for 2nd read cycle

assign dataoutreg2=(s1==2'b00)?dataout1:(s1==2'b01)?dataout2:(s1==2'b10)?dataout3:dataout4;

endmodule

//testbench file for 4*4 register file

module test_reg;

reg [3:0]datain; reg [1:0]s,s1; reg load2,rst3,clk3; wire [3:0] dataoutreg1,dataoutreg2;

register z3(dataoutreg1,dataoutreg2,datain,load2,rst3,clk3,s,s1);

always #5clk3=~clk3;

initial

begin

clk3=1;rst3=1;load2=0;datain=4'b0010;

#5 rst3=0;load2=1;datain=4'b0010;s=2'b00;s1=2'b00;

end

endmodule Wave form

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