SEMICONDUCTOR MATERIALS AND

PROCESS TECHNOLOGY HANDBOOK

MATERIALS SCIENCE AND PROCESS TECHNOLOGY SERIES

Editors

Rointan F. Bunshah, University of California, Los Angeles (Materials

Science and Technology)
Gary E. McGuire, Microelectronics Center of North Carolina (Elec-
tronic Materials and Processing)

DEPOSITION TECHNOLOGIES FOR FILMS AND COATINGS; Develop-

ments and Applications: by Rointan F. Bunshah et al

CHEMICAL VAPOR DEPOSITION FOR MICROELECTRONICS; Principles,

Technology, and Applications: by Arthur Sherman

SEMICONDUCTOR MATERIALS AND PROCESS TECHNOLOGY HAND-

BOOK; For Very Large Scale Integration (VLSI) and Ultra Large Scale Integration
(ULSI): edited by Gary E. McGuire

SOL-GEL TECHNOLOGY FOR THIN FILMS, FIBERS, PREFORMS, ELEC-

TRONICS, AND SPECIALTY SHAPES: edited by Lisa C. Klein

HYBRID MICROCIRCUIT TECHNOLOGY HANDBOOK; Materials, Proc-

esses, Design, Testing and Production: by James J. Licari and Leonard R.
Enlow

HANDBOOK OF THIN FILM DEPOSITION PROCESSES AND TECH-

NIQUES; Principles, Methods, Equipment and Applications: edited by
Klaus K. Schuegraf

Related Titles

ADHESIVES TECHNOLOGY HANDBOOK: by Arthur H. Landrock

HANDBOOK OF THERMOSET PLASTICS: edited by Sidney H. Goodman

HANDBOOK OF CONTAMINATION CONTROL IN MICROELECTRONICS;

Principles, Applications and Technology: edited by Donald L. Tolliver
Semiconductor Materials
and
Process Technology
Handbook
for
Very Large Scale Integration (VLSI)
and
Ultra Large Scale Integration (ULSI)

Edited by

Gary E. McGuire
Microelectronics Center of North Carolina
Research Triangle Park, North Carolina

~
NOYES PUBLICATIONS
np WILLIAM ANDREW PUBLISHING, LLC
Norwich, New York, U.S.A.
Copyright © 1988 by Noyes Publications
No Part of this book may be reprod uced in any form
without permission in writing from the Publisher.
Library of Congress Catalog Card Number: 87-31529
ISBN: 0-8155-1150-7
Printed in the United States

Published in the United States of America by

Noyes PUblications/Wiliiam Andrew Publishing, LLC
13 Eaton Avenue, Norwich, New York 13815

109876

Reprint Edition

Library of Congress Cataloging-in-Publication Data

Semiconductor materials and process technology.

Bibliography: p.
Includes index.
1. Integrated circuits--Very large scale
integration --Design and construction --Handbooks,
manuals, etc. I. McGuire, G.E.
TK7874.S4178 1988 621.395 87-31529
ISBN 0-8155-1150-7
Contributors

Kenneth E. Bean Gary E. McGuire

Texas Instruments Incorporated Microelectronics Center of North
Dallas, TX Carolina
Research Triangle Park, NC
Bruce E. Dea I
Research Center William C. Q'Mara
Fairchild Semiconductor Corp. Aeolus Laboratory
Palo Alto, CA Palo Alto, CA

William C. Dautremont-Smith R. Fabian Pease

AT&T Bell Laboratories Stanford University
Murray Hill, NJ Stanford Electronics Laboratory
Department of Electrical
Richard B. Fair Engineering
Microelectronics Center of Stanford, CA
North Carolina
Research Triangle Park, NC Ronald J. Schutz
AT&T Bell Laboratories
Richard A. Gottscho Murray Hill, NJ
AT&T Bell Laboratories
Murray Hill, NJ John A. Thornton
University of Illinois
Paul S. Ho Department of Materials Science and
IBM Thomas J. Watson Reseach Coordinated Science Laboratory
Center Urbana,IL
Yorktown Heights, NY

v
 NOTICE

To the best of the Publisher's knowledge

the information contained in this book is
accurate; however, the Publisher assumes
no responsibility nor liability for errors
or any consequences arising from the use
of the information contained herein. Final
determination of the suitability of any
information, procedure, or product for
use contemplated by any user, and the man-
ner of that use, is the sole responsibility of
the user. The book is intended for informa-
tional purposes only. Semiconductor raw
materials and processes are potentially haz-
ardous and due caution should always be
exercised in the handling of materials and
equipment. Expert advice should be ob-
tained at all times when implementation is
being considered.

vi
Contents

INTRODUCTION 1
Gary E. McGuire
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1. SILICON MATERIALS TECHNOLOGY 8

William C. O'Mara
Introduction 8
Silicon Crystal Growth 8
Crystal Growth Equipment and Process 9
Dopant and Impurity Incorporation 15
Incorporation of Oxygen 19
Incorporation of Carbon 21
Wafer Preparation 22
Mechanical Shaping Procedures 22
Wafer Etching 23
Polishing 25
Cleaning 25
Material Properties 26
Crystal Structure 26
Electrical Properties 27
Optical Properties 30
Mechanical Properties 31
Process-Induced Defects 32
Oxidation-Induced Stacking Faults 32
Saucer Pits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Carbon-Related Defects ~ 34
Oxygen in Silicon 35
Oxygen in As-Grown Silicon 35
Quantitative Analysis of Oxygen in Silicon 35

vii
viii Contents

Interpretation of Infrared Absorption Spectra 36

Solid Solubility 38
Diffusion Coefficient 39
Donor Formation 40
Precipitation from Solid Solution 41
Denuded Zone Formation 42
Device Application 43
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2. THE THERMAL OXIDATION OF SILICON AND OTHER SEMI-

CONDUCTOR MATERIALS 46
Bruce E. Deal
Introduction and Background 46
Silicon Thermal Oxidation Kinetics 47
General Relationship 48
Thin Oxide Formation 54
Properties of Thermal Oxides 54
Process Variable/Oxidation Reaction Dependencies 55
Effects of the Oxidation Reaction on Surface Properties 55
Oxide Charges 55
Dopant Redistribution 61
Effects of Surface Properties on the Oxidation Reaction 62
Silicon Orientation 62
Dopant Concentration 63
Surface Preparation 64
Effects of Ambients on the Oxidation Reaction 65
Ambient Type 65
Chlorine Additions 65
Nitridation 66
Oxidant Pressure 67
Oxidation Mechanism 68
Atomic Reactions 68
Structure of the Si-Si0 2 Interface 70
Other Oxidation Processes 72
Assisted Oxidation 72
Silicon-Containing Materials 73
Other Semiconductors 74
Future Trends 75
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3. CHEMICAL VAPOR DEPOSITION OF SILICON AND ITS

COMPOUNDS 80
Kenneth E. Bean
Introduction 80
Epitaxial Deposition 82
HCI in Situ Etching 86
Gettering 91
Selective Deposition 94
 Contents ix

CVD of Dielectric Films 105

X-Ray Lithography Mask Fabrication 115
References 125

4. CHEMICAL ETCHING AND SLICE CLEANUP OF SILICON 126

Kenneth E. Bean
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Orientation Dependent Cleaving of Silicon 129
Orientation Dependent Etching and Orientation Dependent
Deposition 149
(110) Orientation Dependent Effects 157
Defect Delineation Etching 172
Slice Cleanup 183
Precleanup Solvent Rinse 187
Choline Cleanup Process 189
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 190

5. PLASMA PROCESSING: MECHANISMS AND APPLICATIONS . . . . . 191

w.e. Dautremont-Smith, Richard A. Gottscho and R.J. Schutz
Introduction 191
Fundamental Aspects 192
Plasmas and Sheaths. . . . . . . . . . . . . . . . . . . . . 193
Response Time and Screening Distance 193
Equivalent Circuits 195
Feedstock Composition 210
Pressure, Flow-Rate, and Residence Time 213
Power Density 217
Plasma-Surface Chemistry 217
Chemical Vapor Transport 218
Plasma Modified Chemical Vapor Transport 224
Mechanisms 230
Modeling 241
Plasma Etching 242
Introduction 242
Outline 242
Pattern Definition and Transfer 242
An Illustration of Plasma Etch Patterning 244
Equipment 244
Parallel Plate Etchers 244
The Hexagonal Cathode Etcher 247
Single Wafer Etcher 248
Endpoint Detection 249
Voltage/Power :249
Optical Emission Spectra 249
Laser Interferometry 249
Defining Process Parameters and Goals 249
Material to Be Etched 251
Feature Edge Profiles 252
x Contents

Uniformity 253
Selectivity --~ 254
Throughput -256
Defect Introduction 257
Radiation Damage Effects 257
Specific Etching Processes 258
Silicon and Silicides 258
Etching of Thermal and LPCVD Oxide 260
Etching of Aluminum Metallization 263
Silicon Nitride 264
Etching of Group III, V Compound Semiconductors 264
Plasma Deposition 265
Introduction 265
Applications of PECVD Materials 268
General Aspects of PECVD and PECVD Reactors 268
Reactor Designs 273
Source Gases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Uniformity Considerations and Interaction of PECVD
Variable Parameters 281
Film Properties and Their Control 284
Materials Deposited and Their Applications 289
Silicon Nitride 289
Silicon Oxide 301
Amorphous Silicon 305
Other Semiconductors, Including Epitaxial Growth 308
Metals 311
Silicides 312
Other Materials 312
Interface Properties 315
Summary and Conclusions 318
References 320

6. PHYSICAL VAPOR DEPOSITION 329

John A. Thornton
Introduction 329
The Vacuum Environment 330
Evaporation 336
Introduction 336
Evaporation Rate 337
Evaporation Sources 340
Wire and Metal Foil Sources 340
Crucible Sources 341
Sublimation Sources 343
Baffle Type Sources 343
Knudsen Cell Sources 343
Electron Beam Sources 344
Other Types of Evaporation Sources 345
Deposit Thickness Uniformity 345
 Contents xi

Evaporation of Alloys, Compounds and Mixtures 346

Introduction 346
Evaporation of Alloys 347
Evaporation of Compounds 347
Special Evaporation Methods 348
Flash Evaporation 348
Hot-Wall Evaporation 349
Close-Spaced Sublimation 350
Multi-Source Evaporation 351
Reactive Evaporation 352
Deposition Rate and Flux Monitors 354
Evaporation Source Material 355
Molecular Beam Epitaxy 355
Introduction 355
Apparatus Configuration 356
Deposition Procedure 358
Coating Growth 360
Applications 362
Sputtering 364
Introduction 364
Basic Sputtering Mechanisms 365
Sputtered Species . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
The Sputtering Yield 371
Sputtering Alloys and Compounds 376
Glow Discharge Sputtering Apparatuses 378
Planar Diodes oi, ••••••••••• 378
Assisted-Discharge Devices, Triodes " 381
Magnetrons 382
Ion Beam Sputtering 392
RF Sputtering 394
Reactive Sputtering 400
Target Fabrication 409
Thin Film Growth and Properties 410
Coating Nucleation and Growth 410
Condensation 410
Nucleation 412
Evolution of Microstructure 415
Growth of Compound Semiconductors from Multicomponent
Vapors 419
The Use of Ion Bombardment for Substrate Cleaning and
to Influence Coating Growth 422
Internal Stresses 429
Metallization of Semiconductor Devices 438
Introduction 438
Metallization Materials Considerations 438
Step Coverage 440
Radiation Damage 443
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' . . 445
xii Contents

7. DIFFUSION AND ION IMPLANTATION IN SILICON 455

Richard B. Fair
Introduction 455
Continuum Theory 456
Special Cases 456
Predeposition 456
Redistribution or Drive-In 461
Diffusion Coefficients 463
Atomic Theory of Diffusion 465
Diffusion Mechanisms 465
The Flux Equation in Diffusivity 466
Multiple Charge State Vacancy Model 470
The Role of Point Defects in Silicon Processing 472
The Silicon Processing Balancing Act 472
Point Defects 473
The Monovacancy 473
The Silicon Self-Interstitial Atom 475
Point Defect Models of Diffusion in Silicon 476
Experimental Observations 477
Diffusion in the Presence of Excess Point Defects 479
Oxidation-Enhanced Diffusion 479
Doping Dependence of Oxidation-Enhanced Diffusion 482
Effect of Chlorine on Oxidation-Enhanced Diffusion 483
Characteristics of Silicon Self-Diffusion 485
Dopant Diffusion in Silicon 488
Arsenic Diffusion Models 491
Phosphorus Diffusion Models 496
Boron Diffusion Models 501
Design Considerations for Implanted-Diffused Layers 505
Arsenic Diffusion 506
Phosphorus Diffusion 510
Ion Implantation 512
Ion Implant System 515
Simple Range Theory 515
Nuclear Stopping 519
Electronic Stopping 519
Critical Energy 520
Projected Range 521
Implantation Masking 522
Ion Channeling 527
Modeling Implanted Dopants in Silicon 528
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

8. MICROLITHOGRAPHY FOR VLSI 541

R. Fabian Pease
Introduction 541
Forming the Resist Film 542
Generation of the Aerial Image for Electron Beam Mask Making 543
Interaction of Electrons with the Workpiece 545
 Contents xi ii

Exposure and Development of Photoresist on Semiconductor

Wafers 551
Formation of the Aerial Image in Projection Mask Aligners 556
Interaction of Ultra-Violet Light with Photoresist 559
Exposure and Development of Photoresist Films on Reflective
Substrates 564
Emerging New Technologies 567
Multiple Level Resist 568
Electron-Beam Direct Write 570
X-Ray Lithography .. " 571
Vote Taking Lithography 573
References 574

9. METALLIZATION FOR VLSIINTERCONNECT AND PACKAGING .. 575

Paul S. Ho
Introduction 575
Wiring Structure 581
Impact of Device Scaling 587
Electrical Characteristics 589
Material Reaction 595
Metallization Reliability 598
Junction and Gate Contacts 598
Electromigration 604
Summary 607
References 607

10. CHARACTERIZATION OF SEMICONDUCTOR MATERIALS 610

Gary E. McGuire
Introduction 610
Surface Analysis Techniques 611
Auger Electron Spectroscopy 611
Photoelectron Spectroscopy 618
Secondary Ion Mass Spectroscopy 624
Resonance Ionization Spectroscopy 632
Rutherford Backscattering Spectroscopy 635
Summary 640
Imaging Analysis Techniques 640
Scanning Electron Microscopy 640
Scanning Transmission Electron Microscopy 647
X-Ray Topography 653
Bulk Analysis Techniques 654
Fourier Transform Infrared Spectroscopy 654
Deep Level Transient Spectroscopy 659
Photoluminescence Spectroscopy 660
Neutron Activation Analysis 664
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

INDEX 669
Introduction

Gary E. McGuire
Tektronix, Inc.
Beaverton, Oregon

There has been a major thrust throughout the semiconductor industry

to establish the capability to process Very Large Scale (VLSIC) and Ultra
Large Scale (ULSIC) Integrated Circuits, as well as, Very High Speed
Integrated Circuits (VHSIC). The generally accepted goals of VLSI tech-
nology are to produce devices with 10 6 gates or memory bits per circuit
with geometries of less than 1 micrometer. The goal of ULSI is to produce
devices with 10 7 -10 9 gates or memory bits per circuit. 1 The goals ofVHSIC
are to develop the technology to produce devices with 1 micrometer
features that have an equivalent gate clock frequency product exceeding
5 X 10 11 gate Hz/cm 2 and a minimum clock rate of 25 MHz. The goals of
ULSI and VHSIC are a natural evolution of current IC technology since the
number of devices on a single IC have nearly doubled every year for the
past twenty years. Similarly, as shown in Figure 1, the minimum horizontal
dimension has been reduced throughoutthe past decade by a factor of two
about every seven years. Even though the minimum horizontal dimension
has been reduced the overall chip length has increased as illustrated in
Figure 2.
The device parameters of gate length, junction depth and gate oxide
thickness have all decreased with each succeeding generation of product.
There is significant interaction between these parameters and device
performance. 2 As shown fn Figure 3, the gate oxide thickness has de-
creased with scaling of the active channel length. The device speed,
minimum gate delay, has also decreased with gate length, Figure 4,
yielding improvements in device performance. Part of the improved per-
formance is a direct result of shorter distances that signals must travel
2 Semiconductor Materials

20
LSI --~.I..--VLSI----+I~SUPER VLSI--+I
1K DRAM
10
• 4K DRAM
7 • 01K SRAM
• 04K SRAM
5 BK DRAM •
4 16K DRAM 16K SRAM
3 eo
MINIMUM FEATURE 64K DRAM 0 • 256K DRAM
SIZE (jon) 2
64K SRAM
oe1M DRAM
1.0 256K SRAM 1M SRAM
0.7
o
.4M DRAM
0.5 o
4M SRAM
0.4

1970 1975 1980 1985 1990

YEAR
Figure 1: Projected decrease in feature size for dynamic and static random access
memories as a function of the year of introduction.

10

V;
2:
,
0
0:::
W
:E:

i= 6
<.:>
z.
LLJ
....J
....J
LLJ
:z:
:z:
c::::e
.
5
0:::
0
I-
(.I)

V; 2
z
«
ex:
I-

2 , . 5 6 7
•
CH I P LENGTH (~1M)

Figure 2: Plot of transistor channel length versus overall chip size showing the
trend toward larger chips even though the feature sizes have decreased.
 Introduction 3

1200

W 1000
0
......,
i-
en
0> 800
c
«
-
C/)
C/) 600 •
W
Z
~
() 400
I
•
I-
W 200
0
X
0
0
a 2 3 4 5 6
ACTIVE CHANNEL LENGTH (Microns)
Figure 3: Plot of gate oxide th ickness as a function of the active channel length.

4--r----------------.. .

O-+------~---..------- ...
o 2 3 4 5
ACTIVE GATE LENGTH (Microns)
Figure 4: Plot of minimum gate delay as a function of the active gate length.
4 Semiconductor Materials

between circuits. Miniaturization also plays a large role in the steady

decrease in the energy utilized per switching operation. The trend in his
parameter, the product of power per circuit and logic delay is shown in
Figure 5. 3

"00'"
o
o

o
o

1960 1970 1980

Figure 5: Plot of the decreasing power-delay time product as a function of the

year of component introduction.

Additional device related concerns arise as a result of device' scaling.

The subthreshold scaling problem is one that posses significant techno-
logical barriers. 4 A plot of the drain current versus gate voltage for a
reference and scaled device, Figu re 6, shows that when the gate voltage is
decreased to belowthe threshold value, the channel current does not drop
linearly to zero but decreases exponentially. This rate of decrease in the
channel current in the subthreshold region is dependent on the gate
voltage and independent of the channel length at a given temperature. If
the designed threshold of the scaled device is too low, a significant amount
of current continues to flow in the channel when the gate voltage is
reduced to zero. As a result, the stored charge of a capacitor on a dynamic
random access memory (DRAM) will leak off between refresh cycles. This
phenomenon precludes scaling of DRAM threshold voltages according to
the dictates of scaling theory, and therefore precludes accurate scaling of
power supply voltages. As DRAM's are made smaller and gate insulators
are made thinner, it may be necessary to operate at higherfields across the
oxide, increase the storage capacitor area to increase the total charge
stored or replace the Si0 2 with a higher dielectric constant material in
order to minimize the effects of leakage current across the channel. 2 The
current leakage in the channel is also complicated by current leakage
around the periphe!y of the device. The leakage rate of DRAM cells around
the periphery has increased with scaling as a result of the change in the
perimeter-to-area ratio of the cell, Figure 7. 5
 Introduction 5

VOS=O.1V

DRAIN
CURRENT
(lOS)

VGATE

GATE VOLTAGE
Figure 6: Plot of the drain current versus gate voltage illustrating the lack of a
sharp cut-off voltage for VLSI devices. Reference: VLSI Technology and Design,
IEEE, O. Folberth and W. Grobman (1984).

600-------------------

•
500

400
JL (nA/em 2) @ 70°C ~.
.~.
300

200

100

1.0 1.5 2.0 2.5

PIA (X 10 em - 1)
Figure 7: Dependence of the current leakage rate of a dynamic random access
memory cell as a function of the periphery-to-area ratio. Reference: P.K. Chatter-
jee et aI., IEEE Trans. Electron Devices ED-26:486 (1979).

The shear complexity of the design of chips containing many circuits

impedes progress. Interconnecting and packaging these devices is another
area of device technology that requires significant development to circum-
vent the problems that arise as a result of device scaling. For example, the
resistance of interconnecting wires increases as dimensions are reduced.
The increasing length of interconnections on a chip as a result of the
increasing number of circuits accentuates this problem. 3
The methodology necessary for achieving ULSI and VHSI circuit
densities and dimensions are related to traditional horizontal scaling, as
well as vertical scaling. Feature sizes have historically been limited by the
6 Semiconductor Materials

lithographic techniques. However, all the available lithographies (optical,

x-ray, ion and electron beam) are capable of patterning geometries less
than 1 micrometer while maintaining acceptable alignment tolerances
and defect levels. 6 The shrinking feature size has also necessitated a
reduction in film thickness in order to achieve the desired physical dimen-
sions and electrical parameters. This has generated new materials and
process technologies to meet these changing requirements.
There are several common themes behind the emergence of these
particular technologies. Foremost among these are small area pattern
definition, registration and replication as driving forces for the various
lithographies and etching techniques. For example, anisotropic etching
removes material in the vertical direction with minimal or no etching in the
horizontal direction. This provides precise replication of the exposed
pattern. Implementation of plasma or reactive ion etching requires thor-
ough characterization of the etch rate selectivity, anisotropy, uniformity
and process reliability. Once the desired material has been deposited and
patterned, there is a need to minimize any subsequent process conditions
that will alter these properties. One approach that has been taken is to use
lowertemperature processes which minimize diffusion of dopants, impuri-
ties and contact metallization or reduce the nucleation of stacking faults,
dislocations and precipitates and dimensional changes in the substrate.
Implementation of ion implantation, chemical vapor and plasma deposition
have lowered the temperature required for many process steps. An alter-
nate approach which reduces the solid state interaction of materials is
rapid thermal processing. The process temperature is ramped up and
down quickly so that the substrate is exposed to an elevated temperature
for only a short period of time.
In addition to the new process technologies, there has been increasing
demands placed on materials. The increasing demands have pushed
some materials beyond their fundamental limits and created a search for
new or improved materials. For example, the electrical conductivity and
associated electromigration problems of Cu of Si doped AI contacts was
clearly unacceptable for VLSI circuits. This led to the development of low
resistivity refractory silicide and doped polysilicon interconnects. Smaller
geometries also dictate higher sensitivity substrates, with fewer defects
and better dimensional control.
In an ultra-small electronic structure, the device is approaching the
dimension of long-range order in the material. Forthis reason one must be
concerned with diffusion, microstructure and phase transitions within the
host material. The nucleation of thin films is generally governed by non-
equilibrium thermodynamics resulting in questions about solid phase
reactions, segregation and agglomeration. Our lack of understanding of
physical phenomena on the microscopic scale has created the need for
extensive characterization.
At the same time device geometries diminished, the analytical tools
with high spatial resolution flourished. The surface and thin film analysis
techniques x-ray photoelectron spectroscopy, Auger electron spectros-
copy, secondary ion mass spectroscopy and Rutherford backscattering
spectroscopy have grown in popularity in parallel to the decrease in the
 Introduction 7

vertical dimension of IC's. The new trace analyses technique Fourier

transform infrared, photoluminescence, deep level transient and reso-
nance ionization spectroscopy have emerged to compliment the more
traditional trace analysis technique, neutron activation analysis, reflecting
the need to characterize the higher purity materials. The low defect density
requirements for IC material$ has given a boost to the defect imaging
techniques, transmission electron microscopy and x-ray topography. The
increased complexity of ULSI and VHSI circuits has been an incentive in
the development of the electrical evaluation technique voltage contrast.
At each new stage of miniaturization physical effects and phenomena
are encountered which were previously unknown orcould be neglected. It
is easy to imagine that this tendency will continue with each new level of
miniaturization. One might expect that the obstacles will be more difficult
to overcome the closer one gets to the ultimate lim itations of the tech nology.
Although the majority of the material in this text does not directly address
these fundamental barriers, it does review the present state-of-the-art and
future directions which is in itself a reflection of the barriers that have
already been overcome.

REFERENCES
1. J.D. Meindl, IEEE Transactions on Electron Devices, ED-31 #11,1555 (1984).
2. A. Reisman, in VLSI: Technology and Design, Otto G. Folberth and Warren D.
Grobman, eds, IEEE Press, New York (1984).
3. R.W. Keyes, IEEE Transactions on Electron Devices, ED-26 #4,271 (1979).
4. F.H. Gaenssien, V.L. Rideout, E.J. Walker and J.J. Walker, IEEE Transactions on
Electron Devices, ED-24, 218 (1977).
5. P.K. Chatterjee, G.W. Taylor, A.F. Tasch, Jr., and H-S Fu, IEEE Transactions on
Electron Devices, ED-26, 564 (1979).
6. A.N. Broers, IEEE Transactions on Electron Devices, ED-28, 1268 (1981).
1
Silicon Materials Technology

William C. O'Mara
Aeolus Laboratory
Palo Alto, California

1. INTRODUCTION

This is the silicon age. Just as previous historical periods were named
by the characteristic material, we may assume that silicon will be seen as
paramount in importance to the era to which some refer as the second
industrial revolution. Certainly the transformation in the way people both
work and relax is being changed sig nificantly by electronic devices such as
computers, control systems, and audio and video products. These electronic
devices are all based on silicon, especially as used for integrated circuits.
Althoug h a large am ou nt of tech nicall iteratu re exists on si Iicon devices,
comparatively little has been written on the material itself. This is especially
true of material of an introductory nature. This chapter attempts a survey of
the way silicon is made, and includes information on material properties,
especially as modified by the presence of small amounts of oxygen. Silicon
turns out to be a fascinating substance, and readers of this view are invited
to turn to the references for further information.

2. SILICON CRYSTAL GROWTH

Pure silicon crystallizes from the melt in an open network of atoms

termed the diamond structure. It occupies the Group IV position below
carbon in the periodic table and has the same arrangement of tetrahedral
bonds found in the crystalline form of that element. Fortunately, synthetic
silicon crystals are much easier to prepare than those of carbon. They also
form the basis for the $30 billion, in 1984, semiconductor-device industry.
8
 Silicon Materials Technology 9

The method for single-crystal silicon growth was invented byTeal and
Beuhler in 1951. 1 It was an extension of earlier work by Teal and Little in
which single crystals of germanium were prepared fortransistor manufac-
turing. Germanium, like silicon, occupiesaGroup IVposition in the periodic
table, and has semiconductor properties that facilitated the initial device
manufacturing. However, the superior properties of silicon were soon
realized and the method was extended to this element. Pure material was
melted in a quartz crucible in an inert ambient, and a seed crystal was
lowered to begin controlled freezing of the melt. Dopants were added as
needed to control the electrical properties of the material. Reference 1
describes this early work in detail.
Production of silicon ingots today follows this same method, although
extensive improvements have been made in equipment, starting material
and process control. This section describes current practice, with emphasis
on material perfection and controlled impurity incorporation. Some people
refer to this method as Czochralski silicon growth, after an earlier experi-
mental method. However, this method was not designed for, nor did it
produce, single-crystal material. 2 The ability of Teal and Little to make
single crystals repeatably was crucial to the growth of the solid-state-
device industry.
Other processes have been developed for silicon-crystal growth. The
most important of these is the floating-zone method, in which the crystal is
solidified from a small molten zone resting on the crystal itself. A polycrys-
talline feed rod is lowered from above into an RF induction coil which melts
its lower end. The rate of lowering is matched to the rate of withdrawal of
the crystal from below in order to maintain a constant melt volume. This
method differs from that of Teal and Little in that no crucible is employed;
the melt is suspended and maintained by surface tension. Because the
melt is not in contact with quartz, no oxygen is incorporated into the silicon.
Some devices, such as high-voltage, high-power transistors, rectifiers and
thyristors require oxygen-free starting material. The majority of devices,
however, including virtually all integrated circuits, benefit from the presence
of dissolved oxygen and therefore require silicon grown from a quartz
crucible.
Several other processes have been investigated for the manufacture
of silicon devices. 3 These include sheet-growth methods using dendrites
orfast-growing silicon-crystal forms, growth from dies orfree-form crystal-
lization. Casting has also been employed to prepare ingots of large-grain
polycrystalline material. One product of these novel growth methods is
infrared window blanks for various applications. The main thrust of work in
this area, however, has been to prepare low-cost starting material for
photovoltaic applications. Currently, casting of polycrystalline ingots is
the most common way to prepare photovoltaic substrates.

2.1 Crystal Growth Equipment and Process

An example of the equipment used for silicon-crystal growth is shown
in Figure 1, and is represented schematically in Figure 2. The photograph
in Figure 1 shows a large water-cooled chamber which contains the
10 Semiconductor Materials

Figure 1: Photograph of a modern silicon-crystal puller (courtesy Kayex-Hamco).

 Silicon Materials Technology 11

CRYSTAL

UPPER
CRUCIBLE CRUCIBLE
SUPPORT INSULATION
PACK
LOWER
SUPPORT HEATER
INSULATOR
PEDESTAL

HEATER
CRUCIBLE CONNECTOR
SHAFT
ELECTRODE

F igu re 2: Sch emat ic cross-sect ion of crysta I pu II er .

heater, susceptor and molten-silicon charge. Mounted above the "hot

zone" chamber is the chamber into which the ingot is pulled. It is raised by
means of a chain mechanism which lifts the seed to which the ingot is
attached. The chain mechanism sits at the top of the crystal-growth
apparatus. To the right of the growth chamber, an electronic console
provides controls for heater power, seed lift, crucible and seed rotation, as
well as means for recording these for reference.
Modern crystal pullers product cylindrical silicon ingots ranging from
100 mm to 150 mm in diameter, from polysilicon charges ranging from 20
kgm to 40 kgm, with an ingot length of approximately one meter. Purified
polycrystalline starting material is loaded into a quartz crucible of 12"-14"
in diameter, along with small amounts of dopant needed to give the desired
electrical properties to the finished material. Because quartz is quite soft
at the melting point of silicon, 1425°C, the crucible is supported by a
graphite susceptor, which mounted on a graphite support which can be
rotated. This rotation helps to minimize the effects of temperature fluctua-
tions which arise from non-uniformities in heater resistance. The heater
itself is graphite formed into a cylinder and machined into a "picket fence"
which surrounds the susceptor. This forms a continuous resistive path for
current which heats it to greater than 1500°C.
12 Semiconductor Materials

In order to accomplish single-crystal growth, three things are needed.

First, a seed crystal must be used in orderthat the desired atomic arrange-
ment will be achieved. The seed crystal is suspended from the chain and
lowered into the melt. It is typical to rotate the seed in a counter sense to
the crucible rotation. This promotes a homogeneous solid-liquid interface,
needed for microscopic uniformity of dopant distribution. The second
requirement for crystal growth is to locate the melt surface with respect to
the heater so that the proper temperature gradient is achieved along the
growing ingot. This is done by raising or lowering the susceptor support.
Initially this is somewhat of a trial-and-error procedure, but once the start
position is established it remains constant for a given puller. During ingot
growth, the crucible and susceptor are raised to maintain a more or less
constant melt position with respect to the heater as the melt volume
decreases. The third requirement for crystal growth is that the central
portion of the melt be cooler than the outer portion, so that freezing can
occur locally while the melt remains in a liquid state. Because heating
occurs from the outside, this is automatically accomplished. However, very
precise control of heatercurrent is required to bring the temperature atthe
center to just the freezing point and not lower.
Molten silicon must be contained in a non-oxidizing atmosphere so
that Si0 2 formation is avoided. Nitrogen cannot be used because of silicon
nitride formation. Argon is most commonly used as the gaseous ambient,
although helium can be employed. Hydrogen, used originally by Teal and
Little, significantly modifies the properties of the material. As the molten
silicon continuously erodes the quartz crucible, silicon monoxide vapor is
evolved from the melt surface. Because of this continual vaporization,
crystal yields can be improved by reducing the pressure over the melt
surface. The reduced pressure, on the order of 30 torr, allows SiO to be
swept away from the furnace into a suitable trap where it cannot interfere
with crystal growth.
Automatic power supplies bring the heater temperature to a value
sufficient to melt the silicon, 1425°C. The seed is lowered into contact with
the melt, and the melt temperature is reduced slightly so that freezing can
begin onto the seed. Freezing proceeds laterallyfrom the 5-10 mm diameter
seed until the final ingot diameter of 100-150 mm diameter is reached. At
this point the seed lift is engaged, and further freezing adds to the ingot
height, but does not increase the diameter..Seed-Iift rates of 50-100 mm
per hour are common for these ingot diameters. The upper portion of the
crystal-growth chamber contains an infrared sensor and lens which mon-
itors the bright edge of the solid-liquid interface during growth. Any devia-
tions in the diameter of the crystal are translated into changes in seed lift
rate. These changes are automatically made in a way that brings the
dimensions of the crystal back within prescribed limits. If the diameter
increases beyond the control limit, seed lift is increased to reduce it and
vice versa for a diameter decrease. Crystal growth proceeds over the
course of several hours until BO-90 % of the melt has solidified. At this point
the ingot diameter is reduced by raising the temperature. Diameter reduc-
tion continues until the crystal tail resembles an inverted conewith a sharp
point. This practice prevents the thermal shock of furnace shutdown from
 Silicon Materials Technology 13

introducing dislocations into the lower end or tang of the crystal. These
dislocations, if introduced, could propagate upward and destroy crystal
perfection in much of the ingot.
An important improvement in crystal growth was made in the late
1950s by Dash,4 which allowed the production of ingots free of dislocations,
termed zero-D growth. The process, represented schematically in Figure
3, involves special growth conditions during the initial seeding process.
The seed is a single crystal of silicon, usually oriented along a < 100> or
<111> direction. Although it is a single crystal, in general it will contain
dislocations or extended disruptions of the lattice. As material is added to
the seed by freezing, the dislocations will propagate. By reducing the seed
diameterto 5 mm or half the initial diameter, and making use of the fact that
dislocations virtually always make at least a small angle with respect to the
vertical axis, the seed can be grown to the point at which all dislocations
have reached its surface. Once a dislocation is at the su rface, it is "pinned",
and substantial energy is required to initiate a new one. Subsequent
growth of the crystal is routinely maintained in the dislocation-free condi-
tion, and all silicon substrates are supplied in this state. The method of
Dash was crucial to the production of ingots of three-inch diameter and
larger, avoiding the tendency of large dislocated crystals to become
polycrystalline. Figure 4 shows the stages of crystal growth in a production
puller, while Figure 5 shows a completed ingot ready for further processing.

DISLOCATIONS

Figure 3: Method of Dash for dislocation-free crystal growth. Any dislocations

in the seed are allowed to grow to the surface and are pinned. 4
14 Semiconductor Materials

Figure 4: View of silicon crystal being solidified from the melt.

Figure 5: Photograph of finished ingot.

 Silicon Materials Technology 15

2.2 Dopant and Impurity Incorporation

Silicon is a good electrical insulator at room temperature in the pure
state. Dopants are intentionally added to lower the resistivity to values that
approach metallic conductivity. Silicon also possesses the property of
conducting electricity by free electrons, as in metals, or by "holes"-the
absence of a valence electron. The hole represents a well-defined conduc-
tor because the crystal lattice is essentially perfect throughout the speci-
men.
Excess holes or electrons for the appropriate conductivity can be
introduced into the lattice by adding specific dopants or impurities during
crystal growth. Elements of Group III of the periodic table cause silicon to
be p-type, or positively conducting via a hole mechanism. Group VI elements
add free electrons to the material and result in negatively conducting, or n-
type silicon. Boron is used for p-type doping, while phosphorus, arsenic
and antimony can be used for n-type silicon. The incorporation of these
elements into the melt is a function primarily of the seg regation coefficient,
a number unique to the material (silicon) and the impurity or dopant in
question.
When a relatively pure material freezes, any impurity is preferentially
rejected. The amount rejected is expressed by the segregation coefficient,

= segregation coefficient = Cs/C 1

= concentration of impurity in the solid

= concentration of impurity in the liquid.

The segregation coefficient, k, is less than one forvirtually all impurities in

silicon except for oxygen. Some common elements and their segregation
coefficients are listed in Table 1. Because the impurity is rejected by the
freezing solid, the concentration in the liquid grows as the ingot is withdrawn.
This is expressed by the following relation:
C s = C ok(1 - g)k-1

= concentration of impurity in the solid being frozen

= initial impurity concentration in the liquid
= segregation coefficient
= fraction of melt solidified.
This relation is shown graphically for a number of different values of the
segregation coefficient in Figure 6. The implication is that the seed end of
the ingot is less heavily doped with impuritythan the tang. Because of this a
resistivity variation will occur along the length of the ingot. For boron-
doped ingots this variation is a factor of two, while for phosphorus it is a
factor of three.
Figure 7 shows the resistivity variation from seed to tail of a boron-
doped ingot. The first part of the ingot contains relatively little boron, sothe
resistivity is hig h. As the melt freezes, the boron concentration bu iIds in the
melt; none is lost by evaporation. Subsequent portions of the ingot contain
ever-increasing amounts of boron, so the resistivity decreases smoothly
from seed to tang. Figure 8 shows the axial resistivity variation of a
16 Semiconductor Materials

Table 1: Segregation Coefficients and Solid Solubilities

of Some Elements in Silicon

Element -h- Solubility (atoms/cm 3)

Electrical Dopants
Boron 0.8 6 x 10 20 p-type
Phosphorus 0.35 1.5 x 1O~~ n-type
Arsenic 0.35 l.9 x 10 II

Antimony 0.023 6.8 x 10 19

Ubiquitous Impurities
Oxygen 1.25 1.2 x 10 18
Carbon 0.07 4 5 x 10 17
Nitrogen 7 x 10- 4.5 x 1015

Metals
Iron 8 x 10- 6 2x 1016
Nickel 2.7 x 10- 6 8 x 10 17
Copper
Gold
4 x
6 x
10- 4
10- 6
1.1 19
x 18
1 x 10'8
Aluminum 2 x 10- 3 2x 10 p-type

002 _I ~'~""- \
00] "-~I:::.:.-.......L..~_--J--_.J..--
I~_--L-_~--I._\~-----J
o 01 0.2 03 0.4 05 06 0.7 0.8 09
Fraction 5011 difled ,1

Figure 6: Incorporation of impurities as a function of melt fraction solidified.

Curves are shown for various values of the segregation coefficient. s
Figure 7: Plot of resistivity of boron-doped sil icon as a function of distance from
seed end. Boron segregation during growth results in a decrease in resistivity
from seed to tang end of the crystal.

11

N TYPE (111)
3 INCH DIAMETER
9

]' 7

s
>-
~
:>
~ 5
U5
UJ
a:

o 5 10 15 20
DISTANCE FROM SEED (inches)
(BREITWISER)

Figure 8: Plot of resistivity of phosphorus-doped sil icon as a function of distance

from seed end. Resistivity dip near seed end is a result of fast growth rate here
and an effective segregation coefficient greater than the equilibrium value. 6
1B Semiconductor Materials

phosphorus-doped ingot. 6 The lower segregation coefficient of 0.35,

compared to O.B for boron, leads to a steeper resistivity gradient along the
ingot. In addition, th is particu lar ingot shows a resistivity variation near the
seed end which does not follow the impurity incorporation expression for
normal freezing. After the ingot has reached the desired diameter, the
initial portion of the ingot is often withdrawn at a greater rate than the lower
portion. This fast freezing causes impurities, especially those with low
segregation coefficients, to be incorporated in a non-equilibrium fashion.
The deviation is always towards an "effective" segregation coefficient
which is larger than the equilibrium value, which explains the high phos-
phorus concentration (low resistivity) in the seed end of the ingot of Figure
B.
In addition, local fluctuations of dopant concentration can occur be-
cause of changes in growth rate or temperature. These can cause a
sudden increase in dopant level as the process deviates from equilibrium.
As a result, the uniformity of resistivity across a silicon wafer may vary by
±200/0, for the case of phosphorus. This variation is shown on a local scale
by means of spreading resistance measurements in Figure g.-Local vari-
ations of boron are typically less than ±1 0%.

J:
== (3
>- ~ CZOCHRALSKI GROWNN PHOSPHORUS (100) 3" WAFER
~ ~ G
~z
(iJ ~ j
cr'--'
~
6

~ 8
>- ~ 7
3f=C-~ 6

~ ~ 5
~ u ~1)=21%
IT:
~ CZOCHRALSKI GROWN 'N' PHOSPHORUS (111) 3" WAFER
o

10 20 30
DISTANCE FROM CENTER - MILLIMETERS

Figure 9: Fluctuations in resistivity from center to edge of a phosphorus-doped

wafer. Instantaneous growth-rate fluctuations also change the effective segrega-
tion coefficient.
 Silicon Materials Technology 19

2.3 Incorporation of Oxygen

In addition to intentionally added dopants, oxygen is incorporated into
silicon crystals due to the dissolution of the quartz crucible. Any material in
contact with molten silicon will dissolve, with vitreous silica dissolving at
one of the lowest rates. It is the only material suitable to contain the melt,
and provides a source of oxygen to the melt thro'ughout the growth
process. The rate of dissolution of the crucible is a fu nction of the tempera-
ture at the crucible wall, and the stirring currents which sweep the oxygen
into the interior. An added factor is the escape of oxygen from the melt
surface in the form of SiD. This latter factor is a constant while the oxygen
source diminishes throughout the growth process. The source of oxygen is
a function of the surface area of the crucible wetted by the melt which
decreases throughout the growth process.
This means that the oxygen incorporated into the crystal at the seed
end is the maximum amount possible for a given set of growth conditions.
Given fixed seed and crucible rotations, the oxygen level will decrease
from seed to tang end of the crystal. This is shown in Figure 10 for a3-inch-
diameter ingot. Modeling of this behavior has been presented by Carlberg
et al. l Because SiD is escaping from the edge of the solid-liquid interface,
the oxygen level is lower at the edge than the center. This fall-off in oxygen
level is shown in Figure 11. This data was obtained from the same 3" dia-
meter ingot as Figure 10.

25
..... I -
- I -

~ - I -
~ - ..4~ -
0.. ']l
e:. 20 ~
..............
z
!~~
- -
0
- -
~
<! - -

~~
cr: - -
~
z 15
~
w
() -

~
Z -
0
-
~
()
z - -
w
(9 10
>- - -
x
0 - -
r- -

SEED 3 6 9 12 15 18 TAIL
DISTANCE FROM SEED (INCHES)

Figure 10: Axial gradient of oxygen in a silicon crystal. Oxygen measured accord-
ingtoASTM F121-80.
20 Semiconductor Materials

20
~.
Q.

E-
z
o 15
~
«c::
f--
Z
w
•
~ 10 • TAIL
o
u
z
w
t9
>- •
3 5

o 10 20 30 40
DISTANCE FROM CENTER OF INGOT (mm)

Figure 11: Radial variation in oxygen level.

Ingot manufacturers have attempted to develop ways to control the

level of oxygen in crystals. This is because the oxygen level affects wafer
performance in several ways, some beneficial, others harmful to device
yield and performance. Oxygen at some level is essential forthe majority of
devices, and is the reason why float-zone silicon, which is oxygen-free,
cannot be used in the vast majority of device applications. In the standard
crystal-growth method of Teal and Little, the control of oxygen level is
primarily obtained by the variation of seed and crucible rotations. 8 In this
way, the stirring currents that sweep oxygen intothe melt and past the solid-
liquid interface are controlled. The limits on this control are due to the fact
that seed and crucible rotations also control the uniformity of dopant
incorporation for electrical resistivity. This limits the oxygen levels to a
range of 10-20 ppmA for standard crystal-growth processes.
The direct determination of the segregation coefficient of oxygen in
silicon byYatsurugi et al. indicated a value of k= 1.25. 9 This value has been
the subject of recent dispute, with indirect determinations orestimates of k
= 0.3 to k = 1.4. 10 A value of k greater than one suggests two distinct
oxygen species, since the "interstitial" oxygen incorporation was shown
by Yatsurugi to have k= 1.0. The predominant form of oxygen in silicon is
this interstitial species, which actually consists of oxygen lying between
two near-neighbor silicon atoms, forming a nearly linear Si-O-Si structure
in place of the Si-Si bond. It is not a true interstitial species. If the segregation
coefficient of this species is 1.0, and the overall segregation coefficient is
1.25, then a second form of the atom in the lattice is indicated. The original
suggestion forthe form of this second species was small oxygen clusters 9 .
I have suggested that the second oxygen species exists in the form of a
fully substitutional atom, which is incorporated into the lattice with a
segregation coefficient of 0.25. 11 This idea can help to explain many of the
puzzling features of oxygen in silicon, such as the existence of oxygen
striations in silicon,12 and the striated distribution of the oxygen donor in
the material. 13 Effects related to precipitation of oxygen from solution are
discussed in a later section.
 Silicon Materials Technology 21

2.4 Incorporation of Carbon

Carbon has a low segregation coefficient of 0.07, which means it is
strongly rejected by the freezing si licon. It is never intentionally added as a
dopant, but may be present from one of three sources. The polysilicon
charge itself may contain carbon, but this is unusual. At times, the silicon
charge may contain previously melted silicon, or "remelt." This remelted
silicon is enriched in carbon from the previous segregation. Finally, the
melt may entrain carbon from CO gas passing over it. The source of this gas
is a water or oxygen leak in the furnace which reacts with hot graphite.
The three situations are depicted in Figure 12. The maximum level of
carbon is due to remelt in the original charge.. The next-lower level of
carbon is due to standard polysilicon in a furnace operated at one atmos-
phere pressure. When the overpressure is reduced to 30 torr, the CO
entrained in the melt is much reduced, and the lower curve of carbon
incorporation is obtained. As will be shown later, high levels of carbon are
uniformly detrimental to material and device performance.

10

5
0

2
~
Q.
e:.
z
Q 1
.....
<!
0:
.....
Z
w .5
u
z
0
u
z
0
en
0: .2
<!
u

.1

.05

.03
.2 .4 .6 .8 1.0
FRACTION GROWN

Figure 12: Carbon concentration versus fraction of melt solidified for three con-
ditions of crystal growth: circles represent the maximum level of carbon due to
remelt in the original charge, triangles represent crystals grown with standard
polysilicon at atmospheric pressure and squares present data for material grow·n
with standard polysil icon but a reduced pressure of 30 torr.
22 Semiconductor Materials

3.0 WAFER PREPARATION

3.1 Mechanical Shaping Procedures

As-grown silicon ingots are subjected to a number of mechanical and
chemical operations to prepare slices orwafers ready for device manufac-
ture. The mechanical steps begin with grinding of the ingot to make it
perfectly cylindrical, followed by the grinding of one or more flats along its
length. The flats define specific crystal planes in the material such as the
(100) or (11 0) planes, and serve to identify wafer orientation and type. The
flatting procedure is guided by X-ray orientation of the ingot. Diamond-
tipped grinding tools similar to those in many machine shops are used for
this procedure. Grinding and flatting operations, as well as the subsequent
mechanical operations of slicing, lapping and edge rounding, introduce
subsurface work damage into the material. Great care is taken to avoid
cracks and fractures, and the remaining damage is subsequently removed
by etching.
Silicon ingots are produced with flats for two purposes. Originally,
finished die on a waferwere separated for packaging by scribing along the
directions of crystal planes and breaking the wafer into squares along
directions of easy cleavage. The orientation flat at one side of the wafer
served to guide the alignment for scribing. Although die separation is now
more commonly done by means of a diamond saw, the crystal planes are
still chosen for sawing. In addition, automatic handling equipment makes
use of the flat for wafer orientation in photolithographic mask alignment
and other operations.
An additional function of wafer flats is the use of a second, minorflat in
combination with the primary(11 0) flat to identifywafertype and orientation.
This function has been standardized by the Semiconductor Equipment
and Materials Institute (SEMI), a trade organization of suppliers to the Ie
industry. Figure 13 shows schematically the four combinations offlats that
identify p- and n-type, and (111) and (100) orientations. This allows visual
verification of these parameters and helps to avoid mixing of wafer lots.
After grinding, the ingot is mounted on a graphite beam for slicing.
Again, X-ray orientation serves to ensure that cuts are made on the correct
crystal orientation. Most (100) oriented ingots are cut parallel to the (100)
0
plane. (111) oriented crystals can either be sliced on orientation, or 3-5 off
orientation towards (11 0). The latter choice is made when an epitaxial
silicon layer will be grown on the wafer in order to improve the growth
kinetics of the layer. Figure 14 shows a schematic diagram of the slicing
process. The mounted crystal is held near a thin stainless-steel blade
which is coated with diamond grit on its inner surface. The blade resembles
a drum head with a central hole, and is rotated in a spindle at several
thousand RPM. The blade is lowered at a rate of 1-3 inches per minute
through the silicon, cutting a wafer or disk from the ingot. Indexing equip-
ment allows the setting of wafer thickness. If the blade does not cut true,
either bow or taper can be introduced into the slice as shown in the figure.
These undesirable deviations from flatness can be detected by an eddy
current sensor, shown mounted above the blade near the crystal. The
 Silicon Materials Technology 23

1
4
----...-----4
45°
PRIMA RY .
FLAT \
I pRIMARY
FLAT

"?,SECONDARY
FLAT
{",} n - TYPE {1"} P - TYPE

I
~, \

T
I P RIM ARY ..----r-----11 Tp RIM A R Y
t
T 1-----'-----..10...----4

SECONDARY
,-t.:
LAT I j -lFLAT
~90°
I
FLAT ~ SECONDARY
FLAT

{ 100} n - T YPE ~
{ OO} P- T YPE

Figure 13: Semiconductor Equipment and Materials Institute (SEM I) standard

flat locations for sil icon wafers.

sensor indicates blade deviation which can be corrected by appropriate

dressing of the grit.
Sliced wafers receive two additional mechanical operations. The wafer
edge is rounded or contoured to reduce edge chipping in subsequent use.
In addition, the front and rear surfaces are made flat and parallel by
planetary lapping. In th is operation, a SiC or A1 2°3 slu rry is used to remove
a small amount of silicon while the wafers are rotated between two steel
plates. This operation leaves wafers flat to as little as 1 ,um deviation of
flatness over the entire wafer diameter.

3.2 Wafer Etching

Mechanical machining to produce a wafer of the desired thickness
and flatness produces a layer or skin on the wafer which is work damaged,
containing numerous dislocations. The damaged layer is removed by a
chemical etching step, which may also reduce work-induced stress and
remove contaminants introduced into the material. Etching can be done
using a mixture of hydrofluoric, nitric and acetic acids, or by using a caustic
KOH bath. The former technique produces a smooth, featureless surface,
whereas the latter etch leaves the surface with microscopic pits and a
specular appearance. KOH etching is finding favor because of its ease of
handling and disposal.
24 Semiconductor Materials

,
Crystal \ Blade
\ Axial Blade

~
\ ---Movement

Blade

blade
/

5 4 3 2 1

Figure 14: Schematic of ingot-sl icing operation. Blade mounting and cond ition-
ing are done carefully to allow for straight cuts. Blade deviation can result in
either bow (cuts 1 and 3) or taper (cuts 1 and 2) in the slice.

Chemical etching is sometimes followed by a re-introduction of damage

in a controlled fashion on the backside of the wafer. D~mage is introduced
by sandblasting with fine quartz spheres, or by abrasion with sandpaper. A
shallow network of dislocations is introduced into the wafer surface. Some
users find this damaged layer helpful in preventing haze formation on the
front side of the wafer during initial oxidation. As a result, wafers treated in
th is way are supplied at customer request. A recent alternative approach is
to deposit a layerof polysilicon on the wafer backside, which functions in a
similar way to abrasion.
A new operation is being introduced into wafer manufacturing, often
after the etching step, in which a laser is used to mark the wafer surface
with an identification code. This code contains pertinent information about
 Silicon Materials Technology 25

the wafer characteristics, and can be read visually or with an automated

reader. The code number is generally placed on the front surface near the
major flat.

3.3 Polishing
Front-surface polishing of the wafer leaves it with a mirror finish
needed for device fabrication. Wafers are mounted on carriers for this
operation, held either by a thin wax layer or by a friction bond to the carrier.
These carriers are pressed onto a rotating polishing pad of polymeric
material while a polishing slurry is applied. Generally the process consists
of two steps on two different polishing machines. In the first step, perhaps
0.001" orone mil of silicon is removed from the surface in a process termed
stock removal. The carrier is then moved to a mach ine with a smoother pad
surface for final, mirror-finish polishing.
The polishing slurry consists of a solution of colloidal silica maintained
at a pH of 11 for stock removal and a pH of 9 forfinish polish. The function of
the silica in the polishing process is not understood. It is probable that the
product of the polishing process is silica itself. That is, the surface of the
wafer is oxidized and hydrated to form a silica that can be wiped away by
the pad. It is curious that one must add the reaction product to initiate the
polishing process. The silica acts as some sort of catalyst, and the primary
polishing agent is probably water!15

3.4 Cleaning
The final step in wafer preparation is a careful cleaning of the surface. A
sequence of acids and bases is used to remove any contaminants, including
wax residues, if any, and metallic contaminants in the polishing medium.
The cleaning process is assisted by adding hydrogen peroxide to oxidize
these materials, and by heating the liquid baths. The basis for chemical
cleaning has been established by Kern. 16
The final bath in chemical cleaning process is usually chosen so that
the wafer surface is hydrophilic, orwater-Ioving. This means that the water
wets the surface as the wafer is withdrawn from the bath, and can be
removed uniformly. A combination of ammonium hydroxide and hydrogen
peroxide is an example of such a bath. On the other hand, a wafer
withdrawn from a hydrofluoric acid bath will be hydrophobic, and waterwill
bead on its surface. This beading can lead to spots on the surface after the
water dries. The difference between a hydrophilic and hydrophobic surface
consists of the difference in the native oxide thickness. Silicon will instantly
grow a thin oxide upon emerging from a chemical bath. In the hydrophobic
case, the oxide thickness is 1 OA or so, while for the hydrophilic case the
oxide thickness can range from 15-50}\, depending on bath characteristics.
This can lead to variations in thickness of a subsequent thermal oxide
layer. This variation is important for thin gate-oxide-Iayer growth in MaS
device fabrication.
Throughout the fabrication process, wafers are inspected for a variety
of parameters including physical dimensions, electrical resistivity, flatness
and surface perfection. Afterfinal inspection, most wafers are packaged in
26 Semiconductor Materials

Class 100 clean rooms in such a fashion that the cleanliness will be
maintained until use by the customer.

4. MATERIAL PROPERTIES

4.1 Crystal Structure

Silicon crystallizes in an open, low-density structure termed the diamond
lattice structure, wh ich it shares with the gemstone modification of carbon,
the single-crystal form of germanium, and one of the crystalline forms of tin.
In this structure, each atom is bonded to four near neighbors arranged
tetrahedrally about the central atom. The local arrangement is repeated
throughout the crystal, giving rise to the unique properties of the material.
Atoms are joined to each other by Sp3 hybrid covalent bonds, which are
quite stable. The bond strength is 25 kcal per moleforsilicon, and the near-
neighbor spacing is 2.35A. If one looks at a silicon lattice containing
several atoms, he can see that a cubic structure is formed. A diagram of this
structure is shown in Figure 15. There are actually two interpenetrating
cubic structures, with an atom at each cube face. The cube side has a
dimension of 5.43A.
The regular crystal structure of covalent bonds is quite inert. Very pure
silicon is a good electrical insulator with an energy of 1.11 eV required to

Figure 15: Silicon lattice structure.!?

 Silicon Materials Technology 27

detach a valence electron from one of the covalent bonds. This property, as
well as some other important properties of silicon, are listed in Table 2.
Silicon is useful for electronic devices because the electrical properties
can be modified by the addition of impurities or dopants. For example,
phosphorus or other Group V atoms substitute for silicon atoms at lattice
positions when added during crystal growth. 13 However, phosphorus has
an extra valence electron, which is easily removed from the vicinity of the
donor atom, and contributes to electrical conduction as in a metal.
On the other hand, if a Group III element such as boron is added as an
impurity, a property unique to semiconductors is manifest. Boron also
substitutes for silicon, maintaining the perfect lattice structure. But boron
has only three of the required four valence electrons, so that one of the
valence bonds is "short" an electron. This electron deficit is termed a hole.
The hole can migrate when an adjacent electron jumps into the bond
lacking one electron. Under the influence of an electric field in boron-doped
silicon, the electrons jump from valence bond tovalence bond. The effect is
as if the "hole" migrates in the opposite direction.
Because silicon can be doped both with donors (such as phosphorus)
and acceptors (such as boron), two types of electrical conduction are
possible in the material. Because of the perfect crystal structure, the
regions of different doping can be maintained permanently separated,
allowing fabrication of resistors, diodes, and transistors in different portions
of the material. The existence of a native oxide allows metallic interconnects
and capacitors to be made on the surface of the wafer, the sum total
constituting an integrated circuit of great complexity.

4.2 Electrical Properties

Figure 16 shows the resistivity versus impurity density for n-type
(negative or electronic conduction due to donors) and p-type (positive or
hole conduction due to acceptors) silicon as determined by Irwin. After a
donor such as phosphorus or arsenic is added to the lattice, it loses its
identity, uniformly adding one carrier per impurity atom. This is true forthe
commonly used donors and acceptors whose carriers are thermally excited
at room temperature, and thus are fully ionized. Polynomial fits to these
curves have recently been published in a form useful for small-computer
data reduction. 19 ,2o
Although each dopant atom adds one carrier to the lattice, the electrical
properties differ depending on whetherthe carrier concentration is high or
low. This is expressed in terms of carrier mobility, which is the average
velocity of excess carriers per unit electric field. When carrier concentration
is low, mobility is relatively high, since the carriers "see" only a perfect
silicon lattice and scattering is minimized. However, when carrier concen-
trations approach 10 17 /cm 3 , the quantity of impurity atoms is great enough
to perturb the electrons or holes. The dopant atoms scatter or screen the
carriers, reducing the mobility. Figures 17 and 18 show this effect as a
function of carrier concentration for n- and p-type silicon. It is for this
reason that high-speed devices are designed using lightly doped silicon.
The velocity for carriers in silicon is shown in Figure 19 as a function of
electric field. The maximum velocity is a function of the material itself, and
28 Semiconductor Materials

Table 2: Some Properties of Silicon

Atomic Weight 28.09

Atoms/cm 3 4.995 x 10 22
Crystal Structure Diamond
lattice Constant (~) 5.43
Density (grams/cm 3 ) 2.33
Melting Point (oC) 1420
Density of Surface (atoms/cm 2 )
14
(100) 6.78 x 10
(110) 9.59 x 10 14
(111 ) 7.83 x 10 14
Energy Gap (eV) 1.11
Density of States/cm 3
Conduction Band 2.8 x 10 19
Valence Band 1.04 x 10 19

Intrinsic Carrier Concentration

10
ni (/ern 3 ) 1.45 x 10
n. 2(/cm6 ) 2.103 x 10
20
1
Intrinsic Resistivity (n-cm) 2.3 x 105
Dielectric Constant 11.8
Refractive Index 3.4
Hardness (Moh) 7
Elastic Constants (dynes/cm 2 )
1.67 x 10 12
0.65 x 10 12
0.79 x 10 12

Young's Modulus (dynes/cm 2)

(111) dire ct i on 1.9 x 10 12
Bulk Modulus (dynes/cm 2) 7.7 x 1011
Heat of Fusion (k ca1/mo1e) 12.1
Thermal Conductivity (cal/sec/em/oC) 0.3
at ZOoC
Expansion on Freezing
(volume increase)
Linear thermal coefficient of 2.33 x 10- 6
expansion (/oC) at 2S oC
 Silicon Materials Technology 29
104

103

102

Eu 10
~
0-
r 10°
~

>
~
en 10- 1
en
LU
a:
10- 2

10- 3

10- 4 ..._ - - - _....._ _...._ _....._ _..._ _...._--------~

1m pu rity concentration (em - 3)

Figure 16: Resistivity of sil icon as a function of n- and p-type dopant concen-
tration, for carrier concentrations 10 14 -1 021jcm 3 ,18

1400 -~-I~--
--I' .,. -r-~

UQ) 1200
V'
I Si
+oJ
1000
0
>
---
N
800
E
u
600
+oJ
>-
..0
400
0
~ 200

Donor Concentration (em --3)

Figure 17: Electron mobility in silicon as a function of carrier concentration?1

30 Semiconductor Materials

500
u
Q)

I 400
+-oJ
"0
C
N
300
E
u 200

-g 100
~

o .----L_ _-'---_ _ .Jo.---..._ _. - l L . - - _ - - - - I ._ _ ---l---

10 1 4 10 15 10 1 6 10 1 7 10 1 8 10 1 9 10 20 10 2 1

Acceptor Concentration (em -3)

1
Figure 18: Hole mobil ity in sil icon as a function of carrier concentration.2

Eiectrons
-~-----~-'_._--
+oJ
>-
U
0_
Qj ~
> t/')

~Eu
.-
~
~
ctl
-
U

Electric Field (V/cm)

Figure 19: Carrier velocity in silicon as a function of electric-field strength. 21

so is about the same for electrons and holes. Because of the lower hole
mobility, the field at which velocity saturation is reached is greaterthan for
electrons.

4.3 Optical Properties

At wavelengths shorter than the band gap energy of 1.11 eV, silicon is
an excellent absorber of optical energy. Since this includes the visible and
near-infrared portions of the spectrum, silicon can be used as a solar cell,
with collection efficiencies near 20% of the impinging photons.
For the mid and far infrared portions of the optical spectrum, undoped
silicon is transparent. As free carriers are added, the transmission diminishes.
The absorption spectru m for n- or p-type silicon possesses a characteristic
 Silicon Materials Technology 31

minimum, whose wavelength changes as a function of doping. This provides

a basis for resistivity measurement using optical absorption in the wave-
length region of 1-100 ,um. Figures 20 and 21 show plots of the plasma
minimum wavelength versus carrier concentration for n- and p-type silicon.
This technique for resistivity determination has recently been extended to
doped polysilicon films as well as single-crystal material. 23
There are a variety of impurities in the silicon lattice which give rise to
local mode absorption in the infrared. This is absorption of optical energy
by the impurity nucleus, which vibrates with characteristic frequencies
against the surrounding silicon lattice. The impurity vibrations lie in the
infrared region of the spectrum, and can be used for quantitative analysis.
This is especially important in determining oxygen and carbon levels,
since they are normally electrically inactive. Other types of quantitative
determination of carbon and oxygen are slow and tedious compared to
infrared. Reviews and recommended procedures are available both for
oxygen 24 and carbon analysis. 25

4.4 Mechanical Properties

It is only recently that the mechanical properties of silicon have been
studied. Peterson 26 reviewed the materials properties with a view towards
the manufacture of micromechanical devices. Sumino et al. 27 described
plastic deformation. These properties are important in terms of wafer

100

E
..3-
.t>
'~

~
E
~

,§ 10
.=E
~
t
~

~
s

Carrier concentration (cm- 3)

Figure 20: Wavelength of the plasma minimum for electrons in silicon as a func-
tion of carrier concentration.2 2
32 Semiconductor Materials

100

E
2-
~
';
'f;
IV

~
E
:::J
10
E
'c
'E
~
~
~
~

10 20
Carrier concentration (cm - 3 )

Figure 21: Wavelength of the plasma minimum for holes in silicon as a function
of carrier concentration. 22

warpage induced by thermal shock in semi conductor-device processing.

The presence of oxygen in the lattice plays an important role in minimizing
warpage induced by thermal shock in semiconductor-device processing.
small precipitates,29 can prevent the propagation of dislocations in silicon.
Oxygen thus plays a role in silicon analogous to that of carbon in iron; small
amounts of impurity provide mechanical strength that is much greaterthan
forthe pure material. Nitrogen can also serve to strengthen silicon, although
it is much more difficult to incorporate during crystal growth.

5. PROCESS-INDUCED DEFECTS

5.1 Oxidation-Induced Stacking Faults

Stacking faults are excess silicon atoms that coalesce to form a
"platelet" which lies between two adjacent (111) planes. Because the
platelet or stacking fault fits between planes, the surrounding lattice is
strained. After a certain strain is reached, the lattice will rupture, producing
a dislocation loop which bounds the fault. Heat treatments such as oxida-
tion can cause the nucleation and growth of stacking faults. 3D Normally
they are electrically inactive, but they can serve as diffusion pipes 31 and
are generally undesirable near the wafer surface where the active-device
regions are located. The defects are produced in silicon in quantities which
depend on crystal-growth conditions, oxygen level, and electrical dopant
 Silicon Materials Technology 33

(boron or phosphorus).32 Generally, material near the seed end, where

growth conditions vary the most, contains a higher level of stacking faults
after a standard heat cycle. While the level of oxygen also affects the
stacking-fault density, it is of secondary importance. Figure 22 shows the
strong variation in stacking-fault (SF) density and oxygen level as a fu nction
of crystal position in boron-doped silicon. A phosphorus-doped ingot
grown by the same experimenters showed stacking-fault levels nearly
three orders of magnitude higherthan forthe boron-doped case. Whilethe
exact cause forthis is not known, it is possibly due tofluctuations in doping
levels, or striations, that are much greater in the case of phosphorus than
for boron.
The bulk stacking faults discussed here are to be distinguished from
surface stacking faults which arise from other causes. As first mentioned
by Rozgonyi,33 bulk and surface stacking faults can be distinguished from
each other by etching and optical microscopy. The surface variety are due
to impurities, scratches, abrasions and so forth. This is another indication
of the importance of the cleaning process prior to each high-temperature
step in order to avoid formation of surface stacking faults.

5.2 Saucer Pits

Certain defects are seen on the silicon-wafer surface after oxidation,
oxide removal, and defect etching. 34 These are termed saucer pits or
shallow pits due to their smooth, featureless appearance. Their appearance
is associated with epi stacking faults, if an epitaxial layer is subsequently
grown. In addition, most capacitors built on regions of high saucer-pit

13 ~
u
10 5 .........

I 12 E
E Oxygen concentration B
co
~
4 "
?: 10 110
'r:;;
C X
Q)
o 10 .2
+-'

~ 10 3
+-'

LL ~
Cl
9 cQ)
C u
~
c
o
~ 10 2 8 u
ci5 c
Q)
Cl
>
X
o
5 10 15
Distance from Seed (cm)

(Diado et a/.)

Figure 22: Stacking-fault concentration as a function of wafer position in the in-

32
got. Faults are seen after an oxidation procedure. Oxygen level is also shown.
34 Semiconductor Materials

densitywill show undesirably low minority-carrier Iifetimes. 35 Recent experi-

ments have determined the presence of fast-diffusing metallic impurities
as the source of these defects. 36 Their elimination is accomplished by a
variety of "gettering" techniques, including back-side abrasion or poly-
silicon deposition, mentioned in a previous section. In addition, oxygen
precipitation in the bulk of the wafer can constitute an "internal gettering"
mechanism which also prevents the formation of shallow pit defects. This
is discussed in the final section on oxygen-related effects in wafer process-
ing.

5.3 Carbon-Related Defects

Commercially available silicon wafers generally contain carbon at
levels of 5 x 1 0 16 atoms/cm 3 or less. 80th producers of polysilicon and
wafer manufacturers routinely inspect material to ensure low levels of this
impurity. This is because carbon in concentrations above rv1 x 10 17
atoms/cm 3 can produce defects which degrade device performance. The
section on crystal growth mentioned the incorporation of carbon as a
function of the low segregation coefficient (k = 0.07), and its incorporation
from the gas ambient in the growth furnace. Figure 12 shows carbon
incorporation at various levels depending on starting material purity and
growth conditions. Ordinarily, the curve corresponding to the lowest carbon
levels applies to commercial material. When the carbon level approaches
7-10 ppma in the growing crystal (corresponding to a melt concentration of
100 ppma or so), silicon carbide will form at the solid-liquid interface,
terminating single-crystal growth.
At levels below this, carbon is incorporated as individual substitutional
atoms in the lattice. If the dissolved carbon level is greater than 2-4 ppma,
subsequent heat treatment may cause it to precipitate. In one case, silicon
wafers with a carbon concentration of 4 ppm a (2 x 10 17 atoms/cm 3 ) were
heat-treated according to an MOS process cycle. 14 Various platelet-like
defects were formed. A Secco etch showed characteristic teardrop-shaped
etch pits, as shown in Figure 23. Transmission-electron microscopy showed

Figure 23: Optical micrograph of etch pits due to carbon-related defects in sil i-
con. Features delineated by Secco etch on 100 surface. 14
 Silicon Materials Technology 35

platelet formation due to precipitation from solid solution. The precipitates

caused lattice strain which was relieved by dislocations in the surrounding
silicon. One of the micrographs showed a platelet morphology character-
istic of f3-SiC, as shown in Figure 24.1 n addition to minimizing carbon levels
so that such defects do not form during processing, gettering processes
for this element have recently been investigated. 37

6. OXYGEN IN SILICON

6.1 Oxygen in As-Grown Silicon

The properties in oxygen in silicon are both a subject of great interest
and great dispute. Experiments designed to measure a certain property
often give apparently different results when done by different investigators.
The problems begin with the determination of the segregation coefficient,
and extend through the precipitation of oxygen from solid solution during
device fabrication. The reason for conflicting resu Its may be due to the lack
of a reference condition for the silicon itself. That is, a given wafer used for
an experiment may have oxygen in a different state than another one used
for the same experiment, even if the oxygen level as measured by infrared
absorption is the same.
6.1.1 Quantitative Analysis of Oxygen in Silicon. Oxygen was
discovered to exist in crucible-grown silicon by Kaiser and Keck in 1957. 38
Since then, considerable effort has been expended in studying its incorpor-
ation into the lattice, since the properties of the material are so greatly
influenced by the presence of small amounts of this element. The amount
of oxygen incorporated during crystal growth is a strong function of the
growth conditions themselves, as mentioned previously. In addition, quanti-

Figure 24: Transmission electron micrograph of (3-Si precipitate formed by heat-

treating carbon-rich silicon. 14 (Photograph courtesy of J. Peng.)
36 Semiconductor Materials

tative measurement of oxygen levels has proven to be difficult, and results

from different laboratories have varied widely. In order to measu re oxygen
levels, direct chemical analysis of some sort is necessary. Trace levels of
this element exist in most environments, including equipment used forthe
analysis, so different groups have obtained widely varying results. Vacuum
fusion has been used to calibrate the infrared absorption at 9 ,um due to
oxygen, which is shown in Figure 25. 38 Once the calibration is done, the
intensity of absorption can be used for non-destructive measurement of
the oxygen level, in the range of 5 x 10 16 - 10 x 10 17 atoms/cm 3 . Most silicon
contains oxygen at a level of 5-10 x 10 17/cm 3 .
The varying calibration results obtained by different groups were
reviewed by Patel. 39 This has resulted in confusion in quoting oxygen
levels when only infrared is used, and reference is made to only one of the
experimental procedures. Recently an extensive re-evaluation of the
measurement was performed by the Japan Electronic Industries Develop-
ment Associati.on,4o and this calibration agrees closely with the original
one of Kaiser and Keck, as well as previous work by Japanese researchers. 41
According to this work, the concentration of oxygen is obtained by multiply-
ing the absorption coefficient of the 9 ,um line by the value 3.03 ± 0.02 X
10 17 atoms/cm 2 •
6.1.2 Interpretation of Infrared Absorption Spectra. The absorp-
tion at 9 ,um is due to a well-defined species termed interstitial oxygen. This
is not a true interstitial in the sense of a free atom which resides in the
openings between silicon bonds; rather, the oxygen forms two strong

o
o
o

o
U)
r---
a
Wo
(.Jo

~~
~o
o
(f)
(0
([

o
U)
(\J

o
81",,-,,-----
0
1400 1'000 800 600 400
WAVENUMBERS

Figure 25: Infrared spectrum of sil icon containing oxygen and carbon. Two peaks
due to oxygen are seen.
 Silicon Materials Technology 37

bonds with near-neigh bor silicon atoms, with a nearly linear Si 20 structure.
The bond angle is 150°-160°.42 The absorption spectrum can be analyzed
as if the Si 20 species existed as a gas, or in other words, as if the silicon
lattice wasn't there at all. The 9 /Lm band is termed the asymmetric stretch-
ing mode of this species. Such a species should show other infrared-active
modes as well.
Figure 25 shows a line at 513 cm 1 or 19.5 /Lm, which is also due to
oxygen. In early studies, this line was thought to be another vibrational
mode of the interstitial oxygen species. However, Bosomworth and co-
workers showed that this could not be SO,42 and the line has remained
unassigned and a source of some controversy. In 1980 I first proposed that
this line was due to oxygen in another site, most probably substituional. 43
The evidence for this assignment came from examining the low tempera-
ture absorption frequencies of isotopes of boron, carbon, and oxygen in
silicon which are shown in Table 3.
The frequencies of Table 3 are plotted versus 1/yffiand are shown in
Figure 26. The straight-line relationship indicates that a simple harmonic
oscillator describes the motion for all the isotopes, indicating that all the
impurities occupy a lattice site with the full Td symmetry of the "diamond"
structure. This means either a true interstitial, or a fully substitutional site.
Baker and co-workers have shown that addition of carbon to pure silicon
causes the lattice to contract in a monatonic fashion until SiC precipitates
from solution. This is strong evidence that carbon exists in a substitutional
site,47 and contrasts strongly with the effect of "interstitial" oxygen, which
expands the lattice. 48 Taken together with the assumption that boron is
also substitutional, this implies that oxygen exists as a substitutional as
well as an interstitial species in oxygen.

Table 3: Low Temperature Absorption Frequencies

for Light Elements in Silicon

Isotope Freguency (cm-') Reference

0 18 506 43

016 517 43

C14 573 44

13
C 590 44

C12 611 44

811 623 45

810 646 45
38 Semiconductor Materials

700

650

I"
E
2
>-
u
z 600
w
~
d
w
a:
u..

550

500 - - - - - - - - - - - - - - - - - - - -
.25 .30
1/y'm

Figure 26: Plot of infrared absorption frequency of Iight elements in sil icon ver-
sus inverse square root of atomic mass. The oxygen absorption near 19.5 pm is
related to carbon and boron absorptions.

The existence of two oxygen species can explain many puzzling

aspects of the behavior of this element in silicon. First of all, it explains how
the segregation coefficient can be greater than one. 11 Incorporation into
two sites in the lattice would proceed independently, but since the same
atom is involved, the individual segregation coefficients would be additive.
It has been shown 9 that the segregation coefficient of the interstitial
species is 1.0, and that the total seg regation coefficient of oxygen in silicon
is 1.25. Therefore the substitutional species has a value of k=0.25. Such a
low value is consistent with other substitutional atoms with excess elec-
trons, such as phosphorus with k = 0.35. It can explain other phenomena
associated with oxygen which are discussed in succeeding paragraphs.
6.1.3 Solid Solubility. The solubility of oxygen in silicon is a strong
function of temperature. Figure 27 shows solubility versus temperature
over the range commonly employed for oxidation and diffusion. The data
are taken from an article by Craven,49 and are plotted according to the
J El DA calibration for infrared absorption. The solid sol ubility at the melting
point isrv2 x 10 18 atoms/cm 3 , but normal crystal-growth processes give
oxygen levels of 5-10 x 10 17/cm 3 . It is important to note that at lower
temperatures the solubility will correspond to a value less than the as-
 Silicon Materials Technology 39

1400 1200 1000 900

10 ..... ....... ..- ....... ..- ...
19

M 10 18
~
>-
~
5
~
co
:::>
...J
0
(I)
Z
w 10 17
">x-
0

10 16

6 8 9

104/T[K]

Figure 27: Oxygen solubil ity versus inverse temperature. Data of Reference 49
are plotted according to the infrared calibration of Reference 40.

grown level. This provides a driving force for precipitation from solution
when the wafer is heated to lower temperatures for oxidation or other
processes. This is the basis for much recent work on controlling such
precipitation for purposes of internal gettering, discussed below.
As is true with other physical properties of oxygen in silicon, the
solubility as a function of temperature is apparently different when meas-
ured by different researchers. The results determined by Craven agree
well with those determined by Hrostowski and Kaiser,50 and Takano and
Maki,51 but other researchers have obtained quite different results (see
the review by Patel 39 for references).
6.1.4 Diffusion Coefficient. The diffusion of oxygen plays an im-
portant role in the creation of defect-free surface layers during device
manufacture, the formation of precipitates, and the formation of donors in
the 450°C temperature range.
Oxygen is a very fast diffuser in silicon, and the diffusion properties
have been measured over a wide temperature range by Mikkelsen. 52 The
results can be expressed in the relation

o= 0.07 exp (-2.44eV/kT) cm 2/sec.

which gives the diffusion coefficient as a function of temperature. Standard

complementary error-fu nction solutions to the diffusion equation apply to
40 Semiconductor Materials

the diffusion of oxygen in silicon. These results agree quite well with those
obtained by Takano and Maki. 51
At low temperatures, in the range 300°-500°C, the situation is more
complicated, and again oxygen demonstrates its duality. An optical exper-
iment was performed which gave an indirect way of obtaining the diffusion
coefficient in this temperature range. 53 The results of the experiment
yielded two quite different diffusion coefficients, depending on the prior
heat treatment of the material. In one case, the diffusion coefficient had the
same value as extrapolated from the high-temperature work cited previ-
ously.51,52In this case, the material had been heated above 1200°C priorto
measuring the diffusion coefficient. It is quite possible that the heating
step produced an equilibrium distribution of oxygen among different sites
which does not exist even in the as-grown case. The second diffusion
coefficient was measured to be one hundred times fasterthan the first one,
and was seen after extended heating at 900°C. At this temperature,
departure from equilibrium is quite probable. The two values of the diffusion
coefficient can be due to the predominance of the interstitial or substitu-
tional species proposed earlier. 43
6.1.5 Donor Formation. A property unique to oxygen in silicon is its
ability to form electrically active complexes when heated at 450°C. This
phenomenon was reported prior to the discovery that crucible-grown
material contained oxygen. 54 The temperature range of donorformation is
quite narrow (::=; ±50°C), indicating a specific mechanism for the process.
The rate of formation and maximum concentration depend on the oxygen
level. The formation rate is proportional to the fourth power of the (interstitial)
oxygen concentration, while the maximum concentration is proportional
to the third power of the oxygen level. These and other properties of the
donor have been reviewed by Gosele and Tan. 55 The formation rate can be
as high as 1013carriers/cm3. sec, and donors can reach a maximum level of
'"\.,5 x 1016/cm 3. Evidently some electrically active complex of more than
one oxygen atom is responsible for the donor behavior. Based on the
formation kinetics, an Si0 4 complex was suggested by Kaiser, Frisch and
Reiss,56 although no reason for the electrical activity was suggested.
Oxygen is a double donor, with levels at 60 and 120 milli-electron volts.
Low-temperature infrared studies show that more than one donor state is
formed, depending on the time of heating at 450° C.5? Heating at tempera-
tures in excess of 500°C causes the donors to disappear. One practical
consequence of this phenomenon is the appearance of donors in as-
grown crystals, due to cooling of the ingot in the growth chamber. Most
wafer manufacturers use a heating step in the range 650-700°C to eliminate
donors formed during ingot cool-down. 58 Otherwise, the resistivity due to
intentionally added dopant would be impossible to measure. Both the
process of donor formation and an nih ilation appear to be due to some sort
of polymerization behavior which can lead to rods, platelets or other
shapes of SiO x precipitates at higher temperatures.
Recently, a convincing model for the oxygen donors was proposed by
Keller. 59 1n this model, three interstitial oxygen atoms surround a substitu-
tional oxygen species in next-near-neighbor locations. Nine configurations
are possible for a strain-free four-oxygen complex. The substitutional
 Silicon Materials Technology 41

oxygen can release two valence electrons to the conduction band once
the strain is compensated. This is the first model to effectively combine all
the observations about the oxygen donor and lends additional credence to
the idea of interstitial and substitutional species existing independently in
the lattice.
One final point about the oxygen donor concerns its formation during
IC-chip fabrication. Device manufacturers often anneal or alloy wafers to
improve ohmic contact of aluminum to silicon, or to remove silicon-silicon
dioxide surface states in MOS gates orcapacitors.lfthe annealing temper-
ature is chosen to be 450°C, as is sometimes done, the resistivity of the
substrate can be su bstantially changed. A slightly lowertemperature, such
as 400°C, will avoid donor formation during this anneal step.

6.2 Precipitation from Solid Solution

In the as-grown state, oxygen 'is ordinarily well dispersed throughout
the material. In device manufacturing, wafers are heated to temperatures
in the range 900-1 200°C for oxidation, diffusion and insulating film deposi-
tion. The oxygen incorporated into the lattice during crystal growth is in a
condition of supersaturation at these temperatures. It will precipitate as
SiO x given enough time and the proper nucleation. When precipitation
does occur, it can happen uniformly throughout the material or non-
uniformly in circular or ring-shaped patterns. These latter are sometimes
referred to as "oxygen swirl," but are disti nct from swirl defects identified in
float-zone silicon. Abe has shown that non-uniform oxygen precipitation
results from growth-rate fluctuations during the crystal-growth process. 12
Manufacturers attempt to minimize these fluctuations and provide wafers
in which oxygen precipitates uniformly.
Uniform precipitation is termed homogeneous, and can be predicted
and controlled. The number of precipitates formed is determined by a
relatively low-temperature "nucleation" process, which consists of heating
for several hours at a temperature in the range 600-900°C. Note that some
wafers may previously have received such an annealing step for purposes
of donor annihilation, which must be taken into account when nucleation is
performed as a separate step in wafer fab. Nucleation causes the formation
of very small cl usters of oxygen atoms, on the order of 1OA in size. 5o These
nuclei serve as sites for precipitation during subsequent high-temperature
processing.
Intentional precipitation of oxygen is carried out as a means of "getter-
ing" trace metallic impurities. Assuming that the wafer receives a thorough
cleaning prior to a high-temperature process, the main source of these
impurities is the furnace heating elements. 51 Metals diffuse through the
quartz furnace liner, and are deposited on the wafers. Metals such as iron,
copper, and nickel are very fast diffusers in silicon. Although the gettering
process is not completely understood, one result suggests that metal
atoms diffusing through the wafer can be entrained in a growing SiO x
precipitate. 52 Once in the precipitate, they are trapped and electrically
inactive. If metals remai n free, however, they can seriously degrade device
performance. The starting oxygen level and the nucleation cycle are
42 Semiconductor Materials

chosen so that precipitation occu rs throug hout the device-man ufactu ring
process. In general, these will differ significantly for bipolar and MOS
processes, and the sequence is usually tailored for each process line. It is
important to leave enoug h unpreci pitated oxygen so that the wafer retains
its mechanical strength and warpage is prevented. 28

6.3 Denuded Zone Formation

In order to employ controlled precipitation of oxygen in wafer fab, a
surface-denuding step is generally required. In this operation, oxygen is
out-diffused from the surface so that its concentration falls to a low value.
Then, since the surface oxygen level is belowthesolubility level during subse-
quent high-temperature treatments, precipitation will not occur and the
active-device region remains precipitate-free. The denuding temperature
and time can be selected based on the initial oxygen level. 63 Optimum
temperature is in the range of 1000-11 OO°C. The denuding step can be
performed before or after nucleation, and may coi ncide with initial oxidation.
Figure 28 shows a wafer cross-section after angle lap and defect etch. The
wafer has received the three-step sequence of denuding, nucleation and
precipitation. A high density of precipitates is seen in the interior of the
wafer, while the surface is defect-free.

wafe r surface

denuded zone

precipitates

Figure 28: Optical micrograph of angle-lapped and etched silicon wafer. Denuded
zone and bulk oxygen precipitates and stacking faults are seen. (Photograph
courtesy of W.M. Bullis.)
 Silicon Materials Technology 43

6.4 Device Application

Controlled oxygen precipitation for impurity removal is becoming
common practice for many device lines. MaS memories constitute one
class of devices whose yield depends on in-process precipitation. Metallic
impurity removal results in very high minority-carrier lifetimes near the
surface, which translates to long refresh times, very desirable in memo-
ries. 62 Bipolar devices can also show improved yields due to "gettering."
Other applications for oxygen precipitates are also being explored.
High precipitate density in the bulk of the wafer reduces minority-carrier
lifetimes in this region, thereby suppressing the flow of lateral currents.
This effect h-as been applied to the su ppression of cross talk in memories,64
and in optical sensor arrays.65 In the latter example, high precipitate
density also resulted in improved immunityto latchup in CMOS devices on
the same chip. It is quite likely that other ways to control the electrical
properties of silicon will be found based on effects due to oxygen.

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of Polycrystalline or Impure Semiconductors and Novel Silicon Growth Meth-
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Silicon 1981," H.R. Huff, R.J. Kriegler, and Y. Takeishi, ed., Electrochem. Soc.,
New York, 1981, p. 101.
9. Y. Yatsurugi, N. Akiyana, Y. Endo, and T. Nozaki,J. Electrochem. Soc. 120: 1975
(1973).
10. R.J. Jaccodine and C.W. Pearce, in "Defects in Silicon," W.M. Bullis and L.C.
Kimerling ed., Electrochem. Soc. New York, 1983, p. 115.
11. W.C. O'Mara, in "Defects in Silicon," op cit., p. 120.
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Sirtl, ed., Electrochem. Soc. New York, 1977, p. 95.
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H.R. Huff, R.J. Kriegler, and Y. Takeishi, ed., Electrochem. Soc., New York, 1981,
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14. W.C. 0' Mara and D. Guidici, Electrochem. Soc. Extended Abstracts, Spring 1979.
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1950, p. 6.
18. J.C. Irvin, Bell Sys. Tech. J. 41: 387 (1962).
19. W.R. Thurber, R.L. Mattis, Y.M. Liu, and J.J. Filliben, J. Electrochem. Soc. 127:
1807 (1 980).
44 Semiconductor Materials

20. W.R. Thurber, R.L. Mattis, Y.M. Liu, J.J. Filliben, ibid, 127: 2291 (1980).
21. D.M. Caughery and R.E. Thomas, Proc. IEEE 55: 219Z (1967).
22. P.A. Schumann, Jr., Solid State Technology, 13: 50, (January 1970).
23. J.P. Lavine, F.C. Lo, F. Moser, B.C. Barkey, and F.T.J. Smith, in Electronic and
Optical Properties of Polycrystalline Semiconductors, K.V. Ravi and W. 0' Mara,
ed., Electrochem. Soc., New York, 1980, p. 96.
24. ASTM Procedure F120-75 and F121-80, Amer. Soc. Test. Mat., Philadelphia, 1985.
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27. K.Sumino, in Semiconductor Silicon 1981, op cit. 208.
28. Y. Kondo, in "Semiconductor Silicon 1981" op cit., p. 220.
29. H.D. Chiou, J. Moody, R. Sandford, and F. Shimura, in VLSI Science and Tech-
nology/1984, K.E. Bean and G.A. Rozgonyi, eds., Electrochem. Soc., New York,
1984, p. 59.
30. C.W. Pearce and G.A. Rozgonyi, in Semiconductor Silicon 1977, H.R. Huff and E.
Sirtl, ed., Electrochem. Soc., New York, 1977, p. 606.
31. C.J. Varker and K.V. Ravi, in Semiconductor Silicon, 1977, op cit., p. 785.
32. K Daido, S. Shinoyama, and N.lnoue, in Rev. Elec. Comm. Labs (Japan) 27:33(1979).
33. G.A. Rozgonyi and T.E. Seidel, in Semiconductor Silicon, 1977, op cit., p. 616.
34. A list of etchants for revealing process-induced defects may be found in Solid
State Technol., Nov. 1983, p. 111.
35. G.A. Rozgonyi and C.W. Pearce, Appl. Phys. Lett. 32: 747 (1978).
36. R.A. Craven, T. Shimura, R.S. Hockett, L.W. Shive, P.W. Fraundorf, and G. Keefe-
Fraundorf, in VLSI Science and Technology/1984, KE. Bean and G.A. Rozgonyi,
ed., Electrochem. Soc., New York, 1984, p. 20.
37. W.E. Bailey, R.A. Bowling, and KE. Bean, in Defects in Silicon, op cit., p.204.
38. W. Kaiser and P.H. Keck, J. Appl. Phys. 28: 822 (1957).
39. J.R. Patel, in Semiconductor Silicon 1977, op cit., p. 521.
40. T. lizuka, S. Takasu, M. Tajima, T. Arai, T. Nozaki, N. Inoue, and M. Watanabe, in
Defects in Silicon, op cit., p. 265.
41. T. Nozaki, Y. Yatsurugi, and N. Akiyama, J. Radioanalyt. Chem.4: 87 (1970).
42. D.R. Bosomworth, W. Hayes, A.R.L. Spray, and G.D. Watkins, Proc. Roy. Soc.
A317: 133 (1970).
43. W.C. O'Mara, Electrochem. Soc. Extended Abstracts 80-1: 475 (May 1980).
44. H.J. Hrostowski and R.H. Kaiser, Phys. Rev. 107: 966 (1957).
45. R.C. Newman and J.B. Willis, J. Phys. Chem. Solids 26: 373 (1965).
46. S.D. Smith and J.F. Angress, Phys. Lett. 6: 131 (1963).
47. J.A Baker, T.N. Tucker, N.E. Moyer, and R.C. Buschert, J. Appl. Phys. 39: 4365 (1968).
48. W.L. Bond and W. Kaiser, J. Phys. Chem. Solids 16: 44 (1960).
49. R.A. Craven, in Semiconductor Silicon 1981, op cit., p. 254.
50. H.R. Hrostowski and W. Kaiser, J. Phys. Chem. Solids 9: 214 (1959).
51. Y. Takanoand M. Maki, in Semiconductor Silicon 1973, H.R. Huff and R.R. Burgess,
ed., Electrochem. Soc., New York, 1973, p.469.
52. J. Mikkelsen, Appl. Phys. Lett. 40: 336 (1982).
53. M. Stavola, J.R. Patel, L.C. Kimerling, and P.E. Freeland, Appl. Phys. Lett. 42: 73
(1983).
54. C.S. Fuller and R.A. Logan, J. Appl. Phys. 28: 1427 (1957).
55. U. Gosele and T.Y. Tan, Appl. Phys. A28: 79 (1982).
56. W. Kaiser, H.L. Frisch and H. Reiss, Phys. Rev. 112:1546 (1958).
57. D. Wruck and P. Gaworzewski, Phys. Stat. Solidi aS6: 557 (1979).
58. W.C. O'Mara, J.E. Parker, P. Butler, and A Gat, Appl. Phys. Lett. 46: 299 (1985).
59. W.W. Keller, J. Appl. Phys. 55: 3471 (1984).
60. N. Inoue, J. Osaka, and K. Wada, J. Electrochem. Soc. 129: 2780 (1982).
61. P.F. Schmidt and C.W. Pearce, J. Electrochem. Soc. 128: 630 (1981).
 Silicon Materials Technology 45

62. R. Huff, H.F. Schaake, J.T. Robinson, S.C. Baber, and D. Wong, J. Electrochem.
Soc. 130: 1551 (1 983).
63. J.M. Andrews, in Defects in Silicon, op cit., p. 133.
64. H. Otsuka, K. Watanabe, H. Nishimura, H. Iwai and H. Nihira, IEEE-ED Lett 3:
1982 (1982).
65. C.N. Anagnostopoulos, E.T. Nelson, J.P. Lavine, K.Y. Wong and D.N. Nichols,
IEEE Trans. ED-31: 225 (1984).
2

The Thermal Oxidation of Silicon

and Other Semiconductor Materials

Bruce E. Deal
Research Center
Fairchild Semiconductor Corporation
Palo Alto, California

1. INTRODUCTION AND BACKGROUND

The thermal oxidation process associated with semiconductor tech-

nology has been used primarily in conjunction with silicon and silicon
containing materials. Attempts to thermally oxidize germanium and com-
pound semiconductors have been generally unsuccessful, except by
employing a field-assisted process such as anodizing. More often,
deposited oxides and dielectrics have been used to passivate compound
semiconductors, while germanium is not a significant factor in today's
semiconductor industry. A description of CVD (chemical vapor deposition)
and other deposition processes used for dielectric films in semiconductor
applications is included in other chapters of this volume.
Silicon semiconductortechnology has depended heavily on the thermal
oxidation process since the 1950's, when silicon devices were first
developed. Initially, thermal oxides were used to selectively mask dopants
during the fabrication of diffused transistors. 1 Additional investigations at
that time by Atalla, Liginza, Spitzer, and otherworkers at Bell Laboratories
provided considerable information about silicon thermal oxides, especially
their passivation properties. 2 ,3 These investigations led in 1960 to two of
the most important developments of semiconductortechnology: the Planar
process invented by Hoerni,4 and the MOS transistor which was first
disclosed by Kahng and Atalla. 5
46
 Thermal Oxidation 47

Many investigations related to silicon thermal oxidation and other

types of dielectric films have been undertaken since 1960. 6 ,7 These have
resulted in a number of technological developments and have helped to
make possible the amazing growth of the semiconductor industry. Some of
the uses of thermal oxides and dielectric films in today's semiconductor
technology are listed in Table 1. Thermal silicon dioxide is and will most
likely continue to be the mainstay of silicon device technology, even as we
move into the realm of sub-micrometer VLSI and beyond.

Table 1: Uses of Dielectric Films in Semiconductor Technology

• COMPONENTS IN DEVICES
• CORROSION PROTECTION
• DEVICE ISOLATION
• DOPANT DIFFUSION SOURCE
• GETTER IMPURITIES
• INCREASE BREAKDOWN VOLTAGE
• INSULATE METAL LAYERS
• MASK AGAINST DOPANTS
• MASK AGAINST IMPURITIES
• MASK AGAINST OXIDATION
• MECHANICAL PROTECTION
• PASSIVATE JUNCTIONS
• SMOOTH OUT TOPOGRAPHY

This chapter deals primarily with the thermal oxidation of silicon. The
kinetics of silicon thermal oxidation is first reviewed, with emphasis on the
general oxidation relationship and the thin oxide regime. Important oxide
properties are then summarized. Following is the most important part of
the chapter, a description of process variable-oxidation reaction inter-
dependencies. Some of the variables included are effects on silicon
surface properties (dopant redistribution, charges), surface property
effects on the oxidation process (orientation, doping, cleaning), and
ambient effects (type, chlorine addition, pressure). After a discussion of
oxidation mechanisms, the chapter concludes with a section on other
oxidation processes and an indication of thermal oxidation applications
and trends with respect to future semiconductor devices.

2. SILICON THERMAL OXIDATION KINETICS

The thermal oxidation process provides superior passivating charac-

48 Semiconductor Materials

teristics for silicon devices as compared to the various deposited dielectric

processes. Used in combination, however, with other dielectrics (e.g.
deposited silicon nitride over thermal oxide), the most stringent require-
ments can be met. In the thermal oxidation process, silicon reacts with
either oxygen or water vapor (steam) at temperatures between 600 and 0

1250°C to form silicon dioxide. The oxidation reaction may be represented

by the following two reactions:

1J

2]

Special marker experiments 8 have demonstrated that oxidation pro-

ceeds by the diffusion of either an oxygen or water species through the
oxide already formed which then reacts with the silicon at the Si-Si0 2
interface. As oxidation continues, the interface moves intothe silicon and a
new, clean silicon surface is produced. As a result, original silicon surface
states (unsatisfied bonds) and contamination are consumed and optimized
device passivation is achieved. From the densities and molecularweights
of silicon and amorphous silicon dioxide, it can be shown that for every
thickness X o of oxide formed, 0.45 X o of silicon is consumed. The exact
nature and charge of the diffusing oxidation species (° 2,0,°2-,0-, H20,
H3 0+, OH-, etc.) have not yet been identified. It is known, however, that for
steam oxidation, considerable exchange occurs between the already
formed silicon dioxide and the diffusing water species. On the other hand,
very little exchange takes place between oxygen and the oxide network.
Thermal oxidation of silicon is normally carried out in a fused quartz
tube in a resistance heated furnace. The silicon wafers are placed vertically
in slots in a flat quartz "boat," most present day furnaces accommodating
up to 200 four to six-inch diameter wafers. For dry 02 oxidation, high purity
oxygen from a liquid source is transported into the furnace tube through
suitable regulators, valves, traps, filters, and flowmeters. For a number of
years, water or steam oxidation was carried out by bubbling 02 or N 2
through a flask of deionized water maintained at a particular temperature.
Thus, aspecified vapor pressure of water could be provided in theoxidizing
ambient. More recently, however, pyrogenic systems 9 have been employed
which permit H 2 to react with 02 at the inlet end of the oxidation tube, thus
providing water vapor of much higher purity and control.
Silicon oxidation data are obtained by determining oxide thickness
(x o) as a fu nction of oxidation time (t) and other variables such as oxidation
temperature and silicon orientation. Typical results are given in Figure 1
and 2, which contain plots of log X o vs log t for silicon oxidation at various
temperatures in dry 0 210 and pyrogenic steam. 11

2.1 General Relationship

As indicated earlier, silicon thermal oxidation proceeds by the diffusion
 Thermal Oxidation 49

- (111) Si
o (l00) Si
0.5

E::i.
en 0.2
(f)
w
z
G 0.1
.-I
w 0.05
o
x
o
0.02

1.0 10.0 100.0

OXIDATION TIME (hr)

Figure 1: Oxide th ickness vs oxidation time for sil icon oxidation in dry oxygen
at various temperatures (after Hess and DeaI 10 ).

2.0-----.----.---.--.,...........r"'?""I""--~...,......--r-~"""'T"'T"~----r----,

1.5
1.0

0.5
E
::L

en
en
w
z
~
u
I
.-

-(111}Si
o (100) Si

0.2 0.5 1.0 2

OXIDATION TIME

Figure 2: Oxide thickness vs oxidation time for silicon oxidation in pyrogenic

steam ("'640 Torr) at various temperatures (after DeaI 11 ). Reprinted by permis-
sion of the publisher, The Electrochemical Society, Inc.
50 Semiconductor Materials

of an oxidizing species through the oxide already formed. This process is

indicated in Figure 3.lt has been proposed by Deal and Grove 12 that during
thermal oxidation three consecutive reactions occur whose fluxes are
equal under steady-state conditions. These are denoted in Figure 3 and are
su mmarized below, along with the expressions wh ich represent the fl uxes
(flux (F) is defined as the number of molecules-in this case oxidant-
crossing a unit surface area in a unit time).

Si02 Si

Partially
Ionized
Silicon

Figure 3: Schematic illustration of the sil icon thermal oxidation process.

(a) Transfer of the oxidant from the gas phase to the oxide
outer surface:
F1 ~ h (c* - Co) 3J
where h is a gas-phase transport coefficient, Co is the
concentration of the oxidant in the outer oxide surface,
and C* is the equilibrium concentration of the oxidant in
the oxide, and assumed to be proportional to the partial
pressure of the oxidant in the gas ambient.
(b) Diffusion of the oxidizing species through the oxide to the
silicon:
F
2
= -Deff Co-Ci
x
o
where Deft is the effective diffusion coefficient of the
oxidizing species in the oxide, C 2 is the oxidant concentra-
tion in the oxide near the Si-Si0 2 interface, and Xo is the
oxide thickness.
(c) Reaction of oxidizing species with silicon at the Si-Si0 2
interface to form Si0 2 :
F s: k C1 [ 5J
3
where k is the interface reaction rate constant.
 Thermal Oxidation 51

By assuming all the above fluxes to be equal, the following general

oxidation relationship has been derived. 12
x o 2 + Ax 0 = B(t+T) [ 6aJ
also written in the form
x 2 _ x. 2 x - x .~
o ~ + o =t [ 6bJ
B B/A

where X o = oxide thickness, t = oxidation time, and A, B, r, and Xi are

constants as defined below:
A = 2 Deff(l/k + l/h) [ 7J
B 2 D
eff
c* /N 1 [ 8J
T = (x . 2
~
+ Ax.) /B
1
[ 9J
where Deff effective oxidant diffusion constant in the oxide;
k,h rate constants at the Si-Si0 2 and gas-oxide interfaces;
C* equilibrium concentration of the oxide species in oxide;
N1 number of oxidant molecules in the oxide unit volume; and
Xi oxide thickness at the start of oxidation.

Two limiting forms of Equation 6 can be noted. At large oxidation

"times," i.e. t»A2/4B and t»r

x 2 -= Bt [10J
o

This equation represents a parabolic oxidation and B is the parabolic

rate constant.
For small oxidation "ti mes," t« A2/4 B and the Iinear oxidation expression
is obtained:
Xo = B/A (t+T) [11J

S/A is the linear rate constant.

From Equations 7 and 8 it can be noted that when the oxidation
process is controlled primarily by the parabolic rate constant (at high
temperatures or thick oxides), the kinetics are affected by changes in the
diffusion process or oxidant solubility in the oxide. The latter is proportional
to ambient pressure. On the other hand, at low temperatures or for thin
oxides, where the linear rate constant predominates, the oxidation is also
sensitive to oxidant solubility in the oxide (and ambient pressure) but
depends on those factors affecting the interface rate constants hand k.
These effects will be discussed in more detail later.
Special mention should be made of the correction factor r which is
related to initial oxide thickness x 1 in Equation 9. It has been noted that for
oxidation in dry O 2, an initial thickness region does not appear to be
satisfied by the general relationship Equation 6. Rather, the plot of oxide
thickness versus oxidation time tends to extrapolate through the thickness
52 Semiconductor Materials

axis at about x = 150A. Thus, in the absence of a model for oxidation in this
region, the practice has been to assign a value of r corresponding to Xi =
150A. Further discussion on the mechanism of thermal oxidation forthese
very thin oxides is presented in the next section.
The thermal oxidation of silicon can be represented by Equation 6 fora
wide range of temperatures, oxide thicknesses, orientations, and oxidation
ambients, provided the dependence of the rate constants Band BI A as a
function of these variables is known. Values of the rate constants have
been determined by rearranging the general relationship Equation 6 into a
linear expression, plotting Xo vs (t+r)/x o and extracting B as the slope and
-A as the intercept from the resulting plots. Arrhenius expressions of the
form

C -- CIe -E/kT [12]

have been used in plotting log B and log BI A vs 1 IT. Such plots are
presented in Figures 4 and 5, and values of the constants for the Arrhenius
expression are tabulated in Table 2. These data can be used to determine
any thickness-time relationship for a given set of oxidation conditions.
Similar data are incorporated in the SUPREM program 13 and related
computer process modeling programs.

1.0

~
~

'"E
C\I

::L H2 0 (640 Torr)

E A =0.78 eV
en
l- 0.1 "- ~
z
~
en
z
0
u
""
w
t:ta::
0.01
u
:::::i
0
en
<t
a::
~

0.001
0.6 0.7 0.8 0.9 1.0
1000/T (OK)

Figure 4: Dependence of the parabolic rate constant B on temperature for the

thermal oxidation of silicon in pyrogenic steam (---640 Torr) and dry oxygen
(after Deal!!). Reprinted by permission of the publisher, The Electrochemical
Society, Inc.
 Thermal Oxidation 53

~
~

E 1.0
~

~
m
t- 0.1
z
~
c.n
8 • (111) Si
0(100) Si
w 0.01
~
a::
B/A (111)
a:: B/A (100) =1.68
<X
~ 0.001
:J

o.OOOl~_----'- _ _....L....-_-----I._ _--'--_-----J

0.6 0.7 0.8 0.9 1.0 1.1
1000/T (OK)

Figure 5: Dependence of the linear rate constant BfA on temperature for the
thermal oxidation of sil icon in pyrogenic steam (~640 Torr) and dry oxygen
ll
(after Deal ). Reprinted by permission of the publisher The Electrochemical
I

Society Inc.
I

Table 2: Dependence of Silicon Oxidation Rate Constants on Temperature

PARABOLIC B. -- C1 e-E 1 /kT

LINEAR

(111) SILICON
DRY 02 C1 =7.72x10 2 p.m 2 /hr

C2 = 6.23 x 10 6 ~m/hr
E 1 = 1.23 eV
E2 = 2.0 eV
STEAM C1 = 3.86 x 10 2 l1m2/hr
(PYROGENIC)
C2 = 1.63 x 10 8 p.m/hr
E 1 =0.78 eV
E2 = 2.05 eV

(100) SILICON C2 (100) = C2 (111)/1.7

54 Semiconductor Materials

2.2 Thin Oxide Formation

As indicated above, considerable experimental evidence is available
which suggests a different or modified reaction mechanism for dry 02 thermal
oxide formation below 200A. This difference has resulted in the requirement
(in the case of dry 02 oxidation) for the use of a constant, 'r, in the general
relationship, Equation 6. A number of investigators have attempted to
model the thermal oxidation process in the very thin regime, but as yet no
one satisfactory relationship has been established. Likewise, the exact
characterization of thin oxide properties, electrical, physical, etc., has not
yet been accomplished. These properties are undoubtedly related to the
kinetics of thin oxide formation and also make accurate th ickness measure-
ments quite difficult.
Among the first to investigate the mechanisms involved in the initial
stages of silicon thermal oxidation were van der Meulen and Ghez. 14,15
They proposed complex reactions at the Si-Si0 2 interface involving both
molecular and atomic reactions with silicon. Thus, various reported pressure
dependencies of the oxidation reaction on oxygen partial pressures could
be explained, with p1.0 dominating forthickeroxidesand pO.5 being prevalent
in the thinner oxide regime. Blanc 16 has proposed a similar model but with
only a pO.5 dependence for thin oxide formation. This, however, does not
satisfy pressure dependencies observed for thicker oxides.
More recently Massoud and Plum mer 17 have suggested that the in itial
stages of silicon oxidation in dry 02 may be represented by the following
equation:

[13 ]

In this expression, the first term on the right-hand side is the contribution
from the original linear-parabolic model. The second term incorporating L 1
is possibly related to effects of residue left on the silicon surface from the
cleaning treatment (X o :::; 15A). The contribution of L2 has not yet been
explained. Subsequently, Han and Helms 18 have proposedthata mechanism
based on parallel diffusion reactions provide even a better fit to oxidation
data over the entire thickness range.
It is important for future applications of devices having sub-micrometer
feature sizes and film thicknesses in the nanometer range (especially
MOS gate and capacitor oxides), that reaction mechanisms be understood
and characterized for oxides in the very initial stages of formation. The
investigations described are a good step in that direction.

3. PROPERTIES OF THERMAL OXIDES

Thermal silicon dioxide (Si0 2) produced by the oxidation of silicon in O2

or H20 at elevated temperatures is essentially amorphous silica. Its proper-
ties are almost identical to those of the fused quartz tubes in which most
oxidations are carried out. The molecular structure is a random version of
 Thermal Oxidation 55

crystalline quartz with each silicon atom tetrahedrally surrounded by four

oxygen atoms. In turn each oxygen atom is bonded to two silicon atoms.
Thermal oxides act as somewhat of a barrierto high-temperature diffusion
of the common dopants B, P, As, and Sband can be used as a maskagainst
ion implantation. Forthese cases, masking is limited and suitable masking
data curves must be used to ensure that the species are prevented from
pene,trating into the substrate. On the other hand, alkali impurity ions, such
as Li+, Na+, K+, and even H+ or H 2 0 can diffuse rapidly through thermal
oxide, even at relatively low temperature. In general, other more dense
dielectric films, such as silicon nitride or phosphosilicate glass, are used in
combination with thermal oxide to passivate against these impurities.
Thermal Si0 2 is normally quite stable chemically. The most common
etchant is an HF-based solution. Optical and electrical properties are
similar to those of fused quartz.
Electrical properties of thermal oxides are extremely critical with
respect to device performance and reliability. Such parameters, as conduc-
tivity, carrier trapping characteristics, and oxide charges, can have an
appreciable effect on today's small-geometry integrated circuits. These
properties have been evaluated by appropriate techniques for varying
preparat'ion conditions. 19 Also critical to devices is the defect density of
passivating oxides. Many investigations have been reported that are
related to dielectric strength, pinhole density, and other oxide properties
which result primarily from impurity incorporation during processing. 2o A
number of common properties of thermal Si0 2 are listed in Table 3.
Various techniques are used to measure properties of thermal oxide
films. One of the most important properties, thickness, is determined
primarily by ellipsometry or other spectrophotometric or interferometric
methods. Typical film thicknesses range from over 1 J-Lm to below 100Ain
special devices. Since structural and optical properties of the thinnerfilms
may differ from bu Ik properties, some difficulties arise in thin oxide measure-
ments.

4. PROCESS VARIABLE/OXIDATION REACTION DEPENDENCIES

The silicon thermal oxidation process has been found to be a direct

function of a number of process variables, including silicon surface proper-
ties. Conversely, some important silicon surface properties are dependent
on the oxidation process. In Figure 6, one form of the general oxidation
relationship (Equation 6b) is re-presented, with an indication of some of
the physical variables wh ich contri bute to the oxidation reaction th roug h the
individual components of the rate constants. In this section, some of the
important inter-relationsh ips between process variabl'es and the oxidation
process are discussed.

4.1 Effects of the Oxidation Reaction on Surface Properties

4.1.1 Oxide Charges. At least fourgeneral types of electrical charges
have been observed to be associated with the thermally oxidized silicon
56 Semiconductor Materials

Table 3: Properties of Thermal Silicon Oxides (2SoC unless indicated)

Physical Properties

Formula

Molecular weight 60.08

3 22
Molecules/cm 2.3 x 10
3
Density 2.27 gm/cm

Melting point

Specific heat 1. 0 Joule/gOC

3
Vapor pressure 10- Torr at l450 0C

Thermal conducti vi ty 0.014 watt/cmoC

Linear coefficient of 0.5 x 10- 6 °C-1

expansion
7
Young's modulus 1 x 10 psi

El.ectrical Properties

Resisti vi ty 5 x 1015 n-cm

Dielectric constant 3.9

7
Dielectric strength -1 x 10 V/cm

Energy gap _8 eV

Optical Properties

Refractive index °
1.462 at 5459 A

Absorption coefficient ~o for E < 8 eV

Chemical Properties

Etch rate (1:10 HF:H 0) °

5 A/sec
2
16
Oxygen solubility 5.5 x 10 cm-3 at 10000C

Water solubility

structure. 21 ,22 These charges and their locations are indicated in Figure 7,
which is a representation of an oxide cross section similar to that shown in
Figure 3. The symbols selected to denote these charges 23 are based on
the following:

Q = effective net charge per unit area at the Si-Si0 2 interface

(C/cm 2),
N = Q/q = net number of charges per unit area at the Si-Si0 2
interface (number/cm 2 ),
o = net density of interface trapped charges per unit area and
energy (number/cm 2 -eV),
q = charge of an electron.
 Thermal Oxidation 57

GENERAL RELATIONSHIP
(Xo - Xi)
+ BIA

PARABOLIC RATE CONSTANT

B = 2 D C*/N 1

1 t--OXIDIZING SPECIES PRESSURE

L-SOLUBILITY OF OXIDANT IN OXIDE
OXIDANT DIFFUSION COEFFICIENT IN OXIDE

LINEAR RATE CONSTANT

BIA = C*/N 1
(11k + 1/h)
t LREACTION AT Si02-AMBIENT INTERFACE
~REACTION AT Si-Si02 INTERFACE
,--.- - - (OXIDE CHARGES)
l"-----OXIDIZING SPECIES PRESSURE
' - - - - - - SOLUBILITY OF OXIDANT IN OXIDE

Figure 6: Relationship of process variables to oxidation general relationship.

TRANSITION
REGION
I

\SiO x Si
I
I

@
MOBILE IONIC
CHARGE Om ++++
OXIDE TRAPPED FIXED OXIDE
CHARGE,Oot CHARGE, Of

Figure 7: Names and location of charges associated with the thermally oxidized
sil icon structure.
58 Semiconductor Materials

A brief description of the four types of charges is presented. As may be

noted, all of them are directly related to the oxidation and associated
processing. Techniques for measuring the charge densities are also
indicated.
Fixed Oxide Charge; Of' N f . As indicated in Figure 7, the fixed oxide
charge is positive and located in the oxide very close to the Si-Si0 2
interface «20 ). It is due primarily to structural defects (ionized silicon) in
the Si0 2 lattice and directly dependent on conditions of oxidation. For
instance, its density which ranges from 10 10 to 10 12 cm- 2 depends on
oxidation ambient and temperature, anneal/cooling conditions, and silicon
orientation. 22 Its density normally does not vary with surface potential
which distinguishes it from interface trapped charge-hence the name
fixed oxide charge.
An important Of process relationship is that the density of Of for either
steam or dry 02 oxidation increases with decreasing temperature. 21 ,22,24
However, a subsequent anneal in an inert ambient such as argon will
decrease the densityof Of to a minimum equilibrium value, giving rise to the
"Of triangle" effect. 21
Another important property of fixed oxide charge is that its effective
density can be increased by the application of high negative fields to
fieldplates of an MOS structure at moderate temperatures (1 00o-400°C).21
This increase is proportional to the applied field as well as the initial Of
density. The interface trapped charge density also increases as a result of
negative field application. Such an effect can lead to instabilities in p-
channel MOS devices.
Mobile Ionic Charge; Om' N m. The mobile ionic charge is primarily due
to the positive alkali ions, Li+, Na+, K+, and also possibly H+. In addition, it is
possible to observe charge effects due to the larger negative ions such as
F-, CI-, and also Cs+, Au+, and the like. These latter ions normally do not
migrate at typical device temperatures, however, and will not lead to
instabilities. Likewise, their presence is more difficult to detect. The field-
induced "drift" of the alkali ions is the leading cause of instabilities in MOS
devices 25 and the rate of drift is inversely proportional to ion size (Li+> Na+
>K+).
Almost every semiconductor device fabrication step can be a source
of ionic contamination. Elaboratesteps have been established to minimize
their effect. Since this is impossible on an absolute basis, special "gettering"
processes have been developed. 26 These involve the use of phosphorus
glass, chlorine species, or other materials which can complex or getter
impurity ions from the oxide and render them inactive. Dense dielectric
films such as silicon nitride are also used to mask ionic impurities from
entering the oxide.
Interface Trapped Charge; 0it' Nit' Ow Closely related in physical origin
to the fixed oxide charge is the main form of interface trapped charge. Both
charges arise from the formation of partially ionized silicon species during
the thermal oxidation process. The main difference is that 0it may be
charged or discharged as a function of surface potential, while Of is not in
electrical communication with the silicon and remains charged. Interface
trapped charge does have many of the same process dependencies as Of'
 Thermal Oxidation 59

such as oxidation temperature, silicon orientation, annealing conditions,

etc. One significant difference between the two charges, however, is that
interface traps can be complexed at low temperatures (300°-500°C) with
an active hydrogen species and thus their effective density reduced
significantly. As- oxidized Nit densities are normally in the 1012cm -2 range,
while after a 400°C forming gas anneal their values drop to below 1010cm -2.
Other types of interface trapped charges result from ionizing radiation,
and the presence of heavy metals (Fe, Cu) at the Si-Si0 2 interface. Both
result in the same kind of charge formation with respect to the silicon band
gap.
Oxide Trapped Charge; Qat' Not. The fou rth type of oxide charge is due
to the presence or generation of trapped holes or electrons in the oxide.
Generally these are produced by ionizing radiation, avalanched junctions,
high currents through the oxide, or other reactions which either tend to
break Si-O bonds in the oxide or otherwise lead to carrier trapping on sites
or traps already present in the oxide. 27 Charge trapping, either due to
ionizing radiation or the presence of high fields leading to avalanching,
have been causeforconcern in the past and will be even more of a problem
as device geometries shrink and radiation producing processes are
employed. Some of these, such as sputtering, plasma deposition and
etching, and electron beam/x-ray lithography, result in considerable
electron-hole trapping and these trapped charges often are not easily
removed. It is possible, however, to modify oxidation processes such that
oxide charge trapping is minimized. Several studies have been reported
which indicate process effects on oxide trapping. 28 ,29
Measurement and Control of Oxide Charges. A number of methods
have been developed for measuring the effective density of charges
associated with thermally oxidized silicon. It is beyond the scope of this
chapter to discuss them all but the reader is referred to reviews by
Nicollian and Brews,? Bartelink30 and Goetzberger et al. 31 These and other
reviews describe measurements particularly of the interface trapped
charge density Nit' and include quasistatic capacitance-voltage analysis,
deep level transient spectroscopy, conductance-voltage analysis, and
others. These methods generally permit measurement of interface trap
charge density as a function of energy across the middle portion of the
silicon band gap.
The high frequency capacitance-voltage (C-V) technique, however, is
the most suitable for on-line measurement and control of charges in
oxidized silicon structures. 32 ,33 It generally involves a high frequency (1
MHz) capacitance measurement as a function of dc bias across an MOS
capacitor. The latter consists of an evaporated metal field plate (normally
an aluminum dot evaporated through a metal mask) over a 0.1 to 0.2 p,m
thermal silicon oxide. The substrate should be medium doped (10 15 to
1016cm -3) silicon of the appropriate orientation. Fixed oxide charge Nf,
mobile ionic charge N m, and oxide trapped charge Not can all be determined
rapidly using C-V analysis. N f is determined by the expression
60 Semiconductor Materials

where V FS = flatband voltage

¢MS = metal-semiconductor work function difference
Co = oxide capacitance
q = electronic charge
k o = oxide dielectric constant
Co = permittivity of free space
Xo = oxide thickness in micrometers

In the case of N m, a bias-temperature stress test is used to measure total

impurity ion content. N m is determined by the following expression which is
based on Equation 14:
10
N = (6V)2.13xlO
m X
o
(~m) [15J

where LlV is the difference between flatband voltages of C-V plots after
positive and negative stress tests. The conditions for the test are normally
+50 and -25 V/p.,m at 300°C for 2 minutes. An example of Nf and N m
measurement using C-V analysis is presented in Figure 8, where C-V plots
before and after bias-temperature stress tests are shown.

"" ~ THEORY
AFTER~\
POS. BIAS \ INITIAL
\
CIC o \----Qm/Co-+-~--.
\ (l::.V)

I
\
\
'- - - ----=---~--~--

Figure 8: The determination of fixed oxide charge density Of and mobile ionic
charge density Om in thermal silicon dioxide using the MOS capacitance-voltage
technique.

Oxide trapped charge density Not is normally determined following a

procedure similar to that used for ionic contamination. In the case of Not,
however, the C-V plots are compared before and after the charge trapping
process and no elevated temperature is employed.
As gate oxides for VLSI MOS devices approach the 200A thickness
range, the selection of a proper value of work function difference ¢MS in
Equation 14 becomes quite critical. In fact,it has been determined that the
effective value of ¢MS can depend on the processing sequence 34 so that
the proper choice of ¢MS becomes especially difficult.
 Thermal Oxidation 61

4.1.2 Dopant Redistribution. It has been known for many years

that silicon dopants seg regate preferentially on one orthe other side of the
Si-Si0 2 interface during thermal oxidation. This dopant pile-up or depletion
at the silicon surface can affect several critical device characteristics,
such as MOS threshold voltage, junction breakdown voltage, and others.
The amount and nature of the dopant segregation depends on several
factors, the most important being the dopant segregation coefficient m (m
= ratio of equilibrium concentration of dopant in the silicon to that in the
oxide), the oxidation rate, and the relative dopant diffusion rates in the
oxide and silicon. 35 In general, n-type dopants such as phosphorus pile up
(m> 1) and p-type dopants such as boron deplete (m< 1). Four possible
redistribution effects are shown in Figure 9. 35 Cases A and C represent
normal p-type depletion and n-type pile-up. However, the presence of
hydrogen causes increased boron diffusion in the oxide (case B) and
greater depletion. In case D, increased gallium diffusion in the oxide leads
to depletion, even though m>1 for this p-type dopant.

OXIDE SILICON OXIDE SILICON

A. m< 1 B. m< 1
DIFFUSION IN DIFFUSION IN
OXIDE SLOW OXIDE FAST
(BORON) (BORON IN H2)

OXIDE SILICON OXIDE SILICON

C. m >1 D. m >1
DIFFUSION IN DIFFUSION IN
OXIDE SLOW OXIDE FAST
(PHOSPHORUS. ARSENIC. (GALLIUM)
ANTIMONY)

Figure 9: Schematic illustration of the dopant distribution as a function of posi-

tion is the Si02 /Si structure indicating the redistribution and segregation of
dopants during silicon thermal oxidation (after Grove et a1 35 ).
62 Semiconductor Materials

Because of the various factors affecting redistribution mentioned

above (segregation coefficient, oxidation rate, dopant diffusion rates),
oxidation variables such as temperature, ambient type, and others will
determine the amount of depletion or pile-up. For instance, steam ambients
and/or lower oxidation temperatures generally result in more redistribution.
Furthermore, oxidation pressures which do not allow equilibrium to be
established also result in modified redistribution profiles. The overall
mechanism of dopant redistribution remains unclear due to its complexity,
and computer techniques will be required to properly model the process.

4.2 Effects of Surface Properties on the Oxidation Reaction

4.2.1 Silicon Orientation. It has been observed for a number of
years that the silicon thermal oxidation process is dependent on the
substrate silicon orientation (see Figures 1 and 2), and that this dependence
is more pronounced at lower temperatures (gOOae). The effect was first
reported by Ligenza36 and later verified by Pliskin. 37 It is now established
that the orientation dependence is reflected primarily through the linear
rate constant and is undoubtedly associated with the Si-Si0 2 interface
reaction (see Figure 6). While a quantitative mechanism has still not been
established, it is assumed that the effect is based on the bond density or
"availability," and it is observed that the (111) orientation results in the
fastest interface reaction while (1 00) silicon is the slowest. As the oxidation
temperatu re decreases and the oxidation process becomes more surface
reaction controlled, the orientation effect thus becomes more pronounced.
An orientation effect related to oxide charge density (Of and 0it) similar
to that for the interface oxidation reaction has also been observed. The
similarity of these two effects leads to the conclusion that oxide charge
origin (Ofand 0it) is directly related to the oxidation process at the Si-Si0 2
interface. A comparison of these two orientation dependent effects is
shown in Table 4.

Table 4: Dependence of Oxidation Linear Rate Constant and

Oxide Fixed Charge Density on Silicon Orientation

OXIDE OXIDATION SILICON B/A Qf/q

TYPE TEMPERATURE ORIENTATION
(OCl (~m/hr) (cm- 2 )

DRY O2 1200 (III) 1.12 1.7 X lOll

(110) 0.90 0.6
(100) 0.56 0.2

WET0 2 1200 (III) 14.40 4.0

(95°C (110) 12.0 1.7
H2O)
(100) 7.2 1.2
 Thermal Oxidation 63

As predicted from the general relationship, the parabolic rate constant

is relatively independent of silicon orientation. However, there is some
indication that for lower temperatures orthinner oxides the silicon substrate
may cause some oxide structural effect, which in turn might result in an
orientation dependence of the parabolic rate constant.
4.2.2 Dopant Concentration. It was observed some time ago that
areas of semiconductor devices having surface dopant concentrations
greater than 1a19 cm- 3 , i.e. emitter regions in bipolar transistors, exhibit
higher oxidation rates than ajoining lightly doped silicon. 37 ,38 Experiments
indicated that the effect for n-type dopants is more pronounced at lower
temperatures or thinner oxides, while for boron doping, an oxidation
increase is noted to some extent overthe entire temperature range. These
results implied that high concentrations of phosphorus affect the oxidation
process primarily through the surface reaction rate constant BfA, while for
boron both B and BfA contribute to the increase in oxidation rate.
More recently Ho and co-workers 39 investigated in more detail the
effect of phosphorus concentration on the thermal oxidation process.
They have attributed this effect to vacancy generation resulting from high
phosphorus concentrations in silicon. These vacancies provide a driving
force for increased interface reaction rates and relate to the more recently
proposed atomic model of oxidation to be discussed in a later section of
this chapter. Boron tends to segregate into the oxide and will therefore
tend to affect the parabolic rate constant which is more important at higher
temperatures. As boron concentration increases, however, that at the
silicon surface will also increase and therefore raise the interface oxidation
reaction rate. Typical oxide thickness- time data are shown in Figure 1a for
phosphorus. 39 Note that the increase of oxidation rate is more pronounced
at lower temperature (BaaOe) and for thinner oxides, which reflects the
greater contribution of the linear rate constant BfA under these conditions.

(f)
(f)
w
z
~

~ 1000A
t-
PHOS. CONC. (cm- ~
w F
o F 3.2 I 10 20
g E 2.8 I 1020
o 1.8 I 10 20
C 7 I 10 19
B 5 I 10 19
A 1 I 10 15
100A L...---l-_L....-J,.....J.....~--L-_1..--J.--L-~--L-_~---...
10' 102
OXIDATION TIME

Figure 10: Oxide thickness vs oxidation time for oxidation time for silicon oxi-
dation in dry oxygen at 800° and 1100°C using (111) sil icon substrates doped
with phosphorus up to solid solubility (after Ho et aI 39 ).
64 Semiconductor Materials

4.2.3 Surface Preparation. Some of the effects mentioned above

relating silicon surface properties to oxidation rate indicate that such
effects are more prevalent at lower temperatures. Asimilar effect has been
noted forthe su rface condition of the sil icon prior to oxidation. If the silicon
surface is not cleaned uniformly it is much more likely that resulting
patches of non-uniform thickness of oxide can be observed at 1OOO°C or
less as opposed to 1200°C. Likewise, if differences in oxidation rate due to
variations in physical treatments such as polishing, lapping, etc., occur,
they will more likely occur at lower temperatures or in the thinner oxide
regime. This again reflects the fact that surface related effects are associ-
ated with the linear rate constant which is much more oxidation rate
controlling at lower temperatures.
Somewhat related to these effects is the observation made by Schwett-
mann and others that the type of pre-oxidation cleaning treatment can
affect the subsequent oxidation rate. An example of this effect is indicated
in Figure 11, where oxidation thickness-time data are shown for three
different cleaning treatments. 40 Since the treatment incorporating ammon-
ium hydroxide results in the slowest oxidation, it is postulated that an
inhibiting nitride layer is formed on the silicon which retards the subsequent
oxidation process. More work is necessary to better understand the
mechanisms involved in these effects, since the use of very thin oxides for
VLSI applications will require more stringent control of thin oxide thickness
and uniformity.

1400

H2 S 04: H 202
1200 CLEAN

NO CLEAN
€ 1000
en
en
w 800 NH 4 0H : H 2 0 2 : H 2 O
z
~
(,) CLEAN
...
i: 600
w
c
x
0
400 1000°C
DRY 02
(100) Si
200 n-TYPE, 2-8.n em

0
0 20 40 60 80 100 120 140 160 180 200
OXIDATION TIME (min)

Figure 11: Effect of pre-oxidation cleaning process on oxide growth rate (after
Schwettmann et aI 4O ).
 Thermal Oxidation 65

4.3 Effects of Ambients on the Oxidation Reaction

4.3.1 Ambient Type. The data presented in Figures 1 and 2 and in
Table 2 demonstrate the considerable difference in silicon oxidation rates
between dry oxygen and steam ambients. While several physical factors
related to Equation 6 can contribute to such differences, in this case the
primary effect appears to be oxidant solubility in the oxide. The solubility of
water in thermal Si0 2 is three orders of magnitude greater than that of
oxygen. 12 As indicated earlier, investigations are now being conducted to
determine mechanisms of oxidant diffusion through the oxide and other
reactions which occur during silicon thermal oxidation. From a practical
consideration, dry oxygen is more commonly used for preparing thinner,
reproducible oxides, such as MOS gates, while steam is employed for
thicker oxides normally used for isolation outside the active junction area.
Variations in 02 or H 20 partial pressures are employed for optimizing
thickness control in certain applications, while small amounts of chlorine
are sometimes added for impurity gettering. Otherwise, no other types of
oxidation ambients have been reported.
4.3.2 Chlorine Additions. In the early 1970's it was reported that the
addition of a small amount of a chlorine species, either HCI, C1 2, or some
organochloro component, to the oxidation ambient can provide several
beneficial effects with respect to the resulting oxide. 41 ,42 These benefits
include improved oxide charge stability, fewer pinholes, reduced interface
trapped charge density, and better device performance in general. It is now
quite common to add a few percent (1-5%) of a chlorine-containing com-
pound, such as HCI, to oxidation ambients used for both MOS and bipolar
devices. It is also common to "clean" oxidation tubes with oxygen- or
nitrogen-chlorine mixtures prior to oxidation.
It has been determ ined that a certain amount of chlori ne remains in the
oxide after oxidation in a chlorine-containing ambient, and that this chlorine
residing very nearthe Si-Si0 2 interface can provide improved passivation.
If too much chlorine is present, however, device properties become degrad-
ed and the oxide may blister and peel off the silicon. In most cases the
oxidation rate increases due to chlorine additions-the greater the chlorine
content and the higher the oxidation temperature, the greater the rate
increase.
The mechanism for chlorine oxidation is not completely understood,
but it is believed that the reaction:

[16J

occurs. It follows that CI 2 must be the primary chlorine species incorporated

in the oxide and is driven to the Si-Si0 2 interface by a field in the oxide
during oxidation. If water is added to the ambient, the above chemical
reaction is driven to the left and less chlorine is incorporated in the oxide.
This is supported by the fact that little chlorine is observed in steam
produced oxides. Figure 12 includes an Auger profile of an 11 OO°C chlorine-
66 Semiconductor Materials

containing oxide as well as a plot of chlorine concentration at the Si-Si0 2

interface as a function of oxide thickness. 43 The latter demonstrates that
chlorine content in the oxide increases with oxidation time.

(i)
....
z
;:)

>-
a:::
<X
a:::
....
CD
a:::
~
....::I:
l!)
Lij
::I:
~ o . •
~·••"'~':··"-"';:';:"'V:""t"''.''\o
<X
W
a.. ....•
o
....
~
<X
W
a..

1100

N'2
I
[3
It')

g
01

00 500 1000
Xo (1)
B. CHLORINE CONCENTRATION VS OXIDE THICKNESS

Figure 12: Auger sputter profile (A) and chlorine concentration vs oxide thick-
ness (8) for thermal oxide prepared in 5% HCI/02 ambient at 11 OO°C using (100)
sil icon (after Rouse et aI 43 ).

4.3.3 Nitridation. So-called inert gases, such as nitrogen, argon,

and others have been used for many years to dilute oxygen ambients,
reduce charge densities, promote dopant diffusion, and to provide an
oxygen-free ambient for cooling and pulling wafers. It was determined,
however, that while argon and helium are inert, nitrogen will react at
elevated temperatures with silicon. In fact, Raider found that a silicon-
nitrogen reaction occurs at the Si-Si0 2 interface even in the presence of
appreciable thicknesses of thermal oxides. 44 In general, however, attempts
to produce silicon nitride films by direct thermal reaction were not success-
ful.
More recently, improved gas purity and techniques have permitted
 Thermal Oxidation 67

reasonably good silicon nitride films to be produced by reacting N 2 or NH 3

directly with silicon at elevated temperatures (1 0000-1300°C), with or
without the use of plasma excitation. 45 ,46 These thin films exhibit improved
properties over thermal oxides (increased breakdown, fewer pinholes,
higher dielectric constant) and are in the thickness range, 50-1 ooA, which
is required foradvanced VLSI MaS structures. However, continuing process
and reproducibility problems appear to preclude their use in actual devices.
On the other hand, it has been subsequently reported 47 that advantages of
the silicon nitride might be achieved while still maintaining the superior
interface properties of thermal Si0 2 by converting the outer portion of the
oxide to nitride using an NH 3 anneal at temperatures greater than 900°C.
The resulting oxy-nitride structures exhibit greatly improved dielectric
breakdowns, resistance to subsequent oxidation impurity, and dopant
diffusion, and improved integrity-all of which make them much more
suitable for submicrometer MaS device application. 48 Auger analysis has
indicated that the actual amount of nitrogen in these nitrided oxide films is
fairly low, most of it concentrated at the outer surface of the oxide or near
the Si-Si0 2 interface. 48
4.3.4 Oxidant Pressure. High pressure oxidation of silicon was first
employed more than twenty years ago by Ligenza and Spitzer3 in order to
accelerate the oxidation process at lower temperatures. They employed a
stainless steel "bomb" which contained the silicon wafer in a steam
ambient. While devices were passivated by this method, it did not become
widely accepted in the industry. More recently, Panousis and Schneider49
reported a high pressure oxidation system more suitable for production.
This system allowed continuous flow of the pressurized ambient through a
quartz tube and was the basis for today's commercial systems. 50 -52 These
systems can be used for dry O 2 or steam up to 25 atm, and have capacities
of up to 200 four-inch diameter wafers. Other experimental systems,
similar to the closed bombs of Ligenza and Spitzer, employing dry02 up to
750 atm, have been reported,52 but are not used commercially.
As indicated in Fig. 6, the general relationship predicts that both the
parabolic and linear rate constants should be directly proportional propor-
tional to ambient pressure through C*, the equilibrium concentration of the
oxidant in the oxide. Thus, the time required to produce a given oxide
thickness should be inversely proportional to pressure. This will provide
several advantages, especially with regard to today's small geometry
devices having very shallow junctions. Junction movement during oxidation
as well as dopant redistribution will be minimized. It has also been found
that defect levels are reduced. These improvements are either due to the
shorter times and lower temperatures eployed for the high pressure
oxidation process, or because of the increased oxidation rate.
Recent kinetic studies of silicon oxidation in steam up to 20 atm have
indicated that both the linear and parabolic rate constants are directly
proportional to steam pressure from 800° to 1OOO°C, as predicted above. 53
For dry O 2, however, while the parabolic rate constant has a linear (8 a P)
dependence, the linear rate constant falls off with pressure 54 (8/A a pO.7).
Typical thickness-time oxidation data for high pressure steam are shown
in Fig. 13.
68 Semiconductor Materials

PYROGENIC STEAM
900°C

2
E
3-
0
)(
1.0
en
C/)
w
z
~
0.5 I
()
i:
l-
I
w
c 0.2
I
x
0
I
0.1 .(111)1
0(100)1
12 hr
0.05
0.2 0.5 1.0 2 5 10
OXDATION TIME, t (hr)

Figure 13: Oxide thickness vs oxidation time for silicon oxidation in pyrogenic
steam ('""640 Torr) at 900°C and various pressures (after Razouk et aI 53 ). Re-
printed by permission of the publisher, The Electrochemical Society, Inc.

Reduced partial pressures of 02 and H 2 0 in inert carrier gases have

been used for producing thin, controlled oxide films. In general, rate
constants are proportional to oxidant pressures down to about 0.1 atm.
However, as film thicknesses approach 200A, the deviation in oxidation
kinetics mentioned earlier occurs and pressure dependencies are not
clearly understood.

5. OXIDATION MECHANISM

5.1 Atomic Reactions

As indicated in Section 2 above, the thermal oxidation of silicon in
either dry oxygen or steam can be characterized by the general relationship
Eq. 6. However, the actual atomic reactions at the Si-Si0 2 interface during
thermal oxidation have not been well understood in the past. More recently
efforts have been made to better characterize these reactions, especially
the mechanisms associated with the rate constant k in Eq. 6. It has been
proposed 55 ,56 that at least three individual phenomena occurat the Si-Si0 2
interface as oxidation proceeds. These are shown in Fig. 14, and are also
proposed to contribute to other effects observed during thermal oxidation.
First, each Si0 2 molecule produced occupies considerably more volume
than that of the silicon reacted. Thus, appreciable strain results at the
interface region as is indicated in the upper box of Fig. 14. This compressive
 Thermal Oxidation 69

Si- (si;' + 02 ....Si-O+O

" ~J
Si -o:(Si;~ +0 .... Si02 ~ (si;)
'-~ ,_/

Si

Figure 14: Proposed mechanisms occurring at the Si-Si02 interface during sili-
con thermal oxidation (after Plummer ss ). These figures were originally presented
at the Spring 1981 Meeting of The Electrochemical Society, Inc., held in Minne-
apolis Minnesota.

stress accounts in part for the excellent passivation property of thermal

silicon dioxide, but can also lead to lattice mismatch and other defects, if
some mechanism does not permit the stress to be relieved.
One of the ways of relieving this stress is shown in the lower box of
Figure 14, which is the generation and diffusion away from the interface of
silicon interstitials. Silicon interstitials produced by the oxidation process
have been proposed to cause enhanced diffusion of dopants in the silicon
during thermal oxidation-OED,5? as well as to promote stacking fault
formation-OISF.58,59 It has also been proposed that they contribute to
charges such as Q f or Q it in the oxide. 55 ,6o For the enhanced dopant
diffusion effect, a relationship relating the oxidation rate and effective
diffusion coefficient has been developed 5?which agrees reasonably well
with experimental data:

Deff = Di + K dt [dX) n [17]

where OJ = the normal diffusion coefficient due to vacancy mechanisms

and K( dx/dt)n = the silicon interstitial contribution. The value of n has been
determined to range from 0.2 to 1.0. An expression for stacking fault
generation and retrogrowth has also been proposed: 59

[18]

where dl/dt = the growth/retrogrowth rate, K2 = the shrinkage rate in the

absence of oxidation, and K 1(dx/dt)n = the interstitial contribution to the
70 Semiconductor Materials

growth rate. The best value of n appears to be 0.4. A number of process

variables in addition to oxidation rate dx/dt, such as ambient type, silicon
orientation, HCI presence, and mechanical damage, have been shown to
affect oxidation-enhanced diffusion and stacking fault generation through
the formation of silicon interstitials during oxidation. 55
The third reaction or mechanism proposed to occur at the Si-Si0 2
interface indicated by the middle portion of Fig. 14, involves the possible
contribution of silicon vacancies to the oxidation reaction. Under normal
conditions (lightly doped silicon) the vacancy concentration is reasonably
low and oxidation proceeds, giving rise to the mechanisms already discussed
(strain generation and silicon interstitial effects). However, for heavier
dopant concentrations (C s = ~ 1020cm -3) enough silicon vacancies are
present so as to provide additional free volume which can accommodate
additional interstitials and as a result, the oxidation rate increases. This
mechanism has been discussed and modeled by Hoand Plummer39 which
helps to explain the well-known heavily doped oxidation effect discussed
earlier.
An understanding of the detailed mechanisms of reactions occurring
at the Si-Si0 2 interface during thermal oxidation, such as those described
above, and the relationship to associated reactions occurring during the
oxidation process, should provide the basis for producing and controlling
the thin oxides required forVLSI circuits. It will also be necessary, however
to understand the details of the diffusion of oxidizing species through the
oxide. Various techniques, such as radioactive exchange,61,62 are being
used for this purpose. Finally, an actual physical "picture" of the oxidized
silicon interface region will be required if all the observed effects and
mechanisms of oxidation are to be explained. The current status of the
clarity of the picture is presented in the next section.

5.2 Structure of the Si-Si0 2 Interface

For at least twenty-five years, investigators have speculated about the
nature and physical structure of the Si-Si0 2 interface region associated
with thermally oxidized silicon. Most of the earlier speculations were
based on electrical characteristics of the interface and MOS devices. It
was initially believed that the interface region depth was less than 200A
but lack of sensitive instrumentation prevented any detailed knowledge
about how much less it might be. It was also believed thatsome of the oxide
charges which resided in this region were due to disrupted Si-Si or Si-O
bonds or other similar defects. Not much more was known about the Si-
Si0 2interface.
In the 1970s and early 1980s, the sophistication and resolution of
analytical tools have improved considerably. As a result, and because of
the increased emphasis of complex device structures, many investigations
regarding the structure of the Si-Si0 2 interface have been carried out.
These have involved Auger spectroscopy, x-ray diffraction, electron miro-
scopy, x-ray photoelectron spectroscopy, Rutherford backscattering,
secondary ion mass spectrometry, electron spin resonance, ellipsometry,
photo emission, and numerous others. In addition, theoretical computer
modeling has been used to predict interface properties. The results obtained
 Thermal Oxidation 71

from these various types of analysis have been correlated with those
obtained using improved electrical techniques such as quasistatic C-V,
DLTS, and conductance-voltage measurements. All of these plus actual
device measurements have provided considerable insight into the exact
nature of the Si-Si0 2 interface. It is not possible here to reference even a
small number of the papers concerning the evaluation of the Si-Si0 2
interface; however, some of the more comprehensive reviews on the
subject of surface and interface analysis may be consulted. 63- 65
The current understanding of the nature of the Si-Si0 2 interface in
thermally oxidized silicon may be summarized as follows. First, it is generally
agreed that the transition region between silicon and the bulk oxide is no
more than 1OAor even one ortwo monolayers.ln this region, the composi-
tion changes rapidly from Si to Si0 2 ; and the oxide is apparently crystalline
in nature immediately adjacent to the silicon. As a result, the physical,
electrical, and chemical properties of the oxide in this transition region are
markedly different from those of amorphous Si0 2 and affect the net
properties of oxides up to 200A or more. There is also a good possibility
that the Si-O bond angles in the transition region and beyond (up to 50A)
are strained, which can also affect oxide properties.
Depending on the oxidation conditions and the silicon orientation, a
limited number of silicon atoms at the silicon surface (as few as one in 10 5 )
might not be bonded to oxygen and thus could act as trapping sites (Oit).
Similarly, some of the silicon atoms on the oxide side of the interface might
be disconnected from adjacent oxygen ions (or certain oxygen atoms
might be missing) and these silicon species could also act as charge or
trapping sites (Of). Although these specific defects or trapping sites have
yet to be positively observed, the evidence for their presence is fairly
conclusive as a result of recent investigations. 18,19,66,69 A proposed cross
section structure of the Si-Si0 2 interface region is presented in Fig. 15,
which includes the possible origin of the four types of oxide charges. This

I /1-", I /~-'\ 1
o /0 \ 0 I N~ \ 0
( " \ \ 8)
I I " +Notl I \~nJ/ I
THERMAL -5i - 0 --\ 5i -r 0 - 5i - 0 - 5i-
Si02 I \,1_// I I
-~- 0 0 0 0
I I /1-'\ I
1
TRANSITION
- 5i - 0 - Si - 0 - ( 5i+
\ I Of /
+- 0 - 5i-
REGION \ I

~-
0
I.
/-"
"\
0
I
/~~, 0
I I Nit \ I H I Nit \ H I
• ( J • I. ~ I.) I. .
51 - \ Fe / - 51 - 51 - \ 51 - j- 51 - 51-

1 'T/ '-I~/
SILICON
- 5i - 5i - 5i - 5i - 5i - 5i - 5i -
I 1 I I I I I 1

Figure 15: Idealized structure of thermally oxidized silicon interface region

showing possible origins of four types of oxide charge.
 72 Semiconductor Materials

concept of the Si-Si0 2 interface structure is the most likely to date. As more
sophisticated analysis equipment is developed, it is reasonable to assume
that a more accurate description of the Si-Si0 2 interface will emerge.
Under any consideration, this interface will playa most important role in
future semiconductor devices.

6. OTHER OXIDATION PROCESSES

6.1 Assisted Oxidation

It is known that various types of radiation can affect the thermal
oxidation process. The radiation can involve electrons, protons, x-rays,
photons (including laser, UV or IR radiation), gamma rays, ions, microwave,
and various types of plasmas. Generally, the net effect of the radiation is to
increase the rate of oxidation. This can occur by either the activation of the
oxidizing species in the gas phase, whereby both the parabolic and linear
rate constants are increased, or by breaking Si-O bonds in the oxide which
could cause increased diffusion of the oxidant through the oxide. It is also
possible that the interface reaction might be increased. Radiation processes
may therefore be employed to increase the rate of thermal oxidation at
lower temperatures. An example of the use of plasma to form thermal
oxides of reasonable thickness at very low temperatures is demonstrated
in Figure 16.70

280

240

200
Ec
~ 160
)(

2 8

Figure 16: Oxide thickness vs oxidation time for silicon oxidation in dry oxy-
gen plasma (30 mTorr, 1 kW, 0.5 MHz) (after Ray and Reisman 70). Reprinted by
permission of the publisher, The Electrochemical Society, Inc.
 Thermal Oxidation 73

On the other hand, these radiation effects might lead to undesirable

results, such as excess oxide charge formation and non-uniform oxide
growth. In fact the use of many radiation-producing processess in VLSI
device fabrication has been the basis for considerable concern by investi-
gators studying the effects of plasma etching, sputtering, electron beam
and x-ray lithography, and other advanced types of processes.7 1
Electric fields similarto radiation influence the oxidation mechanism.
Electric fields have been used to both affect the oxidation reaction and to
study its mechanism. It has been known since the original experiment of
Jorgensen8 that an electric field is probably present in the oxidizing
silicon system. Furthermore, the application of an external field on the
structure can accelerate or retard the oxidation reaction. The complete
picture is still not clear, although some of the radiation processes described
above (plasma, ions, etc.) include the effects of an electric field as part of
the means of accelerating oxidation. In addition, the anodization process
has also been reported to be effective in oxidizing silicon and compound
semiconductors at low temperatures.7 2

6.2 Silicon-Containing Materials

Typically, over the past twenty-five years, the chem ical elements used
to fabricate silicon semiconductor devices have consisted of silicon,
oxygen, and aluminum, with added dopants. More recently, silicon-containing
materials such as silicon nitrides and refractory metal silicides have been
employed as device components. As it turns out, these alternate materials
can be thermally oxidized to form Si0 2 in a manner similar to silicon
oxidation. In fact, the oxide formed is essentially identical to Si0 2 associated
with silicon.
The mechanisms involved in three different silicon-containing materials
used in devices are illustrated in Figure17. The oxidation of polycrystalline
silicon (used for MOS gates and interconnects) most closely resembles
single crystal silicon oxidation, except forthe presence of grains and grain
boundaries in the poly-Si (Figure 17A). This tends to make the process
more complex and less controllable.7 3 ,74 Nevertheless, thermal oxides are
used successfully to passivate and insulate polycrystalline silicon in
today's device structures. In the case of silicon nitride (Si 3 N4 ) (used to
mask oxidation and impurity ions) the mechanism of conversion to Si0 2 is
similarto that of silicon, but nitrogen produced by the reaction must diffuse
out of the oxide (Figure 17 B). The kinetics of Si 3 N4 oxidation appears to
follow the general oxidation relationship but the rate is at least an order of
magnitude less than for silicon.7 5 ,76 The Si0 2 produced is identical to that
obtained by silicon oxidation.
The refractory metal silicides (WSi 2 , TaSi 2, TiSi 2 , MoSi 2) are currently
used in devices in combination with polycrystalline silicon as interconnects
and MOS gates. An oxidized TaSi 2/poly-Si structure is shown in Figure
17C. Thermal oxidation of the silicide apparently proceeds by the diffusion
of silicon atoms from the underlying poly-Si layer up through the metal
silicide.7 7- 79 Assuming a sufficient supply of substrate silicon, stoichiometric
Si0 2 is produced over the silicide, the latter not being consumed by the
74 Semiconductor Materials

Si02
-_;:~,J~J--~l-:>, Poly-Si
POLYCRYSTALLINE SILICON
Si + O2 -""Si0 2
Si

Si02

Si3 N4
SILICON NITRIDE
B. Si02 Si 3 N4 + 3 02 --3 Si0 2 + 2 N2
Si

Si02
TaSi2
C. Poly-Si TANTALUM SILICIDE
Si02 TaSi2 + Si + 02 ~ Si02 + TaSi2
Si

Figure 17: Schematic illustration of thermal oxidation of silicon-containing ma-

terials in which silicon dioxide is reaction product: (A) polycrystalline silicon,
(8) silicon nitride, (C) refractory metal silicide.

reaction. Analysis of the data indicates that the rate determining step is
primarily diffusion of the oxidizing species through the oxide. Values of B,
the parabolic rate constant are almost identical to those obtained for
conventional silicon oxidation, while BfA values are much higher.7 7 - 79 If no
silicon is present beneath the silicide, the resulting oxides are mixtures of
refractory metal and silicon oxides and are generally not stable or repro-
ducible.
Typical thickness-time data for the thermal oxidation of tantalum
silicide deposited over polycrystalline silicon are shown in Figure 18.77
Single crystal silicon oxidation data are included in the figure for comparison.

6.3 Other Semiconductors

One of the reasons that germanium did not become a significantfactor
in semiconductor device technology was that it could not be passivated
through thermal oxidation. Thermal germanium oxides are generally un-
stable and decompose during subsequent high temperature processing.
Alternate approaches, such as anodizing or deposition of silicon oxides,
have been attempted, but the almost ideal passivating properties of
thermally oxidized silicon have helped to make this semiconductor the
main device material over the past twenty-five years.
 Thermal Oxidation 75

o (100) Si
0.5 • ToSi2 on Poly - Si

E
~
o 0.2
)(

en
en
~ 0.1
~
~
:I:
~ 0.05
UJ
9
x
o
0.02

0.01----_~ __ ..L...._.__ _ _ L . . _ _ . . . . . . . L . . __ __ L . . __ _ _ ' _ __ ___'___ __ _ ' _ _ _.......

0.1 0.2 0.5 1.0 2 5 10 20 50 100

OXIDATION TIME, t (hr)

Figure 18: Oxide th ickness vs oxidation time for thermal oxidation of TaSi 2 /poly-
Si structure in dry oxygen at various temperatures (after Razouk et aI 77 ).

Compound semiconductors, such as gallium arsenide, indium anti-

monide, gallium phosphide, and others, have also been difficult to passivate
by thermal oxidation. Li ke germaniu m, the oxides formed are not generally
stable. In addition, the presence of two or more species in the semiconductor
causes competing reactions during the oxidation process and leads to
non-uniform films which depend on such factors as composition, orientation
and other variables. Some success has been achieved using anodic
oxidation for passivating some of the compound semiconductors. In addi-
tion, chemical vapor deposited Si0 2 or Si 3 N4 provide satisfactory diffusion
masks and passivating layers for compound semiconductors used for
devices of various kinds. Because the nature of the interfaces associated
with these passivated structures is so complex, much less is known about
their chemical and electrical properties. Perhaps as more commercial
applications are developed involving compound semiconductors, more
efforts can be devoted to understanding their surface and interface proper-
ties. In certain cases it might even be possible to develop a suitable
thermal oxidation process. Several informative reviews which deal with
thermal and anodic oxidation of compound semiconductors are avail-
able.7 2 ,8o,81

7. FUTURETRENDS

Considerably more stringent requirements will be placed on thermal

oxides as silicon integrated circuit feature sizes move from micrometer
76 Semiconductor Materials

into the submicrometer region. Continuing device scaling will require even
thinner, more reproducible oxides for gates in MOS structures. This implies
improvements or modifications in several areas. First, oxide thickness will
have to be controlled to even closer dimensions than it is now. Because of
differences in optical and electrical properties of thin thermal oxides,
improved or new thickness measurement techniques will have to be
developed. Equally important will be the need to better understand the
oxidation kinetics in the thin region so that control and reproducibility of
the oxide thickness can be achieved.
It will also be necessary to control and understand the effects of
process variables on other oxide properties such as electrical conductivity
and oxide charge formation. Equally important will be minimization of
defects, pinholes, and the like in these ultrathin films. Control of all these
oxide properties implies a better understanding of the Si-Si0 2 interface
region. As device dimensions reach a critical minimum size, statistical
variations in individual oxide charge densities may not permit specific bits
of the device to function.
With respect to thicker oxides used in future device structures, pro-
cedures will have to be developed to minimize or even eliminate oxide
encroachment. Up to now, oxides used to isolate the individual devices
have exhibited some form of "birdsbeak." Since this encroachment can be
of the order of a micrometer, it is obvious that this much "lost" area cannot
be tolerated in submicrometer structures. These oxide isolation problems
are being solved in part by (1) the use of other types of nitride masking
procedures which retard encroachment,82 (2) the fabrication of etched
trench structures which can be filled byvarious types of dielectric materials,83
or (3) selective epitaxial growth of silicon within insulating walls of silicon
oxide. 84
The final answer to controlling all the above properties may lie in our
ability to properly model the oxidation process itself and the resulting
effects on the oxide properties, and ultimately, the device parameters.
Since most future devices will involve very complex, three dimensional
configurations, our ability to model multidimensional aspects (two and
three dimensional) of oxide formation must be greatly improved. Such
modeling will of course be based on advanced computer techniques.
The trend for all semiconductor processing of the future includes
lower temperatures and shorter times-required for maintaining the ex-
tremely small structures in VLSI devices. This may be accomplished by the
use of high pressure and/or plasma-assisted oxidation. More reliable
devices with better performance and tighter specifications have been
produced by the use of chlorine in the oxidation ambient. More of these
types of improved oxidation techniques can be expected in the future.
Finally, although thermal oxides, and silicon semiconductors, have
been the mainstay of device tech nology for more than twenty-five years, Si02
will only be used in the future if it continues to satisfy the technological
requirements. For specific applications involving MOS gate structures,
other dielectrics such as thermal silicon nitride are being investigated.
Whether these or other materials replace thermal oxides in certain cases
remains to be seen. Similarly, it is reasonably certain that other semi-
 Thermal Oxidation 77

conductors, e.g. GaAs, GaAIP, etc., will be used for various applications,
including integrated circuits. It is reasonably certain, however, that both
silicon and thermal silicon dioxide will continue to play major roles in
semiconductor technology.

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3
Chemical Vapor Deposition of Silicon
and Its Compounds

Kenneth E. Be~'n
Texas Instruments Incorporated
Dallas, Texas

INTRODUCTION

The process technology of chemical vapor deposition (CVD) is today

and has for manyyears been one of the key technologies in semiconductor
processing. CVD technology is used throughout the various processing
steps in today's semiconductor manufacturing, starting with the synthesis
of the elemental silicon through thin epitaxial and polycrystalline silicon
films extending on through the oxidation process, the deposition of dielec-
tricfilms of nitrides, carbides, and silicides and metallization films. Tables 1
and 2 list these various CVD technologies categorically in their order of
use in the semiconductor process flow. In Table 3 we list the technology,

Table 1: Chemical Vapor Deposition of Silicon and Its Compounds

• SYNTHESIS
• THIN FILMS
EPITAXY
POLY
• OXIDES
• NITRIDES
• CARBIDES
• SILICIDES
80
 Chemical Vapor Deposition 81

Table 2: CVD Processes and Products

• SILICON SYNTHESIS
SiCI4 + H2
SiHCI3 + H2 }
CVD/FLUID BED
SiH4 + H2
• EPITAXIAL SILICON AND POLYSILICON, PROCESSES
H2 + SiCI4
H2 + SiHCI3
H2 + SiH2CI2
H2 + SiH4
He + SiH4

• SILICON NITRIDE PROCESSES

SiH4 + NH3 + H2
SiH2CI2 + NH3 + H2

• SILICON OXIDATION PROCESSES

THERMAL OXIDE --Si ... 02 or H20 (steam)
'*R.D.O.•• SiHCI3 + 02 + H2
SILANE OXIDE ••SiH4 + 02

• SILICON CARBIDE PROCESSES

SiCI4 + C7HS OR C3Hs

• BORON NITRIDE PROCESS

B2H6 + NH3 + N2
BCI3 + NH3 + H2

'* R.D.O. = Reactor Deposited Oxide

Table 3: Chemical Vapor Deposition for Silicon Device Processing

TECHNOLOGY PROCESS USES

SILICON SYNTHESIS C.V.O. HYDROGEN SEMICONDUCTOR PROCESSING,

REOUCTION OF SILICON - 2800 METRIC TONS. 1980
HALIDE

SILICON EPITAXY HCI ETCHING (CVE)

EPITAXIAL OEPOSITION BIPOLAR
(FROM HALIDE OR MOS - LSI STRUCTURES
HYDRIOE H2 RE OUCTION)

POLYCRYSTAL SILICON THIN FILMS GATE ELECTRODE AND INTERCONNECTS.

THICK FILMS DIELECTRIC ISOLATION STRUCTURES
(FROM HAlIOE OR HYORIOE)

SILICON NITRIDE THIN FILM DEPOSITION MASK FOR DIFF USION, IMPLANT, OR
FROM AMMONIA ANO PREFERENTIAL OXIDATION.
(S,H. OR SiH2CI2) ETCH STOP, DIELECTRIC FILM.
SURFACE PASSIVATION LEADS OVERCOAT.

SILICON DIOXIDE Si HALIDE OR HYDRIDE DIFFUSION OR IMPLANT MASK.

• OXIDANT DiElECTRIC FILM.
(° 2- CO 2, N2O) LEADS OVERCOAT.

SILICON CARBIDE SILICON HALIDE WEAR RESISTANT SURFACE,

AND THIN FILM TRANSOUCER MEMBRANE.
HYORDCARBON PROCESS CONTROL ETCH OR POLISHING STOP.
X RAY LITHOGRAPHY MASK.

BORON NITRIDE DiBORANE AND AMMONIA DIFFUSION SOURCES.

(B 2 H6 & NH 3) X RAY MASK
82 Semiconductor Materials

the process by which the technology is formed, and the uses of this
technology in silicon manufacturing. In the synthesis of ultra-high purity
elemental silicon fortoday's semiconductor manufacturing, we may begin
the process with the hydrogen reduction of an ultra-high purity silicon
halide, such as (SiCI 4) or (SiHCI 3 ) 1-4 by CVD of the elemental silicon, on a
high purity silicon rod such as that shown in (a) of Figure 1. This high
temperature reduction takes place in an all quartz system under very
precisely controlled high purity gas flow conditions. When this CVD reaction
has reached completion we will have obtained a polycrystalline rod similar
to the section shown in (b) of Figure 1. This high purity polycrystalline
silicon material is then broken into small pieces, placed in a high purity
quartz liner or crucible which is then heated to the melting point of silicon,
1420°C. After the thermal stability of the molten silicon pool is established,
a carefully oriented seed, cut from single crystal silicon of the desired
crystal orientation, is dipped into this molten silicon and then slowly
rotated and withdrawn to grow the single crystal of the desired diameter. 5
This melt is carefully doped to provide the desired conductivity type and
resistivity forthe slices or substrates. Figure 1c shows the top, or seed end,
of a single crystal of silicon and Figure 1d shows a sawed slice from such a
crystal. The standard diameter of the silicon slice used by most silicon
device or integrated circuit manufacturers today is 125 mm plus or minus
25 mm while 200 mm is being developed. After the crystal is grown and
sliced by the use of diamond saws the slices are ground, lapped and
chemically/mechanically (chem/mech) polished to remove all surface
damage introduced by the sawing, lapping and polishing operation.

EPITAXIAL DEPOSITION

Shortly after the invention of the transistor in 1947 it became evident

that methods other than diffusion or the grown junction would become
necessary for the production of abrupt junctions of semiconductors from
germanium and then latersilicon. The epitaxial process provides a method
of producing these abrupt changes in concentration of doping atoms, or
even in type of conductivity.
Epitaxy is the process of producing a layer of material with exactly
controlled crystallographic, chemical, physical, and electrical parameters.
The single crystal nucleation of this layer is controlled by the host crystal or
substrate which is of a desired and carefully oriented crystallographic
orientation. It also has the proper conductivity type, and carrier concentra-
tion to fit the device or circuit design. In silicon epitaxY,6-1o the epitaxial
layer is usually formed by the hydrogen reduction of a highly purified
silicon halide or hydride. Table 4 defines the epitaxial process and lists
some of the characteristics needed for the epitaxial substrate. The epitaxial
film is usually a continuous film deposited over a continuous single crystal
substrate as in Figure 2. However it may in some cases be a preferentially
deposited film or it may be deposited over a preferentially doped (in certai n
areas) substrate such as that depicted in Figure 3.
Chemical Vapor Deposition 83

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84 Semiconductor Materials

Table 4: Epitaxy

• Epitaxy is the process of producing a layer of material with con-

trolled crystallographic, chemical, physical and electrical param-
eters.

• In silicon epitaxy, the layer is usually formed by chemical vapor-

phase deposition on a carefully polished and cleaned substrate.

• This substrate also has very exactly controlled crystallographic,

chemical, physical and electrical parameters.

• The sil icon epitaxial layer, or layers, is usually the only active
semiconductor material in the device or circuit.

Epitaxial Film

-=---- Substrate

The epitaxial growth process involves the deposition of a thin layer

of material onto the surface of a single crystal sl ice in such a manner
that the layer has the same, crystallographic orientation as the
original crystal and becomes an extension of the substrate. If the
layer materials are the same as the substrate, e.g., Si on Si, it is
known as homoepitaxy, or just plain epitaxy. If they are different,
e.g., Si on sapphire, the combination is termed heteroepitaxy.

During the deposition (growth) of semiconductor layers, the conven-

tional Nand P-type impurit'ies can be incorporated into the layer.
The control of their concentration, as well as the layer thickness, to
the necessary tolerances, makes the silicon epitaxial process one of
the most demanding steps in the Ie manufacturing process. In fact,
epitaxial processes and technologies are listed in the latest 000
military critical technology list as being 0 f such military importance as
to warrant export controls.
 Chemical Vapor Deposition 85

~ POLISHING DAMAGE LAYER

~- 0
SINGLE XTAL SUBSTRATE (111) 3-5 OFF, (100) 00 OFF

~.-- DAMAGE LAYER REMOVED

HCI VAPOR ETCH IN SITU

~- EPITAXIAL FILM DEPOSITED

Figure 2: Epitaxy .

..-- OXIDE PATTERN

_ - POLISHING DAMAGE LAYER
~ SINGLE CRYSTAL SUBSTRATE
(111) 3.5 0 OFF, (100) 00 OFF.

_ _ DIFFUSION OR IMPLANT (OUF)

N OR P DOPANT

OXIDE PATTERN REMOVED

-=
_~---B1-
~~
DAMAGE LAYER REMOVED BY
HCI ETCH IN SITU

~~~AXIALFILM
SUBSTRATE

Figure 3: " DUF " epitaxy.

In the early days of silicon epitaxy most of the work or efforts were
aimed towards the deposition of thin films on (111 )11 silicon substrates by
the hydrogen reduction of silicon tetrachloride (SiCI 4 ), or the silicon tetra-
bromide (SiBr4 ). In other attempts silicon tetraiodide (SiI 4 ) was also used.
Table 5 lists the silicon bearing halides and silicon hydrides in the order of
use historically and also in the order of descending energy or temperature
required for the reduction. In production today most people use silicon
dichlorosilane (SiH 2 CI 2 ). This material readily decomposes at about 10S0°C.
Silicon hydride (SiH 4 ) decomposes at an even lower temperature. However
there are problems in the epitaxial deposition of thick films using (SiH 4 )
due to thermal decomposition in the vapor phase. When this occurs above
the epitaxial substrate particles form in the gas phase which fall on the
substrate resulting in the formation of spurious nucleation sites. It should
also be noted that trich lorosilane (SiHCI 3), tribromosi lane (Si HBr3)' Silane
86 Semiconductor Materials

Table 5: Silicon Epitaxy

• Silicon Source-Halides-Hydride
• SiCl 4-Early
SiBr4
Sil 4

• SiHCI 3
SiHBr3

• SiH 4
• SiH 2 CI 2
• Reduction Source-H 2
• Vapor Etching-HCI

• SiCI 4
• SF 6
• H2 0
• H2

(SiH 4 ) and dichlorosilane (SiH 2 CI 2 ) all may be thermally decomposed. This

is due to the fact that there is a hydrogen atom which is liberated at high
temperatures. However this is not true in the case of the silicon tetrachloride
or the silicon tetrabromide. These two do not thermally decompose, and
therefore must have a reducing agent, such as hydrogen, present to bring
about the reaction.

HCIIN SITU ETCHING

Shortly after the beginning of attempts to do silicon epitaxy in the early

1960s it was learned that the substrate was of prime importance and must
be extremely clean and free of defects at the beginning of epitaxial
nucleation. All attempts to clean the substrate priorto placing the substrate in
the epitaxial reactor met with high density defect levels in the epitaxial
material. Due to this problem the in situ HCI chemical vapor etching (CVE)
process was developed in 1963. In this process the substrates were
initially cleaned and then placed in the epitaxial reactor. The final cleanup,
removal of contaminants and crystallographic defects, is then done at
approximately 1150-1250°C by high temperature in-situ etching, using
HCI as the etchant. 12 - 13 Other etches which have been experimentally
used are listed in Table 5. However, the development of in-situ HCI vapor
etching was a key development in the history of silicon epitaxial technology
and allowed the production of large volume, low defect epitaxial material.
With the development of today's better cleaning and polishing processes,
 Chemical Vapor Deposition 87

epitaxial layers may in some cases be deposited directly on the substrate

without HCI vapor etching. However, in most cases in-situ HCI vapor
etching is still required and in use throughout the industry.
In Figures 4 and 8 we plot the deposition rate of the halides, and the
hydride as a function of mole percent halide and temperature. In Figure 8
we note that the deposition rate versus temperature is a double energy
curve. In general one wants to operate in the left portion, or in the stable
part, of this curve. This allows larger fluctuations in temperature with
smaller affect on deposition rate. Also, in order to deposit high quality
single crystal epitaxy material with a minimum number of defects one
should operate in the 1 to 2 micron per minute or less deposition rate range
as shown in Figure 4.
Figure 5 is a comparative listing of the processes involved in building
both MaS and Bipolar devices or circuits using epitaxial material. In the
Bipolar process described in Figure 5, the epitaxial film is deposited on a
substrate which has been previously patterned and diffused. This process
allows for the production of very high speed Bipolar devices and/or
circuitry. In the MaS process shown in Figure 5, a p+ substrate is used.
This p+ substrate does not interact as an active component in the MaS
structure but only provides a carrier for the epitaxial film in which all of the

DEPOSITION
12
11
10
9
8
c
·E
-.....
7
E
:i. 6
I
w 5
I-
er 4
a:
3
2rJfirsii\iGtE~~~C.L.L.~~ZZ272sUZ
1
o
-1 _...&.---A---'-_.& ...a.--.a.... -.lL-..L-~--L.-__a..._.&_.a.._J

+
2
ETCHING
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
MOLE %Si HALIDE

Figure 4: Deposition and etch rate vs mol % silicon halide. The deposition rate
is also affected by reactor design. Curves A and B are from a vertical reactor.
Curve C is from a multiple slice vertical reactor in which each slice rotates on its
own s~seeptor. Curve D is data from Henry Therur of Bell Labs using a single
sl ice vertical reactor.
 BIPOLAR PROCESS 00
MOS PROCESS 00

PHOS N+ SOUHCEj
REGROWN
!:PHOS OXIDE
I
-L p+--'J PHDSN+~
E ~ Ie=: :5-J~ en
CD
3(5.
I) (100) P+ SUBSTRATE DRAIN
f) SELF AliGNED·SOURCE·
ii) SUBSTRATE
X1DE
~ o
o °p o EPITAXY 0 DRAIN .-REFlOW OXIDE I ~ .c N
+ ~~ el BASE DIFFUSION
::J
C.
C
,.....
(')

I L-
0 0 0 00

~ r:J~
p+
__
00 000
0 0 0 0 0
0 o
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E
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,.....
g) PHOS OXIDE

G
I
rEPITAXY

j I)' EMITTER DIFFUSION -

CD
""""l

~
en

N.EP~::~;:\ ~
c:) OXIDATION
GATE OXIDE I cl

~~
h) CONTACT OR
glCONTACTOR
I
d) GATE OXIDE GATE OXIDE
POLYSILICON GATE /REMOVED I
~~
J""'"f-W~r'-II--~Sr44L~~~""'~~'+-4
d) ISO LATI 0N DIFF USI 0N
WJa ~ .tFIm
i) METALLIZATION
I) ACTIVE AREA DEFINITION h) METALLIZATION
1

(N CHANNEl·SELF ALIGNED GATE) I

Figure 5: MOS-bipolar process comparison.
 Chemical Vapor Deposition 89

active components are fabricated. However, the p+ substrate provides a

backside ground plane which eliminates effects due to substrate noise
generated by the charging and discharging of p-n junction capacitance as
well as process getteri ng action wh ich enhances the characteristics of the
MOS devices built in the epitaxial film. This structure also reduces the
tendency for latchup in CMOS circuits. In today's CMOS process, many of
the circuitss are built in epitaxial material, which is deposited by CVD
processing. In th is CVD epitaxial process, the interface at the su bstrate p+
material and the epitaxial p- material is of utmost importance. In order to
obtain a perfect interface HCI vapor etching is normally required. This HCI
step is carried out in-situ immediately prior to the epitaxial deposition at a
temperature in the range of 1200°C using approximately2 % HCI in hydrogen.
As can be seen in Figure 6, the HCI etch rate increases rapidly to a
temperature of approximately 11 OO°C. One should operate in the flat
portion of the curve above 11 OO°C in order to have well controlled etching.
If the percent HCI is too high with respect to temperature a rough etch front
will develop. Figure 7 shows the ideal conditions for the useful polishing
effect and the non-ideal non-useful effect. From Figure 7 one can find an

2.0
01.9pm 2.0P~
1.8pm . p 1.8pm
c
'E "1.5
E::i.
w·
r- 1.0
<I:
0:
I
~ 0.5
w
EMISSIVITY UNCORRECTED
0.048 pm
1000 1050 1100 1150 1200 1250
TEMPERATURE,oC

Figure 6: Etch rate (HCI-5% in H 2 ) vs temperature.

~ 5
r-
z
~ 4
0::
W
a..
~ 3
::J USEFUL
--l
o POLISHING
> REGION

i 160 1180 1200 1220 1240 1260 1280

TEMPERATURE,OC

Figure 7: Useful polishing region vs % HCI temperature.

90 Semiconductor Materials

etch rate as a function of temperature for any ratio desired. Forexample 2%

HCI at approximately 1220°C is an ideal etching condition in order to
remove the impurities and damaged region of the substrate surface prior
to epitaxial deposition. We are now ready to perform the epitaxial deposition.
Silicon bearing halides, orthe hydride, may be used in orderto perform our
epitaxial deposition. These materials are shown in Figure 8 with silicon
tetrachloride being the silicon source requiring the highest temperature
for deposition, trichlorosilane (SiHCI~ requiring a medium deposition
temperature and dichlorosilane (SiH 2 CI 2 ) or the silicon hydride (SiHJ
requiring the lowest temperature for deposition. In the deposition reaction,
the deposition rate increases as a function of temperature. The cross-
hatched bar zone shown in Figu re 8 delineates the change-over point from
a kinetically controlled reaction to a diffusion controlled reaction. As in the
case of HCI vapor etching, one should operate in the flat portion of the
curve for well controlled epitaxial deposition. The importance of hydrogen
and chlorine, in the reaction cannot be overlooked. Silicon tetrachloride
decomposes in the presence of hydrogen and thermal energy from the
heated susceptor. This material (SiCIJ does not thermally decompose as
does the other halides (SiHCI 3 ) or (SiH 2 CI 2 ) or the hydride (Si H4 ), without the
presence of hydrogen as a reducing agent. The halides and the hydride all
have a hydrogen atom attached to the molecule, wh ile (SiCIJ does not. The
presence of chlorine in the silicon halide is of importance in preferential
deposition. 14- 15 The by-product chlorine and/or HCI gives the silicon atom
a vehicle in which it may be transported from one nucleation site to
another, which may be a more desirable crystallographic site. The by-
product of silicon hydride, does not contain chlorine making this material
somewhat less desirable for preferential deposition unless ch lorine is also
added to the reaction. 14- 16 The effect of silicon atomic mobility ortransport
will be discussed in a later section.

°c
1300 900 800 700 600
1

0.5
OW
~~
_0: 0.2
-1:1:
e::t:.-
~s: 0.1
0: 0
00:
2e,:,
0.05

1 0.02

0.01
0.7 0.8 0.9 1.0 1.1
10 3
---+ - -
(T/K)

Figure 8: Silicon bearing source and deposition rate reduction vs temperature.

 Chemical Vapor Deposition 91

GETTERING

In the ever increasing packing densityfortoday's technologies ofVLSI

and ULSI circuitry, silicon epitaxy plays a very important role. 10 MOS
circuits built in epitaxial material are in general superior in performance to
those built in bulk silicon material. In the past two years considerable
interest has been placed on improving the quality of epitaxial material for
MOS devices. One of the recent developments which has improved the
quality of epitaxial material has been the denuding of defects from the
substrate surface area prior to epitaxial deposition. This denuding is
accomplished by a thermal process which in most cases, consists of a high
temperature cycle (approximately 11 OO°C), followed by a lower or inter-
mediate temperature cycle (approximately 650°C) then followed by a
high temperature (approximately 1OOO°C) thermal cycle. This denuding
process is highly dependent upon the oxygen and/or carbon concentration
in the original bulk silicon substrate. The initial high temperature cycle
provides sufficient energy to dissolve the oxygen precipitates that are
present and to cause out diffusion of the oxygen from the surface areas of
the substrate. The intermediate thermal cycle provides energy for renuclea-
tion and growth to stability of oxygen precipitates in the center, non out-
diffused, region of the slice. The following high temperature cycle provides
energyforthese precipitates to grow and getter oxygen, heavy metals, and
other defects, during device processing, to these precipitate sites. See
Figures 9 and 10.
Figure 9 shows a cross-sectional view of a denuded substrate after
epitaxial deposition. The high bulk defect density is evident as is the
denuded zone just below the epitaxial silicon interface. In this figure there
are defects at the interface between the epitaxial film and the original
substrate. This indicates that no HCI vapor etching was carried out in this
process. It also shows that the original substrate surface acts as a trap to
hold these defects, which may be bulkstacking faults, oxygen precipitates,
heavy metals, or carbon atoms. Figure 9 is a photograph of a cleaved
silicon slice. No polishing or potting was required prior to the Wright
Jenkins etch in orderto bring outthe defects in the denuded areaas well as
the epitaxial film. It is also interesting to note that the defects at the
substrate/epitaxy interface do not cause defects in the epitaxial film at a 1:1
ratio. It appears that only approximately one out of 10 defects at the
interface actually cause stacking faults or defects in the epitaxial film.
Another method of slice/wafer processing that improves device per-
formance is that of backside gettering prior to epitaxial deposition. There
are several methods of backside gettering including sandblasting or
abrading of the back surface of the substrate to produce defects or traps,
and oxide or nitride films on the backside surface to produce strain fields.
However the most successful appears to be that of depositing a thin CVD
film, approximately 1 micron thick, of polycrystalline silicon across the
back surface of the epitaxial substrate prior to final polishing of the front
side. The high density of defects produced by the grain boundaries and
dislocations, due to the polycrystalline film, provide a very effective getter-
ing mechanism. During device processing heavy metals may be gettered
92 Semiconductor Materials

Q)
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 Chemical Vapor Deposition 93

Figure 10: (a) 90° cleaved cross section, epitaxy on denuded substrate with back-
side-gettering poly Si. layer. 198X P.C. 5 minute W.J. etch. (b) (c) Misfit disloca-
tion extrinsic gettering.
94 Semiconductor Materials

all the way from the front surface to the back surface where they are
trapped at these defect (gettering) sites.
Figure 10a shows a cross-section of a cleaved slice which has a
gettering region at the back surface, a denuded zone just above the
backside gettering media, the high density bulk defect area of the slice,
and then at the top surface a denuded zone just below the epitaxial-
substrate interface. Agai n, a row of defects is noticable at the epi su bstrate
interface indicating that this substrate had insufficient or no HCI vapor
etching, in situ, prior to the epitaxial deposition. This also shows that one
could build in intrinsic gettering at desired positions immediately below
the active device region of the semiconductor circuit. This type ofgettering
immediately below the active surface area is very effective 18 and can also
be designed in discretionarily to provide gettering only at the desired
circuit areas. Figure 1Oa is a cleaved cross-sectional view which required
no polishing or potting prior to the Wright-Jenkins etch to delineate the
defect region, the denuded zone, and the epitaxial layer as well as the back
side gettering polycrystalline silicon film.
As mentioned above, in-situ HCI vapor etch ing will remove the damage
sites and/or surface traps prior to epitaxy. However, one may wish to leave
or form a new damage layer, for low temperature processing intrinsic
gettering, in near proximityto the active device region of the structure. If so,
a film can be deposited between the substrate and the epitaxial film which
is intentionally doped with, for example germanium, to produce a built-in
misfit dislocation strain field. 10,17,18 Figure 108 shows a cleaved cross-
sectional view of a single layer misfit dislocation, extrinsic gettering strain
field, and a single layer epitaxial film. Figure 10c shows experimental
multiple layers of strain field/epitaxial silicon films with increasing Ge
doping in the strain fields as they were deposited. This increase in Ge
doping causes a noticeable increase in the density of misfit dislocations
within the strain field layers. Wright-Jenkins etch was used to reveal these
damage sites.

SELECTIVE DEPOSITION

It was previously mentioned that silicon atoms, deposited from vapor

phase, have surface mobility and tend to deposit in single crystal form at
preferred nucleation sites. In Figure 11 we show a silicon slice which has
both an oxide and an open silicon area exposed. The oxide covers most of
the photographed area with the exposed single crystal area only at the top
of the photograph. As a result of preferential epitaxial deposition, the five
silicon octahedral growths, deposited on the oxide are all crystallographic-
ally aligned with the substrate orientation. This indicates that the nucleation
was due to pinholes through the oxide and not at nucleation sites on the
oxide. If silicon is allowed to deposit out in free space, with no constraints, it
will always form an octahedral shape bounded by eight (111) faces. In
Figure 11, we see the octahedral form of the top four of these (111) facets.
Note the alignment of the (111 's) in each octahedron with each other, thus
indicating that epitaxial nucleation propagates from the substratethrough
Chemical Vapor Deposition 95

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96 Semiconductor Materials

the oxide pinhole. Note also in this figure that the surrounding area is
completely free of polycrystalline silicon deposition or nucleation on the
oxide. This indicates that the silicon atoms, above the oxide area, moved to
a preferred site in the open silicon area. We can take advantage of this
atomic mobility for preferential deposition of silicon at desired sites on an
otherwise oxide or nitride covered mask substrate. Such a mask is shown
in Figure 12. Shown in this figure are five micron diameter circles, on 25
micron centers, opened up through an oxide or a nitride mask on a silicon
substrate. The goal in this experiment is to preferentially deposit epitaxial
silicon in the five micron diameter circles but have no poly silicon nucleate
on the oxide. An epitaxial diode will be formed at the interface of the
original p substrate with the n epi deposit. After the epitaxial growth has
proceeded up through the mask, in this case oxide, lateral spreading
occurs over the oxide to form a large area "epi top" for electron beam
charging. This process provides a very small area p-n junction diode with
very low parasitic capacitance but with a large "epi top" beam collection
area for the production of Vidicon type detectors. In this process the
preferential deposition must be very complete in that single crystal silicon
is nucleated in the open areas. No spurious nucleation of polycrystalline
silicon can be tolerated on the oxide which would bridge across two diode
"epi tops" thus causing a defect in the array. The diode density in this array
is one million diodes per square inch.
Figure 13 is a top view of such an array after preferential deposition.
The (1 00) structure is clearly evident in the epitaxial "epi tops". "Epi tops"
deposited on (111) substrates show an equilateral triangle structure
whereas the (100) substrate gives the perfect square "epi top" orientation.
Figures 14a and 14b show two SEM photographs with 14a being a low
angle SEM of the cross-sectioned substrate/epi structure and 14b being a
near 90 degree cross-section after the oxide had been etched away. In
14a, the original diode area can be seen as well as the mask oxide which
has been broken away with the cleavage of the slice. In the cross-section at
14b the original diode structure or size can be seen at the substrate
interface. The lateral spreading, in all directions, over the oxide is approxi-
mately equal to the diameter of the original diode, thus a 3X increase in
diameter and >9X increase in area.
Other examples of preferential deposition making use of the atomic
mobility of the silicon atom are shown in Figures 15 through 18. Figure 15
shows the preferential epitaxial deposition of silicon in the vertical lines
across the bottom portion of the slice. In this grating there are three micron
wide lines of oxide with two micron wide areas of open silicon between
them. Single crystal silicon is nucleated in the open silicon areas and
grows up through the oxide and then spreads laterally as shown in Figure
18. Also shown in Figure 15 in the top portion of the photograph is an area
with continuous oxide mask with polycrystalline silicon nucleated only on
the top half of this oxide area. The lower half of the oxide area is completely
clean and free of spurious nucleation of polycrystalline silicon. The silicon
atoms have enough mobility, to move to preferred sites in the open silicon
area or to deposit out (at super saturation) as polycrystalline silicon over
the oxide. In this experiment, the deposition temperature was 1150°C and
Chemical Vapor Deposition 97

V)
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98 Semiconductor Materials

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Chemical Vapor Deposition 99

Q,)

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100 Semiconductor Materials

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Chemical Vapor Deposition 101

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102 Semiconductor Materials

Figure 17: Oxide pattern outside corner effect on silicon atomic mobility.

the mole ratio of silicon halide (SiHCI 3 ) in hydrogen was 1.12%. At these
conditions and maskgeometrythe atomic mobility of the silicon atoms was
great enough forthe atom to move approximately 23 microns, which is one
half the distance between the open silicon pattern and the area of heavy
polycrystalline nucleation over the oxide for a total of at least 47 microns.
The atomic mobility is greatly affected by the halide being used, SiH 2 CI 2 ,
SiHCI 3 or SiCI 4 , the mask geometry (open silicon to mask area), and the
operating temperature, which provides the energy to move the silicon
atom. The atomic mobility increases as the temperature increases or as
the mole ratio decreases, or in other words, as the energy to move the atom
increases or the number of silicon atoms competing for a preferred site
Chemical Vapor Deposition 103

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104 Semiconductor Materials

decreases. It should also be noted in Figure 15 that the polysilicon

crystallites along the lower portion of the poly zone over the mask oxide
are much larger than those further up in the field. The larger crystallite size
is due to the availability of silicon atoms migrating from the oxide region
between the nucleation sites and the open silicon grating pattern. Further
evidence of the influence of the silicon availability will be shown in Figure
18 for the deposition of a si ngle crystal film over a dielectric (oxide) grating
pattern.
Figures 16 and 17 also show the effect of the silicon availability on the
growth of large polycrystalline crystallites over an oxide pattern. Figure 16
shows a portion of the pattern which has a large area of continuous oxide
with the open silicon/oxide grating pattern across the bottom and along
the right side of the photograph. Again, the epitaxial silicon nucleates in
the open area of the silicon grating and grows up through the oxide and
then spreads laterally over the oxide. Further note, that the zone along the
bottom portion of the continuous oxide mask area is completely free of
poly nucleation as is that along the right side of the continuous oxide
grating pattern. Further note the increased distance from the bottom right
corner of the continuous oxide up to the arc of the poly nucleation. This
shows the strong influence of the available nucleation sites in the silicon at
the openings along the right side and at the lower edge of the oxide
pattern. In this corner area a silicon atom on the oxide can move either to
the right or to the bottom and find a silicon nucleation site, thus having
twice the effective mobility as those silicon atoms at the extreme left and
extreme upper right of the unpatterned oxide mask area. This figure shows
the affect in a convex or outside oxide pattern.
Figure 17 shows the opposite affect for a concave or inside continuous
oxide pattern. In this case the available atom only has half as many
available sites as in the case of the convex oxide corner. Therefore the
distance from the corner of the open silicon oxide grating to the nearest
polysilicon nucleation site is greatly reduced.
Figure 18 shows an enlarged view of the epitaxial silicon nucleated in
the open areas of the grating, and growing up through the open area then
spreading laterally over the oxide which is three microns wide. Single
crystal lateral overgrowth is evident due to the (1 00) oriented epitaxial
stacking faults. These stacking faults are all aligned with each other as well
as with the edge of the mask, which is aligned with the (110) slice flat
indicating epitaxial nucleation at the (100) substrate. The size of the
stacking faults is considerably larger around the periphery of the grating
oxide pattern. The size of the stacking fault is a method for direct measure-
ment of the thickness of the epitaxial film. 19,21 If one measures the length of
any side of the (100) stacking fault and multiplies that length by 0.707 one
will have the true thickness of th~ epitaxial layer at that point. This example
is direct evidence that the silicon atoms moved from the oxide maskarea to
a preferred site in the open silicon grating. The density of available silicon
atoms is greater along the periphery of the continuous oxide mask, thus
giving rise to a higher rate of epitaxial deposition, and a thicker film, along
the periphery of the open silicon grating area, as indicated by the epitaxial
stacking fault size.
 Chemical Vapor Deposition 105

CVD OF DIELECTRIC FILMS

In today's semiconductor processing flow we quite often use CVD for

the deposition of silicon nitride and in some cases silicon dioxide. These
films may be used as dielectrics or as passivation films. Both atmospheric
and low pressure processes are used forthe deposition of si licon nitride. In
either case, NH 3 , and SiH 4 or SiH 2 CI 2 are used as the nitrogen and silicon
bearing sources respectively (see Table 2).
Figure 19 shows the deposition rate for silicon nitride as a function of
temperature. Again the deposition of silicon nitride as in the case of the
epitaxial silicon process is a diffusion limited and a kinetically controlled
deposition process. One should operate in the diffusion limited portion of
the curve, above approximately 850°C forthe atmospheric pressure mode
of silicon nitride deposition.
Figure 20 gives the deposition rate curves for the deposition of silicon
nitride with a fixed amount of ammonia, 1.2%, fortwo amounts of silane. The
refractive index and the dielectric strength of the silicon nitride film are
greatly affected by the ammonia to silane ratio. In practical operation one
should use a volume of ammonia greater than 10 times that of silane (see
Figure 21) in order to produce good high quality dielectric films. These
films should have a refactive index of 2.0 +/- 0.05. If the refractive index of
the silicon nitride is less than 2.0 the silicon nitride probably contains
silicon dioxide. If the refractive index is greaterthan 2.0 the silicon nitride is
probably silicon rich 22 (Figure 21).

°c
10,-00_ _9-r0_0 _ _80,-0_ _7-r0_0 -,
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10 '----.1.-_'-----'--_1....-----'--_'---....
0.70 0.75 0.80 0.85 0.90 0.95 1.0 1.1
1000ff K

Figure 19: Si 3 N4 deposition rate vs temperature.

106 Semiconductor Materials

°c
1150 1000 900 800 700
H2 FLOW RATE 40 I/min
:2: %SiH4 0.095 •
~ %SiH4 0.065 •
~ 10 3 % NH3 1.2
w
.-ct
a:
:2:
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10 L . . - - - - ' L - _ I . . . - - _ I . . . - - _ I . . . - - _ a . . . - - _ a . . . - - _
0.70 0.75 0.80 0.85· 0.90 0.95 1.0 1.05
1000rr I(

Figure 20: Si 3 N4 deposition rate vs temperature.

In the dielectric isolation (01) process 23 ,24 used for high-voltage, high-
speed, and radiation hardened circuitry, CVO processing is used in several
steps. It is used to deposit oxide, in addition to thermal oxidation, to form a
pinhole-free sandwich of thermal oxide and CVO oxide. It is used in the
polycrystalline silicon deposition step and may be used for the deposition
of silicon nitride and/or silicon carbide films. The 01 process offers advan-
tages in several areas such as radiation hardened capability, high-voltage,
high-speed, and process control capability. However, it is not widely used
due to it's high cost. In normal p-n junction isolation, a reverse bias junction
isolates the active components within the circuit, (Figure 22). The formation
of this junction, however, causes high parasitic capacitance around each
device in the circuit. This parasitic capacitance decreases the speed at
which the device is capable of operating. The isolation voltage between
the two adjacent devices is a function of the resistivity or doping concentra-
tion of the high resistivity side of the junction. The isolation voltage in a p-n
junction isolated circuit or array is normally less than 100 volts, whereas, in
the case of a 01 structure the operating voltage or isolation voltage is
several hundred volts. In fact, in most 01 structures, the isolation will not
break down between adjacent com ponents but will break down across the
surface at voltages of >450-500 volts. In the dielectric isolation process
(Figure 22), the p-n junction isolation is replaced in function by a dielectric
film such as Si0 2, Si 3 N4 , or combinations of Si0 2 , Si 3 N4 , and/or SiC. The
replacement of this large area capacitor or p-n junction isolation around
each device by a thermal oxide and/or other dielectric material effectively
gives the device very high switching speed capability as well as very high
voltage operating capabilities. Oevices produced by the 01 process also
have higher radiation tolerance due to the fact that a radiation particle is
 Chemical Vapor Deposition 107

DEPOSITION SOURCE
SiH4 + NH3 + H2 Six Ny (Si3N4) + Gas By Products
SiH2CI2 + NH3 + H2 SixN y (Si3N4) + Gas By Products

USES
OXIDATION MASK
ETCH MASK
PASSIVATION

I I I I
I DEPOS ITION TEt,'P. -850 C 0

-
FLO'/J RATE 40 I/min
~
% SiH 0.065

.\
4

3
z
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~ NH
3
----- Si Hi ch -------~-.41
-.... Stoichiometric Si3N4

JECS, Vol. 114, No.7,July 1967

Figure 21: CVD-sil icon nitride.

108 Semiconductor Materials

c
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 Chemical Vapor Deposition 109

more readily blocked by the 01 media than by a p-n junction. Theoretically

the 01 process also offers advantages in packing density.
The effect of packing density may be seen in Figure 22 which compares
the 01 process with the junction isolation process. The high packing
density capability of the 01 over that of the p-n junction process is brought
about due to the fact that the p-n junction is subject to lateral spreading of
the junction isolation. Whereas the dielectric isolation is formed by a
dielectric, such as Si02 or silicon nitride, thermally grown or CVO deposited
(see Table 2) on crystallographically sharp, orientation dependent etched,
crystallographic planes. In the case of the 01 structure the final substrate
or carrying media is a thick polycrystalline silicon film, whereas in the p-n
junction isolation process the substrate orcarrying structure is the original
p- single crystal substrate. The formation of this thick polycrystalline
structure is one of the steps which makes the 01 process expensive. The
process is outlined in Figure 23.
Figure 23 shows the flow process for manufacturing the 01 thermal
printer printhead and is in general the same process that would be
required for the production of high voltage isolated, high-speed, or radiation
hardened devices. The process starts with the selection of (100) orientation
silicon of the desired resistivity and type for the bipolar p-n junction
collector. (Not only bipolar devices but also combinations of bipolar and
field affect or MOS structu res can be fabricated in 0 I material). The second
step in the 01 process is to form a mask oxide by thermal oxidation across
the surface of the (1 00) orientation slices. A photolithography mask is then
used to open up the oxide in the desired patterns of the isolated devices.
Th is step is carried out by conventional photolithography processing. After
the oxide has been removed in the desired isolation pattern, an orientation
dependent etch is used to etch trenches or v-shaped grooves into the
(100) oriented substrate. These trenches or grooves are etched around
each component that is to be isolated from its neighbor in the structure and
around each circuit. These isolation grooves are crystallographically sharp
and the depth of the isolation groove is controlled completely by the width
of the oxide opening at the surface. Exact control of the etched depth by
the oxide mask opening permits the etching of built-in thickness indicators
at the same time as the orientation dependent etching of the isolation
moats. These built in thickness indicators are used at the lap and polish-
back process step to provide very accurate indicators of the thickness of
the remaining single crystal silicon in each isolated tank Afterthe isolation
etch step is completed the mask oxide is stripped from the surface and a
thermal oxide is grown across the orientation dependent etched moats
and mesas. In the case for high-voltage or radiation hardened devices, a
second dielectric isolation media such as a CVO oxide is also deposited in
order to ensure a pinhole-free 01 structure. In the case of the electronic
printer as outlined in Figure 23, a silicon nitride film (Figure 21) or silicon
carbide film (see Table 6) may be deposited as the second 01. This film will
also act as a wear resistant film in the final device structure. If the device is
built for high-speed applications, a collector contact media such as a
diffusion or thin epitaxial deposition of high carrier concentration can be
deposited prior to the deposition and/or thermal growth of the 01 media.
110 Semiconductor Materials

(I)
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 Chemical Vapor Deposition 111

Table 6: CVD of Silicon Carbide

DEPOSITION SOURCES

SiC I4
C7Hg Toluene
SiHC I3
+ + ~H SiC + HCI
------.
SiH2CI2 or
C3Hg Propane H2
SiH4

USES

• WIDE BAND GAP / HIGH TEMPERATURE SEMICONDUC-TOR

• WEAR RESISTANT SURFACE
• CHEMICALLY IN ERT ETCH STOP
• X-RAY LITHOGRAPHY MASK PELLICLE

This thin film collector contact structure will be exposed at the top surface
of the final device structure giving extremely low resistance to the collector
contact which provides very fast collector saturation and in turn high-
speed capabilities. Afterthe 01 material is deposited and/or grown, a thick
polycrystalline silicon film is CVO deposited across the structure. This film
is normally the same thickness as the starting substrate, in the order of 0.5
mm in thickness. Afterthe thick polycrystalline silicon film is deposted, the
structure is inverted and the original substrate is ground and polished until
the isolation moats and/or thickness indicators are visible. At this time a
final polish is applied and the structure is ready forfinal device processing.
The starting structure was the collector resistivity material, however, it is
possible to have a collector contact exposed at the surface if desired. In
the electronic printer process the next steps are the formation of the base
and then the emitter by diffusion followed by metallization as in a conven-
tional junction isolation processing. At the grind and polish process step
the extremely hard silicon carbide and/or silicon nitride will act as a
polishing stop. This aids in the planarization of the entire structure. After
the metallization, which may be CVO polysilicon, silicide, or metal, is
applied, in the electronic printer process the structure is bonded down to a
ceramic which has matching metallization leads. The thick polycrystalline
silicon layer is then removed by grinding and/or etching back to the
original ODE surface which is now covered by oxide, nitride, or carbide. All
of these 01 materials act as a good etch stop. However the nitride and/or
carbide are superior in stopping the etch and in providing a wear resistant
surface for the electronic printer.
112 Semiconductor Materials

Figure 24 shows a top view of the electronic printer printhead which is

asmall silicon chipconsisting oftwo5X 7 arrays. Each ofthe35 components
in the arrays are dielectrically isolated from each other. Each array is the
size of an upper case letter or figure on a typewriter. The ODE etched
scribe lines are evident in Figure 23 surrounding each pair of arrays which
are still in slice form. This printhead prints silently at a speed of 120
characters per second. The use of two 35 dot printer arrays in one
printhead allows the high-speed. One array prints and then the other,
alternating as the pri nthead moves across the thermally sensitive paperto
minimize thermal memory effects. This printhead structure must be ther-
mally isolated, electrically isolated, and mechanically stable. The built in
control thickness indicators are visible as five small black rectangles
between the two printhead arrays. The single individual isolated moat
structure in the upper left hand corner of the double array is a thermistor
which senses the print head temperature and controls the voltage to
prevent over heating.
Figure 25a shows a low angle SEM top view and Figure 25b shows a
near right angle or 90 deg cross-sectional view of the 00 E isolation moats.
In (a) a portion of the 5 X 7 printer array is shown. In this particular design of
the printhead, the thermal sensor is shown at the extreme left in Figure (a)
and is located immediately adjacent to the active 5 X 7 printer array
whereas the sensor in Figure 23 is more remotely located. The very exact,
crystallographically sharp, control of the ODE isolation etch is evident
both in (a) and (b) of Figure 25.
Figure 26 shows a conventional high-speed or radiation hardened
circuit produced by the 01 process. The black lines surrounding each
individual component in the circuit is the vertical edge of the 01 film.
Figure 27 shows the electronic printer double printhead following the
metallization step. Again, the black line surrounding each printer dot in
Figure 26a is the 01 media at the surface.
Figure 27 shows an artist drawing of the cross-section as the printhead
would appear at this step. Figure 27c is an artist drawing of the cross-
section of the electronic printer as it would appear in its final structure. The
individual printheads have been bonded to a ceramic header and the thick
polycrystalline silicone has been removed from the active side of the
printer head.
Figure 28 is an enlarged view of the active printhead surface showing
the individually isolated components. Each component heats on command
due to the emitter/collector resistivity, and then cools quickly in orderto by
electrical command thermally addrass the thermal sensitive paper. Each
of these 01 components are approximately 0.35 mm square at the surface
region and are separated only by the thin 01 material which is in this case
approximately 1.5 microns thick on each wall for a total of 3 micron
separation between active components.
Figure 29 shows a SEM cross-section of one of the individual ODE
etched 01 mesas following the thermal oxidation, CVO oxide deposition,
and CVD silicon carbide deposition steps. The 01 films of Si0 2 and SiC are
readily evident in this SEM photograph. Silicon carbide or silicon nitride
would not be required in standard processing for high voltage or radiation
 Chemical Vapor Deposition 11 3

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114 Semicof'ductor Materials

Figure 25: (100) dielectric isolation processing.

hardened circuits and is used here as a process control as well as a wear

resistant surface film media on the final printhead surface.
Figure 30 shows a close up view of a portion of the 5 X 7 dot, mesa
printhead array in its final form, with the ODE mesas covered with silicon
carbide for wear resistance.
Figure 31 shows the relationship of the individually etched and isolated
mesas to the complete printhead array as well as the relationship of the
printer array to that of the ceramic chip to which it is bonded. It also shows
the relationship of the ceramic chip to the electronic printer which is the
size of a standard portable typewriter.
 Chemical Vapor Deposition 11 5

Figure 26: Completed dielectrically isolated circuit.

X-RAY LITHOGRAPHY MASK FABRICATION

CVD of silicon carbide, silicon nitride, silicon dioxide and/or boron

nitride may be used in the processig of x-ray lithography mask 25,26 The
process steps for producing such a mask are shown in Figure 32. In this
case CVD deposited silicon carbide is used to illustrate the process,
however, silicon nitride, silicon nitride in combination with silicon dioxide
or boron nitride can also be used. The process starts byCVD deposition of a
thin film of one of the above mentioned materials onto asilicon substrate'of
the desired diameterforthe final mask This thin film will be the final pellicle
or thin membrane which supports the x-ray blocking mask material which
116 Semiconductor Materials

8
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Chemical Vapor Deposition 117

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118 Semiconductor Materials

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 Chemical Vapor Deposition 119

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120 Semiconductor Materials

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 SILICON SUBSTRATE

.\ ~ < SiC DEPOSIT (CVDI

INVERT
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SILICON REMOVED 0"

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, W"jjM , lj'j'jie " " rrm " " -iiMlte • " GAil" IjiiJ • PATT EAN BYE·BEAM

~ ~
::+
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INVERT :
f\)
Figure 32: X-ray lithography mask fabrication.
122 Semiconductor Materials

may be, e.g., gold. Afterthe th in pell icle orwi ndow, wh ich is transparent to x-
rays and also transparent in the visible wavelength region is deposited, the
structure is inverted and the silicon is etched from the central portion of the
original silicon substrate leaving a supporting ring of silicon around the
periphery of the structure. The gold or x-ray blocking material may be
deposited and patterned prior to this etch step or it may be deposited and
patterned following the silicon etching step. The silicon carbide, silcon
nitride/oxide, or boron nitride film forms an exact replica of the starting
substrate surface at the thin film/substrate interface. This very exact
replica of the polished substrate provides a very flat, highly reflective
membrane surface on which the gold is to be deposited. If silicon carbide is
to be used as the pellicle one may use the hydrogen reduction of silicon
tetrachloride(SiCIJ and propane(C 3 Ha), both being of electronic grade, at
a deposition temperature of approximately 1200°C. The film should be
deposited at as near stoichiometric conditions as can be obtained in order
to produce transparent stress-free films. These conditions can be obtained
by using approximately 0.89% silicon tetrachloride (SiCI 4 and 0.37% pro-
pane (C 3 H a). If one wishes to deposit boron nitride by CVD (see Table 7) one
may use the boron hydride (B 2 H 6 ), diborane, at 4.4% in hydrogen and
ammonia (NH 3 ) 6.6% at approximately 530 degree C in an epitaxial-type
reactor. In general the silicon carbide pellicle is the strongest and most
stable pellicle. The silicon carbide pellicle orwindow may be as thin as 1.5
microns, whereas the boron nitride film must be in the order of 4-6 microns
to form the transparent membrane across a 100 mm diameter mask.
Figure 33 shows the visible transmission of a thin 1.5 micron, silicon
carbide pellicle across a 100 mm diameter silicon slice ring. The central
portion of the sil icon has been removed and the visible transm ission of the
silicon carbide pellicle is evident due to the transmission of the printed
advertisement for the Datachron calculator photograph below it. This thin
membrane or pellicle must have high x-ray transmission and high visible
transmission for rough preliminary alignment of the mask by visible tech-
niques.
Figure 34 shows a photograph of the completed silicon carbide pellicle
with the gold patterned x-ray mask formed on it.

Table 7: CVD Boron Nitride

DEPOSITION SOURCE

BN + H

BBr3 HBr
or + N H3 + H2 BN + or
BCI3 HCI

• SOLID STATE DIFFUSION SOURCE

• X-RAY LITHOGRAPHY MASK
Chemical Vapor Deposition 123

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124 Semiconductor Materials

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 Chemical Vapor Deposition 125

This chapter presents a few of the many chemical vapor deposition

processes used in today's manufacturing of semiconductor devices and
circuits. The references direct you to only a few more of the many articles
on this subject found in the open literature.

REFERENCES
1. DuPont Process: D.W. Lyon, J. Electrochem. Soc., 96: 356 (1949) Process used
by DuPont, Eagle Picher, and Sylvania/Siemens Process: E. Spenke, Semi-
conductor Silicon, Elecrochem. Soc. 1 (1969).
2. Eagle Picher Research Laboratories, Fourth Quarterly Report, Contract #
DA36-039-SC-66042, (July 1, 1956).
3. Eag Ie Picher Process, Sixth Quarterly Report, Contract # DA36-039-SC-64694,
Aug. 1,1956 to Nov. 1,1956, U.S. Signal Corps. Project No. 152 B. Also Final
Quarterly Report, this contract Feb. 1, 1957 to May 1, 1957.
4. W.R. Runyan, Silicon Semiconductor Technology, vol. 12 McGraw-Hili, (1965).
5. G.K. Teal, and J.B. Little, Phys. Rev. 78: 647 (a) (1950).
6. R.C. Sengster et aI., J. Electrochem. Soc. 104: 317 (1957).
7. H. Mark, J. Electrochem. Soc. 107: 568 (1960).
8. H.C. Theurer, J. Electrochem. Soc. 108: 651 (1961).
9. B.A. Joyce and P.R. Bradley, J. Electrochem. Soc. 110: 1235 (1963).
10. KE. Bean, W.R. Runyan and R. Massey, Semiconductor International, 136 (May
1985).
11. KE. Bean, and P.S Gleim, IEEE, 57: 1469 (1969).
12. G.A. Lang and T. Stavish, RCA Rev. 4: 488 (1963).
13. KE. Bean and P.S. Gleim, Electrochemical Society, Fall Meeting, Oct. 1963, late
newspaper, Abs. J.E.C.S. (Dec. 1963).
14. K E. Bean, Thin Solid Films 83: 173 (1981).
15. J.O. Borland, and C.1. Browley, Solid State Tech. 141 (Aug. 1985).
16. H. Kurten et ai, IEEE Trans. Elec. Dev. ED-30, 1511 (1983).
17. G.A. Rozgonyi and C.W. Pearce, Appl. Phys. Letters 31: 343, (1977).
18. A.S.M. Salih et ai, J. Electrochem. Soc. 133: 475 (1986).
19. S. Mendelson, Single Crystal Films, Proceedings of Conference held at Philco
Blue Bell, PA, (May 1963).
20. S. Mendelson, J. App. Phys. 35: 1570 (1964).
21. S.K Tung, J. Electrochem. Soc. 112: 436 (1965).
22. KE. Bean, P.S. Gleim, and R.L. Yeakley, J. Electrochem. Soc. 114: 733 (1967).
23. U.S. Davidsohn and Faith Lee, Proc. IEEE, 57: 1532 (1969).
24. KE. Bean and W.R. Runyan, J. Electrochem. Soc. 124: 5C (1977).
25. T.L. Brewer, R.K. Watts, and K.E. Bean, Electrochemical Society Proceedings of
Symposium of Electron and Ion Beam Science and Technology, 8th Interna-
tional Conf., Electrochemical Society Proceedings, 78-5,453 (1978).
26. H. Luthje, et ai, 30th International Symposium on Electron Ion and Photon
Beams, N-4, (May 27-30, 1986).
4
Chemical Etching and Slice
Cleanup of Silicon

Kenneth E. Bean
Texas Instruments Incorporated
Dallas, Texas

INTRODUCTION

Slice cleaning and wet chemical etching have been key semiconductor
processing technologies since the beginning of semiconductorfabrication in
the late 1940's and early 1950's. The demand for cleanliness, control of
purity: and freedom from defects becomes more stringent with each
advance in device and circuit complexity. This chapter discusses wet
chemical etching of silicon from the standpoint of planar etching, orienta-
tion dependent etching (ODE), concentration dependent etching, and
defect delineation etching. It also discusses the etch composition, the
masking materials used for preferential etching, mask alignment, and
applications for the above etching technologies. We will also discuss
silicon slice cleanup procedures and effects thereof. Table 1 summarizes
the subjects to be discussed, in order of discussion.
Planar etch is a solution that etches silicon in all crystallographic
directions at the same rate. A common formulation is made up by mixing
hydrofluoric acid (H F)~ BO/o byvolume, nitric acid (H N03 ) ~ 75 0/0,'and acetic
acid (C 2 H4 02) ~ 17%. At 25°C this solution etches silicon slices (wafers) at
approximately 5 llm per minute, (see Table 2). Orientation dependent
etches (ODE) have been developed which etch much faster in one crystallo-
graphic direction than in another. For example, a solution of potassium
hydroxide and water(KOH + H2 0) in equal parts (50%-50% weight) at BOaC
etches silicon in the < 110> direction ~ 700 times fasterthan in the <111 >
126
 Chemical Etching and Slice Cleanup 127

Table 1: Chemical Etching and Slice Cleanup of Silicon

*WET CHEMICAL ETCHING *EFFECTS IN (100) SILICON

• PLANAR • FOUR FOLD SYMMETRY

• ORIENTATION DEPENDENT • ETCH SOLUTIONS
• CONCENTRATION DEPENDENT • MASK SYMMETRY
• DEFECT DELINEATION • ALIGNMENT
• SLICE CLEANUP "ETCHES" • APPLICATIONS
*EFFECTS IN (110) SILICON *DEFECT DELINEATION

•
•
• (111)TRACE-FLAT
ETCH SOLUTIONS
ALIGNMENT
• (100) I SECCO
WRIGHT-JENKINS
SCHIMMEL
• APPLICATIONS
SIRTL

·SILICON SLICE CLEANUP

• (111)
IDASH
LEO'S

• STANDARD CLEANUPS
• CHOLINE CLEANUPS

Table 2: Chemical Etches and Characteristics for Silicon

ETCHES CHARACTERISTICS COMPOSITION RATE AND REMARKS REF

PLANAR ETCH ETCH UNIFORMITY HF - HNOJ - HAc ~5 pm/MIN AT 25"C
1
~8% ==75% ~17% (IN ALL DIRECTIONS)
1-3-10 ETCHES P+ OR N+ SILICON HF HNOJ HAc ~Jpm/MIN (100) 2SoC
2
"STOPS" AT P- OR N- 1 3 10
(100) ODE ETCHES (1001 -100 X (111) KOH - NORMAL ~1 Slm/MIN AT BO°C, [100)
DIRECTION PROPANOL - H2O "STOPS" AT P++ INTERFACE
KOH - 250 gm ETCHES Si3N4 AT 14A/HR 3-5
N PROP - 200 gm Si02 AT 20A/MIN
01 H20 - 800 ym
(tl0) ODE ETCHES [1101 60a X (1111 KOH - H2O ~0.8 Slm/MIN AT ao°c
IN (110) SILICON
5-7
DIRECTION 50-50 VOl.
ETHYLENEDIAMINE ORIENTATION DEPENDENT ETHYLENEDIAMINE - ~1.1IJm/MIN AT 100°C IN [lOa).
AND CONCENTRATION PYROCATECHOL - H2O "STOPS" ETCHING AT P++ INTER-
DEPENDENT EDA - 255cc FACE. VERY SLOW ETCHING OF 5-8
H20 - 120cc SiD21~JA;MIN) "NO" ETCH OF
P.C. - 45 glO AI, Au, Ag, Cu, Ni OR Ta.

direction. See Table 2 and Figure 2B.lfwe add normal propanol to the KOH
and H2 0 etch, we can also etch silicon in the < 100> direction approxi-
mately 100 times faster than in the < 111> direction, at BO°C. See Table 2
and Figure 10.
If we mix the same mineral acids used in the planar etch solution in the
ratios of one part HF, three parts H N03 , and 1a parts C2H4 02' we have an
etch commonly known as Dash etch, which etches p+ silicon or n+ silicon,
>7X10 19 carrier concentration, much faster than p- or n- silicon. In
contrast, the KOH-propanol-water etch "stops" (slows down by ~ 20X) at a
p+ interface. The ethylenediamine (EDA) etch, made up of EDA, pyrocate-
chol and water (see Table 2) is also both orientation dependent and
128 Semiconductor Materials

concentration dependent in etching silicon and has the advantage of

etching silicon dioxide very slowly (3 A/min) at 100°C.
In today's high density circuit technology the detection, ordelineation,
of material defects is of great interest and importance. Wet chemical
etching is commonly used to show these defects. In general, these solvents
preferentially etch the damage site due to the strained or damaged crystal
lattice bonding in the defect area. Sirtl, Dash, and Secco etches are
preferred for (111) crystal damage evaluation. Wright-Jenkins, Schimmel,
Yang, and Secco etches are used for (100) crystal defect evaluation. (See
Table 4.)
Silicon belongs to the diamond cubic crystal structure, (perhaps the
most desirable crystal structure to work with). Figure 1 is a model which
shows seven of the low indices planes of the diamond cubic structure we
may choose to use in silicon processing. In general, the (111), (100), and
(110) planes are the predominant planes used in silicon processing today.
However, other planes are also predominant in etching and deposition.
These planes the (331) and the (113), lie in <310> directions. The (221)
and the (112) planes, which lie in the <21 0> direction, are also governing
planes in silicon etching and deposition.
Figure 2 shows the three low indices planes commonly used in silicon
processing in a more vivid display. Figure 3 shows the method of deriving
the Miller indices forthe crystal planes. The(111) plane, for instance, is one
unit length out from the apex of lines A, B, and e in the A direction, in the B
direction, and in the e direction. The plane bounded by the lines connecting A,
B, and e is the (111), which is the predominant plane in silicon processing.
The atomic packing in this plane is the tightest, or most closely spaced,
packing density available; therefore this plane dominates the etching and
deposition conditions in silicon. It is the most stable plane in the silicon
crystal structure and is the most difficult on which to etch or epitaxially
deposit.

Q) (110)
(1)(221)

Q) (Ill)
@(334)

0) (112)
@(114)

(j) (100)

Figure 1: Low indices planes of the diamond cubic crystal structure.

 Chemical Etching and Slice Cleanup 129

x (100) (110) (Ill)

Figure 2: The (100) (110) and (111) planes.

Figure 4 is a photograph of a crystallographic model of the diamond

cubic structure. In the <111> direction we see atoms in a very closely
spaced equilateral triangular arrangement. This view shows the extremely
high packing density. If we rotate this same crystallographic model 54 to 0

the right or to the left, we are looking in a < 100> direction and see that the
atoms are arranged in a square array. The atomic packing density in this
direction is slightly less, making it a more open lattice. Therefore, one
would expect that etching in this direction would proceed more rapidly
than into the more highly packed (111) plane. If we rotate from the (100)
plane 45 or 90 degrees, using this same model then we will be looking in a
<110> direction. The atoms are in a very open lattice structure, which
exhibits the fastest etching and deposition conditions. This open lattice
structure can also be used to advantage for deep ion implantation. Channel-
ing of the ions takes place very readily in this open lattice < 110> structure.
This plane in silicon can also be used to advantage for radiation hardened
circuitry. A radiation particle must travel further in this direction before
colliding with a silicon atom, thus producing less radiation damage, than in
the <100> or <111 > direction. From this figure we can also see that the
high densityofthe(111) planeshould make itaverystrong plane. The(11 0)
plane is 90 degree to the (111) plane. The plate-like high packing density
structure of the (111) planes are held or bonded together by the structure
of the more open lattice (110) plane structure. Therefore, when we break or
cleave a silicon slice, it will cleave along < 110> directions between (111)
planes, separating or breaking (110) bonds.

ORIENTATION DEPENDENT CLEAVING OF SILICON

Figure 5 shows a (100) and a(111) silicon slice that have been cleaved
by pressing the center of each with a hard object, such as tweezers or a
ballpoint pen, when the slice is lying on a pad of paper which allows it to
give, therefore causing it to break. In the case of the (100) silicon slice note
the fourfold symmetry of the (111) cleavage planes. Their traces intersect
130 Semiconductor Materials

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 Chemical Etching and Slice Cleanup 133

the (100) surface in the pattern shown. These (111) planes intersect the
(100) surface plane at an angel of 54.74 degrees. If we look at the cleavage
plane or the edge of the cleaved border of the slice we see a crystallo-
graph ic plane that is inclined to the surface at this 54.74 deg ree angle. In
the case of the (111) slice there are three cleavage planes 120 degrees
apart. When they extend all the way across the slice, they break into pie-
shaped segments with 60 degree angles. The (111) cleavage planes
intersect the (111) surface of the slice at 70.53 degrees. If o~e again
cleaves the sections that have already been cleaved, they will continue to
cleave, in the case of(1 00) into squares or rectangles, and in the case of the
(111) into 60 degree triangular shapes. If we cleave a(11 0) silicon slice it
will cleave 90 degrees to the (110) surface. If we continue to cleave these
sections we will see that they form rhombic shapes as shown in Figure 6.
However, if we look atthe edge orthe cleaved surface wewill see that in all
cases they are 90 degrees to the(11 0) surface. These are the (111) planes.
In today's silicon semiconductor processing there is great interest in
MOS-type structures. For this type of structure the (1 00) slice orientation
is usually used due to the low surface state density at the (100) silicon
surface-silicon dioxide interface.
Figure 7 is a stereographic projection of the standard (001) or (100)
face centered cubic crystal structure. In this projection we are looking
directly at the (1 00) surface as we would in a (1 00) silicon slice. Note that
the four(111) planes which intersect the (100) surface are slightly greater
than half way out to the periphery of the projection (slice) in <110>
directions. In other words, there is a (11 0) plane perpendicular to the (100)
plane and tangent to the periphery at this point. The (111) planes are
actually coming into the (100) surface at angles of 54.74 degrees. The
(111) planes are also at 90 degree angles to each other. Those planes
designated by the Miller indices at the periphery of the projection are
known as directions. Starting at the bottom, orthe periphery closest to the
observer, is a (1 00) plane, indicating that this is a <1 00> direction. Those
Miller indices indicating planes between this (100) plane and the (100)
plane at the center of the projection are lying in this < 100> direction.
Moving to the right of the bottom center we have a <310> direction.
Moving up along the periphery we find a <210> direction, a <320>
direction, and then the < 110> direction, in which the (111) predominant
plane lies. Further examination of this (100) projection shows a four-fold
symmetry in this (1 00) plane. All four quadrants are exactly alike, and the
(111) planes are 90 degrees to each other, as are all other families in this
projection. Note also that in this (100) projection are a <310> direction to
the right of the <100> direction at the bottom of the projection and a
<310> direction to the left of the < 100> direction at the bottom of the
projection. These same two (31 0) planes are also to the right and to the left
of the <100> direction at the top of the projection. Likewise, they are
above and below the <100> direction at the right and at the left of this
projection. This shows there is double four-fold symmetry of <310>
direction planes in the (1 00) projection. In this double four-fold symmetry
of <310> directions the predominant planes are the (311) and the (331).
These planes etch and deposit rapidly in processing. The effect of these
134 Semiconductor Materials

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136 Semiconductor Materials

(331) planes will be noted in future etching experiments as rapidly under-

cutting planes. In some silicon processing, such as the dielectric isolation
process, which is used for radiation hardened devices and for extremely
high-speed and high-voltage switching circuitry, orientation dependent
etching (ODE) is preferred to form the isolation moats around each device
or circuit. To produce these isolation moats, the mask is aligned on the
(100) surface parallel and perpendicular to the (110) flat, a shown at the
lower right of Figure 8. If, the mask is aligned over an oxidized silicon slice
parallel and perpendicular to the (110) flat, and if the mask has openings
one micron wide etched down to the silicon, through the oxide the ODE
described in Table 2 will etch to a depth of 0.707 microns and then
completely stop etching. This is the depth at which the two (111) traces,
aligned with the edge of the mask opening, intersecting the (100) surface,
meet. Due to the very exact crystallographic 54.74 degree angle, we can
accurately predict the depth of the etch as a function of the width of the
mask opening. See Figure 9.
Figure 9 shows the proper alignment of the mask for ODE etching of
the (100) surface. It also shows a cross-sectional drawing depicting the
54.74 degree angle of the (111) plane intersecting the (100) surface.
Figure 10 is a photograph of an actual ODE etched surface. The top
view shows a portion of a 5 X 7 isolation array as used in the processing of
the electronic print-head. The cross-sectional view shows the exactness of
the crystallographic structure with the etch stopping on the (111) planes.
Early in the development of this process it was observed that undercutting
occurred at convex (outside) corners of the mask area as shown in Figure
11 a. Figure 11 b is an enlarged SEM view of this exact crystallographic
etching with etch faceting and stopping on the (331) planes, as previously
mentioned. By carefully measuring the angle of intersection of these
faceted planes with the (1 00) su rface and the angle these facets make with
the (110) flat, these planes were identified as (331 ).In Figure 12 and Figure
14, both (331) and (111 ) planes are shown. In order to compensate for the
undercutting at the corners and to obtain square or right-angle corners, a
mask corner compensation process was developed. By extending the
oxide out over the area that is being undercut, we can compensate for the
fast etching in the <310> direction.
Figure 13 shows the maskcornercompensation design for(1 00) ODE.
It should be noted that different orientation dependent etches terminate
their etching on different crystallographic planes. These planes may be in
<310> directions or in <210> directions, depending on whether the KOH-
propanol-water solution or the ethylenediamine pyrocatechol and water
solution is used. See Figure 14. Figure 15 shows a grossly over etched
ODE structure. The etch time was 70 minutes, or time enough to etch 70
microns deep using a mask designed with corner compensation for a 50
micron, or 50 minute etch.
Figure 16 shows the experimentally derived information for adding
corner compensation to the mask to obtain a 90 degree corner as a
function of etched depth. For example, if one wishes to ODE 30 microns
deep, one must extend the cornerout approximately 17 microns in orderto
obtain a 90 degree or right angle corner. It was previously stated that when
Chemical Etching and Slice Cleanup 137

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138 Semiconductor Materials

PAlTERN OPENED IN OXIDE

0.2 MIL WIDTH, ETCHED 0.14
MILS DEEP, TERMINATES ON
(III) PLANES

(lID) FLAT
[100]
54. 6
74
~ [lll]
SiOZ SILICON
(lID) FLAT

SECTION THROUGH WINDOW

AfTER ETCH IN G

Figure 9: Alignment of mask with (110) flat on (100) plane.

the traces of the two (111) sidewall planes meet at the bottom of the etch
moat the orientation dependent etch stops etching. To verify this statement,
some (100) silicon slices were etched using a mask designed to etch 50
microns deep using the (100) ODE. This mask also has corner compensation
designed to give square or right-angle corners at a depth of 50 microns.
Figure 17a shows a top-focused view of one of these slices, which was
etched for 38 minutes at 80°C. The etch depth is 38 microns. In the left-
hand picture the focus is at the top of the (100) slice. In the right-side of
Figure 17 a the focus is at the bottom of the etch moat. Note that the bottom
is flat at the etch front and is a (1 00) plane, since we have only etched 38
microns deep. Careful measurement of the etch width at the silicon
surface/oxide mask interface shows that the etch moat is 97.5 microns
wide with no measurable undercutting. Also, note that in Figure 17a, atthe
left top focus view there is a slight tip of silicon sticking out at the corners in
all fou r quadrants of the etch moat. Rememberthe corner com pensation is
designed for 50 microns etch depth and we have etched only 38 microns
deep. The slices were then placed back in the ODE solution and etched for
an additional 30 minutes, for a total etch time of 68 minutes. We have now
over-etched by 18 minutes for the corner compensation design. Careful
measurement of the top of the etch moat again show that the etch moat
width at the oxide is 97.5 microns, indicating that there is no undercutting
or etching after the trace of the (111) planes reaches the edge of the oxide
mask. The oxide corner compensation of the mask is clearly visible in both
the top focus and the bottom focus views of Figure 17b. The bottom focus
shows a completely v'd-out etch front with' no (100) remaining. To further
prove this statement, the slices were again placed in the ODE solution for
an additional 30 minutes, making a total of 48 minutes over-etching forthe
 Chemical Etching and Slice Cleanup 139

SEM TOP VIEW (100) 01 ETCH

SEM CROSSECTIONAL VIEW (100) 01 ETCH

Figure 10: Top view and cross-sectional view of ODE etched (100) silicon.
140 Semiconductor Materials

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 Chemical Etching and Slice Cleanup 141

Figure 12: Photograph showing identification of (100) ODE etched planes.

 CORNER COMPENSATION IN OXIDE MASK ~
N
ON ODE ETCHED CIRCUIT

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 Chemical Etching and Slice Cleanup 143

Figure 14: Corner faceting due to (100) ODE etching using different etches.
144 Semiconductor Materials

Figure 15: (100) ODE etched silicon slice.

 Chemical Etching and Slice Cleanup 145

60
55
I
50 I UNDERCUT

45
40
______17 0
CORNER DEPTH
UNDERCUT V5. (MICRONS)
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CORNER UNDERCUT (MICRONS)
5 10 15 20 25 30 35 40
Figure 16: Graph of corner undercutting vs ODE etch depth for (100) silicon.

mask design. Again, the slice was measured at the top of the moat, at the
oxide/silicon interface. The distance across the moat remained 97.5
microns, showing complete stopping of the ODE etching by the (111)
plane, aligned with the mask opening. The cornercompensation is clearly
shown projecting out over the ODE etched moats of this greatly over
etched slice both in the top focus and the bottom focus of Figure 18. The
undercutting to the (331) planes is also shown.
In Figure 15 the angle of intersection of the (331) planes with the (100)
surface plane was observed to be 46.51 degrees. This is considerably
lower than the 54.74 degree angle of intersection of the (111) planes. We
may wish to take advantage of this lower angle to more easily run metal-
ization over these moats and/or mesas and to enhance photolithography
definition. To do so, we merely align the mask parallel and perpendicularto
the <310> direction, as indicated in Figure 7. The <310> direction is
aligned by rotating the mask only 26.56 degrees to the right, orto the left, of
the <110> direction. [This is due to the double four-fold symmetry of the
<310> directions in the (1 00) plane]. Figure 19 shows two (100) silicon
slices that were ODE etched in the same etch solution, at the same time,
using the same uncompensated mask pattern. Slice (a) was aligned with
the <310> direction. Note the loweretch termination plane angle is(46.51
degrees) for the (331) plane in slice (a) compared to a 54.74 degree etch
termination plane angle for the (111) plane in slice (b) which was aligned
with the < 11 0> direction. Also note for slice (a) the 90 degree right angle
146 Semiconductor Materials

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148 Semiconductor Materials

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 Chemical Etching and Slice Cleanup 149

corners, even without mask corner compensation. This is due to the moat
sidewall etch termination being on the faster etching (331) planes which
cause the corner undercutting in the slice aligned with the < 110> direction.
The width of the isolation moat is considerably wider, giving lower packing
density in slice (a) due to undercutting of the mask all along the mesa edge.
Corner undercutting, and fast etching, is observed to be due to the (331)
planes at the corner of slice (b). Figure 20 shows an example of a metal-
ization line over a silicon mesa which was ODE etched with <310>
direction alignment. Note the low angle of the 46.51 degree (331) planes
forming the mesa sides.
The ethylenediamine pyrocatechol and water etch, mentioned in Table
2, may be used as an oxide pin hole characterization tool in (1 00) MOS
processing. If the oxide, especially thin gate oxides, has pin hole problems,
these pin holes may be delineated by etching in the ethylenediamine etch
solution. The delineation will result, and can be counted, due to the etch
termination in the (100) silicon in the form of a perfect inverted pyramid, as
in Figure 21. The etch pit will have perfect four-fold symmetry of (111)
planes even though the pin hole may be irregularly shaped. The pin hole
density of the oxide may be counted through the use of normal bright field,
or Nomarski microscopy. Very small orifices, one micron or less, may be
etched through a silicon slice using ODE and a mask designed to provide
the desired orifice size. The etch depth to mask open ing width is 0.707 x W,
where W is the width of the maskopening. Forexample, a maskopening 10
microns wide aligned with the < 11 0> direction on a (100) silicon slice will
etch 7.07 microns deep and then stop etching. The reverse effect of
generating very sharp points may be obtained by aligning a pattern of small
squares slightly off the < 110> direction to purposely cause undercutting.
This effect is shown in Figure 22. In the photograph at the left side of Figure
22 the etch mask, has been completely undercut and the mask medium
has been washed away. In the photograph at the rig ht side of Figu re 22 the
etching was stopped before the mask was completely undercut, and the
mask can be seen on top of the pyramid.

ORIENTATION DEPENDENT ETCHING AND

ORIENTATION DEPENDENT DEPOSITION

In general, orientation dependent etching (ODE) reactions and orien-

tation dependent deposition (ODD) reactions are complementary in silicon~
Those planes that are slow etch planes, for example (111) planes, are slow
depositing or growth planes. Those planes that are fast etching, for example
(331) planes, are fast growth planes. The experiments depicted in Figures
23 and 24 show this effect.
Figure 23a shows an etch mask for the fabrication of an array of seven
circuits or devices which are dielectrically isolated (01) from each other. In
the 0 I process the normal p-n ju nction isolation that com pletely su rrou nds
each com ponent is replaced by a dielectric material such as si Iicon dioxide
or silicon nitride. This eliminates the very large parasitic capacitance
around each component, giving rise to greatly improved switching speeds.
 METALLIZATION OVER ODE MESA. [310] ALIGNMENT 01
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Figure 20: Photograph of metalleed contact to <310> aligned ODE etched silicon mesa.
 Chemical Etching and Slice Cleanup 151

100 DDE IE.

Figure 21: Inverted pyramid, etch pit, in (100) silicon.
 C11
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(100) ODE, 2040 X 65 SEM (100) ODE, 1240 X 65° SEM
10 p.m SQUARES ON 20 p.m CENTERS NOT ETCHED TO COMPLETION

Figure 22: Photograph of array of pyramids ODE etched in (100) silicon.

 Chemical Etching and Slice Cleanup 153

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Figure 24: ODD deposition, sil icon dielectric, isolated array.

 Chemical Etching and Slice Cleanup 155

It also provides much higher isolation voltage capability between compo-

nents. The 01 gives several advantages to the device and ci rcu it character-
istics, but has one major disadvantage, cost. However, it is used for certain
applications. In the 01 process ODE etching of(1 00) silicon is used to etch
out the V-groove isolation moat. In this figure, the rows of seven large
rectangles are the areas in which the 01 circuitry or components will be
fabricated. The row of successively narrower black rectangles are built-in
thickness indicators for process control in the 01 process. The two squares
above and at the left of each array of seven 01 islands are alignment
markers. These two squares are the same size. However the one at the left
has mask corner compensation. Figure 23b shows the silicon slice surface
after ODE etching 53 microns deep. Note the nearly octagonal shape of
the mesa on the right, which did not have maskcornercompensation.lt is
completely bou nded by the fast etching (331) planes. The mesa at the left,
which has mask corner compensation, is bounded by the (111) planes
except at the corners, where again the fast etching (331) planes are
revealed due to over-etching. Note the large difference remaining in the
surface area in the two mesas which originally were the same size. The
next step in the 01 process is to strip off the mask material and thermally
grow silicon dioxide across the mesa structured surface. A thick poly-
crystalline silicon film ('00.5 mm) is then deposited over the oxide. The
structure is then inverted and subjected to a grind and polish operation to
remove the back portion of the original (100) substrate down to the tip of
the V-groove isolation moats and the thickness indicators. The number of
indicators showing (polished through) tells us the exact thickness of the
single crystal silicon remaining in the dielectrically isolated tanks. Figure
24a is a photograph of this polished back surface. The black lines are the
edges of the thermal oxide (01) isolation. Two of the seven large isolated
device tanks are visible at the top of the photo. At center left the two
alignment markers are visible as a square and an octagon. At center right
two ofthethickness indicators are visible. Again, note the size and shape of
the two single crystal alignment markers, in particular the one defined by
the fast etching (331) planes, which appears as a nearly perfect octagon.
Figure 24b shows these same two alignment markers after epitaxial
deposition. The fast-etch (331 ) planes have also grown fast epitaxially, and
the 00 E etched octagon shape has reverted, or epitaxiallygrown back to a
perfect square, bounded by (111) planes. This is proof that the fast etching
planes are also fast deposition planes. Also, a perfect (100) epitaxial
stacking fault appears at the lower left portion of the corner-compensated
alignment marker.
Epitaxial stacking faults are generally undesirable, and can be com-
pletely avoided by proper substrate preparation and in situ HC1 vapor
etching; however, in some instances they can be useful as process control
indicators. They are readily observed, if present, by use of a Wright-Jenkins
etch (see Table 4) and/or Nomarski interference contrast microscopy.
Figure 25 shows a photograph of (111) and (1 00) epitaxial stacking faults
(ESF). These ESF's can be used to readily verify the crystal orientation of
the silicon substrate. Stacking faults in epitaxial films on (111) substrates
will produce line faults, or equilateral triangle-shaped stacking faults with
156 Semiconductor Materials

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 Chemical Etching and Slice Cleanup 157

the lines or sides of the fault aligned with the trace of the (111) planes
which intersect the (111) surface, and in < 11 0> directions. The (100)
epitaxial stacking faults will be line faults or squares, with the lines or sides
of the square aligned with the trace of the (111) planes, in < 110> directions
intersecting the (100) surface. If the (111) triangles are not perfectly
equilateral or if the (100) squares are not perfectly square, the substrate is
off orientation. The ESF's usually nucleate at the substrate/epitaxial layer
interface. Due to the growth control of the faults by (111) planes, and by
knowing the angle of intersect of the (111) plates with the substrate plane,
one can very accurately determ ine the thickness of the epitaxial layer. This
is accomplished by merely measuring the length of the side of the ESF and
multiplying it by 0.707 for (1 00) silicon, 0.816 for (111) silicon, and 0.5 for
(110) silicon. Figure 25 shows examples of (111) and (100) epitaxial
stacking faults. Further discussion of stacking faults in silicon, both epi-
taxial and bulk SF's, will be found in the section on defect delineation.

(110) ORIENTATION DEPENDENT EFFECTS

We now turn our attention to the orientation dependent effects of

(110) silicon. From Table 2 we see that the (110) orientation dependent
etch is made up of KOH and water, 50/50 by weight, and is carried out at
80°C. The etch rate in the <110> direction is approximately 700 times
faster than it is in the < 111> direction.
The (11 0) stereographic projection in Figure 26 shows that the pre-
dominant (111) orientation planes intersect the (110) surface plane of
silicon at 90 degrees or at the periphery of the projection. The (111) 90
degree planes are not 90 degrees to each other as in the case of the (100)
projection. The symmetry in the (11 0) projection is not fourfold, but mirror
image symmetry. The (111) planes which intersect the (110) surface are
109 and 71 degrees to each other, thus forming a rhombus rather than a
square or a rectangle. Two low angle (111) planes are observed which
intersect the (110) surface plane at approximately 35 degrees. These two
planes may be used forthe maskalignment of thickness indicators, as was
described for (1 00) silicon. Their effect may also be noted where we have
mask alignment with the 90 degree (111) planes. These low angle (111)
planes constantly tend to stop the etching, but because the mask is not
aligned with the trace of these low angle (111) planes, they are not
effective.
Figure 27 shows the method for aligning a mask with the trace of the
vertical (111) planes at the (110) surface, thus giving the shape of a
rhombic pattern. If we open lines parallel with these traces of the (111)
planes through a mask, such as silicon nitride or oxide, and then etch using
the (110) etch as mentioned in Table 2, we will etch moats with vertical
walls which may extend all the way through the slice with practically no
measurable undercutting.
Figure 28 shows SEM photographs of (110) ODE etched slices which
have been etched 80 microns deep. The oxide mask pattern was 10
microns of open silicon with 10 micron spacings between openings. The
158 Semiconductor Materials

STANDARD (110) PROJECTION FOR A FACE-CENTERED CUBIC CRYSTAL

001

117
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Figure 26: (110) stereographic projection for a face centered diamond cubic
crystal.

top photograph is a 1,000X SEM photomicrograph magnification of a

cross section of the cleaved slice which had been ODE etched. The V-
shapes at the bottom of the etched moats are artifacts of the low angle
(111) planes which are trying to stop the etch. At this magnification no
undercutting can be detected at the mask surface. The photograph at
bottom left is a 5,000X SEM photomicrograph showing a portion of this
same cleaved ODE etched slice. In this case the oxide mask is readily
visible at the top of the ridges, but again no undercutting can be measured.
At bottom right is a 1O,OOOX SEM photomicrograph, from which an under-
cutting ratio of less than 1-700 is measured. An extremely large gain in
 Chemical Etching and Slice Cleanup 159

STANDARD (110) PROJECTION FOR SILICON

(FACE-CENTERED CUBIC) CRYSTAL SHOWING RHOMBIC
PATTERN ALIGNMENT WITH THE gOO {111} TRACES

Figure 27: Rhombic shape of (111) planes for 00 E alignment.

surface area can be obtained by this type of ODE etching. If a line one
micron wide is opened and etched 100 microns deep, we have increased
the available silicon surface for device fabricatin by 200X. This vertical
surface can be used advantageously for fabrication of passive semicon-
ductor components such as capacitors, resistors, and isolation. It has also
been used in the fabrication of large area, high efficiency solar cells.
Methods of fabricating active components in these vertical surfaces are
being explored making use of beam technologies.
Figure 29 is a 5,000X SEM photomicrograph, taken at an angle which
shows the top surface as well as the cleaved edge of a (11 0) ODE etched
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Chemical Etching and Slice Cleanup 161

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162 Semiconductor Materials

structure using submicron lithography. Each ridge and space in this case
should be 0.6 micron with 1.2 micron centers. However, if the ridges are
thinner than the spaces between the ridges, this indicates a misalignment
of the mask with a trace of the (111) at the (110) surface. Again, we see the
V-notches at the bottom of the etch moats due to the low angle (111)
planes. The sidewalls of structures such as this may be readily doped to
form junctions by standard diffusion techniques. These sidewalls are also
readily oxidized by standard thermal oxidations. Therefore, by alternate
etching and diffusion we can fabricate active p-n junction structures in
these walls.
Figure 30 is a 57 OX SEM photomicrograph showing the top and the
edge view of a cleaved ODE structure similarto the one shown in Figure 29.
However, in this case the tops of ridges have been pointed by lightly
etching in a 1-3-8 etch. These points are so exact that the surface area
becomes a blackbody. Such a structure may be used as a high efficiency
solar cell, which has the advantages of a large silicon surface area plus a
blackbody surface area that traps all the available solar energy into the
cell.
Figure 31 is a 11 ,500X SEM photomicrograph showing one of these
ridges. Even at this magnification no radius of curvature can be detected. It
should be noted that the sidewalls of these etched arrays are the (111)
planes wh ich may be tilted to any desired angle merely bycutting the slices
off orientation from the (110) in the proper direction.
Figure 32 shows an array which has been etched into a silicon slice
that was purposely cut 10 degrees off the (110) orientation. This effect,
combined with the blackbody etching, may be used to produce optical
collimation for an LED-type display with zero back-reflection to the observer.
If a mask consisting of open lines in the oxide is aligned with the trace of the
(111), and the slice is then turned over and the same type mask aligned
with the other set of (111) traces, we can simultaneously etch these two
patterns to obtain an X-Yarray such as that shown in Figure 33. This figure
shows an SEM photomicrograph, taken at 60 degrees, of a slice which was
simultaneously etched from the top and bottom which has a section
cleaved or broken out of it. In this case we have five micron openings on 20
micron centers. Where the etch from the front and the etch from the back
meet, a sieve with 5 micron openings is formed. We can also electrically
address these ridges in X and Y directions. These ridges are like silicon
crystal whiskers, extremely strong and very flexible. Figures 34 and 35 are
top view SEM photomicrographs of wafers etched simultaneously from
the back and front.
Figure 36 is a close view using the SEM at 1,600X and showing the
simultaneously etched top and bottom ridges. The exactness of the (111)
plane is clearly evident. Also, the low angle 35 degree (111) effect is again
evident in both top and bottom ridges. Figure 37 shows a low power, 45
degree angle SEM photomicrograph taken at the edge of a broken slice
which had previously been ODE etched.
The previous photographs showed the effect of orientation dependent
etching straight down 90 degrees to the surface. Figure 38 shows the
opposite effect, orientation dependent deposition by use of CVD with
Chemical Etching and Slice Cleanup 163

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 164 Semiconductor Materials

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 Chemical Etching and Slice Cleanup 165

Figure 32: SEM photograph of cross-section, (110) tilted 10 (at saw) ODE etched.
166 Semiconductor Materials

Figure 33: SEM photograph of sectioned (110) ODE silicon, simultaneously

etched from top and bottom.
 Chemical Etching and Slice Cleanup 167

Figure 34: Top view of (110) ODE, top side and bottom side, simultaneous
etched X-V grid.
168 Semiconductor Materials

Figure 35: Magnified view of ODE etched (110) silicon as in Figure 34.
 Chemical Etching and Slice Cleanup 169

Figure 36: Magnified close up of (111) planes in X and Y directions and V etched
effect of low angle (111) planes.
170 Semiconductor Materials

Figure 37: Cleaved or broken section of (110) ODE silicon.

Chemical Etching and Slice Cleanup 171

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172 Semiconductor Materials

growth straight up in single crystal columns. In this experiment a (110)

silicon slice was thermally oxidized, a mask was aligned with the trace of
the (111) plane, and the oxide was opened in some areas and allowed to
remain in other areas. The photograph at the left shows a cross section of
the simultaneously deposited single crystal and polycrystalline silicon.
The photograph at the right shows this same area after the polished cross
section has been Sirtl-etched to reveal the polycrystalline and single
crystal structu reo It can be seen that in the areas where there was no oxide
on the original substrate, the single crystal material grows perpendicular
to the (110) surface. In areas where an oxide remained, we see polycrystal-
line silicon, highly ordered, in a (110) direction. These figures show both
the effect of orientation dependent deposition with vertical growth in a
(110) direction and the effect of Sirtl etching to bring out grain boundaries
in polycrystalline material. Table 3 shows some of the uses of anisotropic
etching in (100) and (110) silicon processing.

Table 3: Applications for (100) and (110) ODE in Silicon Device or Structures

(100) (110)
Radiation hardened circuits High voltage diode arrays
Electronic printer Vertical multiple jct solar cell
Crosspoints Wave guides
Iso planar Sensistor
Poly planar I R detectors
V MOS Metallization templates
J FET arrays High value capacitors
D I process th ickness ind icator Optical coli imators
Sol id state pressure transducer Black bodies
Solar cell anti-reflecting surface

DEFECT DELINEATION ETCHING

In today's silicon VLSI/U LSI technology, defect density and, of course,

defect delineation are of great importance. Wet chemical etching is used
to identify and study these defects. In genera'l, the etches used are those
that etch more rapidly on strain field defect areas than on normal single
crystal areas. In some cases decorating agents are also added to more
clearly reveal the defect. Table 4 lists the defect delineation etches
commonly used in industry today, for both (111) and (1 00) silicon.
Figure 39 shows a photograph of a large diameter, double twinned
slice. The twin planes are revealed by a light (30 second) Secco etch. Quite
often in today's processing of silicon we observe defect areas which
appear to be concentric circles in the silicon slice surface. These circles
may be further delineated by Secco etching. (See Figure 40.) They are
normally caused by dopant segregation or oxygen segregation during
crystal growth. Processing for VLSI circuitry places great emphasis on
 Chemical Etching and Slice Cleanup 173

Table 4: Preferential Etches for Defect Delineation in Silicon

ETCH SOlUTION COMPOS ITI ON CHARACTER ISTI CS REF

Dash 1 HF : 3 HNO) : 10 HAC· Delineates defects In 011) silicon, RequIres 1
long etch times, concentratIon-dependant.
Sirtl 1 HF : 1 GM-CrO») Delineates defects In nIl). Needs 2
agitation. Does not reveal etch pits In
UOO) very well.
Seeco 2 HF : 1 (0.15M K2 Delineates O. S. F. in UOO) silicon very 3
cr207) well. Agitation reduces etch times.
Wright-JenkIn s 60 ml HF: 30 ml HN0:3: Delineates defects in BOO) & (Ill) silicon. 4
30 ml (5M Cr03): 2 grams Requires agitation.
Cu (N~)-z : 60 ml HAC
• : 60 ml H20
SChimmel 2 HF : 1 UM CrO)) Delineates defects In Uoo) silicon without 5
agitation. Works well on resi stivlties
0.6 - 15.0 ohm em n & p types.
Modified Schimmel 2 HF : 1 (M CrOJ h Works well on heavily doped (100) silicon. 5
1.5 H2 0
Yang 1 HF : 1 U.5M CrOJ) Delineates defects on 01U, noo), and 6
(l10) silicon without agitation.
• acetic acid Note: agitatIon - ultrasonic

silicon substrate purity and crystallographic perfection at the device/sub-

strate interface. To improve this surface for subsequent device processing,
oxygen out-diffusion techniques are commonly used to denude the surface
areas and form oxygen precipitates to getter impurities and defects.
Figure 41 shows a cleaved (see Figures 5 and 6 as well as discussion)
cross-sectional view of a silicon slice which has been subjected to an
oxygen precipitation cycle. (See section on epitaxy in chapter on chemical
vapor deposition of silicon and its compounds.) This slice has an epitaxial
layer at the top and a backside polysilicon gettering layer on the back
surface. Denuded zones can be observed in the original substrate just
below the epitaxial film and just above the backside gettering polysilicon
film. The central portion of the original substrate shows the large numberof
crystal defects remaining after crystal growth and thermal cycling. Most of
these defects are in the form of bulk stacking faults and oxygen precipitates.
These types of defects are readily revealed byWright-Jenkins orYang etch
in a cross-sectioned orcleaved sample such as the example in Figure 41. It
should be noted that Figure 41 is from a cleaved cross section requiring no
polishing or other preparation prior to the defect delineation etching.
Figure 42 is a photograph of a grooved (100) silicon substrate showing
the fairly high density of bulkstacking faults and dislocations at the bottom
of the groove. The vertical lines are a result of the Philtec groover which
was used to prepare the sample. In this case again the Wright-Jenkins etch
was used to bring out the damage. Note that the large bulk stacking faults,
or elliptical-shaped stacking faults, lie in the < 110> direction, parallel and
perpendicular to the (110) flat and to the edges of the photograph.
174 Semiconductor Materials

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 DISLOCATIONS lOOPS AND DAMAGE AT BOTTOM OF GROOVE
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178 Semiconductor Materials

Figure 43 is also a grooved section of a (100) silicon substrate. Again,

note the large bulk stacking faults lying in <110> directions. There are
also carbon related cone shaped defects lying at 45 degree angles to
these bulk stacking faults. The Wright-Jenkins etch was used to bring out
these defects. Auger analysis shows that the cone-shaped defect is
related to excessive carbon in the silicon.
Figure 44 shows a photograph of the top of an epitaxial film which has
an epitaxial stacking fault. From this stacking fault it is evident that the
epitaxial material is (100) orientation. In this photograph, which was taken
after Wright-Jenkins etching to bring out the dislocations or the damaged
sites surrounding the stacking fault, a clear area is noted around the
stacking fault. This indicates that the stacking fault acted as a getterto the
defects wh ich su rrou nded it. Large dislocations can be seen at the corners
of the stacking fault.
Figure 45 is an enlarged view showing the large conglomeration of
gettering effects at the dislocations on the corners of this same stacking
fault visible after Wright-Jenkins etch. This type of gettering of small
defects to a stacking fault, or to dislocations at the corners of a stacking
fault, is common and is usually associated with gettering of heavy metals in
silicon processing. However, in this case, Auger analysis revealed heavy
carbon on the stacking fault dislocations, no detectable carbon in the
denuded or gettered zone around the stacking fault, and heavy carbon in
the clusters of small defects. This indicates the presence of carbon which
can be gettered to dislocations or damage sites.
Figure 46 is a cleaved cross-sectional view of an epitaxial film deposited
on a previously denuded substrate. The presence of a row of precipitation
defects at the substrate/epitaxial interface shows the necessity for using
in situ HCI vapor etching even in previously denuded substrates. A cross-
sectional view of the denuded substrate shows a very clean area just
below the surface. However, the surface itself acts as a trap for heavy
metals and damage sites, as do the oxygen precipitations in the bulk
material. It is important to note, however, that all these defects at the
epitaxy/substrate interface do not introduce damage or stacking faults
into the epitaxial film. Therefore a technique of designing-in a layer of
defects at the substrate epitaxial interface can be used for extrinsic
gettering at a zone just below the device area. (See Figures 47 and 48).
As mentioned above in situ HCI vapor etching will remove the damage
sites and/or surface traps prior to epitaxy, However, one may wish to leave
or even enhance this damage layer for in situ gettering in near proximityto
the active device region of the structure. In this case we can deposit a built-
in extrinsic misfit, dislocation strain field by intentionally doping, with
germanium, an interface film between the substrate and the epitaxial film.
Figure 47 shows a cleaved cross sectional view of a single layer misfit
dislocation, extrinsic gettering strain field, and a single layer epitaxial film.
Figure 48 shows multiple layers of strain field/epitaxial silicon films with
increasing amounts of Ge doping in the strain fields as they were deposited.
This increase in Ge doping causes a noticeable increase in the density of
misfit dislocations within the strain field layers. Wright-Jenkins etch was
used to reveal these damage sites.
 DISLOCATIONS, lOOPS AND DAMAGE AT BOTTOM OF GROOVE

()
::r
CD
3
o'
~
m
.-+
()
::r
::J
(Q
n>
::J
0..
en
0'
CD
()
CD
n>
::J
c
"0

Figure 43: Photograph of heat treated, grooved and W-J etched section showing dislocations, bulk, stacking faults and II carbon II
"""-J
defect cones, (Magnification less than indicated.) <0
 ex>
o

en
CD
3
o·
o
::J
a.
c
()
~

o
~

s:
n>
~

CD
~

Di·
00

Figure 44: Photograph of (100) epitaxial stacking fault, carbon pits, dislocations and carbon gettering effect, W-J etched.
(Magnification less than indicated.)
 ()
::J'"
CD
3 0

0
~
m
r-+
()
::J'"
::J
co
~
::J
0-
en 0

0
CD
()
CD
~
::J
C
"0

(X)
~
Figure 45: Enlarged view of (100) ESF and getteringo (Magnification less than indicated 0)
 ....A.

00
tv

en
CD
3
o·
o
:::J
a.
c
('")
P+
o
~

~
Q)
P+
CD
~

iii·
en

Figure 46: Cleaved cross-section, W-J etched, denuded substrate with epitaxial film. (Magnification less than indicated.)
 Chemical Etching and Slice Cleanup 183

Figure 47: Misfit dislocation extrinsic gettering.

Figure 49 shows a large stacking fault in a 75 p,m thick epitaxial film.

Epitaxial stacking faults of this size have a cusp around the edge of the
stacking fault that extends slightly above the surrounding surface. With a
microscope such as the Reichert Ultrastar with Nomarski interference
contrast, in the blue phase, the upper left quadrant of the stacking fault will
appear to be red, thus showing that the stacki ng fau It cusp is slightly above
the surface area. This is a method that can be used to determine if
perturbations are above or below the surface. That is, if the blue phase is
used in the Nomarski interference contrast, the upper left-hand quadrant
will appear to be red if the perturbation is above the surface, and the lower
right-hand quadrant will appear to be red if the perturbation is below the
surface.

SLICE CLEANUP

During the past decade the advent of higher packing densities, in large
scale integration (LSI), very large scale integration (VLSI) and now ultra
large scale (ULSI), has created a demand for ultra clean processes and
manufacturing processing areas. One of the first and perhaps most critical
factors is the crystallographic, physical, and chemical cleanliness of the
184 Semiconductor Materials

co
.
~
CI)

:s
CJ')

u:
 PHAS:E

()
::T
CD
3
o·
~
m
r-+
()
::T
::3
co
Q)
::3
a.
~
o·
CD
()
CD
Q)
::3
C
"0

Figure 49: (100) epitaxial stacking fault, photograph taken under Nomarskiinterference phase contrast, no etching. (Magni- ex>
(J'I
fication less than indicated.)
186 Semiconductor Materials

starting substrate or slice, and the subsequent maintenance of this clean

condition throughout the process steps, Table 5.

Table 5: Silicon Slice Cleanup Effects on Processes and Device Performance

• Cleanliness is next to godliness.

• Affects a II device processes
• Oxidation rate
• Oxidation induced stacking faults
• Yields
• Effects device parameters
• MOS - refresh time (lifetime)
• Bipolar low current HFE (Beta)
• Surface state density
• Breakdown voltage
• GOI (Gate Oxide Integrity)
• Defect densities

Complete cleaning of semiconductor surfaces requires that partic-

ulates, organic films, and adsorbed metal ions be removed. Most cleaning
procedures are based on immersion in liquid baths or liquid sprays. In
addition, ultrasonic agitation or brush scrubbing may be required. In some
cases high temperature vapor etching, or low pressure sputter etching
may be used. A good cleanup is complicated by the fact that unless great
care is taken, the materials used for cleaning may contain, and leave
behind, more particulates and metals. Organic solvents are widely used,
but they sometime leave residues themselves. As a result high puritywater
is ordinarily the last stage of a cleanup, preceded by an oxidizing acid etch
to remove any remaining organics. Industry accepted standards (Table 4)
for slice cleanups were reported in RCA Review, June, 1970 byW. Kern and
D. Puotinen. 14
Surface contaminants may be generally classified as inorganic or
organic. Inorganic or atomic impurities such as heavy metals, e.g., gold,
copper, iron and magnesium are lifetime killers in silicon processing.
Sources include process equipment and chemicals, e.g., polishing equip-
ment and media, and acid etchants. In many cases the etchants contain
the contaminants, or remove the contaminant, such as gold, from the
surface and then redeposit it back onto the surface. These contaminants
can best be removed by clean ing sol utions contai ning acids and com plexi ng
agents which dissolve the heavy metal and complex the ionic form to
prevent plating or redeposition from the cleaning solution. The alkali ions
of sodium and potassium are especially harmful in that they may form
mobile charges at the silicon/oxide interface. These charges can move
due to electric fields or temperature changes, thus producing inversion
layers, leakage, and device instabilities. Organic contaminants, normally
photoresist residues, oils (fingerprints) and waxes (from the polishing
 Chemical Etching and Slice Cleanup 187

processing) are usually chemabsorbed on the surface, and are best

removed by cleaning in a hot sulfu ric acid (H 2 S0 4 ) cleaning solution or the
ammonium hydroxide NH 4 0H + H 2 0 2 + H 2 0 cleaning solution of Table 6.

Table 6= Cleaning Solutions

CLEANUP SOLUTION MIXTURE TEMPERATURE

sooe ± SoC
* Choline Clean Choline H20 2 ***NCW·601A H2O
(CH~3N(CH2Ch20H)OH (Surfactant) Ultrasonic 10 min, 10 min
01, H20, spin dry
Percent 3 1 1 95

•• RCA Clean "Basic" NH 40H H2 0 2 H2O 80°C ± SoC

Parts by Volume 1 1 S 10 min 01 water rinse

1 2 7

RCA Clean "Acid" HCI H2 0 2 H2 O 80°C ± SoC

Parts by Volume 1 1 6 10 min 01 water rinse
1 2 8

H2SO 4 H2 0 2
Percent 60 40
70 30

-11 - Ken Bean

·-Reference from RCA Review, 31, fl2, June 1970
···Available from: Wako USA Chern Co.

PRECLEANUP SOLVENT RINSE

Oils and organic residues remaining on the wafer from the slice
polishing process may be removed by rinsing in an organic solvent such as
perchloroethylene or xylene. Freon fluorocarbon solvents are also used
for vapor degreasing or cleaning.
It was shown by Schwettman 15 in 1978 and confirmed later by others, 16,17
(Table 7) that the chemical cleanup process affects the oxidation rate,
oxide charges, surface state density, Qss' the offset voltage, V FB' and
therefore the device or circuit characteristics (Table 8). In bipolar circuitry
the preoxidation cleanup affects the oxide charge density, noise, junction
leakage, low current gain (beta), junction breakdown voltage, minority
carrier lifetime and isolation leakage between devices. In MOS circuitry,
the preoxidation cleanup affects the oxide charge density, lifetime, refresh
time, junction leakage, threshold voltage and breakdown voltage. (See
Table 9).
In 1981 the Japanese authors 18 reported the superior qualities of
choline based cleanups. This cleanup, (Tables 6,7, and 8), is based on the
reactions of trialkyl (hydroxyalkyl) ammonium hydroxide (THAH) or choline,
which is a strong base, and H 2 0 2 . The THAH solution can be made free of
sodium, potassium, and heavy metals. It iswatersoluble, and can be readily
removed by a deionized water (01) rinse. The choline cleanup removes
188 Semiconductor Materials

Table 7: Oxidation Rate vs Pre-Oxidation Cleanup

1400

1200

~ 100'0
tJ')
tJ')
w
Z 800
~
u
:c
.-w 600
o
X 1000°C
o
DRY 02
400
(100) Si
n-TYPE, 2-8U em
• } SCHWETTMANN. etul
200 : E.C.S. EXT. ASS. VOL. 78-1
• TI-KEN BEAN
e E.C.S EXT. ASS. VOL. 81-2
OL-_ _.l...-_ _..l..-_ _1---ll-----Jl-----'--~--~--~---'
o 20 40 60 80 100 120 140 160 180 200

OXIDATION TIME (MIN)

Table 8: MOS Gate Oxide Characterization vs Pre-Oxidation Cleanup

Wax wax BV 0 EBR WOK (NS) =oxide thickness

CLEANUP (NS) (Elec) VFB liV+ liV· Med Calc (NS) by nanometrie measure.

,1 ..1nQ 437 - Rl\

- q)
~1 Q

~1 ':t
'1
74
7R
76
WOK (Elee) = oxide thick·
411 ' 429 ... Ot; -Jj24
ness by CV measurements
~ 412 432 -.88 32.5 4 7.9

VFB = flat band voltage

CHnllNF 4 410 433 . -.95 39.4 28 9.6
BV (Med) = breakdown
Ii 400 429 -.89 + .028 -036 39.0 44 9.8
~2
voltage (median)
r. 404 427 -.84 38.7 9.6

=
o (Calc) defect density
calculated
7 26q 296 -86 256 24 9.5
R 272 298 -.88 + .02 ·030 25.7 34 9.4
EaR (NS) z: oxide electric
Q 277 300 -.87 26.3 20 97
field breakdown voltage
by nanometric measure.

CHnllNF 10 276 301 -.85 29.0 20 10.5

11 26Ei ~01 -85 +025 - 0'4 287 16 10.8
]67 287 -907 28.6 30 109
"
B 107 -.805 B8 17 12 q
14 107 -.813 + .03 +03 13.9 25 13.0
,.. 109 -77 139 16 128

CHOLINE 16 109 -79 139 13 12.8

17 108 -794 + .03 ....02 B8 5 128
18 107 -.75 13.6 9 12.7
OPERATING UNIT: PREPARED BY: GeorgE Brown/Ken Bean DATE: 01·17·86
 Chemical Etching and Slice Cleanup 189

Table 9: Oxide Charges Can Affect the Following Device Parameters

G
E B

+ +

Si

Bipolar MOS

Junction leakage Device threshold voltage

Junction breakdown Channel conductance
Noise Junction leakage
Low current beta Junction breakdown
Leakage between Leakage between devices
devices

organic material since it is a strong base. It etches silicon (3A/min) and

removes native oxides but does not etch thermal oxides. In an experiment
comparing eight diffeent standard cleanups, including all RCA processes,
using radioactive tracers and activation analysis, we found choline to be
the most effective in removing, the lifetime killer, gold (Au) from the silicon
surface. Table 8 compares the MOS gate oxide electrical properties of the
SiOdSi structure, as a function of preoxidation cleanup, for approximately
400A, samples 1-6, 275A, samples 7-12 and 1OOA, samples 13-18, gate
oxides. The oxide breakdown voltage or dielectric strength of the 400A
oxides are over 20°10 higherfor the choline cleaned samples and over 10°10
higher for the 275A gate oxides. No difference is observed in the 100A
oxide due to Fowler Nordheim conduction through the thin oxide.

CHOLINE CLEANUP PROCESS

The choline cleanup appears to be a good silicon slice cleanup. This

cleanup removes, without swabbing, particulate matter, heavy metals,
and even fingerprints that have dried overnight on the slices. Choline
(CH3)3N(CH2CH20H)OH is a strong base which chemically acts some-
what like KOH or NaOH but does not contain sodium or postassium ions.
The "choline clean" consists of 3°1o choline, 1°10 surfactant (NCW-
601 A), 1°10 H20 2 (by volume) in 01 water, 40 to 45° C with ultrasonic for 10
minutes, 10 minute 01 H20 rinse, alcohol spin dry (or hot N2 spin dry) no
swab.
The choline has a rather pungent (fishy) odor and must be used in a
good hood. Choline cleaning solutions have been stored overnight and
190 Semiconductor Materials

reused the following day without degradation, however, this is not recom-
mended at this time.
For a production process a two-step cleanup using e.g., the RCA HCI
(acid) cleanup followed by a choline cleanup is recommended. A multiple
bath setup wherein the slices would go through at least two or three
cleanup solutions, with the solution tanks being rotated from last to first as
the solution is contaminated and/or used up is suggested for each process.

REFERENCES
1. B. Schwartz and H. Robbins, J. Electrochem. Soc. 123: 1903 (1976).
2. W.C. Dash, J. Appl. Phys. 27: 1193 (1956).
3. J.B. Price, ECS Silicon Symposium (1973).
4. E. Bassous, IEEE Trans. Elec. Dev. ED-25: 1178 (1978).
5. K.E. Bean, IEEE Trans. Elec. Dev. ED-25: 1185 (1978).
6. K.E. Petersen, Proc. IEEE 70: 420 (1982).
7. D.L. Kendall, Appl. Phys. Lett 26: 1500 (1974).
8. R.M. Finne and D.L. Klein, J. Electrochem. Soc. 114: 997 (1967).
9. E. Sirtl & A. Adler, Z. Metallk 52: 529 (1961).
10. F. Secco d'Aragona, Phys. Status Soiidi (a), 7:577 (1971).
11. M. Wright, J. Electrochem. Soc. 124: 757 (1977).
12. D.G. Schimmel, J. Electrochem. Soc. 126: 479 (1979).
13. K.H. Yang, J. Electrochem. Soc. 131: 1140 (1984).
14. W. Kern and D. Puotinen RCA Review June (1970).
15. Schwettman et aI., ECS Ext. Abs. 78-1, (1978).
16. Bruce Deal, Fairchild, Personal Communication.
17. K.E. Bean, G.A. Brown, (see Tables 8 and 9).
18. H. Muraoka et aI., ECS Ext. Abs. 81-2: 570 (1981).
5
Plasma Processing:
Mechanisms and Applications

w.c. Dautremont-Smith
Richard A. Gottscho
R.J. Schutz
AT & T Bell Laboratories
Murray Hill, New Jersey

1 . INTRODUCTION

In this chapterwe discuss the use of plasmas in the microelectronics

industry. There are basically two reasons why plasmas are used: (1) to
achieve anisotropic heterogeneous chemistry; and (2) togrow materials or
etch materials under conditions far from thermodynamic equilibrium.
Anisotropy is required since feature widths have become comparable to
feature depths. Non-equilibrium conditions are advantageous in two ways:
firstly, new materials or phases can be grown which would not be thermo-
dynamically favored in an equilibrium process; and secondly, the dele-
terious effects of high temperatures on devices can be avoided.
The chapter is divided into three main subsections: fundamental
aspects, etching, and deposition. The origin of anisotropy and the non-
equilibrium nature of the plasma will be discussed in the first section and
the resultant advantages to device processing will be described in the
following two sections. Since there have been several recent review
articles,1-16 particularly on plasma etching, we have not made an exhaustive
effort to include everything that has been published in recent years on this
subject.
In the first section on fundamental aspects the material is initially
tutorial but rapidly progresses to a discussion of the results of recent
diagnostic experiments which illustrate how power is dissipated in rf glow

191
192 Semiconductor Materials

discharges and how the form of power dissipation affects su rface chem istry.
Plasma-surface chemistry is then discussed first in terms of chemical
vapor transport and then in terms of the molecular interactions between
reactive adsorbates, surfaces, and products.
The second section dealing with plasma etching is oriented toward
process design. The steps involved in fabricating a planar MOS silicon
transistor are outlined in order to illustrate the variety of ways in which
plasma etching is used in microscopic pattern transfer. Trade-offs between
different reactors, and opposing design constraints, are discussed along
with processes for etching specific materials.
The final section deals with plasma deposition of materials for micro-
electronic applications. The plasma-enhanced chemical vapor deposition
(PECVD) of silicon nitride and silicon oxide is discussed in detail, with
emphasis on recent advances in techniques and property correlations.
Amorphous and microcrystalline silicon deposition is discussed from the
point of view of the parallels and contrasts with silicon nitride deposition.
Comprehensive coverage of this widely studied field has not been attempted,
but adequate reference is made to the large number of existing reviews.
Emerging PECVD applications, in epitaxial semiconductor growth (Si, Ge,
GaAs, GaSb), metal deposition, silicide deposition, and the deposition of
non-silicon-based oxides and nitrides, are also covered. Emphasis through-
out the section is on the influence of plasma parameters on the wide range
of accessible film properties, and in particular in indicating those of
relevance in a variety of semiconductor applications. Plasma film growth,
such as oxidation and nitridation, is not discussed.

2. FUNDAMENTAL ASPECTS
The idea behind this section is to present properties of plasmas and
plasma reactors which are common to all types of processes, be they
etching or deposition. The emphasis is on unifying concepts. Where
appropriate we have drawn upon the literature for specific examples to
illustrate a concept; more often than not the examples have come from the
etching literature since etching processes are generally better understood.
In some instances, the subject matter has not been covered completely
and some references may have been omitted for the sake of covering a
wide range of unifying concepts rather than covering one or two areas in
depth. To our colleagues whose work we have not included, we apologize
in advance.
In Sec. 2.1, we discuss some of the fundamental aspects of plasmas
and sheaths, starting with definitions of their properties as they pertain to
plasma processing. Widely used equivalent circuit models of rf plasmas
are discussed in light of recent diagnostic results. The relationship between
the equivalent circuit parameters and processing variables will be empha-
sized. Next, we discuss the plasma-surface interaction. A useful and
general framework for understanding both etching and deposition, chemi-
cal vapor transport (CVT) theory, is reviewed critically in Sec. 2.1. The
salient features of this theory can be summarized in terms of an equivalent
 Plasma Processing 193

circuit for the heterogeneous chemistry. Current thinking and recent

experiments on the microscopic mechanisms at play in both spontaneous
and ion-enhanced etching reactions are also reviewed in this section. In
Sec. 2.3, we review very briefly recent efforts to model various aspects of
plasma chemistry.

2.1 Plasmas and Sheaths

Plasmas mean different things to different people. 17 Basically, they
consist of a "soup" of ions, electrons, radicals, and stable neutrals, but, the
relative numbers of these species depend on operating conditions. Typical
numbers for and characteristics of the rf discharges used in microelectronic
processing are given in Table 1. The primary reason for using radio
frequencies is to avoid charging effects when dealing with insulating
substrate material (e.g. Si0 2 ): dc discharges cannot be maintained with
insulating electrodes because there is no direct current conduction path.
In addition, we will see that rf glows have physical properties wh ich depend
on the operating frequency and which can be used to advantage in
heterogeneous chemical processing. Pressures employed are such that
collisions between neutral and charged species are important. Power
densities employed are such that charge densities are relatively low,
typically 10 8 -10 11 cm- 3 , which means that collisions between charged
particles or between charged particles and low density radicals can
usually be neglected.
Two distinct zones are common to all plasmas: the plasma body and
the sheaths (Figure 1). The body is defined as a low field region where the
number densities of positive and negative species are approximately
equal. In most discharges, electrons- are the dominant negative charge
carrier; and, because the electrons are unbou nd, the plasma body is a good
conductor. Sheaths correspond to electron deficient, poor conducting
regions which exist wherever the plasma encounters an interface (electrode,
wall, etc.). Sheath formation occurs because of the difference in mobility
between electrons and ions, which stems in turn from the non-equilibrium
nature of partially ionized glow discharges (see Table 1): Electrons easily
gain energy from the field and heat up because they do not exchange
energy efficiently with the more massive neutrals with which they collide;
the neutrals and ions, on the other hand, do exchange energy efficiently so
that energy gained from the field is rapidly dissipated and the ion and
neutral temperatures remain close to the wall temperatures. 18
The voltage drop between the conducting plasma and electrodes
occurs in the sheath, resulting in a large sheath electric field. This large
field in turn can lead to gradients in concentration, temperature, and flux of
ions and radicals to and from electrode or device surfaces. Ultimately,
these gradients are responsible forthe non-equilibrium, or low temperature,
and anisotropic heterogeneous processing desired.
2.1.1 Response Time and Screening Distance. How does the
difference in mobility between electrons and ions result in sheath formation?
Consider the situation when a potential difference is applied across a
194 Semiconductor Materials

A A,B

SHEATH ---. ~ A,@ tB

---~. S·ot

ELECTRODE ~

Figure 1: Schematic diagram of parallel plate plasma reactor. Reactant A enters

from left and is removed along with p·roduct B at right. Positive ions, denoted by +,
traverse the sheaths along the electric field lines, ES, and impact surface S where
the neutral reactions, etch ing on the bottom electrode and deposition on the top
electrode, are enhanced (courtesy of C.B. Zarowin).

Table 1: Typical RF Plasma Properties

Pressure 10- 3 to 10 Torr

Frequency 10 kHz to 30 :MHz

Charge Density

Electron Plasma Frequency 100 to 3000 MHz

Ion Plasma Frequency 1 to 5 MHz

Debye Length 0.03 to 1.0 mm

Electron Temperature 1 to 5 eV (Time dependent)

Ion and Neutral Temperature ~ 0.03 eV

E/N (Sheaths)

a 1 Td = 10- 17 V cm- 2
 Plasma Processing 195

plasma. The electrons rapidly drift toward the positive electrode leaving
behind a net positive restoring force, which prohibits further electron
depletion. A steady state is achieved when the plasma potential is sufficiently
positive that electron and ion loss rates become equal. The time it takes
electron plasma frequencY,17,19

(1)

where n is the total charge density, e is the electronic charge, £0 is the

permittivity of vacuum, and me is the electron mass. This frequency is
directly related to the restoring force the electron feels when extracted
from the plasma (hence the dependence on the charge density, n). From
table 1 we see that we is much larger than typical operating frequencies for
the discharges used in plasma processing. Thus, plasma potential adjust-
ment and sheath formation will be virtually instantaneous as far as we are
concerned.
The maximum distance over which charge imbalance can be main-
tained, in the absence of an externally applied force, is the Debye length,17,19

(2)

where k is Boltzmann's constant, Te is the electron temperature, and c e is

the mean electron speed. The screening length is inversely proportional to
we just like the displacement of a spring is inversely proportional to the
restoring force constant. The Debye length is also proportional to the
random energy, or speed, since this energy must be overcome to achieve
effective shielding. Although the two are related, the Debye screening
length is not to be confused with the sheath thickness, which is generally
an order of magnitude larger. The relationship is not an obvious one and
depends on operati ng parameters such as pressure, freq uency, and power
density.20-22
2.1.2 Equivalent Circuits. A simple equivalent circuit which is suit-
able for both dc and rf plasmas is shown in Figure 2a. 19 ,23-29 Both regions of
the plasma are represented by resistors in parallel with capacitors; diodes
are used in the sheaths to represent the differences in ion and electron
mobilities which result in rectification of the applied voltage (see below).
Many of the operating characteristics of discharges used in microelectronic
processing can be understood in terms of the relative impedances of each
of these components (Figure 3). Consider dc or low frequency discharges,
where the reactive impedance is so large that only the resistive components
need to be considered. As mentioned above, the plasma body impedance
will be governed primarily by electron conductivity,

(3a)

(3b)
 (O
0)

LOW FREQUENCY en
RS1 < =r CS1 $f- HIGH FREQUENCY CD
3
o·
0
::J
a.
c
RS1 I ~ -LX S1 (")
ro+

, 0
-t

~RP
Rp ~ I I
A
=rep
s:
Q)
ro+
Rp CD
-t

~
(J)

_ RS2 I !- l.XS2
R
S21
I
r CS2
1 L RS 1 - RS2 »R p XS1 -X S2 >Rp

a b c

Figure 2: (a) Electrical discharge equivalent circuit. Each part of the discharge, sheath and plasma, is represented by a parallel
combination of resistors and capacitors. In addition, the sheaths have diodes in parallel in order to account for rectification of
the applied voltage. (b) Low frequency equivalent circuit. The resistive impedances are much less than the capacitive impedances.
(c) High frequency equivalent circuit. The capacitive impedances in the sheaths are less than the resistive impedances so that a
capacitive current shunt exists.
 Plasma Processing 197

, ",
", , , ",
, ,
, " , " v 1
",
, "
'~
./ "p = WC p

"
/ ""
~
,,
is' ,
1
X :-
S wcs ---',
s
WEoA
'
, , '",
a 104t--~
" ,
--~----_\...-_-_'--._-----
N \ o " , " ,
.ts (mivi ) ~s '"
Rs = C;-oAs '"
I
noe2
I
As '~',
~ ,
Zs ,
,,

101 .....I-- ~ ~ ~ _____'

10- 3 10- 1 1 10
W/21T (MHz)

Figure 3: Plasma impedances vs. frequency. Resistances, Rs and Rp, are deter-
mined by ion and electron conductivities, OJ = 5.5 X 10-'7 mhos cm -1 and 0e =
10-4 mhos cm-1 , sheath and plasma thicknesses, Is = 0.25 cm and Ip = 1.0 cm,
respectively, and the electrode area, As = Ap = 45.6 cm 2 . The capacitive impe-
dances, Xs and Xp, are determined by the th icknesses, areas, and frequency.

where v e is the electron momentum transfer collision frequency, A p is the

plasma cross sectional area, Ip is the plasma length, and R p is the plasma
body resistance. The sheath impedance will be given by the ion conductivity,
defined as in Equation (3) except using the ion mass and collision frequency
(see Figure 3). Primarily because of the mass difference, the ion conductivity
is roughly an order of magnitude smaller than the electron conductivity;
th us the sheath resistivity will always be greater than the plasma resistivity.
At higher frequencies, the sheath and plasma capacitive impedances
198 Semiconductor Materials

must be considered. The capacitances of the sheaths and plasma can be

sim ply estimated from the area of the electrode and the sheath and plasma
thicknesses, respectively (Figure 3),

(oAr S
Cps = -_!-. (4)
, lp,s

From Figure 3, we see for frequencies below 100 MHz, the plasma body
impedance is predominantly resistive. However, the sheath impedance
changes around the ion plasma frequency (Wi':::: 1 MHz), from being pri-
marily resistive at lower frequencies to being primarily reactive at higher
frequencies. In other words, the sheath capacitor becomes a current
shu nt. Above wi' the ions can no longer respond to the instantaneous value
of the field (see below) and so displacement instead of conduction cu rrent
dominates.
2.1.2.1. Experimental Verification. Recently, experimental diagnostic
techniques have been developed which allow the concentrations of free
radicals and ions as well as electric field amplitudes to be measured in situ
and non- intrusively.21 ,22,30-47 For a recent review, see Reference 37. These
techniques allow us to see the extent to which the equivalent circuit model
is appropriate.
2.1.2.1.1 Voltage distribution. How does the electric field vary across
the electrode gap? According to the equivalent circuit model, we expect
the field to be largest in the sheaths overthe frequency range of interest to
plasma processing (see Table 1 and Figure 3). In situ electric field measure-
ments are consistent with the model. The local field is plotted as a fu nction
of position for rf discharges through BCI 3 in Figure 5. For the range of
frequencies studied, 50 kHz to 14 MHz, the field is always greatest in the
sheaths. 21
2.1.2.1.2 Diode behavior. How does the local electric field vary with
time in the electrode sheaths? This has been measured by spectrally
resolving laser-induced fluorescence from parity mixed rotational levels of
the BCI radical formed in rf discharges through BCI 3.21,46,48 The different
parity levels are mixed by the local electric field; the extent of mixing is
dictated by the field strength as well as the excited state dipole moment
and zero-field energy level splitting. 46 ,48 Parity mixing is detected by
recording the intensities of transitions which would be "forbidden" in the
absence of an electric field and whose line intensity is a direct measure of
the electric field amplitude. The technique is illustrated in Figure 4, where
the field has been sampled at two different times during the rf cycle by
firing the laser synchronously with the applied rf. 22 Note that the change
signals for the "forbidden" and "allowed" lines in Figure 4 are equal and
opposite in sign because the "forbidden" component has borrowed intensity
from the "allowed" component as a result of the field-induced mixing. Both
measurements are made one mm from the powered electrode sheath. The
upper trace is obtained at a time when the powered electrode is the
momentary anode (applied voltage a maximum); the "forbidden" line in the
center is weak compared to the "allowed" lines on either side. Thus, the
field is small during this part of the cycle. However, when the laser is fired
 Plasma Processing 199

P(6) Q(5) R(4)

I I I

ANODE

CATHODE

2721 2720 2719

o
WAVELENGTH (A)

Figure 4: Spectrally resolved laser-induced fluorescence from BCI radicals formed

in a 13.5 MHz discharge through BCI 3 at 0.3 Torr and 0.13 W cm- 3 . The upper
trace was obtained by exciting the P(6) transition 1 mm above the powered elec-
trode at a point in the rf cycle when the voltage was a maximum, making the
powered electrode the momentary anode. The lower trace was obtained in a
similar fashion except during the cathodic part of the cycle. Note that the for-
bidden component, Q(5), is strongest during the cathodic cycle when the electric
field is greatest (from Reference 21 ).
200 Semiconductor Materials

during the cathodic part of the cycle (lower trace), the "forbidden" line is
comparable in amplitude to the "allowed" lines. During this part of the
cycle, the electric field is strong. Thus, the applied field is rectified in the
sheaths. As a result of the difference in electron and ion mobilities the
plasma potential is "tied" to the anode potential. This behavior is accounted
for in the equivalent circuit (Figure 2) by placing diodes in parallel with the
sheath resistors and capacitors.
2.1.2.1.3 Frequency response. As the frequency is varied an interesting
transition is seen to occur in Figure 5. The local field decreases by roughly
a factor of two above 5 MHz. The peak voltage which must be applied
across the plates in order to maintain constant power also decreases by
this amount (Figure 6a). From the equivalent circuit model we see that this
transition corresponds to a change in the sheath impedance from being
predominantly resistive below wi to predominantlycapacitive above wi. The
total impedance decreases above 5 MHz as the sheath capacitive impe-
dance becomes less than the ion resistive impedance (Figure 3). At
constant power the ratio of voltages at high and low frequency is given by,

1.5

0 50kHZ

1.2 5MHZ
~

'",b..,
E
u
~
~
0.9
0
...J
lJ.J
«,
~
l.L
u Cl3MHZ
0: 0.6
.-u -lit' . "., ~ ,
w
...J *"-. ~
'-..
W
~
" ·'lI. ,
0.3 .".,......... """" . '" 0
II"""", •
............
0
0 2 4
POSITION (mm)

Figure 5: Preliminary measurements of electric fields in BCI 3 plasma asa function

of position from the powered electrode to the plasma center for three different
frequencies. The laser was fired at a time such that the powered electrode was
the momentary cathode. The vertical scale is accurate to within ± 50 Vfcm (from
Reference 21). The counter electrode is at 16 mm.
 Plasma Processing 201

0.7
(a)
0.6

> 0.5
~

w
(!)

~
0.4 •
:...J
~ 0.3
~
c:t
~ 0.2

0.1

(J)
a
t-
Z
::::>
>-
a:: 6
• PIE
0 LIF <b)
~
f-
eD 5
a::
-c::x:
en
w 4
r=
U5
z 0
~ 3
~
0
•
w 2
tia::
ffi
~
-< a
&5 104 10 5

FREQUENCY (HZ)

Figure 6: (a) Peak voltage for discharge through BCI 3 as a function of frequency
at a pressure of 0.3 Torr and a power density of 0.13 W cm -3. (b) BCI radical densi-
ties as a function of frequency. PIE refers to plasma-induced emission, i.e. ex-
cited state radicals, while LIF refers to laser-induced fluorescence, i.e. ground
state radicals (from Reference 21 ).
202 Semiconductor Materials

(5)

which is in very good agreement with the values in Figures 5 and 6a. This
transition is also apparent when one examines the voltage and current
waveforms in Figure 7. 21 Not only does the current increase and the
voltage decrease above 5 MHz but the phase shift between the two
0
increases toward 90 as the capacitive component becomes an important
sheath current shunt.
2.1.2.1.4 Power dissipation. From the above discussions of voltage
distribution and frequency effects we can see how and where power is
dissipated in rf discharges as a fu nction of frequency. At low frequency, the
sheaths are primarily resistive and the sheath resistance is much greater
than the plasma resistance. Thus, we expect power dissipation to occur
primarily in the sheaths. Ions accelerated by the sheath field can dissipate
their energy in basically two ways. Collisions with neutrals can result in
ionization, excitation, chemical reactions and/or heating; collisions with
electrodes can result in any combination of surface damage, sputtering,
secondary electron emission and/or heating with either implantation or
reflection of the incident ion.
The response of ions to the sheath field and the consequences of this
response at low frequency can be seen very clearly in Figures 8 and 9. 21 In
Figure 8, the density of CI 2 + measured in the sheath by laser-induced
fluorescence is plotted as a function of time. During the positive part of the
cycle when the local field is very small (Figure 4), the ion concentration
builds as a result of both diffusion of ions from the plasma into the sheath
and ionization byelectron impact. During the negative part of the cycle, the
ion concentration decreases precipitously as a resu It of the large cathodic
fields (Figure 4) which sweep the ions out of the sheath toward the
electrode. The extraction of high energy ions at low frequency causes
ionization, excitation, and secondary emission of electrons. This can be
seen in Figure 9 where the uv emission intensity from BCI radicals is
recorded as a function of position across the electrode gap at different
times during the rfcycle. 21 When the ions are extracted during the cathodic
cycle the emission is brightest because the ions and secondary electrons
collide with neutrals and produce a cascade of ionization, excitation
(Figure 9), and dissociation as they are accelerated across the sheath.
This periodic build-up and high-energy extraction of ions in the sheath
has no dc or high frequency analog. In dc anode sheaths, ions build up to
some steady-state level but are never extracted with high energy. In dc
cathode sheaths, the ion concentration can never build up to a large value
owing to the large, extracting sheath field. While the time-averaged flux
may be similar in the dc and low frequency rf discharges, the pulsed ion
bombardment in the latter may make a difference in heterogeneous
reaction rates. In high frequency(Le. above wi) discharges, the ions respond
only to the average field, which is less than at lower frequencies owing to
the resistive to capacitive transition discussed above. The net result at
 Plasma Processing 203

0.2 13 MHz ;I'

0.4
~
/
0.1 / 0.2
/
/
0 /--. 0
/
/
-0.1 / -0.2
/

-0.2 -0.4

0.4 0.2

0.2 ,, 0.1
,,
0
, 0

,
\
-0.1
> -0.2
..:.:::
\ <t
fIIII'fIIII'
'----- -0.2 t-
:: -0.4 z
<9 W
<t 0.04 cr
~
0.4 750 kHz cr
--J ~
0 U
> 0.2 0.02

0 0

-0.2 -0.02

-0.4 -0.04

0.4 0.08
50 kHz
0.2 0.04

0 0

-0.2 -0.04

-0.4 -0.08

O. 0.5 1.0 1.5 2.0

TIME (UNITS OF 7T)

Figure 7: Current and voltage waveforms for discharges through BCI 3 at several
different frequencies and a pressure of 0.3 Torr and a power density of 0.13 W
cm-3 (from Reference 21). One unitof1Tcorrespondsto a 1/2v,wherevistherf
frequency in Hz.
204 Semiconductor Materials

rt')
I 109
E
u
<.J
Q)

o
E

o 2 3 4
TIME ( UNITS OF 1T)

Figure 8: CI 2 + ion density vs. time in the sheath of a 55 kHz discharge through
CI 2 at 0.3 Torr and 0.6 W cm-3 • One unit of 1T corresponds to 18.2 j1sec.

high frequency is that the ions experience a smaller extraction force and
again build up to some steady state concentration.
The response of ions to the instantaneous field and the change in the
amplitude of this field with frequency at constant power affect the energy
with which ions impact electrode or device surfaces. This is evident in the
ion energy distributions measured by Bruce 49 as a function of frequency
(Figure 10). At low frequency, the ions are accelerated to the full sheath
potential, which is approximately the full applied potential (see Figure 5),
on every half cycle as they traverse the sheath. To the extent that there is
ionization and energy loss in the sheath, the ion energy distribution will be
skewed toward lower energies. At 40 Pa (0.30 Torr) of CI 2 and 100 kHz, the
CI+ and CI 2 + ion energies on average are significantly less than the full
sheath potential but the maxim um ion energy is approximately eq ual to the
full sheath potential (Figure 10).49,50 At 13.7 MHz, the ion energy distri-
butions are much narrower and the maximum ion energies are much less
than the peak sheath potential.
Because of the transition from resistive to capacitive sheaths above wi'
power dissipation must shift from the sheaths to the plasma. Since the
current is conducted primarily by electrons in the plasma, the dissipation
mechanisms must involve electron-neutral collisions: ionization, disso-
ciation, and excitation. The shift in power dissipation is evident in Figure
11, where the time-averaged concentrations of excited and ground state
BCI radicals are plotted as a function of position across the gap. Three
different frequencies are displayed; the shifts in emission intensity and
radical density are indicative of the shifts in where power is dissipated.
When these profiles are spatially integrated we can learn not only where
but also how power dissipation changes with frequency. As frequency
increases, the total, spatially-integrated densities of both excited and
 Plasma Processing 205

II

OL...-L---L..--L--1-...l....o-.-JL........-L--L---L--'--............---a..........J.--.L.--'--..I...-.II........L---.l.....-.L.-~~ .....

o 4 8 12 16 20
AXIAL POSITION (MM)
Figure 9: Time-resolved BCI emission obtained from a 50 kHz discharge through
BCI 3 at 0.13 W cm -3 (from Reference 21 ).

ground state radicals also increases (Figure 6b)21,51 because power is no

longer dissipated in the form of ion heating of surfaces and neutrals. Since
total power is kept constant, the power dissipated must be converted to
electron processes resulting in an overall increase in radical, ion, and
excited-state production.
The net effect that operating frequency has on a particular etching or
deposition process depends upon the specific surface chemistry. For
example, Bruce 52 has found that the etch rate of Si in a CCI 4 plasma
increases by more than an order of magnitude as the operating frequency
increases from below to above wi (Figure 12a). The reaction of chlorine
with Si at room temperature without ion bombardment is negligible; the
206 Semiconductor Materials

Cf2 0.3 Torr

0.6 W/em 2
SS ELECTRODES
10 3
Ci) 1 em SPACING
!:::
z:
~

>
cc
<
cc
t- 10 2
ea
cc
~
L&.J
~
"'""-
Z
"C

10

13.7 MHz
Cf+

100 200 300 400 500

ENERGY (VOLTS)
Figure 10: Ion energy distributions, dN/dE, vs. frequency for a discharge through
el 2 (from Reference 49, reprinted with permission of Solid State Technology,
published by Technical Publishing, a company of Dun and Bradstreet).

reaction is ion induced. 49 ,53-55 Thus, the plasma etching of Si is enhanced

by lowering the operating frequency because of the increase in the ion
energy at lowerfrequency(Figure 10). On the other hand, undercomparable
conditions the AI etch rate decreases by a factor of 4 as the operating
frequency is tuned from below to above w j (Figure 12 b). AI etches spontan-
eously in a chlorine environment once the native oxide has been re-
moved. 49 ,54,55 Thus, the AI etch rate increases with frequency because of
the increased production of chlorine atoms and molecules as the degree
of CCI 4 dissociation increases (Figures 6b and 11) despite the decrease
in the bombarding ion energies.
2.1.2.2 Bias Effects. It is commonly observed that in high frequency
discharges with uneq ual electrode areas that a dc bias voltage will bui Id up
between the two electrodes. There is a general consensus as to the cause
of dc bias but not as to its scaling with discharge parameters and in
particular its scaling with the electrode area ratio. First of all, unless a
blocking capacitor is placed in series with the rf generator input (Figure 1),
there will be a dc path to ground and no bias will be observed. The bias
 Plasma Processing 207

5 I
PIE
4 LIF ..,1ItI-'----- 5MHZ
,,'"
,.J /
3 I
I
....-
Cf) 2
I-
Z
::>
>-
0:
<I
0: a
f-
eD
a:: 4 2.5MHZ
~
>- 3
I- ~\

,,:
C/)
Z \
W 2
f-
Z
Z
,
I
o -.,. J
(f)
C/)
~
a
w
4 0.25 MHZ
t.,
3
I \
I \ I
/1I
, I \ "'\
I
I I
,,
I
2
,I "
" /
/""
,,
I

0
0 20

AXIAL POSITION (mm)

Figure 11: BCI radical spatial profiles as a function of frequency for a discharge
through BCI 3 at 0.13 W cm-3 and 0.3 Torr. The arrows indicate the positions of
the parallel plate electrodes. PI E refers to plasma-induced emission (excited states)
and LI F refers to laser-induced fluorescence (ground states) (from Reference 21).
 208 Semiconductor Materials

E 1.5
oce
-....
~

....
LU Si
ce
a:: 0.5
::c
....
~

L.U
u; 0.01 0.1 1 10 100
EXCITATION FREQUENCY (MHz)

3
w Cc.f4: Ar/1:1
:IS
t= 0.4 Torr
-....
::c 75 W
.... ~
~

LU
2
SS ELECTRODES Al
..... -!:. 1 em SPACING
....cec oce-~

t:.
....ce
LU

a::

0.01 0.1 1 10 100

EXCITATION FREQUENCY (MHz)
Figure 12: (a) Si etch rate vs. frequency in a discharge through CCI 4 . (b) AI etch
rate vs. frequency in a discharge through CCI 4 (from Reference 52, reprinted by
permission of the publisher, The Electrochemical Society Inc.).

develops with a blocking capacitor when the electrodes have different

areas because the ion current density to both electrodes is approximately
the same.
It should be noted that an insulating substrate can serve as a blocking
capacitor in the development of a dc bias voltage. However, depending on
the polarizability of such an insulating layer, the sheath field may be
reduced. If the insulator is polarizable it can shield the applied field and a
voltage drop will occur across the substrate.
Zarowin 28 has shown, using the high frequency equivalent circuit
model in Figure 2b, that the ratio of sheath electricfields should be equal to
the ratio of areas. For equal sheath thicknesses, this implies that the
voltage ratio should also be equal to the inverse area ratio:
VI A2
'-=-, (6a)
V2 Al
where Vi is the potential difference between the plasma and electrode i
whose area is Ai. This relationship was derived by assuming conservation
of current density and sheath capacitances which are independent of
current density but proportional to electrode area. One might expect this
approximation to work better at higher pressures, where sheath thicknesses
(and thus capacitances) are not very sensitive to voltage and current. 20
 Plasma Processing 209

The "classical" work on dc bias effects to which most people refer is by

Koenig and Maissel. 24 These authors used the Child-Langmuir law 17 to
relate current and voltage to sheath thickness. The sheath capacitance is
assu med to be proportional to electrode area and inversely proportional to
sheath thickness (see Equation 4). Furthermore, the plasma resistive
impedance is neglected compared to the sheath capacitive impedance at
high frequency so that the discharge acts like a capacitive voltage divider.
This leads to the following equation:

(6b)

This scaling relationship should bevalid only at low pressures becausethe

Child-Langmuir law applies to collisionless sheaths. 17
Experimental testing of these relationships has not been extensive
but the results obtained so far indicate that Equation 6a is generally more
applicable. Coburn and Kay 56 measured sheath voltages as a function of
the area ratio by sampling ions through a pinhole in one of the electrodes.
For an Ar discharge at 0.05 Torr, they fou nd the voltage ratio to scale more
according to Equation (6a) than Equation (6b). More recently, Kohler et
al. 29 made similar measurements on a 13.56 MHz Ar discharge operating
at 20 mTorr. For a wide range of applied rf and dc voltages, the capacitive
sheath model was found to be adequate in accounting for the measured
sheath voltages. These experiments were done in an unbalanced (Le.
unequal electrode area) system and no attempt was made to look at the
electrode area dependence.
In situ measurements of sheath fields in a 13.5 M Hzdischarge through
BCI 3 at 0.3 Torr indicate that both the sheath field and thickness change
with dc bias. The cathode field increases and the sheath contracts with
increasing bias. No changes are observed in the anode sheath. 57 The net
result is that the dc bias voltage appears across the cathode sheath only.
Control of dc bias, by changing electrode areas, rf power, or by using an
external dc powersupply, can be useful in controlling etching and deposition
processes because the sheath voltages determine the energies of ions
impacting device surfaces (for example, see References 27, 28, 58-60 and
references therein). This point is discussed in further detail below (Sections
3.2 and 4.2.1).
2.1.2.3 Limitations of equivalent circuit models. From the above dis-
cussion, it should be clearthat simple equivalent circuits can be useful for
understanding many qualitative aspects of rf plasmas and developing
intuition which can be applied in process design and trouble shooting.
However, it should be equally clearthat the equivalent circuit is really only
a point of departure for complete understanding. The impedances plotted
in Figure 3 are very crude estimates and ignore many aspects of the
discharge physics and chemistry. In particular, the neglect of periodic.
time-dependent variations in concentrations, energies, and fields must limit
the validity of the equivalent circuit model as described above. For example,
one need only look at the voltage and current waveforms for a low frequency
210 Semiconductor Materials

plasma (Figure 7) to see that the simple circuits of Figure 2 are deficient. A
solution would be to consider the resistors and capacitors to have time-
varying impedances. Forexample, the origin of the time-dependent sheath
resistance can be seen in Figure 8. Once the ion density has been
extracted by the field, the ion conductivity must necessarily decrease.
2.1.3 Feedstock Composition. Much has been written about the
effects of feedstock composition on both gas-phase and surface plasma
chemistry so we will not discuss the matter in great detail here. The reader
is referred to recent review articles and references therein for more detailed
information. 4,5,1 0,16,61 There are basically two types of effects that feedstock
composition can have on the plasma: physical and chemical. Most of the
literature has dealt with chemical effects.
2.1.3.1 Chemical effects. The effects of feedstock composition on
gas-phase chemistry depend upon the degree of dissociation of the
feedstock constituents so that these effects are not independent of other
plasma parameters such as frequency (Section 2.1.2.1.3), power (Section
2.1.5), and residence time (Section 2.1.4). Given that there is some degree
of radical production, then the reactions proceed much like one would
expect from fundamental chemical principles. Forexample, the addition of
02 to a CF 4 discharge results in increased production of F atoms and CO
and reduced production of fluorocarbon radicals and molecules. 4,62-64,333
For example, the reaction,

o+ CF a --+ COF 2 +F (7)

proceeds rapidly and exothermically.
The net result on surface chemistry can be complicated owing to the
different reactivities and stickinQ coefficients of various qas-phase species
on various surfaces. For example, when 02 is added to a CF 4 discharge
used in the Si etch rate 63 (Figure 13). However, as more 02 is added, the
increase in the Si etch rate 63 (Figure 13). However, as more 02 is added, the
etch rate goes through a maximum and then declines because oxygen
begins to compete with fluorine for Si adsorption sites. 63 A similar effect
has been seen in the etching of GaAs and InPwith CC1 3F/0 2 discharges. 65
Another effect of halocarbon oxidation is to reduce the extent of polymer
deposition by oxidizing polymer precursors such as the CF2 radical. Poly-
merization is a common problem resulting in sloweretch rates and surface
contamination.
Other feedstock recipes and the rationale behind their usage for
specific etching and deposition applications are discussed in greater
detail in Secs. 3.4, 3.5, 4.2.2, and 4.3.
2.1.3.2 Physical effects. The physical effects associated with feed-
stock composition have to do with changes in the electron energy distri-
bution, electron density, ion energy distribution, ion density, and ion
composition. These changes will, of course, affect homogeneous and
heterogeneous plasma chemistry as well: radical production rates can be
strongly dependent upon the electron density and energy distribution;
surface reaction rates can be strongly dependent upon ion energy.
The effects of feedstock composition on the electron energy distri-
 Plasma Processing 211

1.0
9'e-~
I ,

0.8
/0
1_
~
'-
~

! r '\
W 0

l) 0.6 I '
~
w
I '0
,
> p ,
~ 0.4 I '0
~ I ~,
~ I "
0.2 0 ETCH RATE (Si) 0,

10 20 30 40 50 60
PERCENT 02

Figure 13: Si etch ratevs. O 2 concentration in a CF 4/02 discharge (after Refer-

ence 63).

bution can be seen in Figure 14 where the emission intensities from F and
Ar are plotted as a function of the 02 feedstock concentration in a CF4/°21 Ar
discharge. As the oxygen concentration increases, the Ar emission intensity
decreases indicating that the nurn ber of electrons with energies above the
7504A line threshold must also decrease. In other words, the electron
energy distribution appears to cool. Note that the F atom emission lines at
7037 Aand 6856A, which have similar excitation thresholds, increase with
02 concentration. The overall increase in F atom production byfree radical
reactions (see above and Figure 14) more than compensates for the
decrease in excitation efficiency.
Two explanations for the cooling of the electron energy distribution
with the addition of 02 are plausible: (1) the enhanced production of F
atoms and the introduction of oxygen, both species being electronegative
compared to CF x compounds, results in electron cooling by electron
°
captu re processes; or, (2) the lower ionization potential of and 02 relative
to F and CF x66 results in electron cooling by inelastic ionization of neutral
and 02. Of these two, the second explanation is more viable because
°
electronegative gases do not attach high energy electrons very effectively
(see Reference 67 and references therein). On the other hand, the intro-
duction of a lower ionization potential gas necessarily reduces the average
electron energy since a lower energy collision channel has been opened.
212 Semiconductor Materials

4,------.,-----,------,---....,....----------
CF4+ 0 2
o Ar (7504A) INTENSITY
- EXCITATION EFFICIENCY
FOR F (7037A)

o o o o

.......
0~---'-----'--_---L..-- --.....4-----'---~

(b)

• F (7037A) INTENSITY
• F (6856A) INTENSITY
o F ATOM DENSITY
o'--_--"__---'-__ - - L . _ _---'-- _ _- ' - - _ _"""---_----J

20 40 60
° OXYGEN PERCENTAGE

Figure 14: F and Ar emission vs. O2 concentration in a discharge through CFJ0 2/Ar
(from References 30 and 63, reprinted with permission of the American Institute
of Physics).
 Plasma Processing 213

The importance offeedstock ionization potentials also shows up in the

dynamics of ion production and loss.22 For example, small additions of 02
to an Ar discharge cause dramatic changes in the ion composition. 68
Similarly, when CI 2 is added to a low frequency discharge through N 2, the
ion composition changes drastically. The concentration of CI 2 in the
feedstock need be only 1 0 0/0 forthe N 2+ concentration to drop by an order
of magnitude. The concentration of CI 2+ is virtually the same in this mixed
plasma as it is in a pure CI 2 discharge. 22 This effect is illustrated in Figure
15, where the time-dependent concentrations of N 2+ and CI 2+ are plotted
for various feedstock compositions. The extent of modulation in the ion
concentration waveforms is a measure of the ground-state ion lifetime. For
the N 2/C1 2 mixture, the N 2+ lifetime is determined by the rate of charge
exchange with CI 222 (Figure 15d). Since the ionization potentials for N 2
(15.58 eV) and CI 2 (11.48 eV) are so different, the exchange is essentially
irreversible. The charge exchange reaction must proceed rapidly for the
steady-state ion concentration to be so greatly affected by small changes
in feedstock composition. In this particular case, the reaction rate is
probably enhanced by exchange through the excited state of CI 2+,

Nt + C1 2 -+ N2 + CIt (A2 Il) (8a)

followed by,

(8b)

The excited state reaction (8a) is exothermic by 1.6 eV as opposed to the

ground state reaction which is exothermic by 4.1 eV; thus, reaction (8a) is
expected to lead to a resonant en hancement in the exchange rate.Another
reason why the N2 + density drops when CI 2 is added to the feedstock is the
electron cooling effect mentioned above. Since the electrons can interact
with ch lorine at a lower energy, fewer electrons wi II have a chance to reach
the higher energies necessary for ionization of nitrogen.
An important point to keep in mind, and one which will be emphasized
in Secs. 3 and 4 below, is that the effects of feedstock composition on
discharge properties and chemistry may be totally out of proportion to the
actual feedstock concentrations. Since ion and radical densities can be a
very small fraction of the total gas density, small concentrations of feedstock
additives, or impurities, may drastically alter these minority concentrations.
Moreover, the role that these minority constituents play in the discharge
chemistry can be substantially out of proportion to their concentration,
particularly when it comes to surface processes.
2.1.4 Pressure, Flow-Rate, and Residence Time. Variation of
pressure and flow-rate is commonly employed in the tailoring of a particular
plasma process to a particular device application. Again, the effects of
these parameters on the discharge can be roughly divided into physical
and chemical effects with the caveat that the two are, strictly speaking,
interrelated.
2.1.4.1 Chemical effects. The key parameter in affecting discharge
chemistry is neither pressure, P, nor flow-rate, ¢, but rather the residence
 214 Semiconductor Materials

( 0)
~
>

w
(!)
<t
~
-l -0.25
0
>
-0.5 -

>-
.... 8X107
en (b)
z 100 % N2
~ 6
0

+0 4
V.J
N
x NI
2
+N
Z
0

>- 4X109
r-
ooz 100 % C.e2
w
a
Ol 2 _
~
(\J
Cit
x
+~
~
u 0
>-
~ 8X10 6
(J)
z
w 6
0

+0' 4
W
N
X 2
+C\J
z 0
>-
.-
(J)
4X109 90 % N2
10 0/u Cl 2
(e)
z
w 3
0

t::
Ol 2
C\J
x CJ2!
+(\J
~
() 0
0.5 1.0 1.5 2.0
TIME (UNITS OF .".)

Figure 15: Time-resolved N 2 + and CI 2 + concentrations measured by laser-induced

fluorescence (from Reference 22).
 Plasma Processing 215

time, which is simply proportional to P/¢. This can be seen very clearly in
the mass spectrometric data of Truesdale et al. 69 wh ich is reproduced here
as Figure 16. They studied the plasma decomposition of C 2 F6 as a function
of both pressure and flow-rate and examined the stable products down-
stream from the dischargewith a quadrupole mass spectrometer. The final
concentrations of C 2 F6' CF 4 , and C 2 F4 vary both with flow-rate at constant
pressure and with pressure at constant flow-rate. When the ratio of pressure
to flow-rate is held constant, however, the final product concentrations
also remain constant (Figure 16).

IOO----------.-------~--------
(0)

80

o~

rC2 F4
~
100 .2 .4 .6 .8 1.0 .2 .4 .6 .8 10 PRESS.,
. TORR
FLOW, STD, CC/MIN PRESS., TORR
5 10 15 20 25 FLOW,
I I
! CC/M N

Figure 16: Composition of the effluent from a 50 W C2 F6 discharge; (a) as a

function of flow-rate at constant pressure; (b) as a function of pressure at con-
stant flow-rate; and (c) as a function of pressure and flow-rate at constant resi-
dence time (from Reference 69, courtesy of G. Smol insky).

The best way to vary residence time, Le. with minimal effect on other
plasma parameters, is to vary the flow-rate at constant pressure since
variation of pressure can have pronounced effects on the discharge
physical properties (see below). What happens to the gas-phase chern istry
when the residence time is varied? If we consider the rate of decomposition
216 Semiconductor Materials

and radical production to be fixed for a given power density, then it is easy
to see that the less time the feedstock gas spends in the plasma volume,
the less extensive the degree of dissociation. Thus, at high flow-rates, or
short residence times, the radical density will decrease with increasing
flow-rate. At low flow-rates, or long residence times, the extent of dissociation
may reach a limiting value and a dynamic equilibrium will be established
such that the radical concentrations become flow-independent.
Let us consider the effects of flow-rate on heterogeneous chemistry
when the heterogeneous rates are not rate-limiting: Le. when the surface
reaction probability is large. If the radical products of feedstock decom-
position are the primary surface reactants, then the low flow-rate radical
concentration may be neglible since the heterogeneous reaction acts as a
radical sink and the overall reaction rate may be small because of the small
reactant flux to the surface. At high flow rates, the feedstock may be
insufficiently decomposed to provide radicals for the surface reaction and
again the heterogeneous rate may be small. The overall dependence of the
surface reaction rate on residence time, or flow-rate, will exhibit a maximum
(Figure 17).19,70 The effect of flow-rate on heterogeneous chemistry when
the reaction is surface rather than reactant-supply rate-limited will be
discussed in Sec. 2.2.1.
2.1.4.2 Physical effects. The situation is very different when one con-
siders the effects of pressure and flow-rate on the physical properties of
the discharge and, in particular, the energy distributions of ions and
electrons. The effects of flow-rate on ion and electron energy distributions
are primarily an indirect consequence of the compositional changes
discussed above. However, pressure affects these distributions directly

_____ ~~~~~!5_L~~I~_E1_ _

t
w
SUPPLY RATE LIMITED ETCHING

~
0:::
:r:
u
t-
W

OVERALL FLOW RATE

DEPENDENCE

FLOW RATE----.

Figure 17: General ized flow-rate dependence of etch ing rate for the case where
the surface reaction rate is fast and the reactant is generated in the plasma. Two
limiting cases are obvious: (1) rate is reactant supply limited and (2) rate is re-
actant generation limited (after Reference 70).
 Plasma Processing 217

by affecting collision rates. For example, the energy with which an ion
impacts a su rface is not on Iy dependent upon the sheath field, rffreq uency,
and ion mass but also the rate at which ions collide with neutrals as they
traverse the sheath. 19,56,71 ,72 If the collision mean free path is greater than
the sheath thickness, then ions which enter the sheath from the plasma
boundary will be accelerated by the full sheath potential and will impact
the electrode with a narrow but highly energetic velocity distribution.
Alternatively, if the collision mean free path is much smaller than the
sheath th ickness and if the ions lose all the energy gai ned from the field on
each collision, then

(9)
where E j is the ion kinetic energy at the electrode and F is the sheath field,
assu med to be constant with position over one mean free path, A. The truth
will generally lie somewhere between these two extremes.
Pressure also affects the electron energy distribution. Many electron-
neutral collisions result in the formation of ion-electron pairs. If the electron-
impact ionization mean free path is small compared to the sheath thickness,
this can lead to substantial ionization in the sheath, which in turn will alter
the ion energy distribution at the electrode surface and the sheath
thickness. 2o In general, the overall charge density and plasma impedance
can be expected to change with pressure in a complex fashion. Since the
ion and electron collision mean free paths can be expected to scale
inversely with pressure, Equation 9 suggests that the natu ral variable with
which charged particle energy distributions and denities can be expected
to scale is neither pressure nor sheath field but rather the ratio F/P. This
has been long appreciated by scientists studying dc glow discharge
physics. As we will see in Sec. 2.1.7, it is also a useful parameter in
designing and understanding heterogeneous plasma-surface interactions.
2.1.5 Power Density. Many things can happen when the applied
power density is varied. Generally, ething rates, radical densities, charge
densities, and sheath fields increase initially and then saturate with in-
creasing power. One reason why saturation occurs may be that the plasma
volume often increases as the power is increased and electrons and ions
acquire greater energy. This expansion may result in the discharge "finding"
other grounds and discontunities can result in measured plasma para-
meters. If the plasma volume can be maintained at a constant volume, e.g. by
mechanical or magnetic73 confinement, then an increase in power corre-
sponds to an increase in power density. This in turn will result in higher
electron energies, sheath potentials, and ion energies.

2.2 Plasma-Surface Chemistry

In order to understand the overall plasma-surface interaction it is
necessary to understand the transport properties of the system with wh ich
we are dealing as well as the fundamental interactions between reactive
adsorbate, surface, and product. In this section we first address the
transport problem (Sec. 2.2.1) using recent results derived by
Zarowin. 28 ,58,74,75 In Sec. 2.2.2, we deal with the microscopic interactions
218 Semiconductor Materials

between reactive adsorbates and surfaces which lead to etching and

deposition.
2.2.1 Chemical Vapor Transport. Plasma processing takes place
at sufficiently high pressures that back reactions can be important. For
example, in an etching reaction, the volatile product may redeposit either
on the surface from which it desorbed, another part of the same waferfrom
which it desorbed (e.g. a side wall), or another surface all together(e.g. the
cou nter electrode). For th is reason it is necessary to consider the theory of
chemical vapor transport in order to understand the etching and deposition
of thin films in a plasma environment.
As long ago as 1926, the anomalous sputtering of certain materials
was characterized in terms which we now refer to as chemical vapor
transport 58 ,75-77: involatile cathode materials could be transported via
the formation and subsequent decomposition of intermediate volatile
compounds. For example, in the first experiments by Gunterschulze 76 As,
Sb, and Bi were transported in a hydrogen discharge via the formation of
the corresponding hydrides. Veprek and Marecek 77 showed that thin films
of Ge and Si could be prepared by chemical vapor transport in a hydrogen
plasma. Transport of the elements occured from the cold zone where the
hydrides are formed to the hot zone where they are decomposed. More
recently, Zarowin has expanded these ideas to include the effects of
geometry, flow-rate, and ion bombardment as well as surface temperature.
We will summarize the salient features of his theory below; first, the nature
of chemical vapor transport in the absence of a plasma or ion bombardment
and at zero flow-rate is discussed in terms of an analogy to an electrical
equivalent circuit. 58 ,75 The circuit is useful only in that there are mathe-
matical correspondences between the electrical circuit elements and
elements of the heterogeneous chem istry, so that analysis of the electrical
circuit provides "intuition" for the chemical vapor transport processes. In
the following sections, the effects of flow-rate, loading (or geometry), and
ion bombardment are considered in turn.
2.2.1.1 Equivalent circuit: Zero flow. Consider the generic reaction,

(10)

where S is the surface material to be transported, either etched, at rate a:

per unit area, or deposited, at rate f3 per unit area, A is the reactant which
combines with S to form volatile compound B. The transport of these
species can be neatly summarized in terms of an equivalent electrical
circuit (Figure 18). Transport impedances, which can all be represented in
terms of resistances, correspond to either heterogeneous reactions or
diffusion. For simplicity, we consider only two surfaces, i and j, with reactive
resistances,

(11 )
 Plasma Processing 219

j
I Sf

i __ 1_
Rr - . .
C'O""

Figure 18: Equivalent circuit for chemical vapor transport. The transport of
products from one surface to another is driven by an effective chemical potential
difference between the surfaces which may result in turn from differences in sur-
face temperature or ion bombardment. The effects of flow-rate are represented
by current generators so that in the absence of an effective chemical potential
difference, etch ing but not deposition may occu r (after Reference 75). See text
for definitions of circu it elements.

where Ci is the area of the ith surface and a i =a i+f3i is the reaction conduc-
tance. Slow reactions correspond to large resistances. The diffusive resis-
tance between the two surfaces is given by,

h2
Rd = D' (12)

where h = ~b/Vb is a measure of the separation between surfaces.?5 Slow

diffusion corresponds to a large resistance. The effective chemical potential
difference between surfaces i and j is given by,

(13)

where Ki,j = a i,j/f3 i,j is the equilibrium constant at surface i,j. The term
chem ical potential difference is used somewhat loosely here. A fi nite value
for zeta implies that the equilibrium states for the two surfaces will not be
220 Semiconductor Materials

the same (e.g. if they are maintained at different temperatures). Therefore,

there will be a chemical driving force which produces transport of A and B
between the surfaces. In terms of the product current,

IB = l (14)
R'
where R = Rri+Rrj+R d is the total circuit resistance. The reason for repre-
senting the surface reaction rates and diffusion rate as conductivites
shou Id now be apparent. At zero flow the product cu rrent, or etch ing rate, is
limited by how fast etching occurs on one surface, deposition on the other,
and diffusion of reactants and products in between. If the heterogeneous
reaction rate happens to be limited by reactant generation from a homo-
geneous process, the product current will be limited instead by that
process. This can be seen in a formal fashion by supposing there is a
precursor to reactant A in Equation 10. In terms of the CVT equivalent
circuit (Figure 19), this means that there will be an additional resistance in
series with Rr. In terms of the heterogeneous rate constant, a t - 1 = a A-1 +
a p ,-1 where a p is the sum of the forward and backward rates for the
precursor reaction p .... A.7 5
It is important to note that the above equation forthe product current is
valid, within the framework of the simple generic equation, for any departure
from equilibrium. In equilibrium, Ki = Kj, there is no chemical potential
difference and no net transport of A or B from one surface to another. If a
chemical potential difference is maintained between surfaces i and j, for
example by application of a temperature or electrical potential difference
(see below and Reference 58), there will be net transport of A and B from
one surface to another. Whether B is deposited on surface i and etched
from surface j or vice versa depends on the sign of zeta, which in turn
depends not only on any temperature differences between the surfaces
but also on the reaction energetics. This can be seen most clearly by
expressing the equilibrium rate constants in terms of the surface tempera-
tures and the Gibbs reaction free energy, ilG:

(15)

Thus, when ilG is positive (endoergic), zeta is positive for Ti-Tj>O and the
transport proceeds from the hot to the cold surface. If ilG is negative
(exoergic), zeta is negative for Ti- Tj>O and the transport proceeds from
the cold to hot surface. Regardless of the reaction energetics, the direction
of transport and the transport rates can be controlled by control of the
differential surface temperature.
2.2.1.2 Flow effects. The effects of finite flow rate on the chemical
vapor transport can be summarized by simply adding current generators to
the equivalent circuit as shown in Figure 18. For small flow rates, the
current generators provide an additional driving potential,75
 Plasma Processing 221

where ¢ is the flow rate constant, Le. the reciprocal of the reactor residence
time. Now, even in the absence of a chemical potential difference between
surfaces i and j, net transport of A and B can take place. Flow-rate can be
used as a process control variable in a fashion which is beyond the simple
variation of reactant concentrations by variation of residence time (Sec.
2.1.4).

SELECTIVITY = edpOLy/ilpR/OXIDE
~ 250 50
:;:
i=
c.:I
200 .... >-
~I-
40
w en- • - PH
--'
w
150 w~
=1-
30
en cc.:l 0 - OXIDE
w 100 .... w
c~
20
= 50 :z::W
10
><
0
=-en

50 250 500 750 1000

FLOW OF Hel (seem)
Figure 19: (a) Effect of flow-rate on transport rates showing competition be-
tween flow-rate driven currents and chemical potential driven currents (after
Reference 75). The three curves label a,b,c correspond to chemical potential
differences, r,
greater than zero, equal to zero, and less than zero, respectively.
(b) Example of effect of flow-rate on selectivity of polysilicon etching over
photoresist and oxide (after Reference 75).

At higher flow rates, the flow current generator becomes nonlinear. By

using Kirchoff's law, which says that the sum of the currents into any node
must be zero (Le. conservation of flux), Zarowin derived the complete flow
dependence for the product current:
222 Semiconductor Materials

Iii - ~+~~ (17)

B - R T +~R T '

Both the driving potential difference and the reactive impedance are
modified by finite flow. At very large flow rates, the product current becomes
independent of both the chemical potential difference and the flow rate
and is limited only by the reactive resistance,
pV aU
IB( 00 ) -+ - - , - .- .. . (18)
kT Rl,Jal,J

Providing reactant production is fast, the rate is surface reaction limited.

The complete dependence of Is on flow rate is shown in Figure 19a,
where the product current normalized to its value at infinite flow rate, Is' is
00

plotted against the reduced flow rate, f = <pRd. It is the flow-rate relative to
the diffusive resistance which determines the overall transport rate. It the
diffusion rate of products and reactants between surfaces is slow, Rd large,
then the two surfaces behave somewhat independently and smaller flow-
rates are required to reach the high flow-rate limiting transport rate.
As shown in Figure 19a, three situations arise because of the compe-
tition between the flow-rate current generators and the chemical potential
difference between surfaces i and j (Figure 18 and Equation 17). Since d(2::
o in Equation 17, the flow-rate current generators can either work in
concert with or in opposition to the chem ical potential difference depending
on the sign of (and which surface is considered. The three curves, a, b, c, in
Figure 19a correspond to chemical potential differences greater than
zero, zero, and less than zero, respectively. Note that forthe case when «
0, the product current at surface i crosses zero at some finite flow rate, f o.
This means that below f o deposition occurs while above f o etching occurs.
At f o' no net transport occurs. If the chemical potential differences for
different substrate materials have different signs, this competition can be
used to great advantage in achieving large etching selectivities. For
example, when etching polysilicon in the presence of photoresist and Si0 2 ,
Zarowin 75 reports selectivities of >300: 1 (with respect to Si0 2 ) and >50: 1
(with respect to photoresist) at f o (Figure 19). This behaviorcan be explained
if the chemical potential difference, with respectto the counter conducting
electrode, is greater than zero for polysilicon but less than zero for
photresist and Si0 2 • At flow-rates below f o' deposition of Si occurs on the
photoresist and oxide. Since we have already concluded that (Si-(resist,oxide>O
this means that the deposition of Si onto resist and oxide must be endoergic
(see discussion after Equation 14 above). This example illustrates how we
must consider chemical vapor transport between not only the two electrode
surfaces but also the different parts of nominally the same surface.
 Plasma Processing 223

2.2.1.3 Loading. A commonly observed phenomenon in plasma pro-

cessing is that of reactor loading or the dependence of substrate transport
rates on substrate area (for example see Reference 79). Under conditions
where reactant generation is rate-limiting, transport between surfaces is
unimportant, and flow-rate effects are negligible, Mogab 80 showed that
loading can result from competition between reactant generation, homo-
geneous (Le. gas-phase) reactant loss processes, and reactant loss by
surface reaction. He showed that the reciprocal etching rate should be
linearly related to the substrate surface area:

(lga)

where dzi/dt is the film thickness rate of change (Le. the etching or
deposition rate), T is the gas-phase reactant lifetime, G is the gas-phase
reactant generation rate, p is the su bstrate density, M is the substrate gram
molecular weight, and No is Avogadro's number. The linear relationship ot
Equation 19 has been observed under a wide range of conditions. This
suggests that the assumptions inherent in Mogab's theory may be too
restrictive. The chemical vaportransport theory described above allows us
to examine loading effects when flow-rate effects cannot be ignored and
when reactant generation is not rate limiting.
Under conditions where the substrate transport rate is not limited by
reactant supply, the relationship between flow-rate, substrate surface
area and the transport rate is contained in Equation 17. At zero flow,

(1gb)

Note that Equation 19b also exhibits a linear relationship between the
reciprocal transport rate and substrate surface area. There is a direct
correspondence between the parameters in Equations 19a and 19b:

(20a)

G+-+ ~-~­ (20b)

(R~ + R d )

VM .
T +-+ --(Rl + lid) (20c)
p

The correspondence between a and (J' (Equation 20a) arises because

Mogab only considers etching at surface i and assumes deposition on i or
any other surface is negligible. When this is not so, a must be replaced by (J',
the su m of the forward and backward reaction rate constants. In Eq uation
20b, we see that the volume generation rate in Mogab's theory, G, corre-
sponds to generation by etching of "reactant" at surface j or product
224 Semiconductor Materials

transport current. In the case of zero flow, reactant A and product 8 are
transported in opposite directions from one surface to the otherwhen the
chemical potential difference, " is finite so that one surface acts as a
reactant generator for the other surface. Similarly, the reactant loss time
constant, 'r, corresponds to the sum of the reactive resistance at surface j
and the diffusive resistance (Equation 20c), both of which correspond to
reactant loss mechanisms. The important point is that despite the radically
different assumptions in the two theories, there is a correspondence of
sources and sinks such that the overall functionality remains the same.
Thus, observation of a linear loading effect is not sufficient to determine
the rate-limiting process.
At higher flow-rates, the relationship between reciprocal transport
rate and substrate area is no longer linear (see Equation 17). The loading
effect is predicted to go through a maximum as the flow-rate is varied.7 5
The sensitivity of a process to the numberofwaferswill depend on the flow-
rate in a non-linear fashion. Although some of the aspects of this theory
have been verified (e.g. that there is an effect of flow- rate on load ing), more
experimental data are needed to assess the range of validity of Equation
17. One difficulty in obtaining such data is the change in discharge
composition which usually occurs when the residence time is changed.
(see Sec. 2.1.4). This could result in a change in the rate-limiting step from
heterogeneous to homogeneous. Another complication may arise when
more than one reactant is important. This effect alone can give rise to a non-
linear loading curve. 81 If changes in flow-rate change the relative concen-
trations of these reactants fu rther deviations from the simple theory above
can be expected. To test the range of validity for the CVT equivalent cir-
cuit model, studies of spontaneous reactions, Le. without a plasma, would
be most appropriate.
2.2.2 Plasma Modified Chemical Vapor Transport. Until now we
have considered chemical vapor transport without considering the effects
of the plasma except to the extent that it modifies reactant concentrations
and diffusion coefficients. The major influence of the plasma, however, is to
modify the heterogeneous reaction rates by ion bombardment of the
surfaces. Although electron enhancement of heterogeneous rates has
been demonstrated 82 ,83, the sheath fields ordinarily are such as to repel
electrons and negative ions from device surfaces (see Sec. 2.1.2). In this
section we will see how this effect can be treated in a formal fashion within
the framework of chemical vapor transport theory.28,58,74,75 The following
section (2.2.3) will discuss the kinetic and microscopic origins of the
heterogeneous chemistry and plasma modifications.
In addition to the neutral reaction, Equation 10, we consider a parallel
ion-driven reaction: 74,75
Q'+

S + A+ + e- ~ B+ + e- ~ B (21)
(3+

This reaction is written in a formal fashion for simplicity. The ion need not
correspond to the neutral moiety nor must the product be an ion initially.
Electrons are included in Equation 21 merely to account for surface
 Plasma Processing 225

neutralization of the incident ion as well as production of a neutral product.

In fact, the following discussion is equally valid for energetic neutrals as
well as ions. The key concept in Equation 21 is that there are parallel paths
for production of the final products. Each path has a different rate constant
and activation energy. In terms of the CVT equ ivalent circu it, the energetic
ion (or atom) components correspond to resistors in parallel with the
neutral (or chemical) reaction resistors (Figure 18). However, this analogy
is of limited utility because the neutral component resistances in the
presence of ion bombardment are generally different from the case where
ion bombardment is absent. It is this change in the neutral component
resistance which is formally responsible for synergistic effects.
From Equation 11, the total reaction rate will be given by the sum of the
neutral and ionic components. If each rate is of the form 74

a = NAZexp(-EA/kT) (22a)

13 = NBZexp(- EB/kT) (22b)

(22c)

(22d)

the total rates are given by

at = af1 + fAexp(UA/kT)] (23a)

f3t = 13[1 + fBexp(UB/kT)]. (23b)

where Z is a preexponential rate factor, fA Bis the degree of ionization of A,B

and UA,B = EA,B - EA+,B+ is the difference between the neutral and ionic
activation energies.
Expressing the rate constants in this form allows us to explain a large
number of temperature studies where Arrhenius behavior has been ob-
served (Figure 20). For the case where the back reactions are negligible
and reactant supply is constant,74
-E A
In Ia = -- + In [A] + In [1 + fAexp(UA/kT)]. (24)
kT

For neutral dominated reactions, fA exp (U A/kT)< < 1 and the slope of Is vs.
1IT gives the neutral activation energy, EA. For ion-dominated reactions,
f Aexp(U A/kT»>1 and the slope gives -E A+. The fact that ion-dominated
reactions give smaller slopes (see Figure 20) indicates that the ionic
activation energy is smaller than the neutral activation energy. This is not
surprising considering that the ions have been accelerated to relatively
high energies by the sheath field. Another way to think of this activation
energy difference is to think in terms of effective temperatures. Because
the ion energy is superthermal, the effective temperature for the ion-
surface interaction is much largerthan forthe neutral-surface interaction.
226 Semiconductor Materials

Thus, the same change in absolute surface temperature will correspond to

a much smaller relative change for the ion-surface reaction than for the
neutral surface reaction.
In general, the effect of ion bombardment is to change the surface
reaction energetics.?4,75. To see this, it is more convenient to view the

1000 1000

(j)
I-
Z
:::;)
100 co
D'
S
w >
I-
l-
en
e(
D'
::J:
• z
w
I-
U
I-
~
w w
>
10 - • 10 i=
<
...I
W
D'
PCW/em 2) ECkeatlmole)
\J 0.89
o 0.40
28.4
30.6
••
6 0.15 38.8
• 0.62 34.5 •

1.8 1.9 2.0

10001T
Figure 20: Arrhenius plots showing effects of temperature and power density
on etch rates of InP and relative In atom emission intensity in an 0.3 Torr dis-
charge through e1 2 . The emission intensities are proportional to etch rate. Note
the smaller slopes for the higher power densities suggesting that ion-bombard-
ment is reducing the overall activation energy (from Reference 181 , courtesy of
V.M. Donnelly).
 Plasma Processing 227

parallel reaction (21) as modifying the chemical potential difference, orthe

degree to which the two surfaces differ from the same equilibrium state,
rather than simply a parallel reactive resistance. Consider the equilibrium
constants in Equation 13; the difference between Ki and Kj effectively
determines the chemical potential differences which drive the transport
processes. In the presence of parallel ionic reactions,

I + fAexp(UA/kT) }
I(t = l( . . (25)
. { 1 + f ucxp(U13 /kT)

When the reaction is in dominated,

. {-- [L\G-~U-k1"ln(fA/fB)}
!(t ~ exp (26)
kT '

where Kt is the total (i.e. ionic and neutral) equilibrium rate constant, ~U =
UA - Us' Thus, the effect of ion bombardment is a modification of the
effective free energy. Alternatively, we can think of the surface temperature
as being modified, T* = T/[1-(kTlnfA/fs+~U)/~G]. If ~U/kT>ln(fA/fEJ, the
effective temperature will be hotterthan the actual surface tem peratu reo In
terms of the effective temperature, transport still goes from "hot" to "cold"
for endoergic neutral reactions and from "cold" to "hot" for exoergic
reactions. The difference is that "hot" and "cold" depend upon not only
surface temperature but also ion energies,which can be controlled by
frequency, de bias, and pressure. Thus, we see the complementary nature
of ion-enhanced chemistry and thermally enhanced chemistry. Of course,
they are not the same thing. The product distributions are likely to be very
different since the thermal energy deposition will be statistically distributed
to the various degrees offreedom but the ionic translational energy may be
disposed in very specific ways.
2.2.2. 1 Anisotropy. Now that we formally understand the effects of ion
bombardment on heterogeneous reaction rates we can understand how
anisotropic patterning (see Sec. 3.4.2) is possible. In general we need to
consider transport between not only the two electrode surfaces but
among all surfaces. Specifically, when considering anisotropy, these
surfaces reside on the same electrode but are mutually orthogonal. The
surface which is perpendicular to the electric field lines will experience
more energetic ion bombardment than the surface which is parallel to the
electric field lines as long as the ion transport across the sheath is
anisotropic. This will occur at higher values of F/P (see Sec. 2.1.4 and
Figure 21).
The specific value of F/P which gives a particular anisotropy in the ion
transport directionalitywill depend upon the gas composition and operating
frequency(see Sec. 2.1). For example, the value of F/P, estimated from the
square root of the rf power densitY,28 required for a given degree of
anisotropy is shown in Figure 21. For a pure CI 2 discharge, where resonant
charge exchange can be very effective in reducing the ion energy aniso-
228 Semiconductor Materials

figure 21: Anisotropy as a function of the ratio of the square root of rf power
density to pressure (approximately equal to F/P) for three discharges illustrating
the effect of gas composition on the degree of anisotropy in the ion energy distribu-
tion (from Reference 28, reprinted by permission of the publisher, The Electro-
chemical Society Inc.) and the value of F/P required for a given anisotropy.
 Plasma Processing 229

tropy, the value of F/P required for a specific etch profile anisotropy is
substantially greater than for a discharge through 10% CI 2 in He, wherethe
chlorine cations do not charge exchange effectively with He neutrals. The
value of F/P required forthe same degre of anisotropy in an HCI discharge
is in between because only 50% of the neutrals, at most, will charge
exchange efficiently with CI+ ions.
How the ion transport directionality is transferred to the surface,
producing anisotropic features, will depend upon the relative neutral and
ionic reaction rates, i.e. the neutral and ionic activation energies, and the
ionic activation energy dependence on ion translational energy (Figures
21 and 22).28,74,75. For example, if the reaction is neutral dominated (r 0 = 1 in
Figu re 22), it does not matter how an isotropic the ion energy distribution is,
the etched profile will be isotropic (assuming that there is not a crystalline
orientation dependence to the neutral reaction rate).

lkT'r
2 T

---L
t kT+
---;:-r- ---.
(+::.: Ry::': Rx

!kT+r~ETCH
2
SURFACE/",
OR ELECTRODE

roQ:!l~

8= rD+ 11 - rJ eXP[-I3(~- )J
1

ION ENERGY ELLIPSOID ETCH RATE ELLIPSOID

Figure 22: Schematic illustration of correspondence between ion energy distri-

bution and etch rate profile. Anisotropy in the ion energy distribuion is repre-
sented by an ellipsoid; the ratio of the minor to major ellipsoid axes is governed
by the ratio of the random thermal energy, 3/2kT +, to the parameter p2, which
is a function of F/P and the collision cross section. The degree to which aniso-
tropy in the ion energy distribution is transferred into anisotropy in the etch
rate depends upon the ratio of the neutral to the ionic reaction components. For
example, two limiting cases are illustrated: when the neutral reaction is dominant,
ro = 1, the etch rate ellipsoid is circular or isotropic; when the ionic chemistry is
dominant, ro = 0, the etch rate ellipsoid is determined by the ion energy ellipsoid
(after Reference 75).
230 Semiconductor Materials

2.2.3 Mechanisms. Until now we have considered transport phe-

nomena in plasma processing but have said little about the microscopic
mechanisms associated with heterogeneous chemistry. What are the
reactants and products and how are reactants converted to products? A
tru ly quantitative, microscopic mechanism shou ld allow us to calcu late the
rate constants Q and f3 as a function of temperature. Such detailed mech-
anisms are yet to be developed for surface reactions of interest in plasma
processing. The most well studied system is the etching of Si byfluorinated
and chlorinated compounds such as F, F2 , C1 2 , and XeF 2 • First, we will
consider the fluoride etching of Si in the absence of ion bombardment.
When we consider the effects of ion bombardment, we will focus our
attention on the etching of Si by chloride systems since chlorides do not
etch Si spontaneously at room temperature. Therefore, this system will be
uncomplicated by the presence of a spontaneous, neutral component and
the ion component will be isolated.
2.2.3.1 Spontaneous etching of Si by fluorides. Many fluoride
compounds etch Si spontaneously. The most well studied reactions to
date, however, are those with F atoms, XeF 2' and F2' Flamm et al. have
studied these reactions at relatively high pressures as a function of temper-
ature. 84 -87 F atoms are produced upstream from a Si surface by passing F2
through an rf discharge at 14 MHz. The F atom concentration is measured
above the Si substrate by titration with molecularchlorine. 63 ,88In this fashion,
the etch rate dependence on F atom concentration can be determined. In a
similar fashion, except without the discharge upstream, the Si etch rates
with molecular F2 and XeF 2 are also measured. The reaction with XeF 2
does not exhibit an Arrhenius temperature dependence over the range of
temperatures and pressures studied (Figure 23) but rather shows a
minimum because of competition between reaction and reactant desorp-
tion. At low temperatures, XeF 2 reactant adsorption occurs more readily
but the reaction rate is slower because of the finite activation energy. Thus,
as the temperature is increased, the etch rate first decreases as reactant
desorbs and then increases as activation occurs (Figure 23).
What happens when fluorides come in contact with a Si su bstrate? The
uptake of F2 by a Si surface exposed to F2 can be seen very clearly in the
experiments performed by Winters et al. 8 A thin film of Si was deposited
onto a quartz crystal microbalance and then exposed to F2' The change in
the resonant frequency of the quartz crystal was used as a measure of the
change in the mass of the film (Figure 24). At first there is a mass increase as
the SiF x surface species are formed. Continued exposure leads to etching
and a subsequent mass decrease. Using Auger electron spectroscopy and
x-ray photoelectron spectroscopy, Chuang 89 showed that both XeF 2 and
SiF4 dissociatively chemisorb on Si at room temperature to give an "SiF 2
like" su rface. Note that the reaction of SiF 4with the surface is equ ivalent to
the back reaction in Equation 10 discussed above (Sec. 2.2.1). More
recently, McFeely et a1. 90 ,91 have shown that not only SiF 2 species are
present but also SiF x ' where x=1 and 3, when Si is exposed to XeF 2 •
Moreover, these authors conclude that SiF 2 is a relatively minor species
compared to SiF3 and SiF. However, these authors also report that the
crystalline orientation affects the relative concentrations of the SiF x
 T,K
420 3XO 340 300 260

R = [/-L-min- I ]
1000
P =- [Torr]

~
~

~'Q..
100

"'U
"- n;-
-,-' " (J)

"", 3
, !l)

" , "'U
" , ~
o
10' , , , , , , ,
, t ' ,
C1
I , , ,
CD
(J)
1.6 l.M 2.0 2.2 2.4 2.6 2.M 3.0 3.2 3.4 3.6 3.H 4.0
(J)
3 1
lIT x 10 , K- ~
<0

Figure 23: Etch rate of Si when exposed to XeF 2 as a function of temperature (solid curve and circles). The etch rate minimum
is ind icative of competition between thermal activation of the etch rate and thermal desorption of the reactant (from Reference I\)
c.v
87, courtesy of V.M. Donnelly). The dotted line corresponds to the etch rate of Si when exposed to fluorine atoms.
232 Semiconductor Materials

species under low dosage conditions. At higher dosages when steady-

state etching has been achieved, a substantial amount of fluorine appears

25 ----.----.....-----r---~-___r--_r_-__..,._____,
~ F2 ADMITTED TO SYSTEM
20

15
1
15.5 Hz
N
= 15
[6 X 10 F ATOMS/cm 2]
10
c:I

j
5 SPONTANEOUS
ADSORPTION AND FlUORIDE----{-ETCHING
GROWTH ON Si OF Si BY F2
O'--_---L__~__--'-__--'-__ ~~
_L.__ _...&.___ _

o 2 4 6 8 10 12 14
t (min)

Figure 24: Quartz crystal microbalance response when Si is exposed to F2 • The

decrease in frequency is indicative of an increase in substrate mass (from Refer-
ence 8, reprinted with permission of the American Institute of Physics).

as SiF4 which is most likely trapped beneath the surface. 92 This observation
suggests strongly that the spontaneous etching of Si by XeF 2 proceeds
primarily by slow, sequential fluorination of Si followed by diffusion through
the interface layer and desorption of product SiF 4 . While this mechanism
wou Id be consistent with the formation of Si F4' another mechanism may be
active in producing other products.
What products are formed in the reaction of Si with fluorides? The only
stable product which has been observed downstream has been SiF 4 but
this does not mean that it is the only desorption product. Flamm et al.
addressed this issue by examining the chemiluminescence which accom-
panies the etching of Si by fluorides. 84 -86 They attributed this emission to
the gas-phase reaction sequence:

F -f- SiF 2 --+ SiF; (27a)

SiF; --+ SiF 3 + hv. (27b)

The dependence on temperature of the chemiluminescence intensity

matched that of the Si etch rate suggesting that both reactions resulted
from the rate-limiting reaction of F (or F2) with a fluorinated Si surface to
produce SiF 2 radicals:
 Plasma Processing 233

F + SiF x,surf -+ SiF 2 t. (28)

It is not obvious from these studies whether or not SiF2 is the dominant
reaction product. Moreover, since Flamm et al. did not have an unambiguous
means of measuring the SiF 2 radical (their conclusions rest upon their
assignment of the diffuse chemiluminescent spectrum), it was not certain,
initially, that SiF 2 was indeed a reaction product. However, in a molecular
beam study of the reaction of Si with F atoms, Vasile and Stevie 93 measured
directly the neutral species desorbing from the surface by mass spec-
trometry. By comparing the mass spectral cracking pattern of SiF4 to that
obtained from the products of the surface reaction, they concluded that
15-30% of the reaction products were radicals, presumably SiF 2, and the
rest were SiF 4, More recently, Winters and Houle 94 measured in a similar
fashion the neutral products from the reaction of XeF 2 with Si. They
compared their results to not only the SiF 4 but also the SiF2 cracking
pattern and were able to determine more precisely the product branching
ratios for this reaction. They concluded that the dominant product is SiF 4
(85%) with the remainder of the product distribution comprised of SiF2and
SiF. These results are consistent with those of Vasile and Stevie. Any
microscopic mechanism proposed for the etching of Si by fluorides must,
at the very least, account for these various product yields.
Two reaction schemes have been proposed for the spontaneous
etching of Si byfluorides. Flamm and Donnelly4 have proposed a concerted
reaction model for the F atom etching of Si. In this model, the rate-limiting
step is formation of an SiF 2 radical physisorbed on an "SiF 2 'ike" surface.
This radical can desorb directlytogive the SiF2products observed or it may
react rapidly to form volatile SiF3 or SiF 4, This model accounts for the
identical temperature dependences for the Si etching rate and the SiF3*
chemiluminescence. The reaction is said to be concerted because the
arrival of reactant and formation of a new Si-F bond is coordinated with the
departure of SiF x products.
Another mechanism has been proposed recently by Winters et al. B
They noted that the reaction of F with Si should be similar to the reactions
°
of and 02 with sem iconductors and metals. The latter is believed to occu r
by the so-called Mott-Cabrera mechanism, where an oxide surface is
formed rapidly upon exposure of the clean surface to an oxygen environ-
°
ment. Adsorption of or 02 onto the oxide layer is followed by formation of
oxygen anions by tunneling of electrons from the metal substrate through
the oxide overlayer. The electric field produced by the charge separation
of anions and holes results in field-enhanced diffusion of the anions
through the oxide layer and growth of the oxide layer at the metal-oxide
interface. Winters et al. proposed that the F-Si interaction should proceed
in an analogous fashion with the only difference being that the silicon
fluorides are volatile so that once a new fluoride layer is formed below the
initial fluoride layer, the initial layer desorbs or the underlying layer
percolates out. This mechanism is consistent with the results of McFeely
et al. mentioned above. 90 -92
234 Semiconductor Materials

It seems plausible that both concerted and Mott-Cabrera mechanisms

may be important and that in both cases the rate limiting step giving rise to
the observed activation energ ies mig ht be formation of the su rface fl uorides.
The lower, unsaturated fluorides might be formed by a concerted reaction
whereas the fully saturated fluorides might result from field-assisted
diffusion of F- into the bulk.
2.2.3.2 Ion assisted etching. What hapnens when energetic ions are
simultaneously impingent upon the surface? Coburn and Winters 82 first
demonstrated the synergistic nature of ion-neutral surface reactions by
exposing Si, deposited onto a quartz crystal microbalance, to a XeF2
neutral beam and an Ar+ ion beam: the etch rate with both beams was
greater than the sum of the individual ion sputtering and spontaneous
chemical rates.
Since the pioneering experiments of Coburn and Winters, there have
been many ion beam/neutral beam studies of etching reactions. 8,53-55,94-
123 Considerably more detailed data have been obtained on ion-assisted
etching mechanisms from these experiments than from corresponding
experiments on just the neutral reactions. A typical experimental configur-
ation is shown in Figure 25. An ion beam of variable energy and flux is
directed to a solid substrate which is simultaneously subjected to a neutral
flux, either from a molecular beam or from a small background pressure.
The ion sources are usually differentially pumped to prevent back diffusion
of the radical into the ion source. The neutral flux is varied byeithervarying
the background pressure or by varying the intensity of the beam source.
Some workers have used substrates deposited onto quartz crystal micro-
balances in order to measure etching and deposition rates directly by
measuring the change in the resonant crystal frequency.55,82 When the ion
flux is measured, usually with a Faraday cup, etch rates can be converted
directly into substrate removal yield per incident ion. Yields as high as 25
have been observed in the Ar+ ion-assisted etching of Si by XeF2 (see
Figure 26).
Several studies have been done where the nascent neutral products
are detected using a mass spectrometer housed ina differentially pu mped
chamber butwith a direct line-of-sight to the reacting surface. 53 -55 ,94,107,114-
116,121,122 Mayer and coworkers 109,112 have used Auger electron spec-
troscopy to monitor in real-time the instantaneous reactant coverage in
the etching of Si by CI 2/Ar+. Some studies have also been done where the
secondary ions emitted, e.g. SiCI+ and SiCI 2+, are detected and energy
analyzed. 119,12o The two systems which have been studied most extensively
are the ion-assisted reactions of silicon byfluorides and ch lorides, although
there has been some work also on III_V95 ,99,101,106,111,122 and Si0 2 chemis-
try.96,10oWewill focus primarilyon the reactions between Si and CI 2sincethere
have been more detailed studies of this system than any other and the
reaction is ion induced at room temperature. We will also discuss briefly
the findings in the fluoride experiments since the neutral chemistry is best
characterized there (see above).
Although many measurements have been made on the Si/CI 2/ion
system, the results obtained often appearto be contradictory. The reasons
 Plasma Processing 235

TOP VIEW

VACUUM CHAMBER

RETRACTABLE~ ION GUN

SHUTTER

5cm

DEFLECTION
PLATES
APERTURE
PLATES

QUADRUPOLE MASS - - - J - - + - . PUMP

SPECTROMETER

Figure 25: Typical ion-beam apparatus used in ion-enhanced etching experiments.

Primary and secondary ions are deflected away from the mass spectrometer so
that only neutrals are detected (from Reference 121, courtesy of S.C. McNevin).

forthis are not entirely clear but one problem is certainly the wide variety of
experimental conditions that have been employed (Table 2). Another
possible source of difficulty is the reliability of some of the numbers
summarized in Table 2. In particular, the neutral fluxes reported in the
neutral beam experiments are in every case estimated by assuming
certain characteristics of the expansion. Inon Iy one case is the neutral flux
calculated in this way compared to other independent measurements. 112
With these caveats in mind, let us consider what these experiments tell us
about the mechanisms which are important in ion-assisted etching.
First of all, it seems clear that under certain circumstances the mech-
anism for ion enhancement differs fundamentally from simple physical
sputtering. The clearest evidence forthis comes from the work by Mayer et
236 Semiconductor Materials

25
Ne+ AND XeF 2
iF 20
~
en
:IE
.-
C)

c 15
§..
=
~

;: 10
==
y
t-
~

u; 5
Ne+ AND Cl 2

0
0 10 20 30
GAS FLOW RATE (10 15 MOLECULES/SEC)

Figure 26: Si etch yields vs. XeF 2 and CI 2 neutral flux when a 1 kV Ne+ion beam
is simultaneously incident upon the surface (from Reference 97).

Table 2: Ion Beam/Cl 2 Etching of Si

Heference Cl 2 Flux Ion Flux Ion Energy Area °iDc( .) Substrate

(cm- 2s- 1) (cm- 2s- 1) (keV) (cm 2 )

97,98 0-6 X 10 16 3-6 X 10 13 0.5 0 Thermally

Evaporated
16 15
104 5 X 10 1.7- 6.6 X 10 0-0.4 NG 0-75 Si (100)
54,55 [) X 10 15 1.5 X 10 13 0..1-0.9 Broad >0 Single crystals
Evaporated
109,112 0-6 X 10 16 0.06- 3 X 10 15 0.4-0.9 2.8 0-60 Si (100)
CVD undoped poly-Si
16 14
53, 114".116 0.5- 10 X 10 2 X 10 0.15 60 NO

119,120,123 0- 2.4 X 10 14 1 X 10 13
0.06 0-60 Si (l00)

121 0.02- 4 X 10 14 0- 4.5 X 10 14

0.3-3 0.05 45 p-type Si (100)

a1. 109 ,112 and Okano and Horiike 104 who measured the dependence of the
Si etch yield on the ion beam angle of incidence, OJ' Mayeret al.'s results are
reproduced here in Figure 27. For the case where no neutral reactant is
present and only a rare gas ion is incident upon the surface, the yield peaks
near 60° as expected for a purely physical sputtering process (see
Reference 1 and references therein). However, when CI 2 is admitted to the
system, the etch yield is observed by both groups to peak at normal
incidence (0°). At this angle the ion energy tends to be dissipated into the
bulk via a collision cascade or spike. 124 After correcting the angular
dependence for the physical sputtering component (determined by using
the Ar+ beam alone), Okano and Horiike 104 found the etch yield to follow a
cos OJ dependence, which they attributed to an ion-induced chemical
 Plasma Processing 237

1000
N
EI~E
u

o~l~ 800 400eV

. 6

-
Ct>
Cf)
600

200

o 10 20 30 40 50 60
ANGLE, DEG
Figure 27: Si etch yield vs. Ar+ ion incident angle and ion energy when Si is ex-
posed simultaneously to neutral el 2 (from Reference 109, reprinted with per-
mission of the American Institute of Physics).

reaction or chemical sputtering. 105 A distinction is made between chemical

sputtering and spontaneous etching. CI 2 does not etch Si at room temper-
ature (Reference 53 and references therein) so the reaction is not ion-
assisted as in the fluorine case but rather ion induced. The total etch yield
is a superposition of the physical and chemical sputtering components.
A useful means for gaining insight into the nature of ion-induced
etching is to measure the energy distributions and identities of desorbing
products. Smith et a1. 54 ,55 measured products mass spectrometricallyfrom
the Si/CI 2 /ion reaction. From the dependence of cracking patterns on
ionizing electron energy, they deduced that some of the desorbing species
are radical, unsaturated chlorides, probably SiCI 2 . However, they were not
238 Semiconductor Materials

able to specify how much of the product yield is comprised of these

radicals. Kolfschoten et al. 114 find that most of the products in their
experiments are radicals, SiCI 2 and SiCI. By comparing the cracking
patterns of SiCI 4 with those obtained in their ion beam experiments they
find that only ~ 1 % of the products are SiCI 4. McNevin and Becker 12 1, on
the other hand, found virtually no evidence for radical products and by
similar reasoning to that employed by Kolfschoten et al. deduced that the
primary product is the tetrachloride.
Both Kolfschoten et al. and McNevin and Becker measured product
time-of-flight distributions. Assuming there are no delays due to surface
residence ti mes, these distributions can be converted di rectly into product
kinetic energy distributions. Kolfschoten et al. did precisely that and found
that both the mono- and di-halide products showed a bimodal energy
distribution (Figur~ 28). The low energy component could be explained by
a Maxwellian distribution at room temperature; the high energy component
could be explained approximately using the collision cascade theory of
Sigmund for physical sputtering processes, 124 although a high temperature
Maxwellian provides a better fit to the data. They conclude that Si is
primarily physically sputtered by bombardment with Ar+ despite the
presence of a simultaneous flux of reactive C1 2. It should be noted that
Kolfschoten's experiments are biased toward detection of the physical
sputtering component since their angle of incidence is 60°. Although
McNevin and B'ecker's time-of-flight distribution differs from a room-
temperature Maxwellian, to account for the deviation one would have to
use a sub-thermal distribution. Alternatively, a distribution of surface delay
times might be important in their experiments: the surface exposed to the
ion beam in these experiments was only a small fraction of the total area so
that surface diffusion of adsorbed chlorine from adjacent non-bombarded
regions may have been important. Since ion bombardment will desorb
CI, 112 large area exposu re, such as used by Kolfschoten et al. and Smith et
aI., might lead to a chlorine deficient surface, production of unsaturated
SiCl x radicals, and physical sputtering. Small area exposure, such as used
by McNevin and Becker, might lead to the production of surface delays,
saturated SiCI 4, and thermal desorption. Since McNevin and Becker's
experiments were done at f)j=45°, the primary difference between their
work and the work of Kolfschoten et al. and Smith et al. appears to be the
beam area. An experiment where the ion-bombarded area is varied relative
to the total surface area exposed to chlorine would be very useful in
resolving these discrepancies.
The effect of the neutral flux on the etch yield per ion has been studied
by several groups.97,98,109,112,121 In this case there is general agreement
and the data shown in Figure 26 are typical. Gerlach-Meyer98 interpreted
these data in terms of production of an excited surface species or reactive
"site" with finite lifetime. At low flux, the yield increases linearly121 because
the reactive "sites" created by ion bombardment are greater in number
than the available reactants and so the reactant arrival rate becomes rate
limiting. At higherflux, the yield saturates becausethe neutral reactant is in
excess relative to the rate of "site" production. Mayer et al. 112 showed,
however, that the flux dependence observed could be accounted for
 Plasma Processing 239

10 3

-
::i
d
w
-0
""
Z
-0

la'

100 ""---"-_ _04--_-----...l.--~1 -----'_ _.....

1 _
102 10-1 100
ENERGY (eV) ~

Figure 28: SiCI 2 product translational energy distribution, dN/dE, from the Ar+
ion induced reaction of chlorine with silicon (from Reference 114, reprinted
with permission of the American Institute of Physics).

entirely by considering the competition between ion-induced desorption

of surface chlori ne and sticki ng of ch lorine from the incident neutral beam.
The existence of a surface excited state was not necessary to explain the
neutral flux dependence. Mayer's model is consistent with etch yields
measured over a wide range of ion flux as well as neutral flux. The critical
parameter is the ratio of the two, liP. The Si etch yield was found to have the
following dependence upon coverage and ion current:
I{ = mf3BI + 6(1 - 0)1, (29)

where R is the Si etch yield, m is determined by the molecularity of the

reaction (1/4 for formation of SiCIJ, f3 is the fraction of Si leaving the surface
as a chloride, 8 is the fraction of unchlorinated Si sputtered directly by the
ion, I is the ion flux, and () is the chlorine surface coverage given by,

o=: 1._ (30)

1 + <I>l/P'
240 Semiconductor Materials

where cI> is the ratio of desorption to adsorption coefficients and P is the

neutral flux to the surface. At high ion to neutral flux ratios, () goes to zero
according to Equation 30. This is consistent with the chlorine surface
coverage as measured using Auger electron spectroscopy (Figure 29).
From Equation 29, we see that with low surface coverage (1cI>/P >> 1), the
etch yield reduces to the sputtering yield (R -+ 81) as observed (Figure 26).
At low ion to neutral flux ratios, the surface concentration of chlorine
saturates near unity (see Figure 29 and Equation 30), and the etch yield
saturates at a value dictated by the ion flux and chemical sputtering
coefficient,{3(Figure 26),R-+ m{31.

1. 0 r--------,----.-~-----,------__r___.

60.05 rnA cm- 2

00.10
'fCJ 0.15
00.20

w
..
C)
<X
a:
w
>
o
(.) 0.5
w
z
a:
o
-J
:I:
(.)

o 0.1 0.2 0.3 0.4

ION TO NEUTRAL (ATOM) RATIO

Figure 29: Surface coverage of chlorine on Si as a function of the relative fluxes

of ions and neutrals to the surface. The measurements were made by Auger elec-
tron spectroscopy while the sample was simultaneously exposed to an Ar+ ion
beam and a molecular CI 2 beam (from References 109 and 112, reprinted with
permission of the American Institute of Physics).
 Plasma Processing 241

So we see that the ion-induced reaction of Si with CI 2 can range from

physical sputtering to chemical sputtering depending on the relative
fluxes of ions and neutrals, or more precisely, the surface concentration of
chlorine, and the angle of incidence, energy, current density, and mass of
the ion beam. The reactant surface coverage may affect not only the
overall rate but also the product distributions. Chemical sputtering is
favored at normal incidence where the ions are most effective in disrupting
the surface structure and driving chlorine into the bulk by recoil implantation.
One part of the mechanism would seem to be enhanced production of
chlorides by ion bombardment. These volatile chlorides may then sponta-
neously desorb but ion bombardment could assist in this process also.
Several explanations forthe enhancement of heterogeneous reaction
rates by ion bombardment have been offered in the literature: 4 ,8,98 (1)
surface damage; (2) desorption or clearing; and (3) surface excitation. It
seems likely that all of these explanations have some validity and the
dominant mechanism, if there is one, will depend very much on substrate
and gas as well as operating conditions such as the ratio of neutral to ion
flux. For example, in the ion-induced reaction of silicon with chlorine most
of the evidence above poi nts to ion-assisted desorption and ion-en hanced
product formation. The production of unsaturated chloride radicals with an
energetic translational energy distribution is suggestive of sputter desorp-
tion; enhanced reaction at normal incidence suggests ion-induced damage,
ion-induced surface excitation, and/or ion-assisted radical formation on
the surface. In the case of silicon etching byfluorine, on the other hand, the
ions probably help to desorb subsurface SiF 4 as well as sputter the
partially fluorinated species residing on the surface. But ion-induced
surface damage is probably not an important mechanism because the
spontaneous reaction itself causes substantial surface damage. In a
plasma, where deposition of etch inhibiting material may also be taking
place, ion bombardment could assist in the desorption of this material as
well (see Sec. 3.4.2).

2.3 Modeling
We have discussed plasmas and plasma-surface interactions but it
remains to put everything together in order to describe the system as a
whole. The interaction between various parameters, which will be further
discussed as it pertains to particular applications below, makes the task of
a global model extremely difficult. The approach taken recently by Edelson
and Flamm 125 and by Kushner 126 is to select the most important homogen-
eous reactions and solve the corresponding set of differential equations.
In many cases, the rate constants are unknown and approximations must
be made. In particular, the dependence of a rate constant on temperature
and/or molecular internal energy distributions is unavailable. As if this
alone were not problem enough, no model to date has dealt in a self-
consistent fashion with the spatial inhomogeneities in concentrations and
energy distributions for both neutral and charged species let alone temporal
variations in these quantities.
242 Semiconductor Materials

Another approach to modeling plasma chemistry is to perform compu-

tational "experiments." For example, the energy distributions of ions and
electrons can be calculated by the Monte Carlo method if collision and
reaction rate constants are known along with the local electric field and
any concentration gradients (for example, see References 127 and 128).
This method has the advantage of simplicity and speed but suffers from
being inherently non-self-consistent. However, it could be very useful in
providing insights into how energy distributions and particle flux can be
modified by various plasma parameters.
Much more theoretical and diagnostic development needs to be done
before we can hopeto have even asemiempirical model of some predictive
value. One approach along these lines has already been reported by
Mocella et al. 129 They employed the Response Surface Method. In this
method, a kinetic model relating plasma operating parameters to some
desired outcome, such as etch or deposition rate, is assumed. Given the
form of this model, a minimum number of experiments is determined, in a
statistical fashion, which will optimally determine the model parameters
and, therefore, define the multi-dimensional parameter space. Once this
space is so defined, the effects of any choice of operating parameters can
be determined. Of course, the problem in this procedure is knowing
whether or not the model which one has adapted is sufficiently accurate to
provide predictive power.

3. PLASMA ETCHING

3.1 Introduction
3.1.1 Outline. This section deals with how plasmas are used in
etching processes for microelectronic device fabrication. The method of
patterning, using lithography and etching will be outlined. Etching process
parameters and goals will be defined along with methods of affecting
these parameters. Conventional commerical etcher designs are presented
and examples of specific applications to Si and III-V devices are given.
3.1.2 Pattern Definition and Transfer. The formation of a layer of
material which is only present in predefined areas can be accomplished by
two techniques, lift off and etching. Lift off is accomplished by first defining
a polymer lithographic mask which is the negative of the desired pattern
(see for example References 130 and 131). Figure 30a illustrates the
process. The mask is commonly referred to as photoresist, if optical
lithography is used to define the polymer. Just "resist" is a more general
term which encompasses polymers defined by any exposure tool including
x-rays or electron beams. The layer is then deposited and the wafer is
placed in a solvent which dissolves the resist, removing any part of the
layer on top of the resist. Lift off can only be used when the layer deposition
process does not exceed the temperature at which the resist begins to
degrade, 200-300°C. This section will not deal at all with lift off techniques
but will concentrate on plasma etching.
Etching requires that the layer be first deposited and a positive resist
mask be defined on top. The wafer is then exposed to an environment
 Plasma Processing 243

DEFINE RESIST DEPOSIT LAYER

I)

~
SUBSTRATE
R_E_S_IS_T_
",-I
DEFINE RESIST
SUBSTRATE

DEPOSIT LAYER

2)

ETCH LAYER

3)

STRIP RESIST
STRIP RESIST

3) 4>

(0) (b>

Figure 30: (a) This sequence illustrates pattern transfer using the lift off tech-
nique. (b) This sequence illustrates pattern transfer by etching.

which removes the layerwhere it is not covered by the masking resist. This
process is illustrated in Figure 3Gb. This figure shows shematically that
during the etching process the mask may also be partially removed.
In the following sections we will discuss chemically active plasmas,
however, etching also occurs on exposure to a chemically inactive plasma
where an inert feed gas such as argon is used. Here material erosion or
sputtering 132 is caused by bombardment with positive ions accelerated
across the sheath. A small sputtering component is present in all plasma
etching processes. The etching process known as ion beam milling 133
removes material by sputtering but the ionization and acceleration of the
beam are performed separately, away from the etching material or target
as it is called.
244 Semiconductor Materials

3.1.3 An Illustration of Plasma Etch Patterning. Exactly how

plasma etching techniques are used in I.C. fabrication is illustrated in
Figure 31. This cross sectional view shows part of a planar MOS silicon
transistor whose formation required four etching steps which are sche-
matically shown in Figure 32.
First, gate and source and drain (GASAD) "windows" are etched down
through an isolating field oxide (FOX). Figure 31 only shows a portion of a
GASAD region so no FOX is visible. A thin gate oxide (GOX) is then grown in
the GASAD reg ion and the gate material is deposited over the whole wafer.
In this case the gate is low pressure chemical vapor deposited polycrystalline
silicon (LPCVD poly-Si). The gate area is lithographically masked and any
poly-Si outside this area is etched away. Phosphorus doped LPCVD Si0 2 ,
used as another dielectric isolation, is deposited and then smaller contact
windows, or vias, are etched down to the transistor gate, source and drain.
Only the contact to the source is shown in Figure31.Acomposite conducting
structure of doped LPCVD poly-Si and aluminum is then deposited, defined
and etched to complete the structure.
This illustration shows how the sequence of deposition, lithographic
definition and etching are used to build planar structures. In this case four
etching processes are requiredforthermallygrown Si0 2 , doped LPCVD Si,
doped LPCVD Si0 2 , and doped LPCVD poly-Si/AI composite. The remainder
of Sec. 3 discusses why plasma etching processes are often chosen for
these and other etching applications, what equipment is typically used,
what the general requirements are for such processes and some further
details specific to each process.

3.2 Equipment
3.2.1 Parallel Plate Etchers. The first technologically significant
plasma etching reactor is typically referred to as a parallel plate etcher. It is
configured essentially like the example shown in Figure 1. A round, rf
driven electrode is positioned parallel to another round, grou nded electrode
on which multiple wafers are placed. 134 This arrangement can also be
utilized for plasma-enhanced deposition and is discussed in that regard in
section 4.2.1. Similar considerations discussed there regarding pumping
gases and safety also apply here.
The dc sheath potential, across which ions are accelerated, is deter-
mined by among other things the area ratio discussed in Section 2.1.2.2.
Since the reactor itself is grounded the rf driven area is smaller than
the total grounded area. This leads to relatively low acceralerating
potentials across the ground electrode sheath. For historic reasons etching
in this type reactor at relatively high gas pressure (0.1-2 Torr) is referred to
as plasma etching (PE).
PE is frequently characterized by high selectivity (see Sec. 3.4.4) and
isotropic etching (see Sec. 3.4.2). The dominant mechanism in PE is
thought to be spontaneous etching by chemical species generated in the
plasma with only a small contribution from energetic ions. This is because
the F/P ratio is low.
A more recent embodiment of this geometry is shown in Figure 33.
 "'U
Q)
en
3
m
.,
"'U
o
()
CD
en
en
::J
co

Figure 31: A cross section transmission electron micrograph of an MOS transistor (micrograph courtesy of R.V. Knoell, AT&T
r\)
Bell Laboratories). ~
01
 GROW THERMAL FIELD OXIDE DEFINE AND ETCH GASAD REGIONS tv
~
0'>

en
CD
2 KIIl1fEITillITJ r:i~jIII~jri~fjt~~trmmffimtm
3
SUBSTRATE ~GATE OXIDE 0"
o
:::J
0-
c
(')
DEPOSIT GATE MATERIAL DEFINE AND ETCH GATE ro+
o
~

~
4 :rftffttfi~iftt~~{J WlJJ Ht~jt~ttt~}}~:~:~~~~~~tttf~~jf:tttt~r~~: OJ
ro+
CD
~

DEPOSIT AND FLOW ~

DEFINE AND ETCH WINDOWS en
----
OR PLANARIZE INSULATOR
~~~-~-

DEPOSIT METALLIZATION DEFINE- AND ETCH METALLIZATION

7 8:~ll'

Figure 32: A sequence of patterning and etching to form an MOS transistor.

 Plasma Processing 247

Because the rf power can be introduced into the system in a variety of

ways, it is known as a "flexible" etcher. 135 It can be operated in the PE mode
by connecting B in Figure 33 to an rf power supply through an impedance
matching networkand connecting A to ground. The opposite configuration
where B is grounded and A is rf driven is commonly referred to as either
reactive ion etching (RI E) or reactive sputter etching (RSE). Here the area
ratio is the inve~~e of that in the PE configuration. This mode is characterized
by relatively low plasma pressures, 5-50 mtorr, high ion accelerating
potentials, lower selectivities and frequently anisotropic etching. Now ion
assisted mechanisms, discussed in section 2.2.3.2, contribute more to the
etching process because of the higher F/P value. The flexible etcher can
also share rf power between A and B in the hope of blending etching
characteristics to fill the requirement of a specific process.
3.2.2 The Hexagonal Cathode Etcher. Another RSE mode etcher
of technological significance is the hexagonal cathode etcher shown in
Figure 34. 136 Wafers are mounted onto the six faces of a hexagonal prism
(H EX) which is the rf driven electrode or cathode. The whole metal vacuum
bell jar then acts as the grounded electrode. Here an even larger difference
in area between the two electrodes results in a large dc bias on the HEX
which in turn produces large ion accelerating potentials. The size of the
HEX allows many wafers to be etched simultaneously. Its almost cylindrical
geometry causes relatively uniform rf fields and therefore uniform etch
rates over all wafer positions (see Sec. 3.4.3).
Parallel plate and H EX etchers are both mu Itiwafer, or batch, etchers.
An important disadvantage of these types of etcher is that they are usually
manually loaded while the chamber is vented to atmosphere. Venting the
chamber allows the adsorbtion of contaminants, such as water vapor, onto

B
GAS IN

WAFERS

TO
VACUUM A
PUMP

Figure 33: A schematic illustration of a parallel plate etcher which can be oper-
ated in the PE or the RSE mode (from Reference 134, © 1981 IEEE).
248 Semiconductor Materials

METAL
VACUUM
BELLJAR

WAFERS MOUNTED
TO CATHODE

R.F. DRIVEN
HEXAGONAL
CATHODE

GAS IN

TO
VACUUM
PUMP

III

Figure 34: Illustration of a HEX etcher showing half of the twenty-four wafer
positions.

the chamberwalls which can change etching parameters. For example, it

was shown in the case of fluorine based etching of Si0 2 , that water vapor
dramatically affects the etch rate. 137 This causes differences in measured
etch rates from run to run depending on the relative humidity in the room,
the time the chamber is left open and the time the system is pumped before
etching commences. Manual loading also increases the chance of particles
falling onto wafers which can lead to defects (see Section 3.4.6).
3.2.3 Single Wafer Etcher. Ways to avoid the two problems
mentioned in the last section are to automatically load the sytem through a
load lock. A load lock is a chamber between the etching chamber and
atmosphere, which accepts wafers from atmosphere, is pumped out, and
then delivers wafers to the etching chamber. In this way the etching
chamber is only rarely exposed directly to atmosphere. For simplicity, and
added process control these systems typically etch only one wafer at a
time. Single wafer etchers operate with parallel plate geometry either in
the PE or RSE mode. Some additional trade-offs between batch and single
wafer etchers are discussed further in Secs. 3.4.3 and 3.4.4.
 Plasma Processing 249

3.3 Endpoint Detection

For a typical process, etching proceeds until the nominal film thickness
is etched away. The process then continues until a predetermined "over-
etch" time has elapsed. This overetch must be long enough to satisfy the
etch rate uniformity in the system so that the layer has, in fact, been
removed at every wafer position. It must also be short enough so that the
underlying layer is not unacceptably eroded in areas exposed during the
total over-etch time. An accurate determination of the nominal time to
completion, before overetch, is desirable. This time can be obtained by
visually observing the wafer through a viewing port, or determining the
etch rate of the process, and calculating the nominal etch time. The latter
method depends totally on the reproducibility of the process. Betterways
to reliably determine the nominal etch end point are to measure some
characteristic change in a plasma parameter or optical property of the
wafers.
3.3.1 Voltage/Power. A simple example of endpoint determination
is to hold the rf powerconstant and monitor the dc bias potential. Frequently,
if large areas on the wafer are not masked and etching, the dc bias will
measurably increase or decrease when the etch is completed and the
underlying layer is exposed to the plasma. There are two possible mech-
anisms for this effect. The chemical nature of the plasma changes at end
point because the number of product species is suddenly reduced and
reactants increase. This change in the plasma chemistry affects the
plasma impedance which is reflected in the dc bias-rf power relationship.
Another mechanism can be important in processes where a conducting
film is etching from an insulating (e.g. oxidized) substrate. As this film is
removed, exposing the insulator, the effective sheath capacitance changes,
leading to a change in the measured dc bias.
3.3.2 Optical Emission Spectra. The relative change in concen-
tration of product species can be qualitatively determined by observing
optical emission from excited states in the plasma. A good example of this
technique exists in the case of aluminum etching where the presence of a
line at 261.4 nm, as shown in Figure 35a, is a signatureforthe presence of
AICI.138 Figure 35b shows the significant decrease in the intensity of this
line at end point.
3.3.3 Laser Interferometry. Laser interferometry can be used to
observe the etching of semitransparent films such as Si or Si0 2 . 139 ,14o The
relative phase shift of light reflected from the outer surface and inner
surface of an etching film creates an interference pattern which changes
as the film becomes thinner. This changing phase shift causes an oscillating
component in the total reflected light intensity which is easily measured.
The period of the oscillating intensity is related to the film thickness.

3.4 Defining Process Parameters and Goals

When developing plasma etching processes for each lithographic
level, the following parameters must be considered so that the process
goals are well understood.
 250 Semiconductor Materials

Alel
261.4nm

a 264 262 260

WAVELENGTH (nm)

Ai Ai
CO
OH7

500 400 300 200

WAVELENGTH (nm)

ETCH ETCH
BEGIN END

f ~
>-
~
~
b (f)
z
w
~
z

2 4 6 8 10
TIME (min)

Figure 35: (a) Emission spectrum of CCI 4 plasma at 80 mTorr and 1.5 watts
cm -2 during plasma etching of AI. (b) CCI 4 etching of AI monitored by a spec-
trometer set to the 261.4 nm AICI band (from Reference 137, reprinted with
permission of Solid State Technology, published by Technical Publishing, a
company of Dun and Bradstreet).
 Plasma Processing 251

3.4.1 Material to Be Etched. The chemistry and morphology of the

layer to be etched must be well understood. Details of thin film deposition
processes may result in film properties which significantly affect the
etching characteristics of the film. Impurity concentration, grain size,
density and topography of the etching layer all playa role.
A common situation encountered when etching LPCVD poly-Si serves
as a good example for the effect of film impurities on etching processes.
Chlorine based plasmas typically used to etch silicon remove oxidized
silicon at relatively low rates. The poly-Si etch rate in such etching processes
is therefore very sensitive to the oxygen impurity concentration in the poly-
Si. A low homogeneous oxygen level causes a reduction in the etch rate.
On the other hand, segregated regions of high oxygen concentration can
cause unetched residues commonly referred to as "grass". Figure 36
shows a scanning electron micrograph (SEM) of such a residue.
The film grain size can also affect an etching process. If the film is
deposited under high temperature conditions where nucleation rates are
small and grain growth rate is high then the average grain size can be as
large as the film thickness. Large spherical or columnar grains can cause
rough film surfaces. In addition to causing lithography problems, rough
films must be significantly overetched so that total film removal is assured.
Long overetch times are only possible when the etching process has
adequate selectivity to the mask and underlying layer (see Section 3.4.4).
It is, therefore, extremely important to know the details of film properties
before attempting to design a reproducible plasma etching process.

SILICIDE/POLYSILICON ETCH
EXPERIMENTAL CURVE

en SILICIDE - ....... POLYSILICON ---~~

r- I-----
oMIIl
...

z
:::J
ai
n::
<!
w
o
Z
<!
~
o
W
-.J
l.L
W
0::

ETCH TIME (ARB. UNITS)

Figure 36: Experimental reflectance signal from a 6328;\ laser for a silicide/poly-
Si structure. The signal only shows the initial portion of the poly-Si etch (after
Reference 138).
252 Semiconductor Materials

3.4.2 Feature Edge Profiles. Some plasma etches and virtually all
liquid etches remove material isotropically, that is, the etch rate is the same
in all directions. Figure 37a shows schematically the edge profile of an
isotropically etched masked feature. As is clearly seen such an isotropic
process causes an effective decrease in feature size by"undercutting" the
mask. It is possible to compensate for this reduction in feature size by
providing wider features in the mask, however this is not a desirable
solution for VLSI devices for at least two reasons. First, the undercut, and
therefore feature size, depends on etch rate, film thickness and overetch
time making the feature size extremely difficult to accurately control.
Second, mask compensation wastes area between features which
decreases packing density and circuit speed by requiring longer, more
resistant interconnections.
Anisotropic etch processes where the vertical etch rate is sig nificantly
higher than the horizontal etch rate, are therefore necessary. Figure 37b
shows schematically the results of etching where the horizontal etch rate
is zero. Often the anisotropic ion energy distribution is directly responsible
for anisotropic etching. That is, edge profiles of etched features can be
explained by a vertical etch rate which is much greaterthan the horizontal
etch rate. In this case, if these profiles do exhibit slight undercutting it
occurs at the top of the feature, as shown in Figure 37a. This undercut
should be larger for thicker layers, because the region directly adjacent to
the mask is exposed to the etching atmosphere for a longer time. The
undercut should also be larger for longer overetch times, for the same
reason.
An interesting example of how feedstock composition can affect
anisotropy was reported by Mogab et al. 141 and later discussed by Flamm
et al. 4 Poly-Si etches isotropically in the PE mode using a chlorine feedstock
It was found that adding C 2 F6 to the plasma results in features that are not
undercut. This result is explained by assuming the formation of a "recom-

ETCH I NG PROFI LES

(0) (b)
ISOTROPIC AN ISOTROPIC
MASK

Figure 37: (a) The schematic cross section of a layer isotropically etched with a
mask over a portion of the layer. (b) The cross section of an anistropically etched
layer.
 Plasma Processing 253

binant species" or etch inhibitor on the side walls of the profile. The exact
composition of this deposit on the feature walls is not known but is
suspected to be a polymer. The deposit is also observed on horizontal
surfaces at higher than optimum C2 F6 flow rates. Under optimum conditions
the result is etching on horizontal surfaces, deposition on vertical surfaces,
and anisotropic profiles overall. This interpretation is consistent with the
chemical vapor transport theory discussed in Section 2.2.1. Asimilareffect
has also been credited for the anisotropic etching of aluminum. 142
The recombinant model assumes this passivating layer could be as
thin as a monolayer, however, significantly thicker sidewall layers, easily
visible in an SEM, have been reported. 143 In this case poly-Si was etching in
a CCI 4 plasma. The presence of the layer was again credited with anisotropic
etching. When no sidewall layer was observed the masks were severely
undercut.
Undercut feature profiles are frequently observed that cannot be
explained by assu ming the etch to have a vertical and horizontal component.
A finite horizontal component, no matter how small it is, should always
cause the deepest undercut to occur directly beneath the mask (Figure
37), where the side of the feature is exposed longest to the plasma. The
RSE of GaAs 144 in a mixture of CI 2 and Ar results in profiles shown
schematically in Figure 38. This profile cannot be explained by an etching
process with vertical and horizontal components because the deepest
undercut occu rs well below the mask edge. Redeposition of the su bstrate
material must also playa role in determining the final surface morphology.
The loss of a protective layer on the feature sidewalls is thought to have
produced the undercut profile but a detailed explanation does not exist.
Such a narrowing of an etched feature at approximately half its height has
also been observed in chemically assisted ion beam etching. 145 In this
technique XeF 2 gas is ionized by electrons emitted from a hollow cathode
source. Positive ions are then accelerated by grids in the direction of the
etching wafer. When grid conditions cause a defocussing of the beam it
diverges by as much as 20° and the features are undercut in a mannervery
similar to Figure 38. When the beam is collimated nearly vertical profiles
are observed. This result demonstrates the relationship between the
anisotropy of ion transport and feature profiles.
3.4.3 Uniformity. Ideally the etch rate should be constant, or uniform,
at all etching positions. However, this goal is seldom achieved. Electric
field and composition grad ients can cause large variations in rate. Wh ich of
these is the dominant mechanism must be determined before any improve-
ments can be made. Plasma composition gradients can be caused by local
depletion of the active species. Such depletion can be affected by gas
residence times, which in turn are controlled by source gas flow rates and
loading effects. A nonuniformity which is affected by flow rates therefore
points to a composition gradient mechanism. This problem can often be
solved by a more uniform introduction of the source gas into the reactor.
Electric field nonuniformities are more complicated to deal with since
they are the result of the interactions of virtually all of the plasma parameters.
Often a change in the reactor geometry can improve etch uniformity
without changing desirable properties of the etching process. With batch
254 Semiconductor Materials

Figure 38: Profile of a GaAs substrate etched in a 4: 1 mixture of CI 2 and Ar

(from Reference 143, reprinted with permission from the American Institute
of Physics).

processes one must be concerned with not only intra-wafer but also inter-
wafer uniformity because many wafers are etched simultaneously. Since
single wafer etchers need only provide good intra-wafer uniformity, they
should, in principle, provide superior uniformity with respect to batch
etchers. In practice, this might not always be the case because single
wafer etchers operate at higher power densities and higher etch rates in
order to achieve higher throughput (Sec. 3.4.5). Uniformity is generally
more difficult to achieve at higher etching (or deposition) rates.
3.4.4 Selectivity. A process is selective if it etches the desired
material at a high rate and all other exposed surfaces at a low rate.
Selectivity is defined as

etch rate of material A

SAB = etch rate of material B
Two selectivities must be considered for any etching process. The first is
where A is the material to be etched and B is the masking layer. The
selectivity to the mask must be very high, >5, when thin, 0.2-0.5 p,m,
photoresist is used. Multilayer resist schemes 146 which result in thick, 1.0-
2.0 p,m masks relieve this constraint. The second case is where A is the
material to be etched and B is the underlying layer atwhich the etch should
stop. This selectivity is one of the most important process parameters. It is
during the overetch that this selectivity becomes extremely important. The
 Plasma Processing 255

standard etch time is either calculated from known etch rates or determined
in situ by an end point detection technique (see Sec. 3.3). To determine an
overetch time, the uniformity of the process must be known. An extremely
uniform process might require a small overetch which, in turn, allows for a
poorer selectivity. These two parameters are therefore interrelated.
Other factors also influence the required selectivity of a process. For
example, the gate etch mentioned in Sec. 3.1.3 is shown schematically in
Figure 39. Ideally, at the end of the standard etch time, the material under
the mask will remain while the other material will be totally removed.
However, because of the excellent step coverage of the deposition process,
material on thewall of the FOXwill remain. Thiswill, of course, only betrue if
the horizontal etching component of the process is zero. In order to
remove this "stringer" an overetch of approximately 100 0/0 must be carried
out. As previously mentioned the thin GOX is used as an etch stop. If this
GOX is 200A thick and the FOX is 3000A thick then a selectivity of at least
30 is required if removing 100A of the GOX is permitted. Taking the
uniformity into account will cause the required selectivity to be even
higher.
In practice such a high selectivity along with an an isotropic etch profi Ie
is not easy to achieve. High selectivities are typically achieved in systems
where chemical etch rates dominate. This is not the case when the
physical sputtering contribution to the etch rate is significant. This contri-
bution is relatively independent of etching material and impinging ion
species. It does, however, increase with increasing dc bias voltage. 133 For
this reason higher selectivities are typically achieved in the PE mode, with
its inherently lower sheath voltage, than the RSE mode. Higher selectivities

(I) AFTER PATTERN

DEFINITION
RESIST

FOX GATE OXIDE

AFTER NOMINAL ETCH

TO COMPLETION

(3) AFTER
OVERETCH

... ::::<)

Figure 39: A sequential representation of a gate etch wh ich illustrates the need
for an overetch to remove material deposited on the field oxide wall.
256 Semiconductor Materials

can be achieved in the latter case by reducing the rf power which in turn
reduces the dc bias voltage. As previously discussed operating in this
regime moves in the direction of isotropic etching. A trade off therefore
frequently occurs between selectivity and anisotrophy.
Optimizing the selectivity can often be achieved by the proper choice
of feedstock and flow rates, as pointed out in Section 2.1.3.1. A good
example of affecting selectivity by blending feedstock gasses exists for Si
and Si0 2 in CF 4 /0 2 /H 2 mixtures. 147 Free F atoms are the active etchant
species and the F atom concentration has been shown to depend on the 02
concentration in the feedstock Figure 13 shows how the etch rate of Si is
affected by the 02 concentration in a CF 4 plasma. 63 The etch rate of Si0 2 in
this mixture has a similar dependence on 02 concentration except at
higher concentrations the rate does not falloff so severely as for Si.
Dilution and surface affects playa lesser role because the Si0 2 itself is a
°
source of 2 , Adjusting the concentration of 02 in CF4 can be used to
achieve a selectivity of at least 3 for Si0 2 over Si at 50% 02 in CF 4 ,
The effect of adding H 2 to CF 4 is shown in Figure 40. 148 It is believed
that the sharp decline in Si etch rates at high H 2 concentrations is due to a
decrease in the F atom concentration caused by the scavenging of F
atoms by H 2, forming HF.149 In this system selectivities of 35 can be
attained at 40% H 2 in CF 4, Adding H 2 to the feedstock has the effect of
enhancing polymerformation in the etching chamber. Deposition of polymer
onto wafer surfaces during etching is an undesirable parasitic effect which
is best avoided in commercial processes.
3.4.5 Throughput. The number of wafers etched per unit time is
referred to as the throughput. When the technology exists, economic

70
RF POWER-0.26W/cm 2
60 PRESSURE - 4.7Pa
FLOWRATE-28scCm
c:. o .
SI02
'E
'"E
c:. 4
w
ti0::
30
I
U
J-
w 20

si
10

O_ _~ -"'-_----I'--_-i.--_--A.-_-""_----I"------I

o 5 10 15 20 25 30 35 40 45
0/0 H2 IN CF4
Figure 40: Dependence of Si0 2 and Si etch rates on percentage of H 2 in CF4
feedstock (from Reference 147, reprinted with permission of the publisher, The
Electrochemical Society, Inc.).
 Plasma Processing 257

factors determine an acceptable throughput. For batch etchers, where

many wafers are processed si mu Itaneously, typically acceptable th roug h-
puts require relatively low etch rates of 100-600 A/min. Single wafer
etchers, which must achieve rates at least 10 to 20 times faster for
equivalent throughputs, have to operate at high power density and high
pressure. As discussed in Section 2.2.2.1 it is possible to achieve anisotropic
profiles under such conditions. The high power density can, however, lead
to unwanted wafer heating effects. Wafer heating can cause resist retic-
ulation (cracking and chemical degradation) which leads to unfaithful
pattern transfer. To minimize this effect wafers must be heat sunk well to a
temperature controlled cathode.
3.4.6 Defect Introduction. Any local modification of the original
lithographic pattern is considered a defect. A common type of defect,
introduced during plasma etching is caused by particles falling onto the
wafer during handling or while it is exposed to the etching environment.
The former is common to all processes but the latter is related to the
specific etching process.
When freons are used in the feedstock, plasma decomposition fre-
quently results in polymer deposition onto reactorwalls. 150 As the polymer
film gets thicker it becomes unstable and flakes off onto the etching
wafers. These polymerfilms etch readily in an 02 plasma so that frequently
etchers are cleaned by establishing 02 plasmas at regular intervals between
normal etching runs. Care must be taken when such a cleaning practice is
used because different results may be obtained in a clean system than in a
polymer-coated system. The dynamic equilibrium levels of active species
established in the etcher is different in each case. Two components of this
equilibrium are material depositing onto etcher surfaces and material
being etched from these surfaces. When no polymer exists on the etcher
surfaces equilibrium values of active species in the plasma might be
significantly different than when polymer is coating every surface.
3.4.7 Radiation Damage Effects. In the process of plasmaetching,
device wafers are exposed to various types of damaging radiations: soft x-
rays, uv light, ions and electrons. In the RSE mode the energy of the
positivie ions is considerably higher than the electrons because of the
large potential drop across the cathode sheath. The total radiation dose
affects the electrical properties of devices in a variety of ways.
When accelerating ions with energies of hundreds of eV, strike the
surface of a solid they are implanted into the surface an average distance
of 10-30A 132 During this implant process the crystal structure of the solid
traversed by the slowing ions is disrupted. Bonds are broken and atomic
positions are altered. This, in fact, may be one mechanism by which ions
enhance surface reactivity (see Section 2.2.3.2).
The crystalline damage is significant when the irradiated material is
single crystal and the performance of a device depends on the crystalline
perfection. An example is a schottky diode formed on a Si substrate which
was previously exposed to RSE. Often cryst~lIine damage can be repaired
by high temperature annealing 151 which is already part of subsequent
processing, however, the implanted species from the plasma can only be
removed by chemical etching of the implanted surface layer.
Another target of radiation damage is the gate oxide and field oxide in
258 Semiconductor Materials

MOS devices. When these oxides are directly exposed to RSE, fixed
positive charge is trapped in the oxide, fast interface states are created at
the Si-Si0 2 interface and the oxide contains many neutral electron traps.152
Most of this damage is the result of ionizing radiation. Properties of gate
oxides are typically studied by measuring changes in their capacitance-
voltage (C-V) characteristics. 153 With this method the relationship between
the number of "hot" electrons injected into the oxide and the flat-band
voltage shift has been used to study the neutral electron trap density in
gate oxides directly exposed to RSE.154 Figure 41 shows how oxide
damage caused by RSE can only be completely annealed out at 1000°C.
Of more practical interest is damageto the gate oxide by RSE when it is
covered by the gate material. Th is is the case for the gate etch as demon-
strated in Figu re 39. It has been shown that damage then only occurs at the
periphery of the oxide because of radiation absorption in the gate. 152
Fortunately subsequent processing requires annealing at temperatures
high enough to remove this damage so it usually presents no problems to
device performance.
In the future, MOS devices will be madewith extremely short «1.0}-tm)
gate channel lengths. These devices must have very shallow «2500A)
source and drain junctions 155 which cannot be exposed to the present high
temperature processing. The problem of oxide damage caused by plasma
etching processes will then need to be further investigated.

3.5 Specific Etching Processes

3.5.1 Silicon and Silicides. Virtually all Si IC fabrication schemes

ELECTRON TRAPPING IN RSE'd EXPOSED

500A THERMAL Si0 2

3
10
> METAL
E ANNEAL
->
'<J
ONLY

10
2

10 '5 10 '6
N INJECTED, e/cm 2
Figure 41: Electron trapping in thermal Si0 2 that was exposed during the RSE
of poly-Si as a function of post-RSE thermal anneals (from Reference 152, ©
1979 IEEE).
 Plasma Processing 259

include at least one poly-Si etch process. The most common is the MOS
gate etch. Recently efforts have been made to decrease the resistivity of
poly-Si gates while retaining the stable gate/gate insulator(poly-Si/Si0 2)
interface. This is accomplished by adding a silicide layer to the top of a
normal poly-Si gate. 156 Forthis technique to be useful, it must be possible
to anisotropically etch this bilayer structure, frequently called a polycide,
with the high selectivity discussed in Section 3.4.4.
3.5.1.1 Silicon. A primary concern when selecting a feedstock for any
etching process is that the final reaction product be volatile. Nonvolatile
products lead to residues on the surface which cause either surface
roughening or a total cessation of the etch. Since silicon chlorides and
fluorides are volatile, etching of poly-Si can be accomplished with most CI
and F based feedstocks such as C1 2, CCI 3 F, CCIF 3 , CF 4, NF 3 , SF 6.157
Generally feedstocks containing Fetch isotropically while those containing
CI can yield anisotropic profiles. The spontaneous etching of Si by free F
atoms generated in the plasma causes chemical, isotropic etching.? Un-
diluted CI 2 can be used to etch poly-Si anisotropically in a plasma 141 but a
problem is often encountered in initiating the etch through the surface
native oxide. This problem can be solved by using a CI containing freon
where the selectivity of Si:Si02 is not so great. Theselectivityof Si:Si02 has
been studied in the series CCI 4, CCI 3 F, CCI 2F2, CCIF3 and CF4.158 Results
indicate that selectivity decreases by a factor of five as the F concentration
in the source gas increases. This is consistent with CI not spontaneously
etching Si at room temperature. The characteristics of virtually all poly-Si
etching processes change abruptly when the poly-Si is heavily n-type
doped and activated. The etch rate then increases dramatically, and
isotropic profiles are often observed. When the poly-Si is p-type doped, on
the other hand, etching is indistinguishable from undoped poly-Si. If an n-
type dopant is implanted and etched before it undergoes an activating
anneal, it etches as undoped poly-Si. These facts lead to the speculation
that a high free electron density enhances the interaction of Si with
adsorbed CI atoms leading to higher etch rates and isotropic profiles. 141
Experimental evidence shows, however, that the etch rate does not corre-
late with free electron density159 so the mechanism is as yet unresolved..
3.5.1.2 Silicides. Undiluted CI 2 is ineffective in etching silicides so
most polycide etching processes use CI 2 mixtures or freons. Figure 42
shows a TaSi 2/poly-Si composite which was etched using a two-step
process. The TaSi 2 was first etched using a CCI 3 F feedstock and then the
poly-Si was etched with a CI 2 feedstock. For either a one step or a two step
polycide etching process the selectivity of the bottom poly-Si with respect
to Si0 2 is most important. There are many reports in the recent literature of
one-step processes and the following few are given only as examples.
BCI 3 /CI 2 mixtures are reported to etch TaSi 2/poly-Si composites anisotrop-
ically.16o TiSi 2/poly-Si is reported to etch anisotropically in a CCI 4/ Ar/N 2/H 2
mixture. 161 MoSi 2/poly-Si etches in NF 3 /HCI mixtures with a possible
selectivity of poly-Si:Si0 2 of 30.0. 162 While many mixtures of CI and F
bearing source gases can etch polycide structures, the conditions for a
one-step process which results in tightly controlled profiles along with
excellent selectivity (> 100) to Si0 2 have not yet been reported.
260 Semiconductor Materials

RESI

POLY- si

Figure 42: An SEM cross section of a TaSi 2 /poly-Si structure anisotropically

etched with a two step process.

3.5.1.3 Trench etching. Another application of Si etching has recently

emerged with the need for deep (>5.0p,m) narrow « 1.5 p,m) slots or
trenches in the Si substrate. These trenches can be used to isolate
complementary devices in CMOS circuits. 163 Alternativelyvertical storage
capacitors can be fabricated inside the trenches. 164 A pri mary prerequisite
for such trenches is that they not be undercut. In fact, a negative undercut
is desirable so that when the trenches are refilled with an LPCVD process
no void will form at the top of the trench. Figure 43a shows such a void in a
refilled trench with a slight undercut. Figure 43b shows no void when the
trench walls taper inward. CI 2 based source gases are reported to etch
trenches with these very high aspect ratios. 165
3.5.2 Etching of Thermal and LPCVD Oxide. As shown in Section
3.1.3 two major applications of oxide etching are the initial opening of
GASAD regions in FOX and then the etching of contact windows through
phosphorus doped LPCVD oxide (p-glass). In both these cases high selec-
tivity with respect to underlying Si is important as is the integrity of the
exposed Si surface. The GASAD region is where the MaS transistors are
formed so only minimum damage can be tolerated. Contact window etching
also requires only minimum residue after etching. Such residue has been
shown to increase contact resistance to metals which are subsequently
deposited into the windows. 135
Because of this metal deposition, profile control is very important for
contact window, orvia, etching. Perfectly vertical walls often create problems
 "1J
Q)
(J)
3
Q)

"1J
-,;
o(")
CD
(J)
(J)
~
(Q
a b
Figure 43: (a) A deep, slightly undercut trench which was substantially refilled with LPCVD poly-Si. A void in the poly-Si is J\)
0)
visible. (b) A tapered trench etched and refilled. No void is present due to the tapered trench.
262 Semiconductor Materials

because most vacuum, thin film deposition processes deposit thinner

layers on the walls than on horizontal surfaces. This thinning (illustrated in
Figure 44a) can lead to high resistance regions and, consequently, reliability
problems. Figure 44b shows how this problem can be minimized by
tapering the via walls. Tapering is accomplished by transferring an initial
taper of the photoresist down into the p-glass or other insulator 166 as
shown in Figure 45. Tapering cannot be used if vias are spaced so closely
together that the tops merge together causing a thinning of the insulator.
The thin insulator region at the bottom of the taper also increases the
capacitance between the deposited metal and the conductor under the
insulator. This causes an increased RC time constant which might limit the
speed of the circuit. A tapering process demands tight control over resist
profile, p-glass: resist selectivity, uniformity and overetch time.
Some gases reported to plasma etch oxide are CHF 3 , C 2 F6 , CCI 4 , CF4
and NF 3 .14o,143,147,167,168 All Forms of Si0 2 etch anisotropically under most

THINNING

VERTICAL WINDOW TAPERED WINDOW

(a) (b)

Figure 44: (a) A schematic illustration of vapor deposited AI into a contact win-
dow. Thinning of the AI is evident. (b) Only slight thinning is present with a
tapered window.

TAPERED RESIST BEFORE

WINDOW ETCH TAPERED WINDOW

INSULATOR

(0)

Figure 45: A sequential illustration of how a tapered resist pattern can be used
to form a tapered window.
 Plasma Processing 263

operating conditions with the first three of these feedstocks. Si0 2 can be
etched anisotropically in CF 4 and NF 3 only at low frequencies and in the
lattercase only if it is diluted with an inert gas. 140 P-glass etches fasterthan
LPCVD Si02 which etches faster than thermal Si0 2; P-glass etch rates can
be as much as two times higher than for thermal oxide.
RSE of oxide in a CHF 3 plasma is an example of a system where
polymer formation affects the etching process. In addtion to forming
polymers on the cham ber walls, coati ng of some non-etch ing wafer su rfaces
can also occur. Polymer formation is greater at higher pressures (>40
mtorr) and higher flow rates. This deposition is thought to increase the
selectivity of Si0 2 to Si by selectively depositing onto Si and not Si0 2.
3.5.3 Etching of Aluminum Metallization. Aluminum metallization
can take the form of a pure AI film, an AI/poly-Si composite structure, an AI-
Cu alloy and an AI-Si alloy. While each of these metallizations schemes
have slightly different etching characteristics they all share the many
problems encountered in plasma etching of A1.169-171
AI has a native oxide which frequently etches at a much slower rate
than AI. At best this leads to an incubation period which must be accounted
for when predicting clearing times. At worst, this leads to the etching
surface being extremely rough because of slight nonuniformities in the
native oxide thickness. A reproducible process does not have a high
AI/AI 20 3 selectivity. Mixtures of CCI 4, BCI 3 , SiCI 3 and CI 2 meet this criteria
and have been reported to anisotropically etch AI.171
Once etched, an AI pattern cannot simply be removed from the chamber
into ambient atmosphere. If this is done severe corrosion of the AI takes
place. Presumably a chlorinated residue on the AI reacts with water vapor
in the air to form HCI which subsequently attacks the AI. Two ways of
avoiding this problem are to either rinse the wafers in water immediately
upon exposure to the atmosphere or to proceed, in situ, with an 02 plasma
etch which removes the masking resist and passivates the AI surfaces. 169
While it is certainly possible to anisotropically etch AI, it is frequently
difficult to maintain a process which produces the same anisotropic profile
from run to run over an extended period of time. The etched profile and etch
rate are strong functions of the concentration of the active species, CI, in
the plasma. High CI concentrations lead to high chemical etch rates which
in turn lead to undercut AI profiles. A process which depends on a fully
loaded system to deplete the CI concentration enough to produce an
anisotropically etched profile might undercut if less than a full load of
wafers is etched. 142 The recombinant and inhibiting mechanism has been
credited with the anisotropic etching of AI49 and the presence of a passivated
sidewall layer has been corroborated. 172 This passivating layer is found to
etch readily in an 02 plasma and its formation is probably threatened by
residual 02 in the chamber. Thus, the degree of anisotropy achievable in an
AI etching process may be strongly dependent upon the exposure of the
system to air. This problem is compounded by the formation of porous
aluminum chlorides on the reactor walls. This deposit readily absorbs
water vapor on exposure to air. Heating the reactor walls above room
temperature or using a load reactor decreases the watervaporcontamina-
tion problem.
264 Semiconductor Materials

3.5.4 Silicon Nitride. Most applications of silicon nitride in IC fabri-

cation do not require accurate profile control during etching. This is true for
LPCVD silicon nitride (Si 3N4) or the plasma enhanced chemical vapor
deposited (PECVD) silicon nitride (Si-N-H) discussed in Section 4.3.1. A
typical etch for silicon nitride uses CF 4 + 02 as a feedstock in the PE
mode. 173 This etch suffers from poor selectivity to both silicon and silicon
oxides. The selectivity of Si 3N4 to Si is improved in plasmas which generate
CF x radicals 148,15o and generally plasma parameters which lead to high
Si0 2: Si selectivity also increase the Si 3N4: Si selectivity.4 A recent report 174
shows that Si 3N 4 can be etched anisotropically in the RSE mode with a
selectivity to Si and Si0 2 of 20: 1. Either of two feedstocks, CH 2F2or CH 3F
could produce these results.
3.5.5 Etching of Group III, VCompound Semiconductors. Semi-
conducting alloys of group III and group V elements (1I1-V's) are seeing
increased usage because of their high mobility, large bandgap and rapid
radiative recombination at wavelengths which make useful light sources.
Plasma etching processes which can be used to fabricate III-V devices are
being investigated and have been reviewed in the literature. 4,175,176 This
section will emphasis how these processes are different from those
already discussed and what special considerations must be taken into
account when etching III-V's.
As discussed in Section 3.5.1.1 ,a primary consideration when selecting
a feedstock for a plasma etching process is that a volatile product species
exist. For many etching processes previously discussed these volatile
products are either chlorides or fluorides. Group III fluorides are not
volatile at room temperature so fluorine is not an active etchant for III-V's.
This fact can be advantageously employed by using a fluorine based plasma
to etch a deposited film, such as a metal or PECVD oxide or nitride, with a
high selectivity with repect to the III-V. Chlorine, bromine and hydrogen
react to form either volatile or high vapor pressure compounds with most
group II I and V elements. 177,178 Feedstocks containing one or combinations
of these three elements are most often utilized in III-V plasma etching. 179,18o
However, even in an undiluted chlorine plasma the diverse chemical
nature of the group III and group V elements often leads to non stoichiometric
material removal. It has been shown 181 when etching InP and GaAs in the
PE mode with a chlorine feedstock that In and Ga enriched surfaces
respectively are present after etching. The temperature dependence of
the etch rates indicates activation energies close to the group III trichloride
heats of sublimation. 181 For this reason, product desorption is assumed to
be the rate limiting step.
Unlike the plasma etching of single crystal silicon, the plasma etching
of single crystal GaAs can exhibit crystallographic effects. 51 When the
etching mechanism is believed to be purely chemical, isotropic and free
from ion bom bardment en hancement effects, crystal facets develop under
masked regins. These facets result from the dependence of the etch rate
on crystallographic direction.
When the ion bombardment effects are significant, as in the RSE
mode, anisotropic profiles can be obtained in III-V's144 but two undesirable
etching characteristics are frequently observed. The etching surface is
 Plasma Processing 265

frequently extremely rough 180 and the side wall of masked features fre-
quently slopes in such a direction as to make the feature larger at the
bottom. This second effect which is illustrated in Figure 46 has been called
negative undercut or overcut. Surface roughening is probably related to
nonstoichiometric material removal.
Bu rton et al. 176 reviewed the appl ication of plasma etch ing of the III-V
semiconductors to eight III-V device fabrication processes: (1) etching via
holes for through-the-chip interconnections, (2) etching wells selectively
th roug h one layer of a heterostructu re, (3) etch ing mirror facets or wi ndows,
(4) separating chips, (5) etching integral lenses, (6) etching gratings, (7)
forming mesas for restricting p-n junction area, and (8) etching channels.
They conclude that plasma etching is currently the process of choice in
only the first three applications. While the plasma etching of deposited
layers such as metals, oxides, and nitrides is widely practiced in III-V
manufacturing, the plasma etching of the semiconductor itself is clearly
not as important for III-V processing as it is for Si processing. The converse
is true for plasma enhanced deposition processes, so in the next section
application to III-V technology will be stressed just as applications to Si
technology were stressed in this section.

MASK
OVERCUT

SUBSTRATE

Figure 46: An illustration of a tapered, "overcut" etch profile which commonly

occurs when etching III-Vis (after Reference 176).

4. PLASMA DEPOSITION

4.1 Introduction
In this section, we discuss the application of plasmas to processes in
which material is deposited rather than removed. While this method of
deposition is often referred to as plasma deposition (PO) org low discharge
(GO) deposition, it is more accurately described as plasma-enhanced or
plasma-assisted chemical vapor deposition (PECVO or PACVO), since it is
a CVO process whose rate at a low deposition temperature is enhanced by
energy supplied from a plasma. In the interest of standardization, we will
use the term PECVO throughout this section.
Whereas CVO is a purely chemical process, PECVO additionally involves
physical processes such as ion and electron bombardment of the growing
film. However, as in normal CVO, all the chemical constituents of the
266 Semiconductor Materials

deposited film are introduced in the gaseous phase intothe reactor, whose
design is basically the same as that used for the plasma etching process
discussed in the preceding section. It is this property which distinguishes
PECVD from reactive sputter deposition, the other common reactive
plasma-employing deposition process. Reactive sputter deposition is the
deposition complement of reactive ion etching (RIE) or reactive sputter
etching (RSE), also discussed in the preceding section. In reactive sputter
deposition, only a part of the constituents of the deposited film are supplied
in the gas phase, with the other components supplied in the solid phase as
the sputtering target. These deposition processes are contrasted in Figure
47. PECVD alone is the subject of this section. In recent years, there have
been a number of reviews of PECVD, 182-194 mainly from the standpoint of a
thin film deposition technique. This work considers PECVD from the
standpoint of its use in semiconductor processing applications. Thus in
the ensuing sections, emphasis is on those materials used in semiconductor
processing and on the control of film and film/semiconductor interface
properties to meet the requirements of a given processing application.

PLASMA

•••••••••••••••••
••••••••••••••••••••••••••••••••••••••••••••••••• A8 X
••••••••••••••••••••••••••••••••• ~4~------ +
•••••••••••••••••
••••••••••••••••••••••••••••••••• C
r7777777777777a
HOT SUBSTRATE

A8 X + nC ---. AC n + xB

SPUTTER
TARGET

~:~
••••••••••••t t ••••••••••
••••••••••••••••••••••• I I •••••••••••••••••••••
••••••••••••••••••••••• X + C+ ••••••••••••••••• • •
•••••••••••••••••••••••• ~ •••••••••••••••••• 4 X+C
••••••••••••••••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••••••••••••••••
rzzzzzzzZZZZZZZ21
SUBSTRATE

A + nC -.AC n

Figure 47: Comparison of PECV D and reactive sputter deposition processes,

shown for deposition of a film of generic composition AC n .
 Plasma Processing 267

The major attraction of PECVD is its useful deposition rate at a

temperature significantly lower than that for CVD. PECVD is generally
performed at substrate temperatures in the range 200-350°C, compared
to typical CVD temperatures of 400-900°C. As discussed in section 2,
electron impact dissociation and ionization of reactants occurs in the gas
phase, so that it is reactive atoms and radicals which adsorb and react on
the substrate surface. 188,189 Often thermal energy from the substrate is not
necessary for reaction to occur; instead this thermal energy is usually
needed to enhance surface mobility in orderfordesirablefilm properties to
be attained. Although the ion temperature within the glow region of the
plasma is room temperature (see Section 2.1), ions can be accelerated
across the sheath to impinge on the substrate at energies ranging from a
few to a few hundred eV (see Sec. 2.1.2.1.4). This ion bombardment also
promotes surface mobility, as well as giving sputter-assisted desorption of
volatile reaction products. Thus PEGVD processes are far from thermo-
dynamic equilibrium and can be used to deposit materials or phases which
cannot be deposited by direct GVD. However, from the opposite consider-
ation of radiation induced damage, another attraction of PECVD is that it is
a relatively "soft" plasma process. In comparison to reactive sputter
deposition, the energies of ions incident on the substrate are lower. In
addition, because PECVD has a higher deposition rate for a given plasma
power, the substrate is capped more rapidly by a layer thick enough to
protect the underlying substrate. Thus both the damaging dose and the
energy of these ions received by the su bstrate are considerably lower. 195,196
Figure 48 puts PECVD into context with other competing deposition
technologies with regard to deposition temperature and process energetics.
Sputter deposition and CVD are each discussed in detail in other chapters
of this work. Photo-assisted CVD, also included"in Figure 48, is a recently

t
~ 1000
:::>
1200
1
~ 800
or
0:: >1 EVAPORATION
w ul
a.. PHOTO-ASSISTED
I
:E
w 600 CVD
1
~ r------.,
w 400 I
I- I
I
<l I I
a:: L __ J I
I- 200
en
£D
:::>
en o ~
10-2 ~0-1 1 10 10 2 103 104
PEAK ENERGY OF INCIDENT ATOMIC/MOLECULAR SPECIES (eV)

Figure 48: PECVD in substrate temperature-incident particle energy space in

comparison to other deposition techniques.
268 Semiconductor Materials

developed alternative low temperature CVD technique in which the energy

for gas phase dissociation of reactants is provided by ultra-violet photon
absorption in place of the electron impact which occurs in a plasma. The
U.V. photon flux may originate from a bank of lamps and impinge on the
substrate surface,197 or may be from an excimer laser whose beam is
confined to a thin sheet parallel to and just above the substrate surface. 198
This photochemically assisted CVD process may be very important for
eliminating or restricting semiconductor surface modification effects which
occur due to the electron and ion bombardment associated with plasma
exposure. 188,189 A final laser assisted form of CVD does not involve gas
phase photochemistry, but merely uses thermal energy from absorption of
the laser beam to promote localized CVD,199 and hence this deposition
method is included in Figure 48 in the same parameter space as CVD, with
the provision that only the deposition region of the surface is heated and
not the whole substrate.
4.1.1 Applications of PECVD Materials. The range of deposition
temperatures of PECVD make it particularly attractive for use on compound
semiconductors susceptible to thermal decomposition. Thus many of the
present applications of PECVD are in the processig of the III-V semi-
conductors, GaAs and InP, in the fabrication of high speed electronic and
optoelectronic devices. Table 3 lists a number of these applications.
Applications are also to be expected in II-VI semiconductor processing.
Present Si processing is in general compatible with CVD temperatures,
and since CVD is performed in simple, less-costly equipment, PECVD has
not found widespread applications in Si technology.19o Exceptions to this
are PECVD silicon nitride as a passivation coating, and applications where
the deposition needs to be performed over a temperature-sensitive organic
coating,200 or a low melting point metallization such as AI or Au. Figure 49
shows such a Si processing application in which Si0 2 is plasma-deposited
over photoresist. However, as Si device dimensions are reduced even
further, lower temperature processing will be necessary in order to prevent
diffusion of shallow junctions, and PECVD is expected to find further
applications here.
Historically, PECVD has been used mainly to deposit amorphous,
dielectric compounds of Si (SiN x and Si0 2) and doped amorphous, hydro-
genated Si itself. PECVD of these materials will be considered in detail in
subsequent sections, since these are still the main commercial applications.
However, the wide applicability of PECVD is beginning to be exploited.
Materials which now have been deposited include single crystal, poly-
crystalline and amorphous elemental and compound semiconductors,
metals, oxides, nitrides, silicides, carbides, and polymers. The specific
materials which have been deposited are shown in Table 4, along with the
source gases used and a relevant reference.

4.2 General Aspects of PECVD and PECVD Reactors

PECVD is performed by flowing the pre-mixed source gases to be
reacted and their inert carrier gases (if any) into a plasma discharge in the
vicinity of a heated substrate. Thus the parameters shown in Table 5, along
with their typical values, are PECVD variables which must be specified in
 Plasma Processing 269

Table 3: Applications of PECVD in Semiconductor Process Technology

Application
Si Tedulo1ogy Local thermal oxidation mask (SiN x )
C~ntral lay~r of a tri-layer resist (Si0 2 )
Interlayer dielectric (Si0 2)
Passivai,ion (SiN x )
Contacts (silicides)
------------t--------------------
III-V Technology
- High Speed Electronics MISFET gate insulhtor on InP (Si0 2 )
- Optoelectronics H+, D+ or He+ implant mask (SiO z)
Anti-reflection coatings (on photo-detectors and LEDs)
(SiNxO y ) (SiNxHy )
Laser facet coatings - protective and reflectivity modification.
Etch lvlasks (wet and dry) (Si0 2 ,SiNx )
Contact area definition (Si0 2 ,SiN x )
DiffusionMa.sk (SiNx,Si0 2 )
Encapsulant/passivation (SiN I )
Auxiliary lift-off layer (SiO z)
Growth Mask in epitaxial growth (SiNx , SiO z).
Implant anneal cap (SiN x)'
-r---~-----------------

Energy Technology Photovoltaic material (a-Si(H)}

Anti-reflection coatings on solar cells (SiNx )

Display Tcchr£ology Thin Film Transistor (a-Si(H))

order to define PECVD conditions. It must be stressed that many of these

variables are interactive, and that performance of PECVD with good spatial
uniformity of deposition rate requires a dynamic balance of these para-
meters. Thus it is not reasonable to study the dependence of film properties
on a given deposition parameter by variation of that parameter alone, since
this upsets that dynamic balance (see Section 4.2.3). Instead a more
appropriate approach, both from a mechanistic as well as an applications
aspect, is to vary pairs of variables in tandem in such a way as to maintain
that dynamic balance. For example, in order to study the dependence of
deposited film properties on gas pressure during deposition, the gas
pressure and the total gas flow (at constant flow ratios) can be varied
together in such a way as to maintain spatial uniformity of deposition at a
constant plasma power. Variation of this paircan be followed byvariation of
other pair combinations such as gas pressure and carrier gas flow, or gas
pressure and rf power density, always in such a way as to maintain spatial
uniformity. This leads to the establishment of sets of simultaneous equations
from wh ich the partial differential of film property X with deposition pressure
may be derived. Ideally this should be done for more than one combination
of the othervariables Le., more than one slice in parameter space shou ld be
taken. The above is quite an exhaustive and time consuming procedure.
270 Semiconductor Materials

Figure 49: Schematic representation of a tri-Iayer resist procedure employing

PECVD Si0 2 (from Reference 200, reprinted with permission of Solid State Tech-
nology, published by Technical Publishing, a company of Dun and Bradstreet).
 Plasma Processing 271

Table 4a: PECVD of Dielectric Oxides, Nitrides, and Carbides

Material Deposited Reactants Reference

Silicon Nitride SiH4, NH3 213,218
SiH4, N 2 217,221
SiBr4, N 2 314
Si1 4 , N 2 315

Silicon Oxide SiH., N 2 0 218,239

SiH., CO 2 240
SiCI., O 2 241
Si(OC 2H6)., O 2 242

Silicon Oxynitride SilI4, NH3, N 20 240

Silicon Carbide SiR., C 2H4 or CfI. 218

Germanium Oxide Ge(OC ZH6)., O 2 316

GeH., N 20

Gerlnanium Carbide GeH., C 2H2 317

Tin Oxide dibutyltin diacetate 316

(CH 3).Sn, NzO

Boron Oxide B(OC ZH6 )3, O 2 316

Boron Nitride BBr3' NH3 (fI2) 318

B 21{6, NH3 319,320

Alunlinum Oxide AlCI 3 , O 2 300

(CfI3 hAl, O 2 297

Alunlinum Phosphate (CH3 hAl, PI-I3 , O 2 297

AluminuIn Nitride AlCI 3, N 2 301

Gallium Oxide (CI-I3 )3G a, O 2 302

Galliulll Nitride (CI-I3 hGa, NH3 303,321

Phosphorus Nitride P, N 2 305,306

PI-I3 , N z 306

Titaniulll Oxide TiCI., O 2 318

Ti isopropylate, O 2 316
rriCl 4 , CO 2 322
Titanium Carbide TiCI., Cl-1. 304
Iron Oxide Fe(CO)6 316
272 Semiconductor Materials

Table 4b: PECVD of Semiconductors, Conductors, and Elements

Material Deposited Reactants Reference

amorphous silicon, SiH4 246,256

a-Si(fl) Si 2 H6 261

polycrystalline silicon SiI-1 4 278

epitaxial silicon SiH 4 281

amorphous germanium, GeH 4 323

a-Ge(I-I)

epitaxial germanium GeH 4 285

epitaxial GaAs Ga,As 286

(CI-1 3 )3 Ga, AsH3 287

epitaxial GaSb Ga, Sb 288

amorphous carbon, C 41-1 10 186,324

a-C(I-I) C 2 I-I 2 325

amorphous boron, B 2H 6 326

a-B(H) BCI3, H 2 327
BBr3' H 2 328

amorphous arsenic, AsII3 329

a-As (I-I)

aluminum AlCl 3 290

(CI-I 3)3Al 290

tungsten WF 6, H 2 292

molybdenum MoF 6, H 2 292

MoCI D, H 2 294
Mo(CO)6 293

tungsten silicide WF 6, SiH4 295

molybdenum silicide MoCI o' SiH4 294

titanium nitride TiCI 4 , N 2 , 112 304

tin oxide dibutyltin diacetate 316

(CI-13)4 Sn , N 2 0
 Plasma Processing 273

Table 5: Variable Parameters in PECVD

Direct Variables:

Parameter Typical Value

Reactant Gas Flows 1-1000 secm

Reactant Gas Flow Ratios 1-100

Total Gas Flow 50-5000 scem

(also gas flow pattern)

Electrode Spacing 2-4 cm

Gas Pressure 200-2000 mtorr

RF Power Density 0.03 - 0.5 W cm- 2

RF Frequency 25 KHz - 25 MHz

Su bstrate Temperature

Resultant Variables:

Deposition Rate
Film Composition
Uniformity of Rate and Composition
Film Properties

Similar situations in plasma etching are being treated by Mocella et al. 129
using the statistical technique of Response Surface Methodology to
generate a model parametric expression of the process. Such an approach
has the potential to drastically reduce the number of experimental data
points needed to optimize a multi-parameter process, and therefore its
application to PECVD would be very beneficial. Thus deposition parameters
may be selected to optimize a specific film property for a given processing
application, and the sensitivity of that property to small variations in each
parameter established in order to determine the necessary levels of
parameter control.
4.2.1 Reactor Designs. All plasma deposition systems consist of
the following components: gas sources, gas flow controllers, a gas manifold
and distributor, a plasma chamber incorporating a heated substrate table
and pressure monitoring, an rf generator, a pumping system including
throttle valve, and an exhaust system. This is shown schematically in
Figure 50. In commercial systems, gas flow control employs electronic
mass flow controllers which can maintain absolute flows or fixed flow
ratios, pressure monitoring is by species-independent capacitance mano-
meters, and the pumping throttle valve is servo-controlled to maintain a
constant chamber pressure. Many systems now employ microprocessor
control.
It is the desig n of the plasma cham ber itself, in particu lar the electrode
and gas flow geometries, which distinguishes the various types of PECVD
274 Sem iconductor Materials

MASS
SOURCE FLOW
GASES CONTROLLERS

TEMPERATURE
CONTROLLER

CAPACITANCE
MANOMETER

PARTICLE
FILTER

OIL
FILTRATION
UNIT

Figure 50: Schematic representation of the components of a PECVD system.

 Plasma Processing 275

reactor. The three main categories are shown schematically in Figure 51,
along with the relevant sub-categories. The class (c) shown is to some
extent a sub-division of class (a) in that an individual pair of electrodes is
parallel-plate, but since multiple pairs of electrodes distributed in multiple
columns along a tube which is enclosed in a diffusion-style furnace are
involved, it is a sufficiently different concept to merit separate description.
The parallel-plate, radial flow reactor shown in the first class was
designed by A.R. Reinberg,134,201 for silicon nitride deposition, and is
sometimes referred to as a Reinberg reactor. His original design [(a)(i)]
employed inward radial flow; a later variation,202 using outward flow is also
shown [(a)(ii)]. The radial-flow reactor is the most commonly employed for
plasma deposition. Electrode diameters are usually in the range of 25 to 55
cm, and batch processing is used. Whereas single wafer processing has
certain merits for plasma etching (see Section 3.2.3), it is not a viable
alternative for plasma deposition due to deposition rates (for acceptable
film properties) being rather lower than etch rates that can be employed.
The larger reactors are normally used for Si processing, and can accomodate
about 20 four inch wafers. The smallest reactors are more than adequate
for use in present III-V compound semicondutor technology. A typical
process time from wafer loading to removal is about two hours, depending
on at what temperature it is permissible to laod wafers on to the substrate
table. If native oxide growth on the surface of a III-V semiconductorwafer is
to be avoided or at least limited, it is necessary that the substrate table be
no more than a few tens of degrees above room temperature during wafer
loading. This can significantly increase process time, particularly in the
case of the larger reactors with substrate tables of large thermal mass. Use
of a wafer carrier plate to give a thermal delay slightly longer than the
pump-down time circumvents this problem. The final variety of parallel-
plate reactor, shown in Figure 51 as (a) (iii), is the "shower head" variety,
which employs a perforated upper electrode through which the reactant
gases are introduced into the plasma. An advantage of this scheme is that
the lower electrode (substrate table) is a continuous plate, in contrast to
the annular geometry required for radial flow. A disadvantage is that
cooling of the perforated, powered electrode is difficult, sometimes neces-
sitating pulsed power plasma operation.
The second type of reactor is the tube or barrel reactor, intowhich the rf
power usually is inductively coupled, by a coil around the tube, external to
the plasma region. This type of reactor is shown as (b) in Figure 51.
Capacitive coupling via external electrodes is also possible. As before, the
reactor is coldwall. This type of reactor is very simple and lends itself to
process research studies, but is not suitable for uniform, batch deposition
needed in a production environment. However, it is particularly suitable for
indirect plasma studies in which the substrate is not directly exposed to
the plasma, but is mounted downstream from the glow region. In this way
reactive radicals and atoms, in both excited and ground states, can arrive
at the heated substrate surface if their lifetime is sufficiently long. Since
the substrate is in a field-free region, energetic ion and electron bombard-
ment is avoided. This is beneficial for avoiding or restricting substrate
276 Semiconductor Materials

ai

Shielded
RF Power
Input

l
Electrode

Heater

Rotating Shaft
Out to Out to
VAC Pump VAC Pump
Magnetic
Rotation
Drive

Gases In

a ii
Figure 51: The main types of PECVD reactors (a) parallel-plate with (i) Rein-
berg-design inward radial flow (from Reference 183, reprinted with permission
of the American Institute of Physics) (ii) modified Reinberg-design with out-
ward radial flow (from Reference 202, reprinted with permission of Solid State
Technology, published by Technical Publishing, a company of Dun and Brad-
street), (iii) shower head gas distribution (b) inductively coupled tube and (c)
hot-wall (from Reference 203, reprinted with permission of Solid State Tech-
nology, published by Technical Publishing, a company of Dun and Bradstreet).
 Plasma Processing 277

GASES IN
+

HEATER HEATER I
OUT TO VAC PUMP
ROTATING
SHAFT
!
OUT TO VAC PUMP

MAGNETIC
ROTATION
DRIVE

a iii

PRE-MIXED
GASES IN

RF
COIL
• PLASMA •

HEATED SUBSTRATE
TABLE (GROUNDED
OR FLOATING)

GASES EXHAUSTED
TO PUMPS

b
Figure 51: (continued)
278 Semiconductor Materials

RF
PRESSURE
SENSOR '

Cl ..
I --...

-Side view cross-sectiO/l of system.

R
F
G
E
N
E
R
A
T
o
R

-Front view cross-section of reactor internals.

c

Figure 51: (continued)

 Plasma Processing 279

damage effects, but may not be beneficial to film properties (see Sec.
4.2.4).
The final type of reactor is the hot wall tube,203 shown as (c) in Figure
51. This is basically a diffusion furnace tube into which is inserted a
multiple array of parallel-plate electrode pairs, usually made of carbon.
Each grounded electrode can carry a single wafer in a vertical orientation.
Th is arrangement is suitable for large, regularly shaped Si wafers, but is not
suitable forthe smaller and often irregularly shaped and sized III-Vwafers.
An advantage of th is arrangement is its large wafer capacity; a com mercially
available system has a batch capacity of 84 four inch wafers. However in
many applications its process cycle time is rather longer than that of the
radial flow reactors. Since reactants are introduced at one end of the tube
and both become depleted and are accelerated down a pressure gradient
(thus reducing residence time) as they flow down the tube, it would appear
that the on Iy way to ach ieve uniform deposition is to use a large excess of
reactants and hence operate at low efficiency, a possibly costly operation
if very high purity SiH 4 is being used. One variation of th is type of reactor 204
pulses the applied rf power to prevent downstream depletion of reactants.
Commercially available PECVD reactors have recently been reviewed. 204
A major reactor design consideration not yet discussed is the frequency
of the rf plasma. The frequency range over which reactors have been
operated (~30 KHz to ~30 MHz) can be split into two distinct regimes, as
discussed in section 2.1. In one regime, which we will refer to as low
frequency rf, both ions and electrons respond to the rf field. Thus in one
half-cycle of the applied rf voltage, positive ions are extracted from the
glow region and accelerated across the sheath above the substrates on
the grounded table. Due to the fairly high pressure employed for PECVD
(~1 torr), most of these ions suffer collisions during acceleration through
the sheath. Nevertheless, there is a flux of energetic ions incident on the
substrate with an energy distribution whose high energy tail extends as
high as the amplitude of the rf voltage, which may be a few hundred volts.
This is illustrated in figure 1 O. Thewidth of this energy distribution depends
on pressure, gas species, rf power etc., and can be as large as a few
hundred eV. It is this directional ion flux which is responsible for anisotropy
and enhanced etch rates in low frequency plasma etch ing (see, for example,
Reference 140), as discussed in Section 2.2.2.1. This regime of operation
extends up to a few MHz, with the exact upper limit being determined by
the ion masses, pressure, etc. Above this transition frequency, we are in the
high frequency rf regime, in which the inertia of the ions prevents them
from responding to the rf field which is followed only by the electrons.
Although there is essentially no energetic (>50 eV) ion bombardment of
the sLJlJstrate, there remains a high flux of low energy ions (~25 eV), as also
shown in Figure 10 due to the small positive dc potential of the glow region,
in addition to the energetic electron bombardment. This low energy ion
bombardment is also present at low frequency. The difference in extent
and energy of ion bombardment fundamentally changes bulk film properties,
film/substrate interface properties and in some cases deposition rates.
All the types of reactors discussed can be operated at high or low
frequency, although high frequency(13.56 MHz) isgenerallyusedfortube
280 Semiconductor Materials

reactors. Low frequency operation is simpler in that impedance matching

is accomplished by a variable transformer, whereas high frequency impe-
dance matching requires an L,C network. Possibly because of the difficulty
of impedance matching the complex electrode arrangement in a hot-wall
reactor, low frequency is usually used in that case. 203
An interesting recent development of a PECVD method has been
christened electron beam assisted chemical vapor deposition
(EBCVD).205,2o6In this technique, a 2.5 cm wide, shallow electron beam of a
few keV energy is injected into the reactive gases parallel to and a few
millimeters above the substrate surfaces, in much the same way as an
excimer laser beam was used by the same group for laser photo assisted
CVD.198 A localized plasma is created from which excited and reactive
radicals diffuse to and react on the heated substrate surface. Source gas
compositions and flows, pressure, and substrate temperature are all as for
conventional PECVD. However, the advantage of the method is that the
substrates do not sit on one of the electrodes responsible for maintaining
the plasma. Since there is only small angle scattering of the injected
electrons, the substrate surface is largely free of energetic electron
bombardment. However, since the substrate carrying electrode is a boundary
to the localized plasma generated above it, the glow region generally
acquires a small positive bias relative to the substrate and a sheath region
is formed, as described in Sec. 2.1. Thus the substrate surface is subjected
to low energy, positive ion bombardment. The energy distribution of this
ion bombardment is expected to be similar to that originating from a
conventional, high frequency rf plasma (Figure 10), although the ion flux
may be lower. Thus the technique has some of the benefits of indirect
plasma deposition, but without the substrate being so remote from the
plasma. Therefore, the penalty of reduced deposition rates is avoided. As
with photo assisted CVD, this technique will be looked at for applications
where electrical and optical modification of the semiconductor substrate
surface must be minimized.
4.2.2 Source Gases. A source gas for a given element to be incor-
porated into a PECVD film needs to be a gaseous orvolatile compound of
that element. If a mixture of source gases is to be used, as is usually the
case, the combination must be chosen to ensure that the component
gases do not react in the absence of a plasma, otherwise gas-phase
reaction will occur in the mixing manifold, giving rise to particulate incorpo-
ration and pinholing in the deposited film. The specific source gases which
so far have been employed in various depositions are shown in Table 4.
Note that inert gases (Ar, Ne or He) or reducing gases (e.g., H 2) are
frequently used as diluents or carrier gases. Source gases may be obtained
pure, or diluted, in compressed gas cylinders. Volatile liquids or solids are
supplied in bubblers which are mounted in thermostatically controlled
baths to control the vapor pressure. Vapor may be extracted directly or
transported by carrier gas flow. Another technique which has been used
occasionally is that of plasma transport, in which a plasma is used to
decompose or etch a solid and the vapor-phase product is used as a
source for a plasma deposition downstream (Sec. 2.2.2).
4.2.2.1 Safety Aspects. Unfortunately, a large number of the gases
 Plasma Processing 281

commonly used in PECVD are hazardous, being either highly toxic and/or
pyrophoric. Gases such as AsH 3 and PH 3 , used in III-V semiconductor
growth and as dopant sources for amorphous silicon and P-doped Si0 2,
are in the first category. Gases such as SiH 4 and Si 2H 6 and the organo-
metallics and metal carbonyls are in the second category. Thus stringent
safety precautions are necessary in their use. 207 ,208 This usually includes
the use of exhausted gas cabinets, cross flowor body purge regu lators and
dedicated purge gas supplies, and stainless steel plumbing with welded
joints where possible and metal gasket, gland type couplings where
demounting is necessary. In some cases local safety regulations may also
require the use of co-axial plumbing with inert gas purging of the outer
segment. In other cases, maximum concentration limits may be imposed
for the diluted gas mixtures which may be used.
The next safety consideration is the choice of pump fluid. 206 ,207 Use of
the inert perfluoropolyethelene pump fluids is generally the best choice,
even in view of the expense. It is mandatory to avoid the risk of pump
explosion if pure 02 is one of the source gases, or if the plasma process can
°
produce a significant amount of 2 , Plasma deposition chambers are
cleaned by plasma etching, generally using the fluorocarbon gases de-
scribed in section 3. Etching is efficient due to the large quantity of F atoms
produced in these freon plasmas. Since fluorine reacts with hydrocarbon
oils, this is another reason to avoid their use. In PECVD processes, gas
phase reaction between excited radicals continues downstream into the
pumping port, with resultant fine particulate formation in the pumping
lines. Many materials deposited by PECVD are refractory in nature, and in
fine particle form are highly abrasive. Thus it is necessary to employ high
conductance particle filters between the pumps and chamber. In addition,
oil filtration units on the mechanical pumps are necessary, both for fine
particulate removal and for acid neutralization to prevent pump corrosion.
Other necessary pump precautions are to gas-ballast the pump with an
inert gas, beginning this about 15 min prior to pumping the hazardous
gases and continuing it until well after the deposition is complete. Final
safety considerations are that plumbing on the exhaust side of the pump
must also be of high integrity and all metal construction, since this has to
carry unreacted hazardous gases as well as possibly hazardous reaction
products. In the case of toxic gases, appropriate scrubbers are also
necessary in the exhaust line, followed by monitoring of the effluent gas
from the scrubber. Toxic gas monitors should also be available for personnel
safety in the vicinity of PECVD systems.
4.2.3 Uniformity Considerations and Interaction of PECVD
Variable Parameters. It is by no means simple to model deposition rate
as a function of position in a PECVD reactor. Fortunately it is a relatively
straightforward task to establish empirically a particular set of conditions
which give spatial uniformity(assuming the reactor design itself is capable
of giving uniformity). To obtain uniformity it is necessary to strike an
appropriate balance between reactant supply rate and film deposition
rate. This balance is a function of the other deposition parameters.
Forexample, the deposition rate is primarily controlled by the r.f. power
supplied to the plasma, with a sub-linear increase in deposition rate
282 Semiconductor Materials

towards an asymptotic limit determined by the rate of supply of reactants.

Increasing pressure at a fixed flow of reactants will increase deposition
rate at a given rf power level, due to an increased residence time of
reactants within the plasma. Increasing the substrate temperature may
increase or decrease the deposition rate since the sticking coefficients
decrease, but reaction probabilities of the reactive radicals arriving on the
substrate increase. Thus if one has determined the substrate temperature,
the reaction pressure and the ratio of reactant flows, based on the film
properties required, uniformity is then achieved byvarying the total reactant
flow at a fixed power level, or by varying the power level at a fixed total
reactant flow. This is illustrated in Figure 52, for an inward radial-flow
reactor.
If one has a situation as shown in curve (a), one has three choices to
achieve radial uniformity. If the deposition rate at the outer part of the
substrate table is that desired, then it is necessary to keep the plasma
power constant and increase the reactant flows, while keeping the pressure
constant. Since the reactant concentration at the periphery of the table,
where the gases enter the plasma, is unchanged, the deposition rate there
is unaffected. Thus the rate of removal of reactants at the periphery is
unchanged, but the supply rate is higher, so that the concentration of
reactants arriving at mid-radius is increased, and hence so is the deposition
rate there. At the appropriate flow levels, uniform deposition is ach ieved at
the rate in existence at the outer-radius position, as shown in curve (b).
Alternatively, this effect may be understood in terms of residence times.
Increasing reactant flow rates at constant pressure requires increased

b
r - - - - - - - - - - - - - - - - - - - - - - - - - t R MAX

w
ti
n:: RMEAN
z
Q
r-
(f)
0
R M1N
0-
e
w
0

OUTER MID INNER

SUBSTRATE RADIAL POSITION

Figure 52: Deposition rate as a function of radial position, in an inward radial-

flow reactor, for a variety of deposition conditions (see text).
 Plasma Processing 283

pumping speed, and hence reduced residence times. Thus at the periphery,
the higher supply rate is compensated by the reduced residence time, so
that the absolute reactant depletion (and hence deposition rate) is un-
changed, but the fractional depletion is reduced. As discussed in section
2.1.4, the reduced residence time may modify the homogenous and there-
fore also the heterogeneous chemistry, possibly influencing deposited
film properties.
Conversely, if the deposition rate at the inner-radius position is that
desired, then it is necessary to reduce both reactant flows and rf power.
Reduction in rf power alone will reduce the deposition rate at the outer-
radius position, but radial uniformitywill be achieved at the deposition rate
shown in curve (c), which is the mean deposition rate of curve (a). In other
words, reduction in rf power does not reduce the overall consumption of
reactants in the regime between curves(a) and (c), but continued reduction
in rf power below the level producing radial uniformity as shown in curve (d)
reduces mean deposition rate and consumption efficiency. In this regime,
reduction of reactant supply rates can re-achieve uniformity (curve (e)) at
deposition rate Rmin , and restore consumption efficiency.
Uniformity can also be achieved by varying the pressure, and this is
most easily understood in terms of residence time. At fixed reactant flows,
an increased pressure corresponds to an increased residence time. Thus
beginning with the situation depicted by curve (a), reduction in pressure
can achieve uniformity as shown in curve (c). Conversely, an increase in
pressure will produce even greater non-uniformity than that of curve (a).
However, if one has non-uniformity as in curve (d), an increase in pressure
can be used to produce the uniformity of curve (c). This also demonstrates
that at a higher pressure, a lower plasma power is required to produce
uniformity at the same deposition rate.
Experimental data exactly as depicted in Figure 52 are obtained for
the PECVD of Si0 2 from dilute SiH 4 in Arand N 2 0 source gas mixtures(see
Sec. 4.3.2). In this reaction the heterogeneous reaction rates are rapid, so
that the homogeneous chemistry is rate limiting (this assumption is implicit
in the discussion of Figure 52). In a case where the heterogeneous
reaction rates are slower, as for SiN)( deposition, the points made in the
above discussion are relevant to the reactant supply rate rather than the
resultant deposition rate. This tends to make deviations from uniformity
less severe. Rei nberg 184 has given a detai led discussion of spatial uniform ity
considerations, particularly from the standpoint of SiN x deposition.
The level of radial uniformity of deposition rate achieved by the above
methods in an inward radial flow reactor is shown in Figure 53 for three
different deposition rates. This data is for Si0 2 deposition from a 13.56
MHz plasma fed by 3% SiH 4 in Ar and N 2 0. Power density and total flow is
indicated adjacent to each curve. At a deposition rate of 400A min- 1, rate
uniformity can be ±O.5 0/0 as shown, while ±4% can be achieved routinely.
At deposition rates of 700A min- 1 and 11 OOA min- 1 uniformities of ±50/0
and ±7 % respectively can be achieved routinely. It can be seen that at the
highest deposition rate shown, when deposition rates at the inner and
outer radii are matched, the deposition rate in the center of the table is
about 7% lower. This is thought to be a result of the gas flow pattern
284 Semiconductor Materials

wem- 2 SCCM

0.026 372
-------<:0:>-------0-

5 10 15
SUBSTRATE RADIAL POSITION (em)

Figure 53: Actual radial uniformity achieved for PECVD of Si0 2 from 3% SiH 4
in Ar and N2 0 at three different deposition rates, at plasma power densities and
total gas flows as indicated. The area enclosed between the outer and inner radii
is 85% of the substrate table area. (From the authors laboratory.)
l

between the parallel-plate electrodes at this high flow. Gas is injected

around the periphery of the lower electrode and extracted through a
pumping port in the center of the lower electrode. Thus in the mid-radius
substrate position, the peak of the flow distribution is closer to the upper
electrode, making the mean diffusion distance for dissociated, reactive
species to reach the substrate slightly larger.
4.2.4 Film Properties and Their Control. One of the attractive
features of PECVD is its highly non-equilibrium nature and its large number
of variable parameters. This provides wide possibilities to tailor materials
properties to a given application. In addition to being performed at a lower
temperature, relative to conventional CVD, another advantage is that the
deposition rate is decoupled from the substrate temperature, allowing
substrate temperature to become a property determining variable. A
naturally attendant disadvantage is that it may be difficult to reproducibly
achieve the desired properties. Even though PECVD of SiN x has been in
use for about a decade, it is still much more of an art than a science. General
film properties which can be varied, and the main methods employed to
measure that property, are shown in Table 6.
Film stoichiometry is controlled primarily by the ratio of source gas
flows, which may be very different from the film stoichiometry. Plasma
power and frequency, and substrate temperature are secondary variables
for determining stoichiometry. Refractive index and wet etch rate (in an
aqueous acidic etchant, such as buffered hydrofluoric acid) are both
properties which are very much a function of stoichiometry, and hence are
 Plasma Processing 285

Table 6: Film Properties and Measurement Techniques

Film Property Measurement Technique

Stoichiometry Rutherford Backscattering

Auger Electron Spectroscopy
Hydrogen Content Infra-red Spectroscopy
Nuclear Reaction Analysis
Refractive Index Ellipsometry
Interference Effects
Etch Rate Ellipsometry or stylus step
height measurement
Stress Induced Curvature of Substrate
- Optical lever or X-ray
Adhesion Ramped Pull to Failure,
Scribing, Saw Cutting
Conformality Scanning Electron Micrograph
of step coverage
Pinhole Density Use as a chemical or
electrochemical etch mask
followed by optical microscopy

determined by the same deposition parameters. Both refractive index and

wet etch rate are also affected by film density. Refractive index measures
polarizability per unit volume, and thus is related to density(bythe Lorentz-
Lorenz relationship),209 and so increases with increasing deposition temp-
erature. Etch rate decreases with increasing film density, and is often
related to hydrogen content. Since density increases and H content
decreases with increasing deposition temperature, this produces a de-
crease in etch rate. While substrate temperature is the primary variable for
varying H content, plasma power density, degree of ion bombardment
during growth (determined by operating frequency and reactor chamber
pressure), and the nature of H bonding in the source gas all influence the H
content of the film.
Stress is a film property which is currently attracting much attention.
Film stress is dependent on the nature of the substrate, in terms both offilm
nucleation effects and of mismatch of thermal expansion coefficients, as
well as on deposition conditions. Thus, in general, film stress is affected by
deposition rate in relation to substrate temperature, substrate temperature
itself, and the extent of ion bombardment during growth. As a general
empirical observation, increased ion bombardment causes the film stress
to become (more) compressive. Compressive stress in a film produces
convex cu rvatu re of the su bstrate (viewed from the coated side), so that the
substrate in the region close to the film is under tensile strain. High tensile
stress produces poor crack resistance and increases the film/substrate
adhesion needed to prevent film peeling, whereas high compressive
stress can cause blistering of the film. Low compressive stress usually
indicates good crack resistance in a film, a desirable property for most
286 Semiconductor Materials

processing applications. High stress of either sign can also produce a

number of other undesirable effects, such as enhanced defect migration
rates, anisotropic dopant diffusion profiles, modified etch profiles, and
induced interface electronic states. Thus low compressive stress is the
usual goal in the design of a deposition process. In this respect, PECVD has
an advantage over CVD, in which materials such as SiN x are deposited
under high tensile stress. 190
Increased ion bombardment of the substrate and growing film is also
beneficial for improving adhesion at the film/substrate interface. The
origin of this effect is both physical and chemical. Increased flux and/or
energyof ion bombardment increases physical intermixing at the interface
by momentum transfer processes, and also promotes additional chemical
reaction or chemically driven interdiffusion. Increased substrate temper-
ature also increases adhesion by the latter mechanism.
Ion bombardment can impart anisotropy to deposition processes in a
manner similarto that for plasma etch processes(see Sections 2.2.2.1. and
3.2). Two anisotropic effects are possible in deposition, namely anisotropy
of deposition rate or anisotropy of film properties. PECVD intrinsically
shows a 2:1 anisotropy in deposition rate between parallel and normal to
the electrode surfaces, even for isotropic arrival of depositing species.
This is discussed in the following sub-section regarding step coverage.
However, if ion bombardment has the effect of enhancing heterogeneous
reaction rates and thus rate of film growth, the degree of anisotropy is
increased. Similarly, film properties as above which are modified by the
degree of ion bombardment will be expected to show anisotropy, although
we are not aware of any reports in the literature. For example, the wet etch
rate of a film deposited on a vertical wall could be a few times larger than
that of the film on the planar, horizontal surface. If the thickness on the wall
is also more than a factor two lower, this could give rise in a wet etch
process to the vertical wall becoming "cleared" an order of magnitude
more rapidly than the planar surface.
Conformality of coating is a general PECVD property claimed by most
workers except Adams. 191 The difference appears to be the exact definition
of conformality. By conformality, most workers mean good step coverage
without discontinuity over a sharp vertical step, which is either isolated or
at a distance larger than the step height from an adjacent step. By this
definition, PECVD does give conformal coatings, often with better step
coverage than CVD185 for the stress reasons discussed above. This step
coverage can readily be seen from consideration of the arrival angles of
the reactive species at the substrate surface. At a typical PECVD pressure
of 1 torr, mean free paths are about 50 p,m for the reactive atoms and
radicals. Thus these species have suffered many collisions in the gas
phase before arriving on the substrate surface, and therefore have a
random distribution of arrival directions. This gives rise to a deposition rate
proportional to the sol id angle of the plasma presented to a given element
of surface, so that in the absence of macroscopic surface migration film
thickness on an isolated vertical wall is half that deposited on the horizontal
substrate surface, asshown in part(a) of Figure 54, and part(b) of Figure 55.
As the channel width is reduced, this type of coverage produces the
 Plasma Processing 287

-----1.5

- - - - - - - 1.0 (8)

~--------- 0.5

1.5

1.0 (b)

0.5

/
~-------- 1.5

1.0 (c)

0.5

Figure 54: Calculated step coverage over an isolated vertical step (a), and over
vertical-walled channels of increasing depth-to-width ratio (b and c). Film thick-
ness is indicated as a multiple of the step height (from Reference 191 , reprinted
with permission of Solid State Technology, published by Technical Publishing, a
company of Dun and Bradstreet).
288 Semiconductor Materials

Film (a)

Film (b)

Figure 55: Schematic step coverage (a) conformal, resulting from rapid surface
migration, and (b) with coating thickness determined by solid angle presented to
the plasma, for isotropic reactant species arrival, with a mean free path longer
than the feature size, and for surface migration small relative to the feature size
(from Reference 191, reprinted with permission of Solid State Technology, pub-
lished by Technical Publishing, a company of Dun and Bradstreet).
 Plasma Processing 289

profiles shown in parts(b) and (c) of Figure 54. Adams 191 has shown that the
step coverage of 13.56 MHz PECVD Si0 2, SiN x and a-Si follows this profile
shape, implying the lack of surface migration on the scale of a few hundred
nanometers. Thus coatings which are of uniform thickness regardless of
surface topography, as is shown schematically in part (a) of Figure 55, are
not produced by PECVD. Instead, coatings of thickness determ ined by the
acceptance angle from which reactants are arriving with random directional
distribution, with no significant subsequent surface migration, are produced,
as indicated in part (b) of Figure 55. This type of step coverage is much
better than that obtai ned from lower pressu re tech niques such as sputteri ng
in which there is a significant directionality to the depositing species. Thus
PECVD produces coatings with good step coverage, but these coatings
are not conformal in the strictest sense.
Films with very low pinhole densities less than 1 cm- 2 may be produced
by PECVD.185 Certain deposition conditions need to be met to achieve this
level, dependent on the specific material and source gases involved; this
will be discussed in the relevant subsequent section. There are a number
of general practices necessary to obtain low pinhole densityfilms. Substrate
cleaning and wafer handling techniques are obviously of paramount impor-
tance, as is reactor cleanliness. Reactor cleaning is usually carried out by
plasma etching. This should be performed before the deposited thickness
on the electrodes and chamber walls is such that flaking begins to occur;
for high stress films this occurs at smaller thicknesses. Coating the inside
of the chamber with a thin layer of the material to be deposited directly
after the plasma-etch cleaning is a worthwhile judicious practice. Non-
turbulent rough pumping of the chamberdown from atmospheric pressure
is another beneficial practice.

4.3 Materials Deposited and Their Applications

4.3.1 Silicon Nitride. PECVD silicon nitride is not one material, but
a whole family of materials. PECVD silicon nitride films, unlike those
deposited by normal CVD, are not confined to the stoichiometric Si 3 N4
composition. They also contain much larger amounts of hydrogen, typically
15 to 30 atomic %. Frequently they will contain small amounts of oxygen,
particularly close to the substrate interface, gettered in the initial stages of
deposition. Thus a correct compositional description is SiNXOyH Z ; however,
for the sake of simplicity, we will write this in the abbreviated form SiN x210.
Properties of PECVD Si Nx which make it attractive for the sem iconductor
processing applications shown in Tables 3 and 7 are its hardness and good
scratch resistance, its diffusion barrier properties (to H 20, Na+, and most
dopant atoms), its good adhesion to silicon, III-V compound semiconductors,
other dielectrics and most metallizations, including Au, and its rapid and
uniform plasma etching characteristics. These material specific properties
are in addition to the general PECVD properties discussed in the preceding
section. Schuermeyer211 has reviewed a number of these applications of
SiN x in GaAs processing, and Vanner et al. 212 have described applications
in GaAs integrated circuit fabrication.
There is now a wealth of literature concerning PECVD SiN x' its properties
and their dependence on deposition conditions. Good general coverage
290 Semiconductor Materials

of these topics has been given by Sinha et al.,209,213,214 Reinberg,184 Mar

and Samuelson,215 Rosier and Engle,203 and van de Ven. 185 Maes et al. 216
have recently reported a com parative study of properties of films deposited
in a wide range of commercially available PECVD systems.
4.3.1.1 Source gases and operating frequency. Source gases usually
employed are SiH 4 for Si and NH 3 and/or N 2 for N. Inert carrier gases or
diluents are often used also; the use of He has recently been reported 217 to
be beneficial to deposition uniformity. N 2 is generally used in place of NH 3
in an attempt to reduce the H content of the film; N 2 can be obtained at
higher purity than NH 3 , and also is non-toxic. A disadvantage of the use of
N2 is that the energy to produce an electron-ion pair is higher than that
from N H3,188 and the N 2 dissociation kinetics are much slower than those
of NH 3 .187 This means that an increased N-source to SiH 4 flow ratio is
necessary( discussed below), with either an increased rf powerdensity or a
reduced deposition rate. The latter point is demonstrated in Table 8, in
which the ratio of deposition rate to plasma power density (obtained from
data reported by various groups) is shown. This plasma-power-normalized
deposition rate, in conjunction with the operating frequency, inversely
indicates the dose of energetic incident species received by the sub-
strate/film interface in the initial stage offilm deposition. In addition, it is a
simple inverse indicatorofthe degree of plasma enhancement required by
the reaction in question. At both high and low rf frequency, this ratio is
significantly smaller when N 2 is employed in place of NH 3 . This is an
important consideration regarding physically-induced interfacial modifica-
tion (see Sec. 4.4). It may also be observed from Table 8 that low frequency
deposition, from either N H 3 or N 2 sources, produces higher deposition
rates, suggestive of an ion assisted surface reaction. This is further discussed
below in regard to the lower N 2/SiH 4 flow ratio required at low frequency.
The first reported plasma deposition work, two decades ago, deposited
SiN x from SiH 4 and NH 3.218This was followed a few years later bydeposition
from SiH 4 and N 2.219,220 The radial flow reactor 201 was developed for SiN x
deposition.
In determining which process or process conditions to employ for Si N x
deposition for a given application, it is essential to prioritize the film (or
interface) properties needed for that application. For example, for an
antireflection coating application, refractive index is the primary require-
ment, but low stress and perhaps a low density of induced interface states
may also be desirable. Table 7 indicates the necessary film properties for
various processing applications in which SiN x has been used. It is also
necessary to identify which of these properties are dependent more on
pre-deposition surface cleaning procedures than on the deposition condi-
tions themselves. Having established the required film properties, the
necessary deposition conditions may then be determ ined. Early decisions
to make are whetherto use N H 3 or N 2 as the N source gas, what frequency
plasma is to be used, and whether pure SiH 4 or a dilute (s5 % ) SiH 4 in inert
gas or N 2 is to be used. This option scheme is shown in the flow chart of
Figure 56. Rarely is a choice clear-cut, in that the same result can be
obtained by more than one combination of these three parameters, particu-
larly when one allows for variation in the subsequent deposition parameters
 Plasma Processing 291

Table 7: SiN x Film Property Requirements for Processing Applications

Processing Application SiN x Property Requirements

Device Passivation Diffusion barrier to H2 0, Na+ etc; low stress, good

adhesion; good step coverage; pinhole free; low density of induced
surface states.
Diffusion Mask Diffusion barrier to the dopant in question; low stress;* thermal
stability; good adhesion; pinhole free;
Implant Mask Low stress, good adhesion.
Epitaxial Growth Mask Low stress;* thermal stabilit.y; good adhesion.
Etch Mask Low stress; good adhesion; pinhole free.
Implant Anneal Cap Low stress*; good adhesion; thermal stability; pinhole free.
Laser Facet Coating Diffusion barrier to 0 27 H 2 0, Na+;
low stress; reproducible R.I.; (resistive); minimum induced optical
modification; pinhole force.
Anti-reflection Coating Adjustable, reproducible R.I.;
low stress; minimum induced surface states.
Oxidation 11ask Diffusion barrier to 0 27 OH; thermal stability.
Gate Dielectric Low stress; mininum induced interface states;
reprod. H cont. (low H content).

*at the process temperature

LOW DILUTE
FREQUENCY SiH4
RF

HIGH
FREQUENCY PURE
RF S iH4

Figure 56: Decision chain for selecting a Si N x PECVD process.

listed in Table 5. However, in some cases there is a clear choice. For

example, if low hydrogen content is the highest priority, then low frequency,
N2 , and dilute SiH 4 is the necessary combination of these parameters.
However, this combination has been found to lead to quite high compres-
sive stress in the film at room temperature. This may not be a drawback if
the film is to be used in a high temperature application, where the com-
pressive stress will be somewhat relaxed due to the lower linear coefficient
of thermal expansion of the SiN x relative to the semiconductor substrate.
This will be discussed later in this section.
292 Semiconductor Materials

Silane dissociates very readily in a plasma, even more so than ammonia.

Therefore in order to deposit films with close to bulk stoichiometry(Si/N =
0.75, refractive index ~ 1.95), it is necessary to employ an excess of NH3.1 n
general, a NH 3/SiH 4 and N 2 require a very large excess of N2. Forexample,
in a parallel plate system at 13.56 MHz, Dun et al. 221 found that an N 2/SiH 4
flow ratio of 100 was needed. In an inductively coupled system, where only
the N 2 was fed directly through the plasma,222 an N2/SiH 4 ratio of 250 was
found necessary to obtain the approximately stoichiometric composition.
In the early work using SiH 4 /N 2 mixtures also in inductively coupled tube
reactors,220,223 N 2/SiH 4 ratios of 200 and 670 respectively were found to
be necessary. However, in a parallel plate system at low frequency (30
KHz) a N 2/SiH 4 ratio of~ 4 (Reference 224) and 25-50 (Reference 225) was
found to be sufficient although at low pressure, and high flow rates a flow
ratio in excess of 120 was found to be necessary.202 The origin of the
apparent effect of a lower N 2/SiH 4 ratio being necessary to obtain a given
stoichiometry at low (relative to high) plasma frequency is not clear. As
discussed in Section 2.1.2.1.4 for a single component plasma, the degree
of dissociation at a fixed power density is larger at high frequency where
power dissipation is concentrated within the glow region. If this generality
is still valid for a two component plasma consisting of one easily dissociated
and ionized component (SiH 4) and another component with much higher
dissociation and ionization energies (N 2), then one must hypothesize that
the increased ion bombardment at low frequency enhances the rate of
reaction between absorbed Nand SiH x radicals, perhaps by Si-H bond
breaking. This picture is supported by the higher normalized deposition
rates (Table 8) and the lower H content offilms deposited at low freq uency,
and is analogous to the etching situation depicted in Figure 12(a) and
discussed in Sec. 2.1.2.1.4.
A point to be stressed regarding SiN x deposition is the importance of a
leak-tight chamber and gas input lines. Reactive Si and Si-H radicals
adsorbed onto the substrate surface will preferentially react with an 0
containing species produced by a minor air or water leak into the plasma,
even when NH 3 is used as the N source. The problem is even more severe
when N 2 is used. In addition, all parts of the chamber which come into
contact with the plasma should be well out-gassed before commencing a
Si N x deposition. If the substrates can be adequately protected, outgassing
can be readily achieved by running an Ar or N 2 plasma, but such protection
is difficult in a radial-flow reactor.
4.3.1.2 Film properties and their correlations. The range of values of
properties of PECVD SiN x films which are used in processing applications
are shown in Table 9. The general methods of control of these properties
have been discussed in section 4.2.4. In addition, there are a number of
property dependences specific to SiN x' The deposition parameter de-
pendences of four important film properties are summarized in Table 10.
The refractive index increases with increasing SiH 4 /(NH 3 or N 2) flow
ratio due to an increasing Si/N compositional ratio in the film. This is also
the cause of the increase in refractive index with increasing rf frequency,
and with decreasing rf power. The latter case is due to the decrease in
dissociation of the N source gas, whereas we have speculated above that
 Plasma Processing 293

Table 8: Ratio of SiN x (R.I. == 2) Deposition Rate to RF Power Density

()\ min -1 w-1 cm 2 ) as a Function of Nitrogen Source and Plasma Frequency

(.A min- 1 \\'-1 cm Z) as a Function of Nitrogen Source and Plasma Frequency

N Source
RF Frequency

High 2200-600&
(>5 ~1Hz) 620b
770 e
J320 d

Low 2240 e
«1 MHz) 2330 f
JOOO e

a. Reference 213
b. Reference 217
c. Reference 232
d. Reference 225
e. Reference 185
f. Reference 202

Table 9: The Range of Values of Important Properties of PECVD SiN x and

Si0 2 as Used in Processing Appl ications

Property SiNx SiO z Units

Stoichiometry 0.7 - 1.2 0.50 - 0.55

(SijN or SijO)
Refractive Index 1.85 - 2.3 1.46 - 1.55
Optical Absorption Edge 300-450 <300 nrn
H Content 15-30 0.5-8 at%
Etch Rate 30-1000 2000-4000 A min- 1
(in 6:1 BHF)
Stress 5T - 10Cx lOP (0.5- 3)CX lOll dynes em- z
Adhesion >6X 10 8
>2.5 X 10 8 dynes cm- z
(to Si, Ga~, InP)
Resistivity 1011 -10 17 10 14 - >10 17 Oem
(at 10eV em-I)
Dielectric Breakdown Strength 1-6 3-8 X lOll Vcm- 1

the former case is due to the ion assisted nature of the heterogeneous
reaction. Its increase with increasing deposition temperature is mainly
due to increased density of the film. The optical absorption edge of the film
also moves to longer wavelengths with increasing Si/N compositional
ratio. 226 The refractive index of the film has been shown to be linearly
related to both its Si/N rati0 227 and its(Si-H)/(N-H) rati0 227 ,228(measured by
294 Semiconductor Materials

IR absorption spectroscopy), which indicates the bonding distribution of

the H content of the film. In both these references, these property correla-
tions were forfilms deposited at a 50 KHz plasma frequency from NH 3 and
SiH 4 source gases. However, while Claassen et al. 227 found a linear correla-
tion of refractive index to Si/N as measured by Rutherford backscattering
(RSS), Samuelson and Mar228 did notfind the same correlation with the film
Si/N ratio as measured by Auger Electron Spectroscopy (AES). The RSS
stoichiometry data is probably the more reliable, since that technique is
directly quantitative. Maes et al. 229 have discussed the difficulties in
making quantitative AES analyses of SiN x films. Figure 57 reproduces the
refractive index correlation with (Si-H)/N-H) from both References 227
and 228.
From the data in Figure 57, the refractive index,

n = 0.70(SijN) + 1.39 (31)

and from Figure 58(a)

n = 0.050[(Si-I-I)j(N-II)] + 1.88 (32)

which combined yield:

(SijN) = O.084[(Si-I-I)j(N-fI)] + 0.70 (33)

i I I I I I I
0

2.6 • SiH4 -NH3 -N 2

2.5
• SiH, -NH 3 -H 2
o SiH, -NH 3 -Ar /
n
2.4
/
t
23
2.2
/+
0&+
2.1 /
0. 0 •
2.0
. ... ~
.~

1.9 11:• .0
I

0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.S 1.6 1.7
--+Si/N

Figure 57: Correlation of Si N x refractive index with Si/N compositional ratio of

the fil m, as measured by RBS (from Reference 227, reprinted by permission of
the publisher, The Electrochemical Society Inc.).
 Plasma Processing 295

which indicates, as observed, that at a high (Si/N) ratio, most of the H

content is bonded to Si. This is in qualitative agreement with the report 221
that for films deposited from SiH 4 /N 2, increasing plasma power changes
the dominant H bonding from Si-H to N-H.
In addition, Claassen et al. 227 have shown the dependence of the etch
rate(in 7:1 buffered HF at R.T.) on(Si/N), oralternativelyon [(Si-H)/(N-H)] by
equation 33, forfilms deposited from SiH 4 /NH 3 at 50 KHz and 300°C. This
is reproduced as Figure 59. Overtheirfairly limited range of total H content,
no correlation could be seen between etch rate and total H content.
However, over a wider range of total H content for SiN x films deposited in
various commercial PECVD reactors under a wide variety of conditions,
Chow et al. 230 have shown good correlation between the etch rate and total
H content (measured by the 15N nuclear resonance reaction technique,
described below), over three decades of variation in etch rate. These data
are reproduced as Figu re 60. These workers have also reported a relatively
weakcorrelation between etch rate and film stress, with films undertensile
stress etching more rapidly than those under compressive stress. As
shown in Table 10, the deposition parameters which affect the etch rate
are substrate temperature, rf power density and rf frequency. Increasing
substrate temperature decreases the etch rate, for example by an order of
magnitude from 200°C to 400°C, due to both reducing the H content and
increasing the film density. Increasing rf power density decreases the etch
rate, mainly by reducing the H content to the same extent as reducing the rf
frequency to the low frequency regime. As also ind icated for H content, use
of N 2 in place of NH 3 and use of diluted SiH 4 will also reduce the H content
and hence the etch rate.
Stress in PECVD SiN x films can be varied over a very wide range, as
shown in Table 9. The manner in which various deposition parameters
affect stress is shown in Table 10. In general, high frequency deposition
produces low to medium tensile stress, which is not good for crack
resistance or step coverage. However, higher power deposition and use of
dilute SiH 4 sources reduces this tensile stress, in some cases sufficiently
enough to convert it to the desired low compressive stress. Use of N 2 in
place of NH 3 also aids this conversion. For example, it has been reported 221
that at low deposition rate and an N2/Si H 4 flow ratio of 65, the stress in Si N x
deposited on Si was changed from 1X1 0 9 dynes cm- 2 tensile to 5X1 0 9
dynes cm- 2compressive by increasing the plasma power from 50 to 300W.
Low frequency deposition from SiH 4 and NH 3 source gases produces low
to medium compressive stress, while use of N 2 at low frequency tends to
produce high compressive stress. Koyama et al. 231 have measured the
change in stress in SiN x films deposited in the same parallel-plate reactor
from SiH 4/NH 3 for rf frequencies varied over the range 50 KHz to 13.56
MHz. Variation in stress was over the range shown in Table 9, with cross-
overfrom compressive to tensile stress occurring at about 2 M Hz. Martinet
et al. 232 have also shown a similar change in stress in the SiN x film
produced by changing from 50 KHz to 13.56 MHz, although their stress
values at each frequency were lower than those of Koyama et al. 231
Most of the reported stress data is for SiN x films deposited on Si
substrates. However to a first approximation similar stress values are
measured for films deposited on GaAs and InP substrates. The stress
296 Semiconductor Materials

I I

2.6 • SiH4 -NH3 -N 2

/-
0
+ SiH 4 -N~-H2
2.5
o SiH 4 -NH 3 -Ar +

n
2.4
/
t 2.3
/
a
2.2 0

2.1 0
+/0
+ d'
2.0 04'
o;~
+
1.9 ..
;/
I

0 1 2 3 4 5 6 7 8 9 10 11
--. Si-H/N-H

2.40
0

2.30
><
w
C 0
z 2.20
w
b >
i=
u
~ 2.10
a:
u.
w
a:
2.00

0
1.90

1.80
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
Si-H/N-H BOND RATIO

Figure 58: Correlation of SiN x refractive index with (Si-H)/(N-H) hydrogen bond-
ing ratio in the film: (a) from Reference 227, deposition temperature 300°C;
(b) from Reference 228, deposition temperature 275°C (both reprinted by per-
mission of the publisher, The Electrochemical Society Inc.)
 Plasma Processing 297

100 r---r--.,...-----,--......---,--..,..----r-----w

90 -
.SiH, -NH3 -N 2
R
(nm/min)80 •.+SiH, -NH 3-H 2
oSiH 4 -NH 3 -Ar
t 70 -

60
50
40
30
20
10 -

0.6 0.8 1.0 1.2 1.4 1.6 1.8

----. Si/N
Figure 59: The etch rate of SiN x films in 7:1 buffered HF at room temperature
as a function of their (Si/N) compositional ratio. The films were deposited from
SiH 4 /NH 3 /carrier gas mixtures at a 50 KHz plasma frequency and 300°C sub-
strate temperature (from Reference 227, reprinted by permission of the publisher,
The Electrochemical Society Inc.).

measured in a film at room temperature can be separated into two com-

ponents, one being thermally-induced during cool-down from the deposi-
tion temperature due to the difference in linear coefficients of expansion
of the film and the substrate, and the other being the intrinsic stress in the
film as-deposited. Retajczyk and Sinha 233 deposited Si N x films onto differ-
ent substrates (silicon, quartz and sapphire) of known expansion coeffici-
ents, and then measured stress as a function of temperature. From these
data they computed both the elastic stiffness, and the linear coefficient of
expansion a of their high frequency deposited SiN x' Elastic stiffness, E/(1-
v), where E is Young's modulus and v is Poisson's ratio, of the SiN x was
found to be 1.1 X 10 12 dynes cm- 2 , and a determined to be 1.5X 10- 6 °C- 1 . This
latter value is about half that for bulk Si 3 N4 . Use of these two values in
conjunction with asubstrate permit the thermally induced film stress com-
ponent, afT' to be calculated for SiN x films deposited on other substrates,
by the relationship:

af,T = [E/(l- v)]f (Gf- Gsubstrat(J~"r (34)

298 Semiconductor Materials

:: PLASMA DEPOSITED SILICON

NITRIDE
• ~
r-----

4'
... -..
•
-
fir •

- ...•-•
.•
~

• •
10
.
~LPCVD
""\

o
I
10 20 30 40 50 60
0/0 H

Figure 60: The etch rate of SiN x films in buffered HF as a function of their total
H content (from Reference 230, reprinted with permission of the American In-
stitute of Physics).

Table 10: Direction of Increases in Deposition Parameters on PECVD

Si Nx Properties

Increase of Dep. RF RF SiH 4 /(NHs or N 2 ) N 2 in place

Effect on Temp. Power Freq. Flow Ratio ofNHs

Refractive Index 1 ! 1 1 1
Etch Rate ! ! 1 ! !
H Content ! ! 1 - !
Stress, Tensile - ! 1 ! 1

where 6. T is the difference in temperature between the deposition and

stress measurement temperatures. A positive (TtT calculated by equation
34 corresponds to a tensile stress in the film. Thus for SiN x deposited on
GaAs (a=6.4X 10-6°C-1) and InP (a=4.5X 10-6°C-1) at 300°C, the thermally-
induced contributions to room temperature stress are 1.5 and 0.91 X1 0 9
 Plasma Processing 299

dynes cm- 2 compressive, respectively. Thus it can be seen that in most

cases, the thermally-induced component is a minor contribution to the
measured stress. Similar calculations are also very useful to estimate the
stress in the film when used in an application at elevated temperature. This
will only be an estimate, however, since loss of hydrogen and film densifi-
cation will be taking place simultaneously.
Resistivity of PECVD SiN x can be varied over many orders of magnitude
by varying the Si/N compositional ratio of the film, by the methods indicated
in Table 10. Sinha and Smith 234 have shown that the resistivity rr varies
according to 1n(rr- 1 ) ex: (Si/N), from a value of 10 16 Ocm at (Si/N)=0.75, to
10 10 0 cm at (Si/N)=1.33. Theirdata are reproduced as Figure61. Dun et al. 221
found basically the same relationship for SiH 4 /N 2 deposited films. Note
that at the highest resistivity end, resistivity is quite sensitive to trace
impurities incorporated into the film. Electrical properties have recently
been reported 235 for low frequency PECVD SiN x '

20
10
400W

18
10
350W

E
u 16
....... 10 \
>
(Q

~
,
~300W

N 101 4
0
E
u
c: 10'2
>-
I-
>
I-
(J) -dO
U)
l~
a::

8
10

6
10

4
10
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
si/N
Figure 61: Resistivity vs. (Si/N) compositional ratio for PECVD SiN x (from
Reference 234, reprinted with permission of the American Institute of Physics).
300 Semiconductor Materials

4.3.1.2.1 Measurement of hydrogen content. Having discussed the

strong influence on film properties of both total H content and distribution
of that H content between Si-H and N-H bonds, it is worthwhile briefly
discussing their quantitative measurement. Total H content is measured
absolutely by the resonant nuclear reaction.

(35)

which occurs between an H atom and a 6.405 MeV 15N+ ion. Emitted y rays
are counted. Depth profiling of the H content is achieved by scanning the
incident 15N ion energy upwards from 6.405 MeV. Lanford and Rand 236
used H content data obtained from this nuclear reaction analysis to
provide calibration of infra-red absorption band intensities of the Si-H and
N-H bonds. Adams 191 has summarized the wavenumbers and the calibra-
tion constants of the various Si-H, N-H, and O-H IR absorption bands, as
well as the wavenumbers of Si-O and Si-N bands, which can be observed in
the IR spectra of PECVD SiN x' and Si0 2 and a-Si(H) films. These values are
shown in Table 11. The calibration coefficient K, which is related to the
oscillator strength of the transition, is defined by:

NH = K J a(w)dw (36)

where N H is the number of H bonds per cm 3 and a(w) is the absorption

coefficient (cm- 1) at wavenumber w(cm- 1 ).
4.3.1.3 Recent advances. SiN x films have very recently been deposited
from SiH 4 /NH 3 by electron beam created plasma-enhanced CVD,206 re -
ferred to as EBCVD as discussed in Section 4.2.1. In addition to the
reduced energetic particle bombardment, a further attractive feature was

Table 11: The Position and Strength of the Various IR Absorption Bands
Observed in PECVD SiN x , Si0 2 , and a-Si(H)a

Si0 2 SiN a-Si K

A~signment (wavenumber, em-I) (l016 cm -l)

OIl 3620 1.4

OH 3380 0.4
NH 3340 8.2
BH 2530
SiH 2270 2170 2000 7.1
NH 1170
SiO 1070
SiGH 940
SiR, SiOH 885
SiN 850
SiO 805
SiH 630 2.5
SiN 465
SiO 450

aFrom Reference 191, reprinted with permission of Solid State Technology,

published by Technical Pu blishing, a company of Dun and Bradstreet.
 Plasma Processing 301

the low H content (rv 12 at 0/0) and the undetectability of any Si-H bonded
hydrogen. The origin of this effect is unclear, since in conventional PECVD,
a reduction in H content is achieved by increased ion bombardment(Table
10). It will be interesting to see the level of stress in these films.
A very interesting method of improving the thermal stability of PECVD
SiN x has recently been reported by Fujita et al. 237 On the basis that the H
content cannot be reduced below about 15 at % (Table 9), their approach
was not to minimize the H content, but instead to give it thermal stability by
increasing the H bond strength. This was achieved by simultaneously
incorporating fluorine into the SiN x film, by performing its PECVD from a
SiF4/N2/H2 source gas mixture. It has previously been reported that Si-H
bonds in fluorinated a-Si(H) have increased stabilitY,238 and so the same
effect was expected in SiN x' Thermal stability was indeed improved, in that
annealing at 640°C could be performed without loss of H. However, this
was not the result of an increased Si-H bond strength, since no Si-H bonds
were present in the fluorinated SiN x film, but rather an improved N-H bond
strength. Use of H 2 as a component source gas was necessary to permit
deposition to occur, otherwise etching of the deposited film by the atomic
F produced from the SiF 4 occurred. The function of this H 2 in suppressing
etch ing relative to deposition was attributed to a more rapid removal of the
product F atoms, due to both the reduced residence time and chemical
scavenging.
4.3.2 Silicon Oxide PECVD silicon oxides are a much narrowerclass
of materials than the nitrides, in that their composition is close to stoichio-
metric, with a typical range of SilO ratio from 0.50 to 0.55, as shown in Tabl.e
9, and much lower hydrogen content than the nitrides. On this basis, we will
refer to these materials as PECVD Si0 2 . Partly for these reasons, the
properties of PECVD Si02 show much less variability than those of PECVD
SiN x as shown by their comparison in Table 9. Thus it is an easier task to
deposit Si0 2 films with reproducible properties for use in semiconductor
processing, where they are finding increasing application. A number of
these applications are shown in Table 3. Other factors favoring the use of
PECVD Si0 2 are its low compressive stress, which is almost independent
of deposition conditions over a wide range, its high deposition rate at low
plasma power, its lower deposition temperature and its lack of susceptibility
to the effects of small amounts of air or water vapor contamination of the
deposition plasma. The main applications area in which Si0 2 does not
perform at least as well as SiN x is that at elevated temperature (>500°C)
where diffussion barrier properties are required. This includes applications
such as implant anneal caps on III-V semiconductors (where diffusion of
the more volatile group V element is to be prevented) and dopant diffusion
masks.
The usual source gases for Si0 2 deposition are SiH 4and N20,185,218,239,240
often with the SiH 4 diluted in an inert gas such as Ar. Other source gas
combinations which have been employed are SiCI 4/0 2,241 and in some
early work, Si(OC2HJ4/02.242 The most obvious combination of SiH 4 and 02
cannot be used, since these gases will react spontaneously on mixing (in
the absence of a plasma) to form Si0 2 "smoke" in the gas phase. N 20 is
chosen as the source of 0, since it dissociates readily in a plasma, although
302 Semiconductor Materials

rather less readily than does SiH 4. Because of this, N 2 0/SiH 4 flow ratios
appreciably in excess of 2 are needed to deposit Si0 2 ; the necessary
N20/SiH 4 flow rati0 239 is usually in excess of 15. However, N 20 is more
°
easily dissociated than CO 2 , another possible source, where CO 2/SiH 4
flow ratio of around 200 were needed. 240
Si0 2 is deposited at a higher rate and lower power than SiN x . Deposi-
tion rates employed are usually in the range 250-800A min- 1, although
rates in excess of 2,000A min- 1 can readily be achieved, with some loss
of spatial uniformity. Thus the deposition rate to plasma power density
ratio in a radial-flow reactor is very high, with values ranging from 3,000
A min- 1W- 1cm 2 (Reference 240) to 27,000A min- 1W- 1cm 2 (Reference 239).
These values may be compared with those in Table 8 for SiN x deposition.
Since plasma powers are very low and spatial uniformity of deposition is
sensitively dependent on plasma power (see Section 4.2.3), improved
sensitivity of power monitoring and control is beneficial. For deposition from
SiH 4/N 20/Ar plasmas, this may be achieved by monitoring the broadband
optical emission intensity from the plasma (see Section 4.2.3), which con-
sists almost entirely of near infra-red Ar emission. 243 If Ar is not included in
the plasma composition, the main emission is in the near ultraviolet from
N2 and is much weaker, and thus the technique's sensitivity for deposition
rate and uniformity control is much reduced.
Effects of PECVD parameters on Si0 2 film properties were studied by
Adams et al 239 for high frequency deposition, and by Hollahan 24o and van
de Ven 185 for low frequency deposition. In the work of Adams et aI., for Si0 2
deposited at a relatively low rate, many fil m properties were shown to have
a large discontinuous change at a temperature between 175 and 200°C.
Below that temperature, the films etch rapidly and non-uniformly, have
reduced density and refractive index, and have higher stress. Thus films
deposited below 200°C are not useful in processing applications (at least
forfilms deposited with the other deposition parameters similarto those in
Reference 239).
The refractive index of PECVD Si0 2 is mainly determined by the SilO
stoichiometry which is a function of the SiH 4/N 20 flow ratio. Above a
SiH 4/N 20 ratio of 15 to 20 (and for a deposition temperature of 200°C or
above), refractive index remains constant at 1.47. This value is very slightly
higher than that of CVD Si0 2 (1.44 - 1.46) or thermally grown Si0 2(1.464),
and is probably the result of a very slight oxygen deficiency «2%). This is
supported by the film density (rv 2.30 gm cm- 3) which is slightly higher than
that of fused Si0 2 (2.20 gm cm- 3). This small amount of ° deficiency
possibly results from some Si-H and Si-OH bonding existing in the film.
Lower temperature deposition, or high rate deposition at around 200°C,
produces a lower refractive index due to a reduced film density. There is
evidence that films deposited at low frequency have a somewhat higher
refractive index, in contrast to the situation for SiN x deposition. A value of
1.54 has been reported 185 for low frequency deposition in an outwards
radial-flow reactor at an N 20/SiH 4 flow ratio of 50. The reason for this
higher refractive index appears not to be excess Si, but instead some N
°
content in the film in place of content. A composition of Si01.9No.15 was
reported; 1U5 a few percent N content for similarly deposited films has also
 Plasma Processing 303

been observed by XPS analysis (ESCA).240 Presumably this N content is a

result of N2+ and/or N+ ion bombardment of the growing film which occurs
at both higher energies and higher fluences at low frequency relative to
high frequency.
Hydrogen content of PECVD Si0 2 is much lower than that of PECVD
SiN x' even forthe lower deposition temperature usuallyemployed for Si0 2.
The reason for this is the higher reactivity of Si-H radicals towards atomic
oxygen than towards N-H radicals or other reactive N containing species.
Thus the heterogeneous reaction between Si-H and atomic °
substrate surface occurs rapidly and almost to completion before the
on the

reactants are buried by further depositing material, whereas with Si-H and
N-H reaction to completion does not occur. 185 A disadvantage of the high
°
reactivity of Si-H and is that under certain conditions (high rf power, high
pressure, low flow rate), homogeneous gas phase reaction can occur,
giving rise to particulate contamination and pinholes in the deposited film.
As is the case for SiN x deposition, increased substrate temperature,
increased rf power density and reduced plasma frequency all act to reduce
the H content. A typical range of values isasshown in Table9. The H maybe
present in three different bonding configurations, which are Si-H, Si-OH
and H 20. Their respective IR absorption bands are shown in Table 11. H 20
can be formed in the film during deposition by reaction between H atoms
produced on the surface from Si-H reaction with 0, and other arriving
atoms. Its formation and incorporation into the growing film is reduced by
°
increasing substrate temperature, but is not sensitively dependent on
other deposition parameters. 239 The Si-OH content is similarly dependent
on substrate temperature, and at low N20/SiH 4 flow ratios «20), in-
creases with the N20/SiH 4 flow ratio along with the increase in Si-O
bonding. As to be expected, the Si-H content decreases with increasing
N20/SiH 4 flow ratio, with increasing rf power, and with decreasing SiH 4
content in the discharge. Forfilms deposited at 200°C, the total H content
is about 5 atomic %, distributed approximately in the ratio 9:4: 1 as H 20:Si-
OH:Si-H. At a 250°C deposition temperature, this can be reduced to 2
atomic % or lower.
The etch rate of PECVD Si0 2 films in HF containing etchants does not
show any strong correlation with H content, or even with overall composition.
The main variation is a slight decrease with increasing deposition temper-
ature above 200°C. For deposition temperatures below 20QoC, films etch
rapidly and inhomogeneously.239 Etch rates are typically about an orderof
magn itude faster than those of thermally grown Si0 2, and a factor of 2 or 3
faster than those of sputtered Si02. This may be due to increased porosity,
although this idea is not supported by the density of PECVD Si02, which is
higher than that of thermal Si02 .239
Stress in PECVD Si0 2 also shows far less variability with deposition
conditions than does that in PECVD SiN x . In all cases for PECVD Si0 2 '
deposited on Si, GaAs or InP substrates, the Si0 2 is in the desirable state of
being under low compressive stress. The stress magnitude is increased to
values at the upper end of the range shown in Table 9 by deposition from
dilute SiH 4 in Ar, or by deposition at low frequency. Stress in Si0 2 films
deposited on Si are lower than in those deposited on GaAs or InP, due to
304 Semiconductor Materials

there being less of a thermal mismatch (which is quite large in all cases).
The linear coefficients of thermal expansion are 0.6, 3.2, 6.4 and 4.5 X
10-6°C-1 for Si0 2, Si, GaAs and In P respectively. Elastic stiffness coefficients
have not been reported for PECVD Si0 2, but the values for fused silica
should provide a reasonable upper limit close the the correct values. Thus
using a value of [E/(1 -u)]Si02 = 0.85 X 10-2 dynes cm- 2 in equation 34, the
thermally-induced components of stress in Si0 2 films deposited on Si,
GaAs and InP at 250°C are found to be 0.5,1.1 and 0.75 X 10 9 dynes cm- 2
compressive. While these values are not large on an absolute scale, they
can correspond to being the major component for the Si0 2 films of lowest
stress.
The combined properties of low compressive stress and good adhesion
permit very thick films of PECVD Si0 2 to be deposited without blistering or
cracking occurring. Thicknesses up to 5,um have been deposited. 185 Films
of 3,um thickness have been deposited on GaAs and then patterned by
anisotropic, low frequency plasma etching to leave 3,um wide by 3,um high
stripes of a few centimeters in length which have not lost adhesion to the
substrate. 14o These stripes have then been used as proton implant masks
in the fabrication of proton bombarded, gain-guided GaAs lasers. 244
PECVD Si0 2 fi Ims have consistently high resistivity(Table 9) relative to
SiN x due to less compositional variation and a higher band gap. Additionally
Si0 2 has a lower dielectric constant than SiN x (3.8 relative to ~7.0 at 1
MHz). Both these properties make PECVD Si0 2very attractive for application
as an interlayer dielectric.
The recently developed electron beam CVD (EBCVD) variation of
PECVD, discussed in Sec. 4.2.1 and in the preceding section for SiN x' was
first used to deposit Si0 2.205 Bulk film properties reported were similar to
those of good quality PECVD films deposited at the same temperature,
except for a high pinhole density. It is to be hoped that this is not intrinsic to
the technique, although gas phase reaction and particulate formation
cou Id be a problem with in the localized hig h intensity plasma, just as it is at
high plasma power densities in conventional PECVD of Si0 2.
In another recent advance, Kaganowicz et al. 245 have employed magne-
tron assisted PECVD to deposit Si0 2 at room temperature. The magnetic
confi nement of the plasma increases its density and increases the dissoci-
ation of N 20, so that stoichiometric films (n~ 1.46) could be deposited at an
N20/SiH 4 flow ratio of about three, an order of magnitude lower than that
needed without the magnetic enhancement. The much reduced total gas
flow, as well as the magnetic enhancement, permitted a much lower
deposition pressure (45 mtorr) to be used. At higher N 20/SiH 4 flow ratios,
gas phase reaction was again a problem, producing particulate incorporation
in the film. However, at N 20/SiH 4flow ratios offive or less, featureless films
were deposited. Non-uniformity of deposition rate and film properties is a
problem which will need to be overcome. Film characteristics were not
reported; it will be very interesting to compare them to those of conventional
PECVD Si0 2 films deposited at 200-250°C, as well as to those of films
deposited at lower temperatures.
4.3.2.1 Silicon oxynitride. So farwe have not mentioned intentionally-
 Plasma Processing 305

deposited silicon oxynitrides, SiOXNyH z. This is the same compositional

formula which we quoted as being strictly correct for silicon nitride, but in
this case x is rather larger. Obviously the previously discussed silicon
nitride and oxide are the extremes of this compositional series, and the
properties of silicon oxynitride films can be varied anywhere in between
those of silicon nitride and oxide prepared under similar conditions. As
discussed in Section 4.3.1, the properties of the endpoint composition,
Si NyH z' can themselves be varied over a wide range. Th us the use of sil icon
oxynitride offers the opportunity of obtaining a combination offilm properties,
optimized for a given application, not accessible with either of the end-
point compositions.
Silicon oxynitride is deposited from SiH 4/N H3/N 20 source gas mixtures,
with orwithout inert gas diluents. Nitrogen to oxygen stoichiometry, y/z, is
controlled by the NH3/N 20 flow ratio, bearing in mind that the heterogeneous
°
reaction between adsorbed Si-H radicals and atoms is more rapid than
thatwith N or N-H species. Hence most of the available Owill beconsumed
in preference to N. The nitrogen source used must be NH 3 and not N 2 for
the deposited film to have any significant N content, since the low electron
temperature of the SiH 4/N 20 plasma does not favor the formation of
atomic N from N 2 (or from N 20).
4.3.3 Amorphous Silicon. Amorphous silicon deposited by PECVD
(glow discharge) contains a large amount of hydrogen (10 to 30 at 0/0)
present in Si-H bonds, and in recognition of this, it is generally referred to
as a-Si(H). It is the H content which is responsible for the interest in this
material, since it bonds to and hence neutralizes dangling bond defect
states in the amorphous network This releases the Fermi level from being
pinned at the energy of defect states within the band gap. Movement of the
Fermi level into either the conduction or valence band becomes possible,
allowing doping to produce nand p-type material. It was this discovery a
decade ago by Spear and LeComber246 which prompted the huge amount
of attention which has been devoted to the study of a-Si(H). This was
rapidly followed by reports of the application of doped a-Si(H) in photo-
voltaic solar cells. 247 ,248 The early amorphous silicon solar cell work has
been reviewed by Carlson,249 who has also given a more recent review. 25o
In addition to solar cells, a-Si(H) is being used in a number of other
applications, including other p-n junction and Schottky barrier devices,251
thin film field effect transistors,252,253 and as a xerographic photoreceptor
and in Vidicon-type photoconductive image tubes. 254 There have been a
number of recent reviews of the application of a-Si(H) in these fields,
including Spear et al.,255 various papers in Hamakawa,256 and Hamakawa257
Hydrogenated amorphous silicon usually is deposited by PECVD at
high rffrequency and low plasma powerfrom either pure SiH 4 or SiH 4/inert
gas mixtures at a substrate temperature of 200-300°C. Variations on the
above scheme are the use of a dc plasma, the use of Si 2H 6 in place of SiH 4,
and the application of a negative bias to the substrate table to increase ion
bombardment of the growing film. Fritzsche 258 has reviewed deposition
conditions and resultant heterogeneities (compositional and microstruc-
306 Semiconductor Materials

tural) in a-Si(H). Doping of the a-Si(H) is readily achieved by introduction of

controlled small amounts of PH 3 (for n-type) or 8 2H 6 (for p-type) into the
plasma. Many of the considerations discussed in the section on silicon
nitride relating to the influence of PECVD parameters on the film properties
are relevant here, particularly those pertaining to H content of the film,
without the complicating consideration of a changing Si/N stoichiometry.
As for SiN x deposition, the absence of vacuum leaks and of outgassing is
very important, since 02 and H 20 will be gettered by the depositing film.
It shou Id be noted that wh ile most Si N x deposition has been performed
in radial-flow, parallel plate reactors, much of the work on a-Si(H) has been
carried out in asymmetric rf diode sputtering systems (but at high enough
pressure and low enough power to ensure that sputtering of the driven
electrode did not occur). Thus there is not a symmetrical gas flow situation,
and the bias voltage developed by the driven electrode is appreciably
higher and the plasma potential lower than that in the case of the sym-
metrical electrodes of a radial-flow system. Hamasaki et al. 259 have recently
reported the benefits of closely surrounding the driven and substrate
electrodes by a grounded mesh cage, which makes the interelectrode
potential distribution look like that obtained in the symmetric radial-flow
reactor, with a very low driven electrode bias. This shifted to higher energy
the energy distribution of ions accelerated across the sheath into the
substrates, but also eliminated the high energy tail of the incident particle
energy distribution, wh ich was due to energetic neutrals reflected from the
driven electrode at high cathodic bias (as occurs in sputter deposition).
This had the effect of permitting much higher rates of deposition from SiH 4
(3000A min- 1 in place of 'V 200A min- 1 without the ground mesh) without
degradation of the materials properties usually associated with high rate
deposition. In fact, thermal stability of the optoelectronic properties of the
high-deposition-rate a-Si(H) showed considerable improvement.
In other work, use of inert gas (He or Ne) diluted SiH 4 permitted an
increased deposition rate from an increased rf power density without gas
phase reaction occurring,260 due to the overall increased gas throughput/
reduced residence time. Alternatively, disilane (Si 2H 6) has been used in
place of SiH 4 , with an order of magnitude increased deposition rate, and
apparently also a reduced stress, without any increase in rf power density.261
However, this magnitude of deposition rate increase only applies for
specific low power conditions. Kuboi et al. 262 for example, obtained only a
factor two difference in deposition rate from Si 2H 6 and SiH 4 flows carrying
equal Si content at low power, but no increase in deposition rate at higher
powers, where presumably both SiH 4 and Si 2H 6 were being almost
completely dissociated. These authors also reported an interesting effect
for deposition from Si 2H 6/D 2 mixtures, in which it was observed that for low
power deposition, the majority of the hydrogen content of the deposited a-
Si was in the form of H (from unbroken Si-H bonds), whereas at high power,
a disproportionately high D content was produced in the film. This is a
similar effect to that observed in the deposition of SiN x from SiH 4/N 2
mixtures,221 where at low power most of the H content of the film was
present as Si-H from unbroken bonds, but at high power the majority was
 Plasma Processing 307

present as N-H. For the case of SiH 4/D 2 mixtures, this effect was not
observed by Kuboi et al. 262
The degree of doping also has been reported to increase the hydrogen
content,263 but in addition to reduce the temperature at which the rate of
loss of hydrogen is a maximum. This indicates that the average bond
strength of the H has been reduced. Doping also has an effect on the
microstructure of the film, changing the distribution of the H bonding sites.
Hirose 264 has studied the optical emission spectra of SiH 4/H 2 plasmas
without and with magnetic confinement, and correlated the em itting species
to the infra-red spectrum of the deposited film. It was fou nd that a decrease
in the SiH emission intensity relative to that of H 2 corresponded to the
formation of partially microcrystalline films in which the doping efficiency
was extremely high, as discussed later in this section.
Microstructure of the a-Si(H) film appears to be the key property in
determining device-related properties such as doping level, carrier mobility
and photoconductivity. Knights and Lujan 265 fist showed that a-Si(H) films
were frequently not homogeneous random networks. Theyfound that high
power deposition at low temperature, in particular from Ar diluted SiH 4,
produced an island structure film with columns of typical a-Si(H) propagating
normal to the substrate but with only low density material between these
columns. Earlierwork266 had shown films deposited underthese conditions
to have high densities of non-radiative recombination centers (low photo-
luminescence yield). At a substrate temperature of 230°C, for which the
optically-active defect density was minimized for low power deposition
from pure SiH 4, there was no observable microstructure in the film down to
a resolution of 1OA. However, deposition at this temperature either at high
power or from very diute Si H 4 produced fi Ims of colu mnar morphology and
high optically-active defect density. Deposition under these conditions,
but with the addition of a negative substrate bias to give increased ion
bombardment of the growing film, eliminated the columnar morphology
and strongly reduced the defect density. It was postulated that the inter-
column regions were not voids, but were at least partially filled by a
crosslinked polysilane, (SiH 2)n' The origin of this columnar morphology
was identified not as a low density of nucleation centers in the initial
growth, but as imperfect coalescence of islands growing from each nuclea-
tion center.
Inhomogeneous films at the opposite end of the structural order
spectrum in the class of materials which still are described as hydrogenated
amorphous silicon are currently of great interest. These are films in which
there are microscopic quasi-crystalline ordered regions of low hydrogen
content embedded in a disordered, truly amorphous network containing
large amounts of hydrogen. The occurrence and growth of these quasi-
crystalline regions is promoted by high doping levels, increased substrate
temperature, increased plasma power density, magnetic confinement of
the plasma, and high hydrogen content in thesourcegas mixture. 258 ,264,267,268
As the quasi-crystalline content is increased, the percolation limit is
exceeded and a highly conductive film results. This is the reason for the
strong interest in such films, which are also referred to as microcrystalline.
308 Semiconductor Materials

The conductivity of these microcrystalline films can be varied by

doping over the range from about 10- 12 0- 1cm- 1 to about 100- 1cm- 1 for
both n- and p-type films, in contrast to an upper limit of about 10- 20- 1cm- 1
for both n- and p-type amorphous films. 246 ,269 For example, by employing
magnetic confinement of a relatively high power plasma and a substrate
temperature of 300°C, at a PH 3/SiH 4 flow ratio of 5.6X 10-3, Hamasaki et
al. 270 deposited n-type microcrystalline films of room temperature conduc-
tivity of 270- 1cm- 1. Conduction activation energy was the low value of 10
meV. This same group270 reported p-type microcrystalline films of conduc-
tivity 7.80- 1cm- 1, produced by a dopant flow ratio, 8 2H 6/SiH 4, of 2.6X 10-2.
The increase in doping efficiency and conductivity reported by Madan
and Ovshinsky271 for doped fluorinated amorphous silicon, a-Si(F,H),
deposited from SiF4/H 2 plasmas, was originally thought to be due to
improved efficiency of dangling bond termination by F relative to H,
producing a reduced density of localized states. This report sparked a
great deal of interest in the fluorinated material, which has been reviewed
by Matsumura and Furukawa. 272 However, it has now been realized that
the improved doping was not due to superior dangling bond termination,
but was in fact due to the films being microcrystalline, with the presence of
F being conducive to microcrystallization. 272 ,273 As described above, non-
fluorinated microcrystalline films can have equally high conductivity.
Kuwan0 274 has reviewed the relevant properties of a-Si(H) in much
greater detail than the above brief discussion of some of the more pertinent
points. Hirose264 has reviewed fabrication techniques and growth mecha-
nism of a-Si(H), Hamakawa275 has reviewed the device physics and design
of a-Si(H) photovoltaic cells and Haruki and Uchida276 have reviewed their
fabrication and performance.
4.3.4 Other Semiconductors, Including Epitaxial Growth. The
semiconductor films which have been deposited by PECVD are poly-
crystalline silicon, and epitaxially grown single crystal films of silicon,
germanium, gallium arsenide and gallium antimonide, in addition to amor-
phous silicon discussed in the preceding section. The application of
PECVD to epitaxial growth is relatively new, and is an area where much
progress is to be expected within the next few years. The closely related
area in which plasmas are employed in the growth of single crystal materials,
that of epitaxial crystal growth by sputter deposition, is also of much
current interest, and has recently been reviewed. 277
In the preceding section we discussed amorphous silicon films and
extended the discussion to include films referred to as microcrystalline.
The latter consist only partially of crystalline material, embedded in an
amorphous network, with the mean size of the crystall ine reg ions no larger
than a few tens of Angstroms. The films described as polycrystalline have
crystalline regions an order of magnitude larger, which are separated from
each other only by grain boundaries. These polycrystalline silicon films
(often, but incorrectly, referred to as polysilicon) may be deposited by
PECVD under conditions which are an extension of those needed to
develop microcrystallinity, in particular a further increased substrate temp-
erature up to the 400-650°C range. Such temperatures are still somewhat
lowerthan those for direct CVD, the most common method of deposition of
 Plasma Processing 309

polycrystalline silicon. The extent of choice of source gas is identical to

that for deposition of a-Si(H). Those which have been employed for poly-
crystalline and single crystal Si PECVD are shown in Table 12.
For depositions performed in tube reactors from inductively-coupled,
high frequency plasmas,278,279 polycrystalline Si films were obtained at the
low substrate temperature of 400-450°C. In both cases the grain size was
large, on the scale of a few hundred Angstroms (500A was reported in
Reference 279). In contrast, in a capacitively coupled, hot wall reactor
operating at low frequency(Figure 51 c), a substrate temperature of 625°C
was required for the onset of crystallization. 28o For this substrate temper-
ature, the grain size was only 100A and the polycrystalline structure
described as poorly defined. It is not clear whether the highertemperature
needed for polycrystalline film formation was due to the use of the chlorinated
silane source gas, or to the damaging effect of the energetic Ar+ ion
bombardment present in the low frequency plasma acting in opposition to
crystal growth. These low frequency plasma deposited films 280 were in
compressive stress, as is obtained for SiN x films deposited in this type of
reactor, but of even higher magnitude. Values of 6X1 0 9 dynes cm- 2 and

Table 12: Gases and Temperatures Employed for PECVD of Polycrystalline

and Epitaxial Silicon

Source G~ 1\1ixture Deposition Temp. Morphology

(OC)

625 Polycrlstalline
"-' 100A grain size

400 Polycrlstalline
"-' 500A grain size

450 Polycrvstalline
few hu·ndred A.
grain size.

600 Polycrystalline

SiH4/H~ 750-900 Single Crystal

SiH 4/H 2 800-900
SiHI 760
SiHf 775
SiH 4 /GeHl 600-850

a. Reference 280
b. Reference 279
c. Reference 278
d. Reference 330
e. Reference 281
f. Reference 331
g. Reference 283
h. Reference 282
j. Reference 332
310 Semiconductor Materials

1.2X 10 10 dynes cm- 2 were reported for the undoped and doped films
respectively. For these plasma conditions, PECVD does not offer any
process temperature reduction relative to low pressure CVD from a SiH 4
source. In fact temperatures 25-35°C higher were found necessaryforthe
onset of polycrystalline film formation.
Plasma-enhancement has been found to be very effective in reducing
the substrate temperature for epitaxial Si deposition to the 600-900°C
range, from the 1050-1200°C required by low pressure CVD. Pre-deposition
plasma cleaning and native oxide removal from the Si substrates was
found to be very important in permitting epitaxy at these lowtemperatures.
This was performed reactively in H 2 plasmas 281 ,282 or by inert gas sputter
etching. 283 Deposition of both epitaxial and polycrystalline Si films by
PECVD is relatively new, and there is much work yet to be carried out in
order to characterize these films. Reif 284 has recently reviewed the epitaxial
growth.
Germanium single crystals have been grown epitaxially on NaCI(1 00)
substrates by PECVD285 from GeH 4/H 2 mixtures at 450°C, about 150°C
lowerthan required by normal CVD. A high frequency, inductively coupled
plasma was employed. It was found that the plasma power had to be
restricted to the minimum level possible in the initial stage of deposition
until nucleation was complete. This was necessary to avoid plasma-
induced damage to the NaCI surface, and subsequent damage propagation
into the Ge film. After nucleation, the plasma power could be safely
increased to give a usefully high deposition rate of 1700Amin- 1. Electrical
properties of these epitaxial Ge films look very promising.
Hariu et a1. 286 ,287 deposited epitaxial GaAs films onto GaAs(1 00) and
Ge(1 00) substrates at temperatures above 350°C and 500°C, respectively.
In contrast to conventional PECVD in which one fu nction of the plasma is to
dissociate the reactant gas molecules, the Ga and As sources were
elemental, with their fluences to the substrate provided by thermal evap-
oration of elemental sources within th PECD chamber. An inductively
coupled plasma was maintained between the substrate and the evapo-
ration sources, in a low pressure (rv 20 mtorr) of Ar in the earlierwork286 and
H2 in the later work. 287 Thus the function of the plasma was to supply
energy to the growth surface to increase surface migration velocities and
hence permit epitaxy at these reduced temperatures. Alternatively, one
may regard the plasma as providing a locally enhanced surface temperature.
A second effect of the exposure of the substrate to the plasma was the
plasma etch oxide removal from the GaAs surface at the beginning of
growth; this effect was also beneficial in promoting the low temperature
epitaxy. Auger analysis showed the absence of interfacial oxide for the
plasma-enhanced growth but its presence for a deposition without plasma-
en hancement. In add ition, a uniform level of oxygen was detected th rough-
out the film but not in the plasma-enhanced grown material. Thus the
plasma exposure has the added beneficial effect of reducing contaminant
incorporation into the epitaxial growth. It should be noted that epitaxial
growth was promoted only within a limited range of plasma power; pre-
sumably at higher plasma power, competing damaging effects of the
plasma become dominant.
 Plasma Processing 311

Using the same plasma-enhanced elemental evaporation technique,

with a hydrogen plasma, Sato et al. 288 have grown epitaxial GaSb layers on
GaAs at temperatures as low as 340°C. Use of a hydrogen plasma in place
of an Ar plasma was found to be beneficial to the electrical and optical
properties of the GaSb layer. Electronic properties of undoped p-type
layers were equal to those of layers grown by MBE or MOCVD at much
higher growth temperatures.
Device quality, epitaxial GaAs layers have also been grown by Pande. 289
The method employed was plasma-enhanced MOCVD, in which conven-
tional Ga and As vapor phase sources (tri-methyl galliu m and either arsine
or tri-methyl arsenic) were used, but with the additional requirement
relative to normal MOCVD that the arsenic source be passed through a
plasma upstream from the substrates. The growth surface was not exposed
to the plasma. Thus the approach is quite different from that of Hariu et
al. 286 discussed above. The rationale for Pande's approach is that in normal
MOCVD of GaAs, the arsenic source dissociates less readily than the
gallium source, and the high growth temperature and excess arsenic
source flow are necessary to achieve sufficient dissociation of the arsenic
source. Thus the growth temperature can be reduced by pre-dissociation
of the arsenic source alone in the upstream plasma. Epitaxial layers with
good morphology were obtained at 425°C, in com parison to temperatu res
in excess of 600°C necessary for normal MOCVD growth.
4.3.5 Metals. Many of the commonly employed metallizations in
semiconductor processing may be deposited by PECVD, generally
excepting the noble metals forwhich no vapor sources are readily available.
In silicon technology, the most common metallizations at present are
aluminum and highlydoped polycrystallinesilicon. The latterwas discussed
in the preceding section. For VLSI applications, the current trend is to
replace these metallizations by transition metal silicides or perhaps tran-
sition metals themselves. These have improved electromigration resistance,
lower resistivity (than polycrystalline Si), and can be patterned into sub-
micron features. The PECVD of AI and of the transition metals Mo and W is
discussed in this section, and transition metal silicides will be discussed in
the following section.
Sou rce gases for metal deposition are usually an organometallic or a
volatile halide vapor, transported into the plasma by either hydrogen or by
an inert gas. PECVD of AI from both types of source, AICI 3 and (CH3)3AI, has
been described by Ito. 29o AI films deposited at room temperature had the
lowest resistivity (~1 X 10-5 0 cm), but this is about a factor 4 higherthan that
obtained by sputtering or evaporation. This was believed to be due to
incorporation of trace amounts of oxygen. Films deposited at higher
temperatures had higher resistivity and the oxygen content was detectable
by Auger analysis. (CH3)3AI reacts spontaneously with oxidizers, and a
freshly deposited AI surface is an excellent 0 getter, hence very low leak
and outgassing rates and high gas throughputs in conjunctin with high
deposition rates will be necessary to produce lower resistivity films.
PECVD of tungsten and molybdenum has been reported byTang, Chu
and Hess 291 ,292 and further discussed in the review of Hess. 192 These
workers have employed tungsten or molybdenum hexafluoride source
312 Semiconductor Materials

gases for PECVD at high frequency in a parallel-plate reactor. In both

cases the use of hydrogen as a reactive diluent was necessary to achieve
deposition. This is necessary because the plasma dissociation of WF 6 or
MoF 6 produces atomic fluorine, which is a very effective etchant for W or
Mo. Thus the process of Wor Mo film formation by reaction ofWFn or MoFn
adsorbed radicals on the heated substrate surface is in competition with
the etching process. Addition of hydrogen produces atomic hydrogen in
the plasma, which acts as a scavengerfor atomic fluorine, allowing deposition
to become the dominant process. Thus deposition rate increases with H 2
flow to a maximum value, and then begins to decrease with further increase
in H 2 flow due to a reduction in residence time becoming the dominant
effect. A H 2 /WF 6 flow ratio of 3 was employed for W deposition, and a
H 2 /MoF 6 flow ratio of 7 for Mo deposition. 292 Metallic, smooth W films were
deposited for substrate temperatures in the range 300-350°C at a power
density of 0.06W cm- 2 and 200 mtorr pressu reo Auger analysis showed the
W films to be oxygen free, and also did not reveal any F content. However,
resistivity of the as-deposited films was about an order of magnitude
higherthan that of bulk W, and a factor4 higher than that of high temperature
CVD W films. Higher hydrogen flow during deposition produced lower as-
deposited resistivity. In all cases a short high temperature anneal could
reduce the resistivity to close to the bulk value, apparently without signif-
icant grain growth. Hence, trace amounts of F incorporation, below the
detection limit of Auger analysis, which could be out-diffused at elevated
temperature were suspected to be responsible for the high as-deposited
resistivity.
4.3.6 Silicides. Silicides of tungsten and molybdenum have been
deposited by PECVD from Wand Mo halide source gases in conjunction
with silane. Akimoto and Watanabe 295 deposited WSi x films from a SiH 4/WF 6
source gas mixture in a high frequency, parallel-plate plasma reactor.
Additional hydrogen, as needed to permit W deposition (see Sectio 4.3.5),
was not necessary, since an adequate H atom supply for F atom scavenging
was provided by the SiH 4 decomposition. Rapid surface reaction kinetics
between WFnand Si H radicals produced high deposition rates of 500 A
min-1, an order of magnitude faster than for deposition of W alone. The
W/Si stoichiometry in the film could be controlled over a verywide range by
variation of the WF 6 /SiH 4 flow ratio. This determined the as-deposited
resistivity, with W rich films having lower resistivity. For films of W/Si ratio
around unity, PECVD WSi x films have similar resistivity to those sputter
deposited. High temperature annealing reduces this resistivity, although
curiously, for films with W/Si close to unity, annealing at temperatures
higher than 500°C does not produce any further reduction relative to the
value reached at 500°C.
Tabuchi et al. 294 added SiH 4 to their MoCI 5/H 2 mixture employed for
Mo deposition, and deposited films with a wide range of Mo/Si stoichiometry.
Resistivities as-deposited were high.
4.3.7 Other Materials. Many other materials have been deposited
by PECVD, as shown in Table 4. Those of interest in semiconductor
applications will be discussed in this section. This includes various oxides,
nitrides (dielectric and metallic), and polymer films. Other materials,such
 Plasma Processing 313

as various forms of carbon and carbides which are mainly used as anti-
wear and anti-corrosion surface coatings, are not considered here, but
have been reviewed in some detail by Ohja. 186 In addition, the growth of
surface native oxides, nitrides, and carbides, by exposure to oxygen,
nitrogen and carbon contain ing plasmas respectively, is not covered here.
These are also covered in the review of Ohja, 186 and the former, wh ich is of
great relevance in semiconductor processing, is covered in an earlier
chapter of this work. 296
In addition to the previously discussed nitride, oxide and oxynitride of
silicon, other oxides and nitrides are also of interest for microelectronics
applications. In particular, for processing of III-V semiconductors, the use
of non-silicon based dielectrics can be advantageous, since Si is an
amphoteric dopant in III-V compound semiconductors. This can be a
concern for high temperature processing applications, such as implant
annealing caps. An appropriate alternative is the use of oxides and nitrides
of the group III elements, from which unintentional doping of the III-V
semiconductor cannot occur.
The oxides and nitrides of group III elements which have been deposited
by PECVD include the oxide and nitrides of boron, aluminum and gallium. A
potential advantage of the use of the oxide or nitride of gallium or aluminum
is that it is feasible to deposit these materials in the same reactor as that
used for the MOCVD growth of the III-V material itself, to wh ich the vapor
phase supply of the group III element is already connected. Thus one can
deposit the group III oxide or nitride directly onto a freshly grown III-V
surface which has not been air exposed or etched in any way. This offers
the possibility to study a very clean dielectric/semiconductor interface
and to obtain interfaces with low densities of interface states, of great
interest for MIS applications.
It is for this last application, on InP, that Meiners 297 has studied
PECVD AI 20 3 and, in addition, PECVD AIPXO y The former was deposited
from trimethylaluminum, (CH3)3AI, and O 2. These reactants were only
mixed at low pressure within the deposition chamber above the heated
substrate. The plasma reactor was of the indirect variety, and only the O2
reactant was passed through the upstream plasma chamber. Substrate
temperatures in the range300-450°Cwere employed, and the film resistivity
was found to increase with deposition temperature. However, even for a
450°C deposition temperature, the resistivity of 1014 0 cm obtained was not
sufficiently high for meaningful capacitance-voltage studies from which
interface density of states could be obtained. This relatively low resistivity
does not appear to be a result of the PECVD technique. AIPXO y films were
deposited by the same indirect plasma technique, but with the addition of
pre-pyrolyzed PH 3 above the substrate. These films were of much improved
resistivity, with values in excess of 10 16 0 cm obtained for a deposition
temperature of 375°C. The deposited film composition with regard to the
AI/P ratio was AI rich relative to stoichiometric AIP0 4. These AIPXO y films
produced the best interface properties with InP yet reported, with interface
densities of states within the gap of 1X10 11 cm- 2eV-1. Low densities of
states for the InP interface with PECVD Si0 2 had previously been report-
ed,298,299 but these were rather irreproducible and very dependent of the
surface cleaning technique prior to dielectric deposition. 298
314 Semiconductor Materials

AI 20 3 films have also been deposited by PECVD from AICI 3 and 02

source gases 300 in a lowfrequency, inductively coupled plasma, at substrate
temperatures in the range 400-500°C. AICI 3 was transported into the
plasma from a variable temperature bubbler using the 02 as carrier gas.
Adherent films of up to several microns thick could be deposited on silicon,
suggesting that stress in the AI 20 3film was low. AICI 3was also employed as
the AI source in the PECVD of AIN x films from an AICI 3/N 2 plasma. 301 Films
were only deposited over the temperature range BOO-1200°C in order to
compare their properties to CVD films deposited at the same temperature.
Gallium oxide is of interest for use as a dielectricfilm, particularlyon Ga
based III-V semiconductors. It has been deposited on GaAs in an attempt
to eliminate the detrimental occurrence of elemental As at the interface
between GaAs and its native oxide. 302 Trimethylgallium in argon and
oxygen were fed into a magnetically confined high frequency plasma at a
low pressure (~1 mtorr). The optimum deposition temperature was 150°C,
and films of Ga 20 3 stoichiometry were deposited. Fluorine was incorporated
into the Ga 20 3 film by addition of a small amount of CF 4 to the plasma. This
was done in the initial stage of deposition in an attempt to compensate
dangling bonds and hence interface states produced by oxygen at a GaAs
surface. An alternative approach to eliminate the effects of oxygen at the
GaAs/dielectric interface is to use a nitride in place of an oxide, and GaN is
a natural candidate for this application. Matsushita et al. 303 deposited
approximately stoichiometric GaN films by PECVD from trimethylgallium
and ammonia, with Ar or N 2 diluents, in an inductively coupled plasma.
Properties of the films such as H content, stress, resistivity, etc. were not
reported.
Titanium nitride is a technologically interesting material both for
microelectronic applications as well as for tribological and decorative
coatings. Interest for semiconductor applications arises from its metallic
conductivity and its excellent diffusion barrier properties. While the normal
method of deposition is by reactive sputtering, TiN x has also been deposited
by PECVD.304TiCI 4 vapor in H2 carrier gas and N2 source gases were fed
into an inductively coupled plasma to which the substrate was directly
exposed. TiN x filmscould be deposited down t0250°C, but temperatures in
excess of about 350°C were needed to obtain good adhesion to Ni
substrates. Stoichiometry or electrical properties were not reported.
Another interesting dielectric nitride, which is composed entirely of
group Velements, is P3NS' This material has been deposited byVeprek and
ROOS30S from elemental phosphorus and nitrogen sources by a plasma-
enhanced chemical transport technique. A high frequency N2 plasma
generated above amorphous phosphorus plasma etched the phosphorus
and produced vapor phase PN species in the plasma. These then produced
deposition of PN x films on a heated substrate exposed to the plasma.
Stoichiometry of the deposit could be varied up to P~Ns' In later work,
Veprek et al. 306 used conventional PECVD from PH 3 and N2 source gases
in a high frequency plasma to deposit hydrogenated P3Ns films. At a
N2/PH 3flow ratio in excess of 10 and a substrate temperature of~330°C~ a
film of P3NS stoichiometry but with an additional 13 atomic% H contentwas
deposited. Infra-red spectra showed the existence of both P-H and N-H
bonds. However this H content does not appear to modify the dielectric
 Plasma Processing 315

properties relative to the hydrogen-free P3 N s deposited by the plasma-

enhanced chemical vapor transport. In addition, the H is tightly bound and
reported to be stable up to 700°C.
Polymeric organic materials may also be deposited by PECVD (Refer-
ences 307 -309 and references therein). In plasma etching, this can either·
be a problem to be circumvented or an effect to be employed beneficially.
For example, as discussed in Sec. 3.4.4, the addition of H 2 to a CF 4 etching
plasma promotes polymer deposition in competition with etching. Since
under dynamic equilibrium conditions, the thickness of polymer present
on an Si0 2 surface is less than that on a Si surface, the effect of polymer
deposition is to enhance the Si0 2 /Si etch rate selectivity. However, this
can also result in undesirable contamination of the etched surface.
Retajczyk and Gallagher310 have studied PECVD polymer films with
regard to their dielectric applications in microelectronics. Fluorocarbon
polymeric films were deposited in a high frequency plasma in a parallel
plate reactor from tetrafluoroethylene (F 2 C=CF 2 ) monomer source gas.
The deposited polytetrafluoroethylene (PTFE) films had a number of attrac-
tive properties. These included a low dielectric constant (beneficial to
minimizing capacitance in interlevel dielectric applications), very low stress,
excellent adhesion, and general chemical inertness, but with the ability to
be patterned by oxygen plasma etching.

4.4 Interface Properties

An ideal interface can be defined as one which is atomically abrupt, i.e.,
of submonolayer width, with each of the materials at either side existing in
a state unperturbed by the presence of the other. This is generally not the
case for most practical interfaces. An interface often can be characterized
by the extent of interfacial mixing or compound formation, and by the
extent of the substrate surface modification. The former is frequently a
chemical effect, albeit ion-assisted, (although it can occur by a purely
physical process), whereas the latter is a physical effect.
Interfacial mixi ng or compou nd formation generally is a fu nction of the
chemical identities of the two materials involved, as is the case in thermal
CVD. However, in PECVD interfacial reaction rates may be greater or less
than in thermal CVD, due to the competing effects of a rate reduction dueto
the lower bulk substrate temperature and a rate enhancement due to ion
bombardment (giving an increased effective surface temperature). This
rate enhancement occurs by the same mechanism as that in which ion
bombardment increases the rate of heterogeneous reactions involved
either in film growth (see, for example, Table 8, in Section 4.3.1 for SiN x
deposition) or in etching (see Section 2.2.2). Intermixing can also occur by
the physical mechanism of momentum transferwhen incident ion energies
are high, as in lowfrequency PECVD(seeSections2.2.2 and4.2.1). The use
of a low pressure shifts the incident ion energy distribution to a higher
value, and the deposition of a material from a plasma from which the
deposition rate to plasma power density ratio is low increases the ion dose
received in the interface region. Hence both those deposition conditions
will favor the possibility of physical intermixing occurring.
316 Semiconductor Materials

Even if intermixing does not occur, the ion bombardment discussed

above can also produce damage in the atomic structure of the substrate
surface. In the case of a monocrystalline substrate, this structural damage
may be in the form of complete or partial amorphization of a thin surface
layer, or in a less severe case, the formation of vacancies and interstitials
within the lattice. This type of surface structural damage may be of concern
in semiconductor processing applications where the deposited film acts
as an etch mask or a diffusion mask.
Both of the above discussed modes of structural deviation from an
ideal interface are also expected to modify the electrical and optical
properties of the near-surface region of the semiconductor. For example,
electrical modification may be observed in the form of an increased
density of mid-gap interface states, modified Schottky barrier heights,
reduced carrier mobility, surface carrier type conversion and modified
Ohmic contact formation. A related, optically observable effect is a reduction
in photoluminescence yield due to increased non-radiative recombination
rates.
Structural modification of a monocrystalline surface may be observed
by Rutherford backscattering (RBS), with the best sensitivity obtained
under channeling conditions with detection of nuclei backscattered at
grazing exit angle. This technique enables the number of atoms displaced
from equilibrium lattice sites to be counted, and this is a direct mesurement
of the degree of damage. The method has been employed to study the
interface between an InP(100) surface and Si0 2 and SiN x dielectrics
deposited by PECVD over a wide range of deposition conditions, and for
comparison, films deposited by rf diode sputtering. 195,196
In Figure 62, we show the areal density of In atoms producing back-
scattering measured for a clean, native oxide stripped InP surface and for
similarly prepared surfaces subsequently coated by rv 50Aof Si02 , deposited
either by high frequency PECVD, or by rf diode sputtering in an Ar:0 2
atmosphere. It may be seen that there is no measurable increase in the
number of off-lattice site In atoms for the PECVD Si0 2 coated surfaces at
any plasma power density up to the Ii mit studied (0.32 Wcm- 2 ), at which the
Si0 2 deposition rate was 1500Amin- 1.1 n contrast, diode sputtering of Si0 2
produced significant surface damage and/or interfacial mixing at all power
densities, reaching a saturation level of 5.5X1 0 15 cm- 2 displaced In atoms
(equivalent tothetotal number of In atoms in 30AI n P) at aboutO.25 Wcm- 2 .
Thus the PECVD Si0 2 /1 nP interface is abrupt on a monolayer scale, with no
induced structural modification of the InP surface. In laterwork,196 we have
also looked at InP/PECVD dielectric interfaces for PECVD situations in
which the interface region receives a larger and/or more energetic ion
dose. These were low frequency PECVD Si02 (increased energy), high
frequency PECVD SiN x (increased dose) and low frequency PECVD SiN x
from SiH 4 /N 2 (increased dose and energy). Ratios of deposition rate to
plasma power density and of incident ion energy distributions for these
cases have been given in Sections 4.3.1.1 (inc. Table 8), 4.3.2, and 4.2.1
(inc. Figure 10). In all three cases, a monolayer abrupt, damage-free
interface was also produced. However, the low frequency PECVD of SiN x
f~om a dilute SiH 4 in N2 plasma appeared to be on the verge of producing
 Plasma Processing 317

12

10 SPUTTER DEP.
'7o 10

- 8
,
C\J

E
u 6
en
:: L _ wr4== ... PECVD
o
.- 4
~ EXPT/UNDAMAGED InP (100)

2 CALC.

O~ ---' --'L-- ~

0.01 0.1 10

PLASMA POWER DENSITY (Wcm- 2 )

Figure 62: Surface structural damage produced in an InP (100) surface asa func·
tion of plasma power density as a result of Si0 2 deposition by PECVD at 13.56
MHz compared with deposition by rf diode sputtering from an Si0 2 target in an
Ar :0 2 atmosphere (from Reference 195).

measurable structural modification. Since GaAs and Si have each been

shown to be less susceptible than InP to low energy ion bombardment
damage,311 it is reasonable to assume that PECVD will produce sharp,
damage-free interfaces on those materials also, except in cases where
chemical interactions occur.
On a more sensitive scale, when electrical characterization techniques
are employed which are sensitive to atomic displacements at the parts-
per-million level (as opposed to the percent level at monolayer sensitivity
forthe channeling described above), PECVD is generallyfound to produce
modification of a semiconductor surface. As a generality, low frequency
PECVD is more damaging than high frequency. For example, low frequency
PECVD of SiN x from SiH 4 /N 2 onto GaAs produces interface states in a
broad band peaking at about 0.6 eV below the conduction band edge, with
the high peak density of 1.5 X 10 13 eV- 1cm- 2.312 The use of high frequency
PECVD SiN x as an interlayer dielectric on normally-off GaAs FETs produces
strong degradation of the FET I-V characteristics. 313 However these authors
also reported that the PECVD could be made degradation-free merely by
isolating the GaAs wafer from the grounded electrode by the use of a
quartz spacer. The authors believed that the deposition was made damage-
free by elimination of ion bombardment due to elimination of the potential
difference between the wafer and the plasma. However it is by no means
clear that this was the effect responsible, since even a floating potential
surface acquires a negative bias relative totheglow region of the plasma in
order to equalize the incident electron and positive ion fluences. Since at
the 13.56 MHz employed, the sheath behaves capacitively (see Section
318 Semiconductor Materials

2.1.2.1.3), the additional capacitance of the quartz spacer beneath the

wafer relative to the capacitance of the su rrou ndi ng element of the sheath
will act as a voltage divider, so that some reduction in incident ion energies
will be achieved. This argument is, however, only applicable if the sheath is
not disturbed. This would not be the case if the quartz spacer was thick
enoug h for its capacitance per unit area to be as large as that of the sheath
(i.e. a voltage reduction to zero is not possible).
Regarding interface state generation by PECVD of a dielectric onto
InP, a number of general observations may be made. First, both chemical
and physical effects are important. It is not sufficient merely to eliminate
radiation-induced damage. For example, SiN x is not a good gate dielectric
on InP,298,299 since it causes the Fermi level to be pinned in the upper half of
the band gap. It is assumed that these interface states are the result of the
chemical interaction of the InP surface with the reducing, H containing
ambient involved in SiN x deposition, producing P vacancies at the interface.
In contrast to GaAs, however, presence of native oxide at the In P/dielectric
interface does not pin the Fermi level. Direct PECVD, as in a parallel plate
reactor, is probably not suitable for InP MISFET applications, but indirect
PECVD of Si0 2 can produce a low density of interface states. 298 These
results were, however, rather irreproducible, and very dependent on the
preceding cleaning and etching of the InP surface. Good results with
PECVD Si0 2 were also obtained by Woodward et al. 299 even with direct
plasma exposure of the InP surface in a system with external electrodes.
Since tetraethoxysilane (TEOS) and O2 were used as source gases, at a
substrate temperature of 300°C, it is possible that a few monolayers of
deposition occurred by thermal CVD prior to ignition of the plasma, thus
protecting the InP surface from the effects of direct plasma exposure.
These authors attributed their interface quality (relative to that with SiN)
to the minimization of P loss in the oxidizing deposition ambient. Finally,
the best electrical interface properties reported to date were recently
obtained by Meiners 297 using indirect PECVD of AlPXOy(this is described in
Section 4.3.7). Perhaps the presence of PH 3 in the deposition ambient
further reduced or eliminated any phosphorus deficiency in the InP surface
or in any interfacial native oxide layer.
In summary, in the absence of chemical interaction, PECVD materials
form monolayer sharp interfaces with monocrystalline semiconductor
substrates, and do not produce structural su rface damage even for PECVD
with direct plasma exposure at low frequency. In addition, PECVD is
applicable to high quality electronic interface formation, but in situations
where the plasma is employed only to pre-dissociate the reactants and
direct plasma exposure is avoided.

5. SUMMARY AND CONCLUSIONS

We have shown in this chapter how plasmas are utilized in semicon-

ductor processing for both etching and thin film deposition after first
discussing the fundamental aspects of glow discharge physics and chem-
istry and emphasizing unifying principles which pertain to both etching
 Plasma Processing 319

and deposition. Electrical properties of the plasma were described in

terms of equivalent circuit models and some of the shortcomings of these
models were given. Plasma chemistry in the gaseous state and the current
understanding of plasma-surface interactions were reviewed in depth.
The effects of changing interrelated plasma parameters such as frequency,
pressure, rf power, loading, feed gas, etc. were qualitatively described with
reference to quantitative models wherever possible. In particular, emphasis
was placed on the effects offrequency on the energetics and anisotropy of
ion bombardment, with discussion of the circumstances under which this
produces anisotropy in the etching or deposition process.
Though a detailed understanding of all plasma interactions is clearly
lacking, many plasma processes are presently in commercial use. An
approach to developing a plasma etching process was given along with a
review of standard reactor geometries. Some standard etching proceses
were also described. An in-depth review of plasma-enhanced chemical
vapor deposition(PECVD) has been given from the point of view of its appli-
cation in semiconductor technology. Generalities of PECVD were presented
first; these included the necessary properties of PECVD materials for their
applications in microelectronic devices, the types of PECVD reactor in use
and their relative suitability for different applications, source gases which
can be used, control of deposition uniformity and the attendant loss of one
degree of freedom in plasma parameter variation, and the generally appl ic-
able methods of influencing PECVD film properties. Following this, the
specific PECVD processes and range of process parameters for deposition
of the materials (dielectrics, semiconductors, and metals) of interest in
microelectronics were discussed in detail. For the well-studied, silicon-
based materials, emphasis was placed on recent developments in tech-
niques and on the intercorrelation of film properties, as well as on their
dependence on the interrelated PECVD parameters for the specified
process. In particular, the PECVD processes for Si0 2 and SiN x were
contrasted, in terms of the differences resulting from rapid heterogeneous
reaction rates for Si0 2 deposition, but slow, rate-limiting heterogeneous
reaction rates in SiN x deposition. In addition, the PECVD of numerous
other materials of relevance, including elemental and compound semicon-
ductors and II I-V dielectrics has been included.
The last ten years have witnessed a rapid growth in the application of
plasma processes. The general utility of PECVD has been recognized and
it has been applied for more materials than just the silicon-based ones to
which it was more-or-Iess restricted in the mid-seventies. In particular,
PECVD has recently been applied to epitaxial growth at reduced temper-
ature, with significant growth expected in this area in forthcoming years.
During this preceding decade more effort was frequently expended in
developing processes that fitted specific needs than in attempting to
understand the dominant mechanisms responsible. More recently there
has been a growing interest in unravelling the many interrelated chemical
and physical phenomena to gain a better understanding of processes
already in use. As this understanding increases, the future should bring
innovations, especially in the area of reactor design and feedstock blending,
to yield better process control and reproducibility. Other areas of current
320 Semiconductor Materials

research and growth potential include microwave discharges and hybrid

plasma-laser-electron beam processes. These techniques are principally
aimed at eliminating the damaging effects of exposure to the many forms
of radiation present in an rf discharge.
Forthe present, though a lack of understanding is frequently a limiting
factor, plasma processing is still the only known method of achieving, on a
commercial scale, desired etching and deposition properties. In view of
the continued feature size reduction for VLSI in Si technology, and the
expanding III-V technologies, we expect to see a continued increase in the
research, development, and commercial exploitation of plasma processing.

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 Plasma Processing 327

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6
Physical Vapor Deposition

John A. Thornton
Department of Materials Science and Coordinated Science Laboratory
University of Illinois
Urbana, Illinois

1. INTRODUCTION

The term physical vapor deposition is used to denote those vacuum

deposition processes such as evaporation and sputtering where the
coating material is passed into a vapor transport phase by physical mecha-
nism-i.e., evaporation, sublimation, or ion bombardment. Physical vapor
deposition methods are the most universal of the available means for
depositing thin films and coatings. Metallic, dielectric, and semiconducting
coatings, in some cases with unique properties, can be deposited. Sputtering
is particularly effective for providing controlled deposition of materials
with complex composition. No attempt is made in this chapter to give a
complete discussion of these technologies. The objective is instead to
simply highlight those aspects that are of particular importance in semi-
conductor device fabrication and processing.
The metallization of semiconductor devices constitutes one of the
primary applications of physical vapor deposition. Originally most device
metallization was done using evaporation. The current trend is toward
increased use of sputtering. The reasons are (1) the effectiveness of
sputtering for depositing refractory metals and materials of complex
composition, such as silicides, which are coming into increased use in
device design, and (2) the recent development of sputtering technologies
(magnetron sputtering) that minimize substrate radiation damage and
offer greatly increased production capabilities. In fact, it has been estimated
that about 70% of the 1983 wafer metallization activity involves the use of
magnetron sputtering.

329
330 Semiconductor Materials

Other applications where sputtering plays a prominent role include

magnetic thin films for recording applications, thin film resistors and
capacitors for hybrid interconnect circuits, as well as microcircuit photo-
lithographic mask blanks and transparent conducting electrodes. Sputtering
may also be used to deposit microcircuit insulation layers, although chem-
ical vapor deposition (CVD) or plasma-assisted CVD is a more common
method for these particular coatings.
Physical vapor deposition is also used to deposit thin films for piezo-
electric transducers, photoconductors, waveguides for integrated optics
devices, and luminescent films for display devices. A potentially very large
application is the fabrication of thin film photovoltaic devices for direct
energy conversion.
A rapidly developing new method called molecular beam epitaxy
(MBE) uses evaporation from multiple sources to deposit device quality
semiconductors such as GaAs with precisely controlled doping profiles.
MBE is finding increasing application for microwave and optoelectronic
devices, with the promise of novel future devices which will incorporate
specially synthesized su perlatticestructu res having properties not found
in homogeneous materials.
This chapter is divided into seven sections. Section two reviews some
of the important aspects of the vacuu m environment which relate to vacuu m
deposition. Section three discusses vacuum evaporation, and Section
four discusses the application of vacuum evaporation to molecular beam
epitaxy. Section five discusses deposition by sputtering. Section six dis-
cusses and the growth and properties of thin films and coatings, with
particular attention to the influence of deposition parameters, such as
concurrent ion bombardment, on coating properties. Considerable atten-
tion is also given to internal stresses because of the importance of these
stresses in the performance and adhesion of device metallization layers.
Finally, Section seven reviews some of the major considerations in the
important application of device metallization.

2. THE VACUUM ENVIRONMENT

The unit of measure for pressure in vacuum systems is the Torr or

Pascal. The Torr (1 Torr = 1 mm Hg) is a carryover from the time when
pressure measurements were made primarily with manometers. Starting
about 1975, most technical publications began changing to the Inter-
national System of Units (SI), where the unit of pressure is the Pascal (Pa).
The Pascal is the MKS unit of pressure: 1 Pa = 1 N/m 2 =7.5 mTorr (1
mTorr = 0.133 Pa). Most pressure gauges are still calibrated in Torr or
microns ( 1 micron = 1 mTorr). Therefore Torr will be used in this text,
although both Torr and Pa are given in many cases.
Vacuum systems can be classified as high vacuum (10- 3 to 10-6 Torr),
very high vacuum (10- 6 to 10- 9 Torr), and ultrahigh vacuum (below 10- 9 Torr).
Figure 1 shows schematic drawings of several typical pumping configura-
tions. The high vacuum pumps may be of the oil diffusion orturbomolecular
(Figure 1 a), getter(Figure 1 b), or cryogenic (1 c) type. Pumping systems are
 PRESSURE
. / INSTRUMENTATION
GAS
INJECTION
CARBON
~. VANE PUMP

VACUUM VACUUM VACUUM

CHAMBER CHAMBER CHAMBER

SORPTION
GATE VALVE ROUGHING GATE VALVE

TRAP

TRAP DIFFUSION OR
TURBOMOLECULAR
PUMP
CRYOPUMP MECHANICAL
o / \ PUMP
TITANIUM "1J
LN 2 CRYOPUMP :J'"
SUBLIMATION '<
::i...,
UPUMP MECHANICAL
PUMP
SPUTTER
ION PUMP
~
(J)
a"
c <
Q)
"0
b CRYOGENIC PUMPED SYSTEM o..,
o
a GETTER PUMPED SYSTEM CD
"0
DIFFUSION OR TURBOMOLECULAR
o(J)
PUMPED SYSTEM ;::::+
0"
::J

Figure 1: Schematic drawings showing vacuum pumping systems of the various types used in deposition technology: (a) dif- c.v
fusion or turbomolecular pump configuration, (b) getter pump configuration, and (c) cryogenic pump configuration. c.v
~
332 Semiconductor Materials

discussed in References 1-4. Our concern here is with the "vacuum state"
that is achieved and its implications on the deposition process.
Consider a cubic vacuum system with sides 1m in length. The volume
is 1m3 . The internal surface area is 6 m2 . An ideal metal surface contains
about 2x1 0 15 adsorption sites per cm 2 . When the chamber is exposed to
the atmosphere, an even larger density of molecu les wi II become attached
onto the walls because of surface irregularities and multilayer adsorption.
The number of molecules per cubic centimeter in a room temperature gas
is about

n = 3.3x1 0 16 p particles/cm 3 (1 )

where p is the pressure in Torr. Thus when pumping is initiated we have the
task of removing (760 Torr)(3.3x1 0 16 molecules/cm 3 - Torr)(1 0 6 cm 3 ) = 2.5x
10 25 molecules from the volume and at least(2x1 0 15 molecules/cm 2)(6x1 0 4
cm 2) = 1.2x1 0 20 molecules from the walls.
Now consider a cham ber fi lied to an initial pressu re Po with an ideal gas,
which has no interactions with the walls other than reflections. When such
a chamber is evacuated by a pump of constant volumetric efficiency, the
pressure will decrease with time according to the equation.

p(t) = Po exp (-t/r) (2)

where the time constant, r= VIS, is a function of the chambervolume (V) and
pumping speed (S). Suppose that the pumping system for our 1m3 chamber
has a speed of 1000 liters/sec. Then r = 1 sec. Typical values are in the
range from 0.1 sec to a few seconds. 5 Thus Equation (2) predicts that the
pressure in our chamber will decrease exponentially once pumping has
commenced, dropping almost an order of magnitude during each 2 sec
interval.
Now consider the removal of atmospheric gases from a chamber. The
relationship given by Equation (2) is obeyed, after a few seconds from the
start of evacuation and until a pressure of about 10 Torr is reached, as gas
is removed from the volume of the chamber. Subsequently, the evacuation
will become rate-limited by outgassing from the chamber walls. Under
these conditions, the pressure will decrease much more slowly, obeying
an equation of the form

p(t) = Q(t)/S (3)

where Q(t) is the total outgassing rate from the surfaces within the chamber
at thetime t. The outgassing rate, Q(t), and therefore the chamber pressure,
decrease as a function of time, because internal diffusion and surface
desorption deplete the reservoirs of stored gas entrapped on the chamber
internal surfaces.
The dwell time of an atom or molecule on a surface under vacuum will
depend on the binding energy between the molecule and the surface, and
on the surface temperature. See Equation 13 in Section 6.1. Physisorbed
gases with binding energies of the order of 0.1 to 0.5 eV desorb quickly
 Physical Vapor Deposition 333

during the initial pump-down and do not contribute to Equation 3. At the

other extreme, chemisorbed gases with binding energies of 1.5 t03 eVare
released at very small rates, which are persistent but do not contribute
significantly to the gas load. The troublesome gases are those which
produce significant outgassing on the same time scale that is used in
executing the deposition processes. These gases have desorption energies
of about 1 eV. The most notable example iswater.ln some cases water may
condense on vacuum surfaces to thicknesses of hundreds of monolayers. 5
Figure 2 shows the specific outgassing rates (primarily water vapor)
for several engineering materials. 6 The specific outgassing rates typically
obey an equation of the form q = qo(tclt)n, where n varies from about 0.5 for
elastimers and plastics to about 0.3 to 1 for metals.? Thus the total
outgassing rate can be expressed as

Q(t) = A qo (tclt)n (4)

where A is the chamber surface area. The time to is a reference point where
q = qo. For approximate calculations to can be taken as the point at which
the high vacuum valve is opened.
Consider the case of our 1m3 chamber after three hours of pumping.
Assume that the chamber is constructed of stainless steel and that the
high vacuum pump has a speed of 600 liters/sec. The specific outgassing
rate for stainless steel after 180 min. of pumping is seen in Figure 2 to be
about 4x1 0- 8 Torr-liters/sec-cm 2. From Equation 3 we estimate the chamber
pressure to be (4 X 10-8 Torr-liters/sec-cm 2)(6 X 10 4 cm 2)(600/liters/sec)
or 4 X 10-6 Torr.
In practical deposition systems unwanted gases are a result of desorp-
tion from the deposition sources, substrates, and hot filaments as well as
the chamber walls. Back-streaming gases from the pumps also contribute
contamination species. After prolonged pumping, the residual gases are
typically H 20, CO, CO 2, 02 and N 2.1 For a residual gas pressure p (given in
Torr), the impingement rate on a substrate surface is

R = 3.51 X 1022 p(mT)-1/2 molecules/cm 2-sec (5)

where M is the molecularweight in grams and T is the temperature in oK It

is useful to keep in mind that at a residual gas pressure of 10-6Torrtheflux
of gas incident on a (substrate) surface within the chamber corresponds to
the flux associated with a deposition rate of about 1 A/sec for a material of
typical density.
The achievement of vacuums less than about 10-7 Torr in room tem-
perature systems generally requires prohibitively long pumping times.
Therefore, baking of the walls is used for ultra high vacuum systems.
Because of the temperature dependence of the adsorbed atom binding
(see Equation 13), this procedure is extremely effective. Thus the number
of molecules pumped from a system at 200°C in one second can equal the
number that would be pumped in a whole day at 20°C.5 It is important to
note that the entire system must be heated at one time, because many of
the liberated molecules in a partially heated system will recondense on the
334 Semiconductor Materials

t n

10-4 " , ,
q qo(f)
=

"
..... ,t~~PF1€
N- "fl,j~f4
E ',1):::::0
u l"A ' .... :!OJ
I
u(lJ~ ............
10-5
u
OJ
0.$$) ' ............
~
' .........

..
Vl
!.-
......
OJ

! .-
!.- ,
10-6 "", ,
0
t-
LJ..J ,
t-
«
~
, , " "~IIV,
~>.
0:: ,, ,~~&
c...:> ,, ""~&~
Z
10-7 , ,0- ,~~<
(/) ' ','J~
t
(/) ,~
« ',-</)-; "q~~
',V)
c...:> ,~o
t-
::::> " U')-; ", , ,
0 ' "<6
~~
U 10-8 ,~~
" ", ,
LL..
u ':0,,
LJ..J
a.. ,,
(/) ,,
10-9
,,
,

10- 10 .-. _ .......

1 10 100 1000
TIME (Minutes)
Figure 2: Specific outgassing rate as function of time for various materials. From
Reference 6.

cooler surfaces, from which they can provide a continued source of

impurity gases.
The required pumping time will depend on the application. Deposition
processes are often started when the chamber pressure has reached an
empirically determined value. High pumping speeds are often equated
with cleanliness because of the relationship expressed by Equation 3. This
is not necessarily correct. 4 Two extremes are illustrated in Figure 3. In the
case shown in Figure 3a, the "coating apparatus" fills much of the chamber
and the deposition area is large. The gettering capacity of the coating flux,
 OUTGASSING SOURCE OUTGASSING
COATING FLUX
FLUX FLUX

SUBSTRATES SUBSTRATES III \

CONTAMINATION
f - I FLUX
K_P_

~
COATING fMT
FLUX

p ..... •
RESIDUAL
GAS PRESSURE

/
\
SOURCE

VACUUM PUMPS PUMPS '1J

::::T
CHAMBER VACUUM '<
en
CHAMBER o·
~

~
"0
o~

IMPURITY LEVEL
TOTAL OUTGASSING FLUX . Kp/ JMT oCD
TOTAL COATING FLUX IMPURITY·LEVEL '- TOTAL COATING FLUX
"0
oen

a b
;::;:
o·
::l

Figure 3: Schematic illustration showing influence of apparatus geometry on the way in which wall outgassing affects the coating c..v
impurity level.
c..v
01
336 Semiconductor Materials

Qc' is large compared to the capacity of the physical pumping system. In

such systems the purity of the deposit will be roughly proportional to Q(t)/Qc.
Therefore, the deposit purity depends on the pumping time, t, and the
deposition rate, but is independent of the pumping speed of the vacuum
system. In the case shown in Figure 3b, the deposition process is confined
locally and represents a small perturbation to the vacuum system: Le., the
gettered flux is small compared to the physically pumped flux. In this case
the flux of residual gas which enters the deposition region is given by
Equation 5 and is therefore dependent on the residual gas pressure in the
chamber. For a given pumping time, a larger pump will therefore decrease
this pressure and improve the purity of the deposits. Actual situations will
generally lie between the two extremes shown in Figures 3a and 3b.
However, most production deposition systems will tend toward the case
shown in Figure 3a.

3. EVAPORATION

3.1 Introduction
In the evaporation process, vapors of the coating material are released
from a source because of heating. The source material may be in the liquid
or solid state, depending on its vapor pressure relative to its melting point.
Almost any conceivable method can be used to heat the sou rce. One of the
most common methods is resistive heating, either of the source material
itself or of a support containing the material. Other common heating
methods involve the use of an electron beam, a laser beam, or an arc
discharge to produce local surface heating of the source material.
The evaporation process is usually carried out at a sufficiently low
pressure (typically 10-5 to 10-6 Torr) so that the evaporated atoms undergo
an essentially collisionless "Iine-of-sight" transport to the substrates. In
this connection it is useful to remember that the mean free path of gas
particles is about equal to

X= 5/Pm' cm (6)

where Pm is the pressure in m Torr. Thus at a pressure of 10-4 Torr, Xis of the
order of 50 cm and about equal to the size of a typical vacuum chamber. A
second reason for using a low pressure is to avoid oxidation of the hot
source material and the condensing coating. The substrates are generally
unbiased, Le., electrically isolated or at ground potential.
The advantages of evaporation include the possibilities of high deposi-
tion rates and the fact that the source material can be in a relatively simple
form. Evaporation is most effective for depositing low melting point materials.
Although evaporation can be used for refractory materials, the high tempera-
tures make the process more difficult to execute. Accordingly, it is estimated
that about 90% of the commercial applications of evaporation involve the
deposition of aluminum. Difficulties of stoichiometry control are encoun-
tered in evaporating many alloys and compounds. It is for this reason that
sputtering is replacing evaporation for many microcircuit metallization
 Physical Vapor Deposition 337

applications (see Section 1). A host of special techniques have been

developed for evaporating multi-component materials. These include flash
evaporation, hot-walled evaporation, co-evaporation from multiple sources,
and reactive evaporation. Several of these methods have proven very
effective for depositing semiconducting coatings of high quality.
References 8 to 10 contain detailed discussions of coating deposition
by evaporation.

3.2 Evaporation Rate

The rate at which atoms pass into vacuum from a heated source is
given by the Hertz-Knudsen equation

W = 3.5x1 0 22 a p*/(MT)-1/2 atoms/cm 2-sec (7)

where p* is the vapor pressure in Torr, T is the temperature in oK, and M is

the molecularweight in grams. The parameter a is the evaporation coeffici-
ent. It is dependent on the cleanliness of the evaporation surface and
can range from unity for clean surfaces to very low values (10- 3 ) for dirty
surfaces. 9 The evaporation coefficient can also be less than unity in the
case of materials that evaporate as molecu les for wh ich the Iiqu id-to-solid
phase change involves a change in degree of freedom. 9
Thevaporpressure, p*, isa verysensitivefunction of temperature. This
is shown in Figure 4 for several materials. Thus maintenance of a constant
evaporation rate requires extreme control over the temperature. This is
often a difficult task. This problem is frequently avoided by using an in situ
thickness monitor to simply indicate when the desired coating thickness
has been achieved (see Section 3.7) or by evaporating a fixed charge of
source material to completion.
Rough estimates of required source operating temperatures are com-
monly based on the assumption thatvapor pressures ofrv 10-2Torr must be
established to produce useful condensation rates. Temperatures, To' that
give p*=1 0- 2 Torr are given in Tables 1 and 2 respectively for typical ele-
ments and inorganic compounds of interest in electronics related applica-
tions. More detailed tables are given in References 8-10.
The average energy of the evaporated molecules is 3/2 kT where T is
the source temperature. Thus for the case of gold, where the source
temperature is 1400°C at p* = 10-2Torr, the kinetic energyofthe evaporated
Au atoms will be about 0.20 eV.
The emission of vapor from a liquid or solid surface obeys the cosine
emission law for the case of clean metal surfaces where a = 1, and to first
order for other cases. 9 Thus the evaporated flux from a small source, of
area Ae and evaporation rate W, which is incident on an elemental substrate
area located at an angle ¢ off the perpendicular axis of the source as
shown in Figure 5, yields a deposition flux per unit area of the substrate
that is given by

Wd = -
W-Ae Cos'+' CosO
'I-' (8)
rrr2
338 Semiconductor Materials

10 .....- . . - -.....-,..,..-".-....,.............~-.......,..................~~-.....-.,-...,......

@ MELTING POINT

10.6 _ _ __. _ _ ...

300 400 500 600 800 1000 1500 2000 3000 4000
TEMPERATURE (OC)

Figure 4: Equilibrium vapor pressures of several elements and inorganic com-

pounds of interest in electronics related appl ications.

where r is the distance from the source to the substrate. The CosO term
accounts for the fact that the substrate may not be perpendicular to the
line of centers connecting the source and substrate. The thickness growth
rate of the film is given by

(9)

where N A is Avogadro's number, and M is the molecularweight and p is the

mass density of the deposit.
Deposition rates forthe evaporation process are clearly dependent on
the material being evaporated, the type of evaporation source, and the
position and orientation of the substrate surface. Consider the case of
aluminum evaporation from a 1 cm diameter source onto a substrate
located 15 cm directly above the source (Coset> = 1) and oriented to face
the source (CosO = 1). Thus we have r = 15 cm (this is atypical distance),
and Equation 8 yields Wd = W/?O? From Table 1 we see that a source
temperature of 1220°C is required to provide p* = 10- 2 Torr. We assume
that this temperature is used. Therefore, from Equation? with p* = 10-2
 Physical Vapor Deposition 339

Table 1: Temperatures and Support Materials for Evaporating Elements

Commonly Used in Electronics Related Processing

Melting Temp. (OC) at

Predominant Temp. (OC) 10- 2 Torr T/TN Support
Element Vapor Species --.IM-- T ~ Materials **

Aluminum Al 659 1220 1.61 W,C,BN

Antimony Sb ,Sb 2 630 530 0.89* MO,Ta,BN,Oxides
4
Arsenic As 4 ,As 2 820 300 0.52* Oxides,C
Beryllium Be 1283 1230 0.97* Mo,Ta,W,Oxides
Cadmium Cd 321 265 0.91* Mo,Ta,W,Oxides
Chromium Cr '" 1900 1400 '" 0.77* Ta,W
Copper eu 1084 1260 1.13 Mo,Ta,W,C,A1 20 3
Gallium Ga 30 1130 4.63 BeO ,A1 2 0 3
Germanium Ge 940 1400 1.38 Mo,Ta,W,C, A1 203
Gold Au 1063 1400 1.25 Mo,W,C
Indium In 156 950 2.85 Mo,W,C
Lead Pb 328 715 1.64 Mo,W
Molybdenum Mo 2620 2530 0.97*
Nickel Ni 1450 1530 1.05 W,Oxides
Pa 11ad ium Pd 1550 1460 0.95* W, A1 20 3
Platinum Pt 1770 2100 1.16 W,Oxides
Silicon 5i 1410 1350 0.96* BeO, Zr 02'C
Silver Ag 961 1030 1.06 MO,Ta,C
Tantalum Ta 3000 3060 1.02
Tellurium Te 450 375 0.90* Mo,Ta,W,C, A1 203
Tin Sn 232 1250 3.02 Ta,W,C,A1 20 3
Titanium Ti 1700 1750 1.03 Ta,W,C,ThOZ
Tungsten W 3380 3230 0.96*
Zinc Zn 420 345 0.89* No,Ta,W,C,A1 203
Zirconium Zr 1850 2400 1.26 \V

*Haterials that can be evaporated effectively from solid state.

**See References 8 and 9 for more detailed specifications.

Torr, T = 1493° K, an aluminum molecular weight of 27 gm, and a = 1, we

obtain W= 1.75x10 18 atoms/em-sec. From Equation 8 we obtain W d =
2.5x1 0 15 atoms/cm 2 -sec. If we assume a bulk density of 2.7 gm/cm 3 for the
aluminum deposit, we obtain D = 4.1 Nsec orO.41 nm/sec using Equation 9.
Rates of 1 to 10 nm/sec are typical for many materials. In practice, for a
low melting point material such as aluminum, a p* of about 10- 1 Torr and a
deposition rate of 4 nm/sec would be more typical for many applications.
Finallywe can considerthe impurity levelwhich we might expect in our
aluminum coating. We assume a p* of 10- 1 Torr, so thatthe deposition flux is
2.5x 10 16 atoms/cm 2 -sec. We assu me that the residual gas pressu re du ring
deposition is 10-6 Torr. Thus, using Equation 5 and the molecularweight of
oxygen, we estimate a residual gas flux of 3.6x1 0 14 molecules/cm 2 -sec
reaching the substrate. Since each oxygen molecule contains two atoms,
the implied impurity level is about 30/0. High purity starting material, high
deposition rates, and/or low residual gas pressures are required to assure
high purity deposits.
340 Semiconductor Materials

Table 2: Direct Evaporation of Inorganic Compounds Commonly Used

in Electronics Related Processing

Melting Temp. (OC) at

Predominant Temp. (OC) 10- 2 Torr T/T M Support
Compound Vapor Species * ---.IM.-- T ~ Materials **

A1 2 0 3 A1,O,AlO 2030 -1800 0.90 Mo,W

A120, 02 (A10) 2

1n203 1n, ln 20,02 Vapor species Pt

observed at
1100-1450 oC 9

SiO SiO 1025 MO,Ta

Si02 SiO,02 1730 ""' 1250 0.76 Mo,Ta,W

Ti0 2 TiO,Ti,Ti0 2 1840 Low vapor

°2 pressure at
20000C 9

H0 3 (W0 3 ) 3 ,W0 3 1473 1140 0.81 Pt

Zr02 ZrO,02 2700

ZnS 1830 1000 0.61 Mo

(150 atm)

ZnSe 1.520 820 0.61

(2 a tm)

CdS S2 ,Cd,S ,S38 ft 1750 670 0.47 C,Mo, Ta, W

(100 a tm) A1 2 0 3

CdSe Se2,Cd 1250 660 0.61 A1 2 0 3

PbS PbS,Pb,S2(PbS)2 1112 675 0.68 Mo

MgF 2 MgF 2' (MgF 2 ) 2 1263 1130 0.91 Mo

. (MgF 2 )3

CaF 2 CaF 2 ,CaF 1418 1300 0.93 Mo

*Given in order of decreasing prominence.

**See References 8 and 9 for more detailed specifications.

3.3 Evaporation Sources

Several common types of evaporation sources are shown schematically
in Figure 6.
3.3.1 Wire and Metal Foil Sources. Thesimplest evaporation sources
are resistance-heated wires and metal foils of various types. A wire source
isshown in Figure 6a and a metal foil source isshown in Figure6b. They are
commercially available in a variety of materials and sizes, at sufficiently low
 Physical Vapor Deposition 341

EMISSION FLUX FROM SMALL SOURCE OF AREA A c '

We = W A e Cos ¢

DEPOSITION RATE PER UNIT AREA

WA
Wd = ~ Cos ¢ Cos tJ
1Tr

Figure 5: Flux passing from small area source to elemental substrate area dAs
which inscribes solid angle dw.

prices to be discarded after one use if necessary. The wire or foil supports
must be fabricated from materials which have negligible vapor ordissocia-
tion pressures at the operating temperatures. These temperatures are
typically in the range from 1000 to 2000°C. Wetting of the wire or foil
surface by the evaporant is also desirable in orderto achieve good thermal
contact. Detailed recommendations pertaining to wire or foil support
materials for various evaporants are given in References 8 and 9. These
recommendations for a few evaporants are summarized in Tables 1 and 2.
The most commonly used support materials are tungsten, molybdenum,
and tantalu m. Su itable wire or foil sources are available to evaporate small
charges of nearly all the elements except the refractory metals themselves.
The maximum capacity of wire and foil sources is typically a few grams.
The usual approach is to calculate the charge of source material that will
provide a given deposit thickness, using a relationship of the form of
Equation 8 for the apparatus geometry in question, and then to evaporate
the entire charge. The wire/foil approach is in general too time-consuming
for most production applications, but it is an effective method, for example,
for depositing test electrodes in laboratory studies.
3.3.2 Crucible Sources. Crucible sources are required to support
molten metals in quantities of a few grams or more. Since the melt is in
contact with the container for prolonged periods of time, the selection of a
noncontaminating and thermally stable crucible material is very important.
Detailed recommendations for crucible materials are given in References
8 and 9. The non-metallic support materials summerized in Tables 1 and 2
apply strictly to crucibles. Thus it is seen that graphite and the refractory
 w
~
(\)
METAL FOIL SOURCE RESISTANCE HEATED CRUCIBLE
RESISTANCE HEATED WIRE
(j)
CD
~\gDSJ 3
f).
o
a ~
Q.
C

b c
(')
r-+
o
~

~
Q)
r-+
SUBLIMATION SOURCE CD
~

05"
.+,.~. RF HEATED CRUCIBLE (jf

,'I.
,I' ,,
\ III,

,,\'"" CHROMIUM
ROD

RADIATION
SHIELDS HEATER
MOLTEN METAL

d e
Figure 6: Schematic illustrations showing several types of evaporation sources.
 Physical Vapor Deposition 343

oxides are commonly used in addition to the refractory metals as crucible

materials.
A wide varie'ty of methods are used to heat the crucibles. The most
common methods are radiation heating from a surrounding oven, conduc-
tion and radiation heating from a surrounding coil as shown in Figure 6c,
and rf induction heating as shown in Figure 6e. The latter method has the
advantage that energy is coupled directly into the evaporant metal, so that
it is not necessary to produce crucible temperatures in excess of the
vaporization temperature in order to produce heat flow.
3.3.3 Sublimation Sources. Figure 4 shows that the vapor pressures
of materials increase continuously with temperature and do not show an
abrupt change at the melting point. Tables 1 and 2 show, in fact, that many
elements and compounds reach a pressure of about 10-2 Torr before
melting (Le., TciT M <1 in Tables 1 and 2) and hence can be sublimated at
rates which are practical for coating applications. Direct wire and foil
evaporation is particularly effective for metals with significant sublimation
rates. Figure 6d shows a rod type sublimation source that has been used
for chromium. 9 Sublimation sources remove the problem of contact with
foreign support materials.
3.3.4 Baffle Type Sources. In the evaporation of many materials the
spontaneous release of absorbed or occluded gases can cause the violent
ejection of droplets or, in the case of sublimation, particulates of the
evaporation material. These particles can become incorporated into the
growing film. To avoid this problem, baffled sources are often used which
inhibit direct line-of-sight transmission from the evaporation charge to the
su bstrates. These baffles are typically constructed of Ta and are mai ntained
at sufficiently high temperature to prohibit condensation (see Figure 11 in
Section 3.5). Atoms or molecules incident onto such baffles are generally
re-emitted in a cosine distribution. 8
3.3.5 Knudsen Cell Sources. A Knudsen cell is an evaporation
crucible with a small exit orifice. The orifice is made small enough so that
the evaporation flux passes through it via free molecular flow. The flux is
emitted in a near cosine distribution if the thickness of the orifice is
negligible. 8 Formation of a molecular beam occurs under conditions of
free molecular flow when the apertu re is in the form of a tube. Although the
flux is not baffled, the small size of the orifice makes Knudsen cells
relatively immune to the spitting described above. A principal advantage of
the Knudsen cell is that, when the surface area of the evaporant is an order
of mag nitude larger than the apertu re, control of the evaporant temperatu re
establishes the pressure, p*, which exists inside the cavity in front of the
orifice. Since there is no phase change as material passes through the
orifice, Equation 7 with Q= 1 is closely obeyed. 8This removal of uncertainty
over Q allows effective control of the deposition rate by controlling the
source temperature. (Holland draws the analogy between the use of a
Kn udsen cell and the use of a cavity for obtai ning black body radiation from
a substrate whose emissivity is less than unity.8) Therefore, Knudsen cells
are particularly important when film stoichiometry is to be controlled byco-
evaporation (see Section 3.5).
The general term "effusion cells" is used to identify the class of cells
344 Semiconductor Materials

with flow orifices that are restricted but not necessarily small enough to
satisfy the free molecular flow conditions that are implicit in the particular
case of the Knudsen cell. The flow from effusion cells can be theoretically
predicted if the fluid dynamics of the flow through the orifice is properly
taken into account. However, as a general rule the emission characteristics
as a function of temperature from effusion cells, including Knudsen cells,
are determined experimentally. Figure 7 shows an array of effusion cell
sources used for multi-source deposition of semiconducting coatings of
CulnSe 2 . 11 Effusion cells playa very important role in the process of
molecular beam epitaxy, which is discussed in Section 4.
3.3.6 Electron Beam Sources. Figure 8 shows a schematic diagram
of an electron beam evaporation system. Since the beam is concentrated
on the evaporating surface, while other portions of the evaporant are
maintained at lower temperatures, the evaporant can form its own crucible.
Hence, interactions between evaporant and support materials are greatly
reduced. Electron energies are typically in the 3 to 10 KW range, with
power levels in the range 2 to50 KW. Therefore, relatively high evaporation
rates can be achieved, even forthe refractory metals. Rod-fed sources can
provide a large inventory of coating material. Therefore, electron beam
sources are the most commonly used evaporation sources for large scale
production applications. However, two difficulties that must be dealt with
are, first, that electron beam sources are vulnerable to spitting because of

QUARTZ CRYSTAL
I HEATER I MONITOR

SUBSTRATE

VACUUM -----
CHAMBER

SHIELD

SOURCE
HEATER
COMPUTER
ASSEMBLY
CONTROL

PUMPING
THERMOCOUPLES PORT

Figure 7: Knudsen cell evaporation sources arranged for co-evaporation to form

coatings of Cu InSe2. See Reference 11.
 Physical Vapor Deposition 345

SUBSTRATES

ir·········:································,········ :.:.;.:.: ':/i - - ~~~~~R

VAPOR FLUX

MOLTEN
,,\\t
\ \\\\I'
\ \ \,\\
f I, :! ~
..:.'
MAGNETICALLY FOCUSED
ELECTRON BEAM
POOL
\

ii
EVAPORANT
SUPPORT ELECTRON
BEAM SOURCE

SOURCE MATERIAL
TO VACUUM (MA Y BE ROD WITH
PUMPS AUTOMATIC FEED)

Figure 8: Schematic diagram of electron beam evaporation source.

the high power densities at the point of beam impact, and second, that the
deposition flux is nonuniform as discussed in Section 3.4.
3.3.7 Other Types of Evaporation Sources. Several other types of
evaporation sources have been developed to deal with the particular
problems associated with forming stoichiometric coatings of alloys and
compounds. These are discussed in Section 3.5.

3.4 Deposit Thickness Uniformity

It is difficult to maintain a uniform evaporation temperature over large
surface areas because of radiation losses. 9 Consequently, relatively small
area sources are nearly always used. Deposition fluxes in the substrate
plane are therefore non-uniform, and some type of substrate movement is
generally required.
A small source emitting from its surface according to the cosine law
will provide uniform deposition overthe inside of a spherical surface if the
source is placed on the circumference. 8 This is easily seen from Equation 8
by noting that Cos¢ = CosO, and r = 2 R CosO, for all deposition points on
the circumference of a sphere of radius R. Therefore, planetary substrate
holders of the type shown in Figure 9, which continuously move the
substrates over a hemispherical surface with its center placed about one
radius above the source, are commonly used.
Theoretical deposition profiles calculated from Equation 8 are given in
References 8 and 9 for evaporation from point sources, small area sources,
extended strip sources, cylindrical rod or wire sources, and ring and
circu lar disk sou rces, all depositing onto plane receivers. The calcu lations
show that the thickness uniformity of coatings deposited from flat filament
or crucible sources cannot be improved significantly by enlarging the size
of the sources, but that ring sources are particularly effective in providing
346 Semiconductor Materials

SUBSTRATES

Figure 9: Schematic illustration of planetary type substrate tooling for small

area vacuum coating source.

near-u niform deposits over relatively large areas. In particu lar, the deposit
thickness is uniform over an area about equal to the area inside the ring
when the substrate is placed above the ring at a distance equal to its
radius. This is also an important consideration when using ring type planar
magnetron sputtering sources. See Section 5.6.
Theoretical and experimental deposition profile data are also given in
References 8 and 9 for several practical evaporation sources. The degree
to which wire baskets of the type shown in Figure 6a duplicate a point
source depends on the density of the wire winding. A dense winding
promotes directional emission from the open ends. 8 Flat metal strips or
shallow dimpled boats of the type shown in Figure 6b have been found to
yield near cosine-law emission. The emission patterns from practical
effusion cells of the type shown in Figure 7 tend to be more directional, and
to have a more pointed maximum in the center than the cosine emission
pattern, because the requirement of negligible aperture thickness is
usually not satisfied. The emission patterns from crucibles with relatively
wide openings, and cylindrical cone shaped side walls which can act as
extended emitting surfaces, tend to follow the cosine emission law, although
the deposition profiles are slightly more directional than those predicted
for cosine emission from a flat surface source. Electron beam sources tend
to behave as small area sou rces, but often depart from the cosine em ission
law because the hig h evaporation rates, wh ich are typically ach ieved, yield
high enough vapor densities in the immediate vicinity of the source to
cause collisional scattering of the evaporated molecules.

3.5 Evaporation of Alloys, Compounds and Mixtures

3.5.1 Introduction. The constituents which are present in most inor-
ganic compounds, alloys, or mixtures differ in their vapor pressures. Conse-
quently, during evaporation the composition of their vapors, and hence of
their condensates, is not the same as that of the source material. This
behavior is known as incongruent evaporation.
The available thermochemical data are seldom sufficient for predicting
the conditions necessary to achieve coatings of the desired composition.
AccordinQ'Y, the approach is usually empirical. Often, because of incon-
gruent behavior, coatings of the desired composition cannot be reached
 Physical Vapor Deposition 347

by direct evaporation. This has led to the use of special methods such as
flash, two-source, and reactive evaporation. These processes are discussed
in Section 3.6.
- 3.5.2 Evaporation of Alloys. The constituents in alloys evaporate
independently of one another, mostly as single atoms. However, the vapor
pressures of the individual constituents are not equal to their pure metal
values at the temperature in question, because there is a contribution to
the chemical potential when one metal is dissolved in another. Most
metals evaporate incongruently, and this has led to the use of sputtering
where extreme composition control is necessary. An example is the
deposition of Nichrome (Bo%Ni - 20 %Cr) to form thin film resistors. How-
ever, in the important case of Permalloy(BS%Ni - 1S% Fe), the evaporation
is sufficiently congruent to permit the use of simple single source evapora-
tion for many applications. 8
Electron beam evaporation can significantly expand the range of
materials which can be evaporated with reasonable composition control. 10
This is possible because the electron beam source creates a small molten
region, as shown in Figure 10. During an incubation period the molten
region becomes deficient in the volatile species. The composition is then
rate-limited by the passage of material by diffusion from the solid into the
melt, across interface "A" in the figure. If the vapor pressure difference is
not too large for the constituent diffusion rates, a steady state is developed,
where the composition of the melt is just such as to produce a vapor
composition equal to that of the solid. It is reported that reproducible
compositions of Ni-20Cr, Ti-6AI, Ag-SCu, Ag-10Cu, Ag-20Cu, Ag-30Cu,
and Ni-xCr-yAI-zY have been successfully achieved by electron beam
evaporation. 1o
3.5.3 Evaporation of Compounds. In the evaporation of compounds
the transition to the vapor phase rarely occurs without changes to the
molecular species. Thus evaporation is usually accompanied by molecular
dissociation, association, or a combination of both processes. Dissociation
represents thermal decomposition and generally makes simple direct
evaporation impractical. The species formed in the direct evaporation of a
number of compounds are summarized in Table 2.

EVAPORATED
FLUX

MOLTEN -_-.L;:;::'

REGION

RATE LIMITING
FLUX

Figure 10: Schematic drawing showing equilibration of molten region during

electron beam evaporation.
348 Semiconductor Materials

There are, however, some important compounds that do evaporate as

constituent molecules and thereby maintain their composition. Most not-
able are SiO, MgF 2 and CaF 2, a fact which explains the successful use of
thin evaporated coatings of these materials in the optics industry.12 Similar
behavior is found for B20 3, GaF 2, and most of the divalent group IV oxides
such as GeO and SnO (SiO-like species).9
Generally, the tendency to produce a dissociated vaporflux increases
with increasing evaporation temperature and decreasing pressure. The
evaporation of most oxides requires temperatures in excess of 1500°C.
The binary oxides of Be, Mg, Ca, Sr, Ba, and Ni evaporate predominantly by
dissociation into metal atoms and oxygen molecules, although their vapors
may contain molecular species and in some cases lower oxides. The
tendency to form suboxides is stronger among group th ree metals such as
AI and In (see Table 2). Generally, congruent evaporation is more likely to
be attained with binary oxides than with sesqui- or dioxides, because the
higheroxides tend to lose oxygen attemperatures which are too lowforthe
volatilization of the resulting suboxides. 9 However, it is reported that A1 20 3,
Si0 2, and Th0 2, as well as MgO and BeO, films have been successfully
deposited by direct evaporation using electron beam heating. 9The oxides
of Ti, Zr, Nb, Ta, Fe, and Cr are examples of materials which do not
evaporate congruently and forwhich difficulties have been encountered in
obtaining stoichiometric films by direct evaporation.
The II-VI compound semiconductors are important examples of com-
pounds that undergo complete dissociation on evaporation. However,
both the group II and the group VI elements in these compounds are
relatively volatile, with the consequence that they are amenable to direct
evaporation,13 with the coating stoichiometry being controlled by the
substrate sticking coefficient.
The III-V compound semiconductors are an example of materials that
undergo severely incongruent evaporation. The vapor pressures of the
group V constituents, such as P, As, and Sb, are orders of magnitude
greater than those of the group III elements, such as AI, Ga, and In.
Accordingly, these compounds are difficult to deposit by direct
evaporation. 8 ,13,14
Bi, C, Si, Te, P, As, and Sb are examples of materials that undergo
association to form polyatomicspecies. Forexample, As yields AS 2and As 4.
Other examples are the oxides of molybdenum and tungsten, which can
yield (M0 3)n and (W0 3)n species with n typically equal to two or three.

3.6 Special Evaporation Methods

Several special evaporation techniques have been developed for
depositing materials whose constituents have different vapor pressures.
3.6.1 Flash Evaporation. In this technique small quantities of the
constituents in the desired ratio are evaporated to completion from a
common source using a temperature sufficiently high to evaporate the
less volatile component. Often the evaporant is dispensed as a steady
trickle onto a hot filament. A wide range of apparatus configurations have
been devised for dispensing the source material. See Reference 9. The
method is applicable to the evaporation of alloys, metal-dielectric mixtures,
 Physical Vapor Deposition 349

and compounds. In most cases, the vapors impinging on the substrate are
highly supersaturated, so that the film composition is not affected by the
condensation coefficients. (Condensation coefficients are discussed in
Section 6.1.) The most common problem is incomplete evaporation due to
particle ejection and deflection. Ni-Cr alloys, Cr/SiO cermets, GaAs, InP,
Cu 2 S, and BaTi0 3 are examples of materials that have been deposited by
flash evaporation.
3.6.2 Hot-Wall Evaporation. In this techniquefilms are grown under
conditions that are close to thermodynamic equilibrium.15-16a A schematic
drawing of a hot wall evaporation apparatus is shown in Figure 11. The
evaporated flux is passed into an enclosure with walls held at a sufficiently
high temperature so that condensation is precluded. Accordingly, stoichio-
metric coatings can be deposited, even on substrates maintained at such
high temperatures that one or more of the constituents has a low condensa-
tion coefficient. Since wall condensation is proh ibited, the vapor pressures
of the volatile constituents simply build up until they deposit onto the
substrates at steady state rates that are equal to the rates at which they
enter the enclosure from the evaporation sources. For example, near-
stoichiometric CdTe films have been evaporated from a single CdTe
source maintained at 600°C, with a hot-wall temperature of 500°C, and a

SUBSTRATE
TEMPERATURE - T s

HOT WALL
T>T s
- - - - VACUUM
CHAMBER

EVAPORATION
SOURCES

PUMP

Figure 11: Schematic illustration of hot-wall evaporation system. Baffle of type

discussed in Section 3.3 is shown on one of sources. Arrows show coating flux
directions and are not meant to imply individual atom trajectories, since atoms
are generally re-emitted from walls and baffles in a cosine distribution.
350 Semiconductor Materials

substrate temperature 465°C.16 If two sources are used, as shown in

Figure 11, then the stoichiometry of the coating can be controlled. Thus
non-stoichiometric n-type CdTe coatings were deposited using Cd and
CdTe sources at the following temperatures: Cd-330°C, CdTe-600°C, hot-
wall-550°C, substrate-515°C.16
The key advantage of the hot-wall method is that coatings of materials
with volatile constituents can be grown with controlled composition at
elevated temperatures. Elevated substrate temperatures are often desi-
rable, since coating properties tend to approach bulk values as the substrate
temperature is increased. See Section 6.2.
3.6.3 Close-spaced Sublimation. This is anothertechnique in which a
net thermal transport of coating material occurs under conditions close to
thermodyunamic equilibrium. Figure 12 shows a schematic drawing of a
close-spaced sublimation apparatus. A flat plate source of coating material
and the substrates are maintained in close proximity to one another, being
separated by only a few mm. The temperatures of the source and substrates
are both maintained at values such that the sublimation rates are signifi-
cant, but with a temperature difference so that a net transport of coating
material occurs from the source to the substrates. The space between the
source and substrates is so small compared to the lateral dimensions that
little escape of the vapors occurs. Hot walls, such as those shown in Figure
12, may be used to further hinder this escape. Relatively high deposition
rates can be achieved. For example, CdTe films have been deposited at 67
nm/sec using a CdTe source temperature of 660°C and a substrate
temperature of 600° C, and CdS films at 1000 nm/min using a CdS source
temperature of 720°C and a substrate temperature of 550°C.17
As with the hot-walled method, the advantage of close-spaced subli-
mation is that near-stoichiometric coatings containing volatile constituents

GAS
INLET

VACUUM - . -
CHAMBER HEATER

WALL T>T,
~t:::::;:~~~=:;:::~ __-I---I- SUBSTRATES
NO CONDENSATION
SUBLIMATION

HEATER

PUMPING
PORT

Figure 12: Schematic illustration of close-spaced sublimation type deposition

apparatus.
 Physical Vapor Deposition 351

can be deposited at relatively high substrate temperatures. The films can

be doped by introducing a gaseous impurity. In asomewhat similartechnique
called close-spaced vapor transport, a reactive gas is introduced which
promotes the formation of volatile species and thereby permits the trans-
port to take place at lower temperatures. 18
3.6.4 Multi-source Evaporation. In this method two or more inde-
pendent sources are operated simultaneously, thereby permitting the
deposition of multiconstituent materials which are not amenable to direct
evaporation. The types of sources employed are the same as in single-
source evaporation. An apparatus using effusion cells was shown in Figure
7 and one using open crucibles is shown schematically in Figure 13. By
controlling the power delivered to the sources it is possible, in principle, to
circu mvent the problems of fractionation and decom position encou ntered
in the direct evaporation of most alloys and certain compounds.
There are two central problems in this technique. The first is control of
deposition rates in the exact constituent ratio desired. Control is generally
achieved through direct measurement of the particle fluxes in the vapor
streams. (See Section 3.7.) This feedback method is used for the open
crucible Cu-In-Se evaporation shown in Figure 13. The emission rate from
effusion cell type sources is generally a reproducible function of the
source temperature. Therefore, the effusion rates in multi-source systems
usi ng effusion cells can be controlled byfeed-forward systems that control
the temperatures within the cells, as indicated in Figure 7. The second

VACUUM
CHAMBER
SUBSTRATES QUARTZ CRYSTAL
\ MONITOR (Se)

I HEATER'
I/i\\ ::::::::{\:~:: H:ti}:}:{
SENTINEL
SENSOR SELENIUM
(In &Cu) CRUCIBLES

\\1 .......--- HEATER

CONTROL
HEATER ~
CONTROL

INDIUM
BOAT

WATER COOLED
SHIELD PLATE
COPPER PUMPING
BOAT PORT

Figure 13: Mu Iti-source evaporation system using open crucibles to deposit

Cu InSe2 semiconducting coatings. See Reference 19.
352 Semiconductor Materials

problem encountered in the multi-source evaporation method is the limited

deposition area overwhich coatings have a uniform composition. It is also
important that the sources be arranged to minimize deposition flux angle-
of-incidence effects. See Section 6.2.
Multi-source evaporation permits the co-deposition of materials that
do not form compounds or solid solutions. An example is the co-evaporation
of ceramic oxides and metals such as SiO and Cr or Au to form cermet thin
film resistors. Other examples are metals such as Nb-Sn and compound
semiconductors such as ZnS, CdS, CdSe, BiSe, BiTe, GaAs, InAs, InSb,
AISb, and CulnSe 2, as shown in Figures 7 and 13.
In the case of many compounds the condensation rate is not solely a
function of the ratio of the arriving constituent fluxes, but is also determined
by surface reactions on the substrates. For some compounds involving
constituents of widely differing volatility, a substrate temperature can be
selected such that only the stoichiometric compound can survive and
grow. In such cases less stringent control of the individual impingement
fluxes is required. In fact, one of the important advantages of multi-source
evaporation is its applicability to this so-called "three temperature method".
See Section 6.2. Multi-source evaporation with extreme control over
substrate reactions forms the basis of a special method called "Molecular
Beam Epitaxy" which is discussed in Section 4.
3.6.5 Reactive Evaporation. In this technique a metal is evaporated
in the presence of a reactive gas in order to form a compound of the metal
and the reactive gas. The technique is most commonly used to form
coatings of metal oxides that cannot be evaporated directly because of
complete or partial decomposition. Table 3 lists deposition conditions for
reactive evaporation of some metal oxides. 9
Deposition conditions are selected so that the reactions occur at the
substrate surface. Consequently, the growth process is controlled by the
impingement rates of the metal and reactive gas atoms, the condensation
coefficients of the two species, and the substrate temperature. The central
problem in reactive evaporation is that while the condensation coefficient
of the metal constituent is usually near unity, the condensation coefficients
of the reactive species become very low as full stoichiometry is approached
in the deposit. This is shown forthe Si+0 2case in Figure 14, where an 02/Si
impingement ratio of between 10 2 and 10 3 is required to form coatings
having a composition approaching Si0 2.
It is generally found that the use of high reactive gas pressures, to
provide high impingement ratios, has detrimental effects on film properties:
for example, reduced hardness and refractive index. See Section 6.2.
Accordingly, as can be seen in Table 3, deposition rates are usually kept
low, in the few angstrom per second range, to provide the required high
reactive-gas-molecule to metal-atom impingement ratios without requiring
gas partial pressures above 10-4 Torr. Elevated substrate temperatures
are also generally used in orderto promote the surface reactions, to lessen
the detrimental effects of high reactive gas pressures, and to provide
significant improvements in structure. Coatings deposited at elevated
substrate temperature exhibit improved crystallinity, density, hardness,
optical constants, and dielectric properties. By contrast, films deposited at
 Physical Vapor Deposition 353

:E
..J
iJ..
2.0 '1 1

/
. . _1-
/
"
••
.1 ........

~ 1.5 /
/
Q /
ro- I·
cd:
/

.--
CI:
z 1.0 /
0
u ./
::; •
@ I·
zw 0.5 I
t=)
>- /(
X /
0 /
I I
0
10. 1 100 10 1 102 103
02/Si IMPINGEMENT RATIO

Figure 14: Film stoichiometry versus oxygen-to-silicon impingement ratio for

reactively evaporated fil ms. Data from Reference 20.

Table 3: Reactive Evaporation of Metal Oxides

Evaporated Desired Oxygen Deposition Substrate

Metal Metal Oxide Pressure (Torr) Rate (K./s) Temperature (oC)

A1 A1 20 3 10- 5 - 10- 4 400-500

Cr Cr203 2x10- 5 300-400

Ta Ta20S 10- 4 - 10- 3 700-900

Ti Ti0 2 10- 4 300

Ba+Ti BaTi03 10- 2 2-8 770-1025

Data from Ref. 9.

low su bstrate temperatu res tend to have amorphous or poorly crystallized

structures (see Section 6).
The low reactive gas condensation coefficient occurs because the
reactive gas molecules must undergo dissociative chemisorption on the
surface of the growing film, with the resulting reactive atoms being incorp-
orated into the coating. The reaction process can be stimulated, and high
deposition rates can be achieved, by using a plasma to dissociate the
reactive gas molecules and/or to produce other species that promote the
surface reactions involved in compound formation. The process is generally
referred to as plasma assisted or activated reactive evaporation (ARE). The
reactive gas may be passed through a hollow cathode discharge,21 or an
354 Semiconductor Materials

external electrode may be used to create a plasma discharge in the

deposition chamber as shown by the ARE apparatus in Figure 15. TheARE
process has been successfully used, for example, to produce oxide,
carbide, nitride and sulfide films of various metals. 1o,23

3.7 Deposition Rate and Flux Monitors

One of the disadvantages of evaporation, as com pared, for exam pie, to
sputtering, is that the rate of passage of material into the vapor phase is a
very nonlinear function of the power delivered to the source. Thus as a
general rule, the evaporation flux must be monitored to control the deposit
thickness. Deposition rate and species flux monitors also playa very
important role in the multi-source evaporation process. Several types of
rate monitors are available. They are discussed in detail in Reference 9.

1) Ionization Gauge Rate Monitors. These devices are similar to

hot cathode ionization gauges. They monitor the atom density
in the vapor phase by ionizing the vapors and measuring the ion
current. The obvious difficulty is residual gas contributions to
the current.
2) Mass Spectrometers. Quadrupole mass spectrometers are
small enough so that they often can be conveniently arranged

I SUBSTRATES(S)
ELECTRODE

POWER
SUPPLY

ELECTRON BEAM
EVAPORATOR

VACUUM
CHAf,'SER
VACUUM
PUMPS

Figure 15: Schematic drawing of apparatus configuration for activated reactive

evaporation. From Reference 22. See Reference 23.
 Physical Vapor Deposition 355

to intercept the vapor flux. This method is frequently used in

molecular beam epitaxy (see Section 4).
3) Electron Impact Spectroscopy. The vapor flux is passed through
an electron beam which produces an atomic line emission that
is monitored, usually with a narrow band filter and photomulti-
plier. An electron impact spectroscopy type sensor is used to
monitor the Cu and In fluxes in the apparatus shown in Figure
13.
4) Microbalances. The balance is used to measure the accumu-
lated coating mass on a thin vane.
5) Crystal Oscillators. This method utilizes the piezoelectric prop-
erties of quartz and the fact that the resonant frequency is
influenced by the accumulation of a mass of coating material on
the surface of the crystal. A quartz crystal monitor for controlling
the Se evaporation rate is shown in Figure 13.

3.8 Evaporation Source Material

An advantage of the evaporation process as compared, for example, to
sputtering, is the sim pie form of the starting material; Le., the material does
not have to be in the form of a sputtering target. However, the need for
purity cannot be overemphasized. Impure source material not only results
in impure coatings, but alsocan lead to the difficulties of "spitting" discussed
in Section 3.3. These problems are particularly severe for electron beam
evaporation because of the high power levels involved. Therefore, vacuum
melted, rather than power metallurgy, metal rod sources shou Id be used in
electron beam evaporation.

4. MOLECULAR BEAM EPITAXY

4.1 Introduction
Molecu lar beam epitxy(M BE) is a mu Iti-sou rce evaporation process, of
the type discussed in Section 3.6, which is done with extreme control over
the deposition parameters in order to exploit the kinetic processes of film
growth that are discussed in Section 6.1. MBE has been applied primarily
to the growth of single crystal films of compound semiconductors. Thermal
molecular beams of each constituent of the film are directed to converge
on a si ng Ie crystal substrate under cond itions su itable for epitaxial growth.
Deposition rates are low (typically about 0.1 nm/sec). The low deposition
rates reduce the temperature required to achieve epitaxial growth (Figure
47 in Section 6.2). The low growth rates are made feasible by the use of
ultra-high vacuum systems which have base pressures in the 10- 10 to 10- 11
Torr range and thereby reduce the residual gas contamination flux incident
on the substrates, as discussed in Section 2.
The slow growth rates permit very precise control of layerthicknesses
in the nm range. Shields are used to provide abrupt initiation or cessation
of the molecular beam fluxes and thereby to create sharp interfaces or
356 Semiconductor Materials

precisely controlled doping profiles. The reduced growth temperatures

minimize the disturbance of these built-in composition profiles because of
bulk diffusion.
An important advantage of M BE over most otherforms of epitaxy is the
abilityto include in situ facilities for process monitoring and control and for
surface analysis. These diagnostic tools include (1) quadrupole mass
spectrometers to monitor the composition of the incident beam and the
residual background gases; (2) high energy electron diffraction (HEED)
systems to monitor the surfacE:. structure of the substrate and coating; and
(3) Auger electron spectroscopy(AES) systems to mon itorthe com position
at the substrate surface before and during coating.
Excellent reviews of MBE are given in References 24 to 31.

4.2 Apparatus Configuration

Figure 16 shows a schematic diagram of a typical MBE deposition
chamber. The systems generally have three to eight evaporation sources.
Resistance or electron beam heated sources are usually used. However,
gas phase sources may be used. 32 This arrangement is sometimes referred
to as chemical beam epitaxy. Crucibles are typically made from pyrolytic
boron nitride because of its inertness to metals such as Ga and AI. Source
temperatures are generally controlled to within about O.2°C, using thermo-
couples inserted within the crucibles. 26 Precise temperature control of the
individual cells is essential because of the strong temperature dependence
of the evaporation rate (see Section 3.2). Thus, temperatu re fluctuations of
± 1°C can result in molecular beam flux variations ranging from ±2 to 4%. 28
Sh utters are provided, as noted previously, to abruptly control the flux from

AUGER
ANALYZER
QUADRUPOLE MASS
SPECTROM ETE R

VIEW PORT

FLUORESCENT
ELECTRON SCREEN
GUN

LIQUID
NITROGEN
SHROUD

EFFUSION CELLS

Figure 16: Schematic illustration of MBE deposition chamber with sources con-
figured for depositing GaAs type films.
 Physical Vapor Deposition 357

a source which in turn is controlled to provide a given steady state

emission.
MBE pumping systems typically use carbon vane, turbomolecular, or
sorption pumps for the initial chamber evacuation. Titanium sublimation,
ion pumps, and liquid nitrogen cryopanels are generally used for high
vacuum pumping, although oil diffusion pumps have been used. Most MBE
apparatuses have load locks for introducing the substrates. This is an
important consideration, since long pumpdown times and chamber heating
are generally required to reach ultra-high vacuums in an apparatus that
has been exposed to the atmosphere.
An important aspect of MBE systems is that liquid nitrogen cooled
shrouds are usually designed to cover as much of the wall surface as
possible in the deposition chamber. See Figure 16. In addition to impurity
species such as watervapor and CO, these cryogenic surfaces tend to trap
any coating atoms that are re-emitted from the substrate (sticking coeffici-
ent less than unity). Thus the flux of a given species arriving at the substrate
can be accu rately controlled by the power delivered to its sou rce. The goal
is generally to keep the partial pressures of residual gases with a high
sticking coefficient below 10- 14 Torr in the vicinity of the substrate. 28 A
general guideline is to provide sufficient Iiquid-nitrogen-cooled surface
area in the deposition chamber to yield a pumping speed for water that
exceeds 20,000 liters/sec. 27 In addition, liquid-nitrogen-cooled shrouds
are usually provided in the vicinity of the evaporation sources to prevent
intercontamination and thermal cross talk.
The schematic drawing in Figure 16 shows a number of characteriza-
tion tools, including an Auger spectrometer and an ion sputter gun. A
common practice is to configure MBE apparatuses with separate chambers
for sample analysis and deposition. A diagram of a typical commercial
system of this design isshown in Figure 17. A photograph of the apparatus
is shown in Figure 18. Such systems consist typically of (1) a sample entry
or load-lock chamber with a turbomolecular pump, (2) a sample analysis
chamber with an ion pump, Ti sublimation pump and cryopump, and (3) a
deposition chamberwith similar pumping. The deposition chamber shown
in Figure 17 is equipped with a quadrupole mass spectrometer and a
HEED system. The test chamber is configured to incorporate an ion
sputter gun with provisions also for a range of surface analysis tools such
as Auger electron spectroscopy, X-ray photoelectron spectroscopy, or
secondary ion mass spectroscopy.
The quadrupole mass spectrometer is probably the single most import-
ant analytical tool in an MBE system. 27 The second most widely used
technique is HEED. These instruments are placed in the deposition chamber,
as shown in Figure 16, and are also recommended for production systems. 28
Ion gauges are often used for neutral beam monitoring. Auger electron
spectroscopy is the most commonly used method of composition analysis.
Load lock systems introduce substrates in short time periods ('"\.,15
min) while the growth chamber is maintained in the 10- 10 Torr range. In a
typical machine designed for small production runs, a batch of five two-
inch wafers is introduced into a preparation and analysis chamber, where
they are stored and sequentially cycled through the growth process, while
358 Semiconductor Materials

SAMPLER ANALYSIS MOTORIZED

MANIPULATOR CHAMBER SAMPLE
AND HEATER ROTATION

¥ QMA
SHUTTER
\

SUBSTRATE~
TRANSPORT
CONTROL

VERTICAL ~
CA~~m~GE~~ «( L- E-BEAM
EVAPORATOR
VACUUM \ ~ FLANGE
(OPTIONALj

CONSOLE lr--_e \_-r --------.--...'r----.....

""'"
Ti SUBLIMATION
PUMP AND CRYOPANEL

Figure 17: Commercial MBE deposition system (PHI Model 425). Drawing cour-
tesy of Physical Electronics Division of Perkin-Elmer, Eden Prairie, MN.

five freshly prepared substrates are inserted into the sample entry chamber
and evacuated. 34 Loadlock systems of this type have been designed which
can operate for more than 100 hrs without exposure of the growth environ-
ment to atmosphere. Such systems have wafer processing rates of 3 to 4
wafers per hour. Typical systems can provide epitaxial films with thickness
uniformity of better than 5% over substrates 2 inches in diameter, with
extremely uniform epitaxial layers over about 15 cm 2 of each wafer. 34 New
systems can handle 3 inch wafers, with a general trend to greater produc-
tion capabilities.
The substrates in Figure 16 are shown mounted on a carrousel. Such
carrousels incorporate substrate heaters and thermocouples such that
temperatures up to about 700°C can be maintained within about 0.2°C.26 A
precision manipulator permits the substrates to be accurately positioned
for deposition and HEED analysis.

4.3 Deposition Procedure

Substrate surface preparation is a critical part of MBE. A typical
preparation procedure will be described in some detail, since it applies in a
general sense to all of the vacuum deposition methods. A starting substrate
Physical Vapor Deposition 359

*-
o
c
o
'en
,:::=
o
en
C,)

c
~
+-'
C,)
(1)

UJ
co
C,)
'en
>
...c:
0..
*-
o
>
en
Q)
+-'
!.-
~
oC,)
o
+-'
o
...c:
0..

J:
0..
(/)
~
+-'
co
!.-
co
0-
0-
co
c
o
'';;
'en
o
0-
(1)
"C
UJ '
coZ
~~
*- (1)~
o :~
...c: co
g-et
a,~
0"C
bUJ
.r::. ~
0.. ~

ooE
~t.y
Q) C
a- , -
::S~
C')!.-

u:~
360 Semiconductor Materials

is typically covered with a contami nation layer consisting of carbonaceous

compounds and oxides which must be removed. The most detailed MBE
work has involved the deposition of GaAs onto single crystal GaAs substrates.
The (100) plane is chosen for the technologically important reason that it
has orthogonal (110) type cleavage planes. 27 A typical preparation pro-
cedure involves polishing with a diamond paste followed byetch-polishing
on an abrasive-free lens paper soaked with a sodium hypochlorite or
bromine/methanol solution. 28 The substrate is then rinsed in trichloro-
ethylene, methanol, and distilled water, following which it is boiled in
hydrochloric acid, free etched in sulfuric acid, again rinsed in distilled
water, and finally soldered with In to a Mo backing plate. At this point the
substrates, which are generally contaminated with both oxygen and a
small amount of carbon, are introduced into the MBE chamber.
A typical in situ process within the M BE chamber involves the use of
ion bombardment to remove foreign materials from the su rface, and Auger
spectroscopy to verify that the surface is clean. The sample is then passed
into the deposition chamber and annealed to remove the surface damage
created by the sputter clean ing. In many cases thermal desorption rather
than ion bombardment may be used to avoid composition changes due to
preferential sputtering. It is well established that temperatures in the 525-
535°C range evaporate the passivating oxide film on GaAs without causing
surface composition changes because of incongruent evaporation of the
GaAs.28 In any event, the HEED system is used to verify the crystalline
quality of the substrate surface prior to deposition.
The sources are then adjusted to tempeatures that provide the desired
deposition rates. The shutters are closed during this operation to prevent
deposition on the substrates. The substrate temperature is adjusted to the
desired value and the appropriate shutters are opened to commence
deposition. The HEED system can be used to provide periodic verifications
that epitaxy is proceeding. The quadrupole mass spectrometer is used to
mon itor the beam fluxes and the residual gas partial pressu res. Finally the
coated substrates are withdrawn through the load-lock system.

4.4 Coating Growth

The general principles that govern the growth of evaporated and
sputtered coatings are discussed in Section 6. MBE creates an environ-
ment in which remarkable control can be exerted over these growth
processes. Table 4, from Reference 26, lists some representative semi-
conductors which have grown by MBE. Most of the detailed studies of
growth kinetics have been done on GaAs. However, sufficient work has
been carried out on other binary com pou nds such as InAs, In P, and AlAs to
show that similar behavior is observed for most combinations of AI, Ga, and
In with P, As and Sb. 35 The essential feature is that at the substrate
temperatures used, the column III elements (AI, Ga, In) have near unity
sticking coefficients on the growing coating surfaces, while the sticking
coefficients of the column V elements (P, As, Sb) are dependent on the
density of column III atoms which are available on the surface to react.
Typical substrate temperatures are rv600°C. The excess column V species
 Physical Vapor Deposition 361

Table 4: Representative Semiconductors Grown by MBE

(From Reference 26)

Group IV

Silicon Binary Binary Binary

Germanium GaAs PbTe ZoTe
GaP PbS ZnSe
GaSb PbSe CdTe
lnAs SnTe CdS
InP
lnSb
AlAs
Ternary Ternary Ternary
GaAIAs PbSnTe ZnSeTe
GaAsP PbSnSe CulnSe2
GaAsSb PbSSe
CalnAs
GalnP
GaSbAs

are lost by re-evaporation. Thus, near-stoichiometric coatings can be

grown under a range of deposition conditions, provided that there is an
excess flux of the column V element arriving at the substrate. This type of
growth is described in Section 6.3.
It should be noted that even at the UHV pressures of 10- 10 to 10- 11 Torr
used during MBE deposition, doping levels of 10 17 to 10 18 cm- 3 would
result if all the impurities which are incident on the substrate were incorp-
orated into the film and were electrically active. 36 (See Section 2.) Fortun-
ately, the sticking coefficients for residual gases on III-V compounds are
sufficiently low so that the electrically active im pu rity concentrations are in
the 10 14 to 10 15 cm- 3 range. The main residual impurity in MBE GaAs is
carbon, which appears to be a shallow acceptor with an energy of around
26 meV.27,28 Therefore, undoped GaAs films are generally found to be p-
type. The question of residual impurities and their effects is one that
should be considered in evaluating any new MBE materials and/or appli-
cations.
The incorporation of dopants is a key consideration in MBE. Dopant
incorporation is governed largely by reaction kinetics rather than by
equilibrium thermodynamics. 26 Doping levels are typically less than 10 19
cm- 3. Many of the dopants which are useful in otherforms of epitaxy do not
behave well with MBE. The actual behavior is strongly dependent on the
substrate temperature and the surface reconstruction which occurs during
growth. 26 It is difficult to dope with an element having a high vapor
pressure, since such materials are desorbed prior to incorporation. There-
fore, dopant incorporation is a contemporary research area in MBE. Con-
siderable attention is being given to the use of ion beams. 28 ,3o,37-4o In this
case, the dopant flux is directed at the substrate in the form of an ion beam
with energies in the 0.2 to 1.5 keV range. The kinetic energy of the incident
362 Semiconductor Materials

ions appears to permit them to penetrate into the lattice of the growing
coating to a sufficient degree so that the incorporation probability is
increased.
The complexity of the doping problem is illustrated by the GaAs
technology. Commonly used dopants are Sn, Si, and Ge for n-type and Be
for p-type GaAs.27,28 Tin, which is the most commonly used n-type dopant,
illustrates the complexities that can occur. Surface segregation causes
the Sn to accumulate on the surface in a concentration which is several
orders of magnitude largerthan that in the bulk. The rate of incorporation is
controlled by the Sn surface concentration and the Ga vacancyconcentra-
tion within the GaAs.27 The Sn segregated on the surface precludes the
formation of abrupt changes in doping concentration, since its concentra-
tion cannot be reduced to zero by simply closing the shutter at the Sn
source. Anothersource of complexity occurs because many of the dopants
are amphoteric. For example, under As-rich conditions Ge tends to be
incorporated as a donor, while under Ga-stabilized conditions (see Section
6.3) Ge is incorporated predominantly as an acceptor. 27 Th~se examples
illustrate how the dopant incorporation is dependent on relative substrate
arrival rates of As and Ge atoms as well as the doping flux itself.
The difficulties in forming p-type GaAs are even more severe. The
conventional acceptor dopants for GaAs such as Zn and Cd have high
vapor pressures and therefore low incorporation coefficients. Beryllium
has shown the most promising p-type doping properties, but is an extreme
toxicity hazard. 27 The ion beam technique has been successfully used to
incorporate Zn+ and provide carrier concentrations in the 1019cm-3 range. 28,37
Manganese has been used but causes adverse su rface deg radation. 27 Ion
beam deposition has also been proven effective in Si MBE.40,41

4.5 Applications
M BE is particu larly effective when control over thickness, composition,
and doping profiles are critical to device performance. Such requirements
are often encountered in microwave and optoelectronics devices. These
needs have stimulated the development of MBE technology in general
and GaAs technology in particular. MBE has been used not only to produce
state-of-the-art performance in conventional structures, but also to produce
totally new types of thin film devices. Table 5 lists some devices which
contain epitaxial structures grown by MBE.
GaAs field effect transistors are typically used as low-noise microwave
signal detectors and microwave signal generators. Both low noise and
high-powerfield-effecttransistors require n-type layers less than 1000 nm
thick. Low-noise FET's have been reported using 100 nm thick, heavily
doped, MBE GaAs layers. 27 The linearity of power FET's can be improved
by tailoring the doping profile, a requirement that can be achieved by M BE.
Microwave varactors, mixer diodes, and 1M PATT diodes are otherexamples
of devices in which controlled doping profiles are required and therefore
where MBE is useful. 27
The formation of low-resistance contacts to n- and p-type GaAs, as well
as Schottky barrier diodes on GaAs, is also of great technological importance
 Physical Vapor Deposition 363

Table 5: Devices Whose Epitaxial Structures Have Been Grown by MBE

(From Reference 34)

Discrete microwave devices

Low noise FETS
Power FErS
Novel FET structures
It-WATT diodes
Mixer diodes
Varactor diodes
Gun diodes

Discrete optoelectronic devices

Laser diodes
Waveguides
Integrated optics
Taper couplers
Light-emitting diodes
Photodetectors

Other devices
Diodes
MIS capacitors
Superlattices
Tunnel triodes
Solar cells

in microwave and optoelectronic device fabrication. The unique capabili-

ties of MBE are well suited to first growing the epitaxial layer structure
needed fordevice operation, and then growing the required metal film onto
the freshly deposited semiconductor surface in the same growth cycle
without breaki ng vacu um. The sem iconductor su rface is never exposed to
the atmosphere or solvents. M BE in situ metallization makes the repro-
ducible production of ideal metal-semiconductor interfaces feasible. 29
This is a particularly important consideration as very small circu it dimensions
are contemplated.
The high electron mobility transistor (HEMT) and the multiquantum
well (MOW) laser are examples of novel thin film devices which have been
produced by MBE.ln the case of the HEMT device, a thin Ga 1 _xAl xAs layer is
grown in the middle of a GaAs active channel. As a result of the greater
electron affinity of the lower bandgap GaAs, the donor electrons from the
Ga 1_xAl xAs layer thermalize in the GaAs active layers, where they are no
longer scattered by the ionized parent donors. Such devices can have very
fast switching times (in the 10 ps range).34
The double heterojunction injection lasers consist essentially of a thin
active layer at the interface of a p-n junction. 34 The higher refractive index
of the active layer with respect to the confinement layers forms an optical
waveguide that, with cleaved mirror faces, can define a resonant optical
364 Semiconductor Materials

cavity. The band energies of the active layers are such that the charge
carriers injected under forward bias are trapped in the active region. In
recent work, lasers with unique performance have been fabricated by
making the active layers have the form of quantum well superlattices
consisting of alternate layers of materials with different bandgaps and with
layer thicknesses less than the Debye length. Thus, in one example, fourteen
GaAs quantum-well active layers, only rv14 nm thick, were sandwiched
between Alo.27Gao.73As confinement layers rv13 nm thick. 34 ,36 Injection
MOW laser diodes are of great importance in fiber optics communication
systems, because laser operation can be tailored to emit at frequencies
well above the standard lasing frequencies of the host material, and
thereby to control the losses in the fiber optics. The deposition of superlattice
structures with properties not found in homogeneous materials is an
active area of current research which can be expected to yield a host of
applications in the future. 42 ,43

5. SPUTTERING

5.1 Introduction
Sputtering is a process whereby material is dislodged and ejected
from the surface of a solid or a liquid due to the momentum exchange
associated with surface bombardment by energetic particles. A source of
coating material called the target is placed into a vacuum chamber along
with the substrates, and the chamber is evacuated to a pressure typically in
the range 5x1 0- 4to 5x1 0- 7Torr. The bombardi ng species are generally ions
of a heavy inert gas. Argon is most commonly used. The sputtered material
is ejected primarily in atomic form. The substrates are positioned in front of
the target so that they intercept the flux of sputtered atoms.
The most common method of providing the ion bombardment is to
backfill the evacuated chamber with a working gas in the 1 to 100 mTorr
pressure range and to ignite an electric discharge with the target serving
as the cathode or negative electrode. Such an apparatus configuration is
shown schematically in Figure 19. Applied potentials are typically between
500 and 5000V. Direct currents are generally used when the target
material is a good electrical conductor. Radio frequencies are used when
the target material is poorly conducting or an insulator. Deposits of poorly
conducting metallic compounds can also be formed by dc sputtering the
metallic component while injecting other constituents in the gas phase.
This is known as reactive sputtering. A voltage bias may be applied to the
substrates so that they are at a negative potential relative to the plasma
and therefore subject to an ion bombardment that can influence coating
properties. This is known as bias sputtering.
The most striking characteristic of the sputtering process is its uni-
versality. Since the coating material is passed into the vapor phase by a
mechanical (momentum exchange) rather than a chemical or thermal
process, virtually any material is a candidate coating. Films containing
almost every element in the periodic table have been prepared by sputter-
 Physical Vapor Deposition 365

CATHODE
WORKING
GAS FEED

TARGET ',' GROUND

','
',' SHIELD
::: "

ION FLUX
POWER
SPUTTERED
SUPPLY
FLUX

PLASMA
Ii +
::
" ANODE

~~,
SUBSTRATES ~':'~:':':~':':'~:':':~':':'~:':':~':':'~:':':~':':'~:':'::: VACUUM
CHAMBER

Figure 19: Schematic drawing showing glow discharge sputtering apparatus of

the planar diode type,

ing. Alloys and compounds can generally be sputter-deposited while

preserving their composition. For example, organic bone has been sput-
tered, with the deposits having an amorphous microstructure rather than
the crystalline structure of the target material, but an identical composition. 44
PTFE (Teflon) has been sputtered to produce films having many of the
properties of the starting material. 45 ,45 However, most applications involve
metals and more common compounds such as aluminum oxide. One of the
primary applications of sputtering is for interconnect metallization in
integrated circuits. Other areas attracting increasing attention are films for
magnetic47 and optical data storage. 48
A series of review papers in References 49-59 trace the recent develop-
ment of the physics and technology of sputtering.

5.2 Basic Sputtering Mechanisms

In sputter deposition we are concerned primarily with what is termed
physical, as opposed to chemical, sputtering. In physical sputtering, the
bombarding particle transfers kinetic energy to the target atoms and
incurs the subsequent ejection through the target surface of those atoms
which acquire sufficient kinetic energy to overcome the local binding
forces. In chemical sputtering, chemical reactions induced by the impinging
particles produce an unstable compound at the target surface, which
subsequently passes into the gas phase. 5o Chemical sputtering is particu-
larly important in plasma etching applications. See chapter on plasma
etching.
366 Semiconductor Materials

The fundamental event in physical sputtering is an atomic collision. It

is therefore useful to review the case of asimple binary hard-sphere elastic
collision, in which an incident particle of mass M j and velocityV j impacts on
a line of centers (zero impact parameter) with a target particle of mass M j
which is initially at rest as shown in Figure 20a. Three observations can be
made: (1) the target particle is driven deeper into the target by the
momentum exchange, (2) the momentum passed to the target particle is
greatest when the two particles are of identical mass, and (3) the bombarding
particle will be reflected if its mass is less than that of the target particle.
From the first observation listed above we see that a single binary
collision will not, in general, produce sputtering. The ejection of a sputtered
particle, due to a bombarding particle incident normal to the target su rface,
requires a sequence of collisions so that a component of the initial
momentum is changed by more than 90°. Sputtering should therefore be
envisioned as a statistical process that occurs as a result of a collisional
cascade which is initiated by the incident energetic particle. A general
picture of the collisional events within the cascade has been provided by
theoretical and computer modeling studies. 61 -66 At the bombarding energies
of interest in sputter deposition, the sputter ejection is believed to result
primarily from the scooping action as a low energy knock-on passes
underneath an adjacent atom, or from a primary knock-on or reflected ion
which approaches the surface from within the target and dislodges a
surface atom by striking it on the under side. Both cases are shown in
Figure 20b. Although the energy from the impinging particle is partitioned
over a region of target material that may extend 5 to 10 nm below the
surface,67 the particular collisions that give rise to sputtering occur primarily
within about 1 nm of the surface. 66 ,67 It is interesting to note that recent

INCIDfNT
ION

@V j INCIDfNT
SPUTTERED ION

I
M._Mt)
I""'V~::: _ I-
( Mj +M
V·
I
ATOM
~
J SPUTTERED

: t: :!I!I !I\1:!I;~a;~l:l l!,---

:!l:I: .: l;li: :i
t ATOM

~ LOW ENERGY
OOOO~ KNOCK-ON
r
LATTI CE
PRIMARY
KNOCK -ON
ATOMS

a b
Figure 20: Schematic diagram showing some of the momentum exchange proc-
esses that occur during sputtering; V i is the ion velocity, V t is the target atom
velocity, and the prime denotes velocities after the collision. From Reference 59.
 Physical Vapor Deposition 367

computer simulations indicate that some cascades produce no sputtered

atoms while others produce two orders of magnitude more ejected atoms
than the average measured value. 66 Thus the majority of the sputtered
atoms originate from a small fraction of the cascades. Therefore, these
simulations suggest that one should not think of the average cascade,
which may produce one or two sputtered atoms, as being the typical
sputter-producing cascade. The majority of the sputtered atoms originate
from cascades producing perhaps 10 or more ejected atoms.
The general nature of collisional cascades in "knock-on" sputtering
have been classified into (1) the single knock-on regime, (2) the linear
cascade regime, and (3) the spike regime. 64 In the single knock-on regime,
recoil atoms, resulting from the collisions between the incident particles
and the target atoms, receive enough energy to be sputtered but not
enough to produce recoil cascades. In the linear cascade regime, recoil
atoms produced by the interaction of the bombarding particle with the
target have sufficient energy to generate recoil cascades. However, only a
small fraction of the target atoms within the cascade volume are set in
motion. In the spike regime, the density of recoil atoms is so high that the
majority of the atoms within the spike volume are set in motion.
The bombarding particle masses and energies that are used in sputter
deposition produce behaviors that fall into single knock-on (low and
medium eV range) and linear cascade (keV range) regimes. The single
knock-on regime also appears to apply to a process called ion-induced
desorption, which is very important in sputter cleaning and bias sputtering
(see Section 6.4). Thus theoretical studies indicate that the sputter desorp-
tion of nitrogen from tungsten occurs via mechanisms where (1) the
bombarding Ar ions are reflected from the tungsten lattice and dislodge
the nitrogen atoms by striking them from beneath, and (2) the nitrogen
atoms receive momentum directly from the incident ions and escape by
being reflected from the tungsten lattice. 68 The spike regime applies to
heavy ions or molecules that strike the target at high. energies.
The second observation concerning the basic momentum exchange
shown in Figure 20a is that the momentum exchange between the bombard-
ing particle and the target particles is greatest when their masses are
equal. The actual sputtering process is complicated, of course, by the fact
that it involves a complex sequence of collisions of various types involving
the bombarding particle and the various species that compose the target,
as well as the target atoms interacting among themselves. However, as a
general rule for a given material, the sputtering rate will be highest when
there is a good match between the masses of the bombarding particle and
the atoms within the target. 69 ,70 Accordingly, argon is generally used as a
sputtering working gas because of its inertness, its mass compatibility with
materials of engineering interest, and its low cost.
The third observation from Figure 20a is that the bombarding particle
may be reflected backward in asingle collision if its mass is less than that of
the target atom. The energy of the reflected particle may be a significant
0
fraction of its initial energy. For a 180 reflection (line of centers impact)
this fraction is (M j-M t)2/(M j+M t).2 Thus for a 500 eV Ar particle, mass 40,
0
undergoing a 180 reflection on a Motarget, mass96, the reflected particle
368 Semiconductor Materials

will have an energy of85 eV.lf M j > M t , a 180 reflection of the bombarding 0

particle requires more than one collision.

In most sputtering applications the majority of the bombarding particles
are ions. An ion approaching a clean conducting surface has a high
probability of being neutralized by an emitted electron priorto impact.7 1,72
Consequently, the reflected particle will be neutral and unaffected by the
electric field in the vicin ity of the negatively biased target. Therefore, when
M j < M t the sputtering process produces a flux of energetic reflected
working gas species as well as sputtered particles. At low working pressures
these reflected atoms can reach the substrates with a substantial fraction
of their initial energy. The bombardment of a growing coating by these
reflected working gas atoms can have an important influence on coating
properties and can result in the reflected atoms becoming entrapped in
the coating. 73 -78 Figure 21 shows the concentration of entrapped working

ENTRAPPED WORKING GAS

4 ~ MoINe

",

TaQ../'"
",UW
.",
0 ......
...c: " "Gd
,,-
~
Q,)
,('
Q.
Rh // \
u
'E
o
q,/ METAL FILMS
5 0.4 ZroO~o SPUTTERED
en / / 0 D. MolAr IN Ar
~
Co:)
/ Nb
o I
w
I
~
~ I
a: /
~ 0.1 I
w
I
CjSS
I
0.04 I
. I
T'OQCr
I ~ Mo/Kr
,
,,
VO

0.01 ~ ~~ ~ ....
o 2 3 4 5
MASS RATIO (Mt/M g )

Figure 21: Entrapped work ing gas in metal coatings deposited at low pressures
using cylindrical-post magnetron sputtering sources. 77 Circular data points refer
to metals sputtered in Ar. Triangular data points from study in which Mo was
sputtered in Ne, Ar and Kr .78
 Physical Vapor Deposition 369

gas as a function of the target-to-working gas mass ratio for metallic

coatings sputter-deposited at low working pressures. Bombardment by
these reflected atoms is an important consideration in controlling coating
properties and is discussed in Section 6.5.
It is clear from our previous discussion that the processes induced
within the target involve a much larger number of particles, and a much
greater amount of energy, than is represented by the actual sputter
ejection process. The binding energy of a surface atom (sublimation
energy) is typically in the range from 5 to 10 eV,?9 The energy, Ed' to
displace an atom from its regular lattice site in the bulk is about 25 eV.80 For
a typical material, an incident 500 eV bombarding particle will produce, on
the average, about one sputtered atom with a kinetic energy of about 20
eV. Therefore, most of the particle energy, about 450 eV neglecting
reflection, is dissipated within the target. This will result in the displacement
of about 450/(2 E~ = 9 target atoms. 81 In metals a very efficient process of
recovery sets in so that the final defect density is much smaller. 80 However,
particularly in covalently bonded materials, high incident particle fluxes
can cause an amorphous surface layer to develop.82 In addition, the
probability of the incident particles being trapped in the target increases
rapidly above a threshold energy of about 100 eV.83 Thus an inert gas
density, which depends on a balance between the rates of implantation
and release, will develop near the target surface. At very high bombarding
particle fluxes the density of entrapped gas can be large enough to
influence the sputtering process. 84 Thus the impacting particles can have
a very great effect on the target material in addition to simply producing
surface erosion. It is for this reason that ion bombardment of a coating
during deposition can be used effectively to modify its properties (see
Section 6.4).
5.3 Sputtered Species
The sputtered species are primarily atoms. 53 ,55 However, atomic clus-
ters and molecular fractions have been observed as well as positive and
negative ions. Relatively little experimental data is available on the ejection
of sputtered material as molecules or clusters.
Mass spectroscopy measurements indicate that the proportion of
material ejected as dimers (two-atom clusters) is a few percent or less for
Ar-sputtering of metals. 85 -8? The fraction oftrimers isan orderof magnitude
less. Computer modeling indicates that metal atom clusters are not sput-
tered as a unit, but form in flight because the sputtered atoms come into
close proximity as they leave the target surface. 88
The formation of molecular fractions is much more common in the
sputtering of compounds. Measurements for alkali halides and oxides
indicate that molecu larfractions can accou nt for a significant proportion of
the total sputtered flux. 89 -92 For oxide targets the MO dimer fraction
increases with the strength of the M-O bond. 50 AI 20 3 and AIO molecules
have been identified from the Ar+ sputtering of A1 20 3,91,92 PrO from Pr2°3,90
and SnO from Sn0 2.90
Molecular fractions have also been observed in reactive sputtering.
Thus Ar+ bombardment of oxidized W was found to yield WO and W0 2
370 Semiconductor Materials

species. 93 Similarly, O 2 + bombardment of Mo produced MoO and Mo0 2 as

well as MO,93 and O 2 + bombardment of Ti and Zr produced TiO and ZrO
species. 94 The mechanism for the formation of molecular fractions from
compounds, or in reactive sputtering, may be similar to the pure metal
case, with the bonds forming just as the atoms leave the target surface.
The fraction of positive ions in the sputtered flux is generally less than
one percent and is relevant mainly to surface analysis methods such as
SIMS.55,95,96 In a glow discharge sputtering source, the electric field over
the target surface prevents the escape of positive ions. However, negative
ions can be accelerated to very high energies in this field and ultimately
impact on the substrates. The yield of negative ions can be very high for
targets which contain the combination of one constituent with a low
ionization potential and another with a high electron affinity.97,98 For
materials such as SmAu, it has been found that the flux of negative ions
reaching the substrate can be large enough to cause a significant reduction
in the deposition rate via backsputtering. 97
The sputtered atoms are ejected from the target surface with con-
siderable kinetic energy-for example, 50-100 times higher than in vacuum
evaporation. 53 ,55,59 The energy distribution is approximately Maxwellian,
with a most probable energy of about one half the surface binding energy,
and a slightly overpopulated high energy tail, so that the average energy is
of the order of 10-40ev. 53 See Figure 22. Increasing the bombarding ion
energy increases the population of the high energy tail. However, the
average energy of the ejected particles ceases to increase significantlyfor
ion energies above about 1 keV. 53 The atoms ejected from most metals
(Z>20) under Kr bombardment have average velocities which lie in a relative-
ly narrow range (4 to 8 km/sec), so that the average kinetic energies increase
with the ion mass as shown in Figure 22. Ejection velocities under Ar

60 .....- -.....- - -.....- - - . . . - - - . .I . - - -...

AVERAGE EJECTION ENERGIES I
KRYPTON BOMBARDM ENT :
IONENERGY-1200eV . Re: ·U
-----r-----t-----i---w:-r-~-
I I ........... Y
I

: : yrapt
20 - -----2~~~~ ~.zri~2Rh -- ~ ----- _.L
. \\,.NI ~ I Au
__----
Ti~ . . . . . eGe: .Pd: I
AI"Sii V-';
·Cu I . I :

o.. . .~e/
. : Co :
I
A9:
I
:
I

o 20 40 60 80 100
ATOM IC NUMBER
Figure 22: Average energies of sputtered atoms produced by 1.2 KeV krypton
ion bombardment. The line corresponds to a velocity of 6 Km/s. Data from Ref-
erence 53.
 Physical Vapor Deposition 371

bombardment are about 20% lowerthan for Kr bombardment,37 and thus in

the range of 3 to 6 km/sec. Several theories have been developed to
describe the energy distribution of atoms sputtered from a target. 99 A
relatively straightforward model by Thompson permits a calculation of the
energy distribution of the sputtered atoms as a fu nction of the incident ion
energy, the ion and target atom atomic masses, the interatomic potential,
the surface atom binding energy and the nearest neighbor spacing of the
target atoms. 100
Atoms sputtered from polycrystalline or amorphous targets under
perpendicular ion incidence at typical working energies (1 to 3 keV) are
ejected in nearly random directions as a consequence of the multiple
collisions that occur within the target, and therefore have near-cosine
distributions. 53 At low ion energies('"I.J 1 keV) the distribution may beslightly
under cosine (more emission at large angles) and at higher energies ('"I.J3
keV) over cosine. 52 Under oblique incidence the target atoms are sputtered
in the forward direction from smooth surfaces. However, the roughness of
most practical targets causes a trend toward random emission. This is
particularly true for polycrystalline targets, where the difference in yield for
different crystallographic directions can lead to an increase in surface
roughness as sputtering proceeds. Thus a cosine distribution is generally
a good approximation for calculating deposition profiles. Particles sput-
tered from single crystal targets, or from targets with a high degree of
preferred orientation, are preferentially ejected along crystallographic
directions. 53 This apparently occurs because low energy atomic interac-
tions in solids involve collective types of motion that may be more or less
columnated in specific directions. 54

5.4 The Sputtering Yield

The sputtering process is quantified in terms of the sputtering yield,
defined for a monoelement target as the average number of target atoms
ejected per incident particle. For multi-element targets one has the partial
sputtering yield of component i, defined as the average number of sputtered
atoms of component i per incident ion, and the component sputtering yield,
defined as the partial sputtering yield of component i divided by the
equilibrium surface concentration of species i during sputtering. 101
The yield depends on the target species and its surface topography,
and on the bombarding species and its energy and angle of incidence. It is
insensitive to the target temperature. 53 The yield is also independent of
whether the bombarding species is ionized or not, as ions have a high
probability of being neutralized by a field-emitted electron priorto impact
as discussed in Section 5.2. However, ions are generally used because of
their ease of production and acceleration in a glow discharge. At the
bombarding energies used for sputter deposition, molecular bombarding
species behave as if the atoms of the molecule arrived separately with the
same velocity as the molecule and initiated their own sputtering events. 53
High energy molecular bombardment in the spike regime can induce
nonlinear behavior and a sputtering yield that is substantially higher than
twice the single particle yield. 54
372 Semiconductor Materials

Sputtering yields are generally determ ined experimentally. Figure 23

shows experimental yield versus ion energy data for several materials
sputtered with Ar ions under normal ion incidence. Additional data are
given in Table 6 and in Reference 105. The yield dependence on the
bombarding ion energy is seen to exhibit a threshold of about 10-30 eV,
followed by a near-linear range which mayextendtoseveral hundred eV.At
higher energies the dependence is less than linear. The sputtering process
is most efficient from the standpoint of energy consumption when the ion
energies are within the linear range.
Considerable progress has been made in theoretically predicting the
sputtering yield forelemental materials. Sigmund's Iinearcascadetheory61-64
correlates well with experimental values in the near-linear energy range 106
and has become the most widely used. The analysis expresses the sputter-
ing yield as

(10)

where K is a constant in the range from 0.1 to 0.3, M j and M t are the masses
of the incident ion and target atom respectively, E is the energy of the
incident ion, and Uo is the binding energy of the target atom (usually taken

4.0 r---~-~-~----,.--.,--.-~-_-_

ARGON
Ag
3.5

3.0
r::
o Cu
.:::
E
o 2.5 Pb
~
o
~ 2.0
>:
"
z
ffi 1.5
Ni

~
~
::>
0..
(I) 1.0

0.5
 Physical Vapor Deposition 373

as the sublimation energy). a(Mt/M j ) is a monotomically increasing function

of Mt/M j , which is tabulated in References61 and 64. Attypical mass ratios
(M t /M j rv 2) the value of a is about 0.3.
The Sigmund formulation has been correlated with existing yield
measurements and then used to estimate yield values for elements such
asCd, Zn, Sn, and Sbwhere low energy experimental data are not generally
available. 106 Accordingly, theoretical values are listed on Table 6 where
experimental values are not available.

Table 6: Sputtering Yield for Various Materials Under Argon Bombardment*

Target Ion Energy (eV) Yield Reference

Au 600 2.8 54
Bi 500 6.64 56
Cd 500 7.20 106
Cr 600 1.3 54
Dy 500 0.88 56
Er 500 0.77 56
Eu 500 5.02** 106
Gd 500 0.83 56
Hf 500 0.70 56
In 500 3.25 106
Ir 500 1.01 56
Fe 600 1.3 54
Mn 500 1.9 56
Nb 600 0.65 54
Nd 500 2.65** 106
Os 600 0.95 54
Pb 500 4.81 ** 106
Pd 600 2.40 54
Pr 500 2.40* * 106
Pt 600 1.60 54
Rb 500 9.20* * 106
Re 600 0.40 54
Rh 600 1.50 54
Sb 500 2.83 56
Se 500 3.35** 106
Sm 500 0.80 56
Sn 500 1.20 56
Ta 600 0.60 54
Tb 500 2.25** 106
Te 500 4.34 ** 106
Th 600 0.70 54
W 600 0.60 54
Zn 500 5.07** 106
Zr 600 0.75 54
*See Figure 23 for elements not given in this table.
**Theoretical prediction.
374 Semiconductor Materials

The general dependence of the sputtering yield on the ion angle of

incidence is indicated in Figure 24. 107 The relationship provides another
example of the surface nature of the sputtering process. An ion which is
incident on the target surface at an angle () will, to first order, have its path
length increased by a factor Sec () before it leaves the depth, d, where
the primary sputtering momentum exchange occurs. At large angles of
incidence, ion reflection dominates and the yield decreases. In glow
discharge sputtering devices the ions generally approach the target in a
direction normal to the target surface. The relationship shown in Figure 24
is of particuiar significance when the target surface is highly irregular. This
will be discussed in Section 5.5.
Note in Figure 23 and Table 6 that the yields of most metals are about
unity and within an order of magnitude of one another. This is in contrast,
for example, to evaporation, where the rates for different materials at a
given temperature can differ by several orders of magnitude. See Section
3.2. It is this universality that makes sputtering such an attractive process
for many applications.
Figure 25 shows the dependence of the sputtering yields for Ag, Cu,
and Ta on the species of the bombarding ion. 10B Although the ion energies
are considerably above those used for sputter coating technology, the

SfC8~;
I
I
I
I
I
I
I
I

8
max 7T/2
ANGLf OF INCIDfNCf (8)

Figure 24: Schematic diagram showing variation of sputtering yield with ion
angle of incidence. Ion energy is constant. From Reference 59.
 Physical Vapor Deposition 375

I
I

: : : : : : : SILVE R
50 - - - - ~I - - - - "t"I - - - - -+ - - - -
I
~ - - - - + - - - - -+ - - - - ~ - - - -
, t I I
- - - - +I - - --
I I I I I I I I
I I I I I I I I

z 40 ----1----~- --- ~ -- --l----~--Xe- -1-- -- ~I -- -l-- --1----

o I
, I
I
I
I
I
I
I
I
I
I
I
I
I
I
I I , I I I I I I
(/)
I I I I I I I I I

~ 30 ----+-----+---- +----+-----+ -- -+- -- +----+-----~----

I I I t I I I I
t-
<: I I 'Kr I : I !
: : : : I , I : cOP FE R
~ 20 ----~----+----~-- ~ ---+----~----+---- ----~----
I I ' , I I I I
I I I , I I , I

: Ar: I : ~ j :

10 ----~--- ~- -+----+- --+----+----

N I I I I
.e : I TAN t ALU M
I I

o L...-....&C.....a::ll.......Slojl:::~T~j"----'---~Z~r----L--"'---~---------
o 10 20 30 40 50 60 70 80 90
ION ATOMI C NUMBER

Figure 25: Sputtering yields for various ions impacting at normal incidence on
silver, copper, and tantalum surfaces at high energies (45 keV). Data from Ref-
erence 108.

figure does illustrate the trends. It is seen that the noble gas ions give the
highest yields. Of particular interest is the fact that yields vary much more
with ion species, a factor of 100 or more, than they do with atom species, a
factor of 10. 53 This occurs because the bombarding ions form alloys or
compounds with lower sputtering yields on the surface of the target. Note
that the yields are particu larly low for active species such as Be, C, Mg, Si.
Ti, and Zr. The formation of target surface compounds with reduced
sputtering yields is commonly encountered in reactive sputtering. See
Section 5.9.
It was mentioned in Section 5.2 that inert working gasspecies become
entrapped in the target. The amount of gas entrapped in a target can be
large enough to influence the sputtering yield,84 although this is not a
problem in most practical applications. The mechanism of release is still
unresolved. 109 Measured equilibrium argon densities in tungsten imply
that if the release is by argon sputtering, then the inert gas yield is an order
of magnitude larger than that of the host tungsten lattice. 83
An im portant consideration in reactive sputtering and sputter clean ing
is the sputter desorption of reactive gas species that have become chemi-
sorbed on the surface of a target or substrate. Calculations and measure-
ments indicate that such species are sputtered as atoms with yields that
are of the same order of magnitude or higher than those of elemental
materials. 58 See Section 5.2.
Sputtering apparatuses are generally calibrated to determine the
deposition rate under given operating conditions. However, yield data of
the type described above are often used in projecting rate changes when
changing coating materials and in estimating the amount of material
removed during sputter cleaning and bias sputtering. The erosion rate is
given by
376 Semiconductor Materials

R= (0.10) JSMA/p nm/sec (11 )

where J is the ion current density in mA/cm 2 , S is the sputtering yield in

atoms/ion, M Ais the atomic weight in grams, andp is the density in gm/cm 3
of the target material.

5.5 Sputtering Alloys and Compounds

An important advantage of the sputtering process is that the composi-
tion of a sputtered film tends to be the same as that of the target, provided
that (1) the target is maintained sufficiently cool to avoid diffusion of the
constituents, (2) the target does not decompose, (3) reactive contaminants
are not present, (4) the target-to-substrate transport is the same for all of
the constituents, and (5) the sticking coefficients at the substrate are the
same for all of the constituents. 95 Composition control of alloys and
compounds is a very important consideration for many electronics-related
applications, as discussed in Section 5.1, and has led to wide usage of
sputtering.
In sputtering multi-component materials, one finds in general that the
different components are sputtered at different rates. 82 ,99,11 0,111 This creates
a surface or"altered" layerwh ich has a different com position from the bu Ik.
However, if conditions (1) and (2) above are satisfied, conservation of mass
requires that one sooner or later reaches a situation where the sputtered
flux leaving the target has the same composition as the bulk. In this
equilibrated condition the composition of the altered layer isjust such that
the effective sputtering yield times the surface concentration for each
species is proportional to its composition in the target. The thickness and
composition of the altered layer will depend on the target material and
sputtering conditions. Typically thicknesses are similar to the range of the
bombarding species, with values of 30-1 00A.82,99,11 0,112 A change in sput-
tering conditions will in general require an adjustment of the altered layer.
Thus one must allowforsuitable equilibration times when sputtering multi-
component materials. It is important to note that the effective sputtering
yield of a constituent in an alloy orcompound will not be the same as that of
the constituent by itself, because of the different binding energies and the
different atomic masses involved in the collision sequence within the alloy
or compound. 62 ,63,111
Failures to achieve coatings having the same composition as the
target can generally be traced to a violation of one of the points listed
above. The most straightforward case is that of homogeneous single
phase alloy targets. Suitably cooled and equilibrated targets will yield
stoichiometric fluxes. However, the angular distribution of ejection for the
various sputtered constituents may not be the same. 82 This is particularly
true for constituents with significantly different masses. Thus failure to
achieve stoichiometric coatings from such targets is generally the result of
a failure to satisfy conditions (4) or (5) cited above.
The case of multiphase alloy or pressed powder targets can involve
the development of an altered layer, \,Ivith a mod ified surface topography as
well as composition. For example, when the phases in a multiphase alloy
 Physical Vapor Deposition 377

target have significantly different sputtering yields, the inhomogeneous

sputtering yield over the target will cause an irregular surface topography
to develop.107,113-116 This development is exacerbated by the angular
dependence of the sputtering yield (see Figure 24). The altered layer can
therefore assume a macroscopic character, in which the surface area
exposed to grains or phases with high sputtering yields is shrunk so that
the surface is enriched with low sputtering yield material. In such cases,
the equilibration time will increase with grain or powder size. The process
is complicated by surface diffusion or gas phase backscattering of sputtered
atoms, both of which can cause a mixing on the target surface of atoms
from the various phases. 117 For example, low sputtering yield material from
protruding grains can be sputtered onto recessed grains of high yield
material. The low yield material can then serve as seed species for the
development of a surface topography consisting of a forest of densely
packed cones on the high yield materiaI. 82 ,116,118-123 The cone-covered, or
otherwise modified, su rface topog raph ies can develop a very low effective
sputtering yield because atoms are sputtered back and forth many times
before they clear the surface. 124,125 Nevertheless, the important point is
that despite these aberrations, after a suitable equilibration time conser-
vation of mass dictates that the sputtered flux match the bulk composition,
provided that conditions (1) and (2) cited at the beginning of this section
are satisfied.
Uniform compound targets of materials such as carbides and silicides
should behave as the single phase alloys described above and yield
stoichiometric erosion fluxes as soon as an equilibrated altered layer is
formed. However, particular caution should be exercised when using
pressed-powder targets. High contamination levels may be present
throughout such targets because of the large surface area contained in
the starting powder. 126 ,127
Compound targets incorporating volatile constituents such as oxides,
nitrides, and halides often yield deposits that are deficient in the more
volatile constituents. 128,129 The fact that volatile species may evaporate
rather than be sputtered from the target surface will not alter the overall
material balance, provided that the loss is limited to the surface. Thus an
equilibrated target should yield stoichiometric emission flux. The problem
is that the volatile species are likely to have low substrate sticking coeffi-
cients, with the consequence that some of the evaporated material is
pumped away, therebyyielding non-stoichiometric deposits. The problem
is generally solved by a form of reactive sputtering in which "make-up gas"
containing the volatile species is injected into the sputtering chamber.
See Section 5.9.
Composite targets consisting of relatively large regions of different
materials are sometimes used. The sputtering rate from each region will
depend on the sputtering yield and electron secondary emission coefficient
as well as the degree to which gas scattering of the sputtered flux causes
mixing between the target regions. Therefore, an empirical approach is
generally required.
Caution must also be exercised when using targets composed of
compounds having poor electrical and thermal conductivity. Cracking
378 Semiconductor Materials

often limits allowable current densities. The problem is particularly important

for planar magnetrons where concentrated heating occurs under the
plasma ring. 13o Poorthermal conductivity leads to high surface temperatures
and may result in the loss of volatile constituents by evaporation or
sublimation. The high electric field in a poorly conducting target can act in
concert with the high temperature and promote diffusion within the target.
The sputtered flux must pass through the working gas to reach the
substrates. Significant gas scattering of the sputtered flux occurs in those
apparatuses which operate at elevated pressures. See Section 5.6. The
scattering is dependent on the mass of the sputtered atoms. The conse-
quences of scattering depend on apparatus geometry. Thus the composition
of the flux of sputtered atoms which arrive at the substrate in a planar
electrode apparatus may be quite different from that which leaves the
target. Bycontrast, gas scattering has a much lesser effect on the composi-
tion in a cylindrically symmetric apparatus.
Any substrate that is in contact with a plasma will be subject to resputter-
ing, if the potential difference between the substrate and the plasma
exceeds the threshold of the sputtering yield for some of its constituents.
Accordingly, coatings deposited by bias sputtering, see Section 6.4, are
vulnerable to the loss of high yield constituents. In some cases, controlled
resputtering is used to deposit coatings with a range of compositions from
a given target. 131

5.6 Glow Discharge Sputtering Apparatuses

A key problem in industrially implementing the sputtering process is to
provide a uniform and copious supply of ions overthe surface of the target.
The low pressure glow discharge has proven to be the most cost-effective
source of ions. Glow discharge plasmas are discussed in the sputtering
context in References 57 and 132. A wide range of glow discharge
apparatus geometries have been used in attempts to (1) increase the ion
supply and thus the sputtering rate, (2) increase the target area and thus
the available deposition area, (3) reduce the plasma heating of the substrates,
(4) permit a lowering of the working gas pressures, and (5) facilitate the
coating of particular substrate shapes. 59 The emphasis here is on those
apparatus types which are commonly used in the electronics industry.
5.6.1 Planar Diodes. The planar diode shown in Figure 19 is the
simplest of the sputtering apparatus configurations. One electrode, typically
10 to 30 cm in diameter, is configured to mount the target. The substrates
are mou nted on a table, wh ich is typically spaced 5 to 10 cm from the target
and generally serves as the second electrode. When operated with dc
power, the target electrode serves as the cathode and the substrate table
as the anode as shown in Figure 19. If ion bombardment during coating
growth is desired (bias sputtering) the substrate table is also biased as a
cathode and the chamber wall or an auxiliary electrode will serve as an
anode (such a system is strictly a triode-three electrodes-but is still
generally referred to as a diode). When operated with rf power, the electrodes
change cathode/anode roles on each half cycle. Consequently, it is neces-
sary that the substrate electrode be made considerably larger than the
 Physical Vapor Deposition 379

target electrode, so that the sputtering is concentrated at the target. See

Section 5.8. Sometimes this can be accomplished by connecting the
chamber wall and substrate table together as a common electrode. Bias
sputtering in the rf case is often accomplished by controlling the external
impedance, to adjust the relative power input to the target and substrate
electrodes. 133,135 Ground shields such as those shown in Figure 19 are
typically used to suppress current flow from all except the desired surfaces
of the electrodes. The target electrode is generally water cooled. The
substrate table may include provisions for heating or cooling the substrates.
The condition for sustaining a discharge in an apparatus of the type
shown in Figure 19 is that the rate of production of ions in the plasma
volume be adequate to balance the fluxes of electrons and ions that pass
to the electrode and chamber wall surfaces. First, consider the dc case.
The current in such a discharge is carried in the vicinity of the cathode
primarily by positive ions and in the vicinity of the anode by electrons.
Because of the relatively low mobility of the ions compared to the electrons,
most of the electrical potential that is applied between the electrodes by
the power supply is consumed in a "cathode dark space," or sheath
region adjacent to the cathode. 57 Dark space thicknesses are typically
1 to 4 cm, depending on the pressure and current density. Accordingly,
strong electric fields are formed, and ions passing from the plasma volume
to the cathode are accelerated by these fields and on impact at the
cathode produce the desired sputtering. A small number of "secondary
electrons" are emitted from the cathode as a consequence of the ion
bombardment 136 (about one for every ten ions in the case of argon ions
impacting on a metal cathode 137). These electrons are accelerated in the
cathode dark space to energies approaching the applied potential, and
enterthe plasma volume (negative glow) where, known as "primary electrons,"
they exchange energy and produce the volume ionization required to
sustain the discharge. 57 ,132 Unfortunately, the energy exchange between
the primary electrons and the working gas is relatively inefficient, so that it
is difficult to sustain a high current density plasma discharge in the planar
diode electrode geometry. Thus working gas pressures are relatively high,
3 to 10 Pa(20 to 75 m Torr), and current densities are low, typically less than
1 mA/cm 2 . The energy exchange in the rf case is more efficient, so that
considerably lower pressures, 0.5 to 2 Pa(5 to 15 m Torr) can be used. See
Section 5.8.
There are therefore three factors that characterize dc sputtering with
planar diode sources: (1) the cathode current densities and sputtering
rates are low, (2) the working pressures are high, and (3) the substrates are
in contact with the plasma. Typical operating conditions for metal sputtering
are: cathode current density-1 mA/cm 2 , discharge voltage-3000V, Ar
pressure-10 Pa. cathode-to-substrate separation-4 cm, deposition rate
-0.7 nm/sec. 52 (See Figure 28).
Because of the high gas pressure, the motions of both the ions and the
sputtered atoms are dominated by collisions. Thus, Ar ions passing through
the dark space undergo charge exchange collisions with neutral Ar atoms
that produce fast neutrals and "slow" ions. 138,139 Consequently, the target
is not bombarded by a current of ions having an energy equal to the
380 Semiconductor Materials

potential drop across the dark space, but instead a much larger number of
ions and atoms having energies that are often less than 10% of the
potential difference across the cathode dark space. 140 This redistribution
of energy can actually prove to be an advantage. Because of the nonlinear
dependence of the sputtering yield on the bombarding particle energy
(see Figure 23), ten 300 eV particles can, for example, produce more
sputtered species than one 3000 eV particle.
Gas scattering of the sputtered particles has several important conse-
quences. At the pressures used for dc planar diode sputtering, the transport
of sputtered species from the target to the substrates is largely by dif-
fusion. 141 The deposition rate is therefore reduced because a significant
fraction of the sputtered particles diffuse back to the target or to the
chamber walls. It is estimated that about 10% of the sputtered material
reaches the substrates in a well designed planar diode. 142 Because of the
diffusion nature of the transport, surfaces that are adjacent to a substrate,
but do not shield it optically from the target, can still rob it of coating flux.
The complexity of this diffusion transport, along with the charge exchange
processes in the cathode sheath, makes it necessary to determ ine deposi-
tion rates experimentally for each set of operating conditions. Another
important consequence of the collision-dominated transport of the sputtered
atoms is that their initial high energies of ejection (see Section 5.3) are
reduced to near thermal values by the time they reach the substrates
under typical planar diode dc sputtering conditions. 55 ,143,144,145,146
The fact that substrates in a planar diode are in contactwith the plasma
means that they are subjected to bombardment by ions and electrons from
the plasma. 132 The energies and relative fluxes will depend on the potential
of the substrates relative to the plasma potential. The substrates are also
subject to bombardment by the energetic primary electrons, 147 particularly
at the lower operating pressures, and to electromagnetic radiation from
the plasma. The plasma bombardment can be beneficial to the structural
properties of the coatings. See Section 6.4. However, bombardment by
energetic species can cause damage to semiconductor devices. See
Section 7.0.
As noted above, planar diode systems can be operated at lower pressures
when rf power is used. However, the general behavior differs from that
described above only in degree. Thus the charge exchange and gas
scattering of the sputtered flux will be less, while the substrate bombard-
ment by primary electrons will be greater.
Substrate heating rates are relatively high in planar diodes. Typical
rates are in the range from 100 to 300 eV/atom deposited. 148,149 The major
sources of heating are bombardment by the primary electrons and species
from the plasma. Uncooled substrates typically reach temperatures in the
300 to 500°C range.
Planar diodes were the most commonly used sputtering apparatus for
many years, but are being replaced by magnetrons for most metal deposition
applications. The present applications of planar diodes are primarily for rf
sputtering of various poorly conducting compounds. They are also used for
magnetic materials because of the limitations of magnetrons for this
application.
 Physical Vapor Deposition 381

DEPOSIT
VACUUM CHAMBER
CLEAN (PRESSURE - 5 MILLITORR)

TARGET

ANODE

TUNGSTEN
FILAMENT

TARGET FILAMENT
POWER SUPPLY POWER SUPPLY
0-2 kV DC AUXILIARY 0-10 VAC
SUBSTRATE TARGET

~--_+_--_--+_o
+ - - - QO+----r-------
-
PLASMA POWER
SUPPLYO-50 VDC
+----~

Figure 26: Schematic drawing of enhanced thermionically supported discharge

system with a tungsten filament hot cathode. This apparatus, developed by Bat-
telle Northwest Laboratories,tso uses a unique auxiliary target to continually
deposit a fresh low work function material such as thorium onto the cathode
filament. This significantly reduces the required filament power.

5.6.2 Assisted-Discharge Devices, Triodes. In assisted or sup-

ported discharge apparatuses an electrode system that is independent of
the target is provided for sustaining the glow discharge. The most common
such configu ration is the hot cathode triode. Such an apparatus is shown in
Figure 26. 150 Electrons are emitted at the cathode surface by thermionic
emission ratherthan ion bombardment. This largely uncouples the volume
ionization requirement for sustaining the discharge from the secondary-
electrons. Consequently, hot cathode triodes can be operated at low
pressure (0.5 to 1 mTorr). Driving voltages for the thermionic discharges
are typically only 50-1 OOV, although the current may be several amperes. A
magnetic field may be used to confine the plasma. The targets may be
driven by dc or rf power.
Typical operating conditions for metal sputtering are as follows: target
current density 1-20 mA/cm 2 , target voltage 500-1500V, Ar pressure 1
mTorr (0.13 Pa) cathode to substrate spacing 5-10 cm, deposition rate 1-
20 nm/sec.
The substrates mayor may not be in direct contact with the plasma.
However, in the absence of a magnetic field they will be subjected to
bombardment by energetic electrons originating from the target. Triodes
operate at sufficiently low pressures so that the sputtered atoms may
undergo a near-collision less transport to the substrates and preserve
382 Semiconductor Materials

much of their initial kinetic energy. Furthermore, energetic neutral working

gas atoms, which are generated at the cathode by the neutralization and
reflection of ions as discussed in Section 5.2, can also pass to the substrates
with little loss of kinetic energy.146 These atoms can become trapped in the
growing coating, particularly if the substrate temperature is low. Thus the
trapped argon content for coati ngs deposited with a triode has been fou nd
to be largerthan that for similar coatings deposited with a planardiode.7 5,76
5.6.3 Magnetrons. The recent development of high performance
magnetron sputtering sources that provide (1) relatively high deposition
rates, (2) large deposition areas, and (3) low substrate heating, is revolution-
izing the sputtering process by greatly expanding the range of feasible
applications. 59 ,151
Magnetron sputtering sources can be defined as diode devices in
which magnetic fields are used in concert with the cathode surface to form
electron traps which are so configured that the EXB electron drift currents
can close on themselves. 152 ,153 Magnetic field strengths are sufficient to
confine the electrons but not the ions. However, the ions tend to be
confined electrostatically in the vicinity of the electron component of the
plasma. Typical magnetic field strength values are a few hundred gauss.
The secondary electrons which are emitted from the cathode surface as a
consequence of the ion bombardment, and are accelerated in the dark
space to become energetic primary electrons, are trapped in the vicinity of
the cathode by the magnetic field. The trapping of the primary electrons in
a well designed magnetron is sufficiently effective so that these electrons
are able to transfer most of their energy to the plasma, and thereby to
cause the production of large numbers of ions, before they are lostfrom the
system. 154 Furthermore, the ions are produced in the immediate vicinity of
the cathode, so that they have a high probability of making theirway to the
cathode and therefore participating in the current flow that produces
sputtering.
Magnetron sources can be configured in many different forms. Several
of the more common types are shown in Figure 27. Properly designed
magnetrons of all the types yield comparable total sputtering rates when
operated at com man cu rrents. 154 The discharge current-voltage (I-V) char-
acteristic provides a very revealing signature identifying the nature of the
discharge process. I-V characteristics for a cylindrical-post magnetron
(Figure 27 A) and a planar magnetron (Figure 27 H) are shown in Figure 28
and com pared to a planar diode. The low operating voltages, and the nearly
flat I-V characteristics for the magnetrons (small voltage charge for large
increase in current) are a signature of efficient energy exchange processes
within the plasma discharge. 154 High impedance, constant current, power
supplies are generally used for magnetrons.
The cylindrical-post magnetrons (Figures 27A, B, 0), planar magnetrons
(Figure 27 H), and gun type magnetrons (Figure 271) are the most commonly
used types in the electronics industry. The cylindrical magnetrons shown
in Figures 27 A and 27 B use uniform magnetic fields generated by coils
located external to the vacuum chamber. 59 The magnetic fields for the
plasma ring type devices shown in Figures 270, E, G, and I are usually
generated by permanent magnets positioned behind the target. Small
 A
A
c

A
A

ELECTRICALL Y
FLOATING SHIELD

A B c D

c
A

""U
::::r
'<
(j)
A
a·
~
<
m
"0
A
o
o""'"
F G CD
E H "0
o
(j)
Figure 27: Schematic illustrations of various types of magnetron sputtering sources. In each illustration A is anode, 8 is mag- ;:::+:

netic field direction, C is cathode. (A) cylindrical-post magnetron with electrostatic end confinement,t53 (8) cylindrical-post 0"
:::J
55
magnetron with magnetic end confinement,t54 (C) rectangular post magnetron,154 (D) ring discharge post magnetron/ (E)
56 53 57
spiral discharge magnetron/ (F) cylindrical hollow magnetron/ (G) ring discharge hollow magnetron/ (H) planar mag- c..u
netron,t58 (I) "gun type" magnetron. 159 00
c..u
384 Semiconductor Materials

PLANAR DIODE
DIRECT CURRENT
6000 Ar PRESSURE = 6.5 Pa RECTANGULAR TYPE
ALUMINUM TARGET / PLANAR MAGNETRON
t'i\ RF SINGLE ENDED
/~
Ar PRESSURE = 0.13 Pa
,@
\ @ AI 20 TARGET
3000 @ 3

tIP/'
/

/~~/O)
Vl

-0
~
w l::1/
~,

"
c:t
I-
.....J
@
/"
K
o 1000
>
w

"~ ,..--e-e -0- 0 - -

~-~__o-o
_e-e'.··--
I
600
.-~- \
~
(,)
en
Q
RECTANGULAR TYPE
300 CYLINDRICAL POST PLANAR MAGNETRON
MAGNETRON DIRECT CURRENT
DIRECT CURRENT Ar PRESSURE = 0.13 Pa
Ar PRESSURE = 0.13 Pa ALUMINUM TARGET
ALUMINUM TARGET

100 - -------...- - - ....

0.1 0.3 0.6 1 3 6 10
DISCHARGE CURRENT (A.mperes)

Figure 28: Current-voltage characteristics for planar and cylindrical magnetron

sputtering sources compared to those for a planar diode.

planar and gun type magentrons are particularly suitable for retrofitting
existing vacuum chambers. Cylindrical-post and rectangular planar mag-
netrons have the advantage that they can be scaled to long lengths to
facilitate large deposition areas. 151 ,153,160
Cylindrical-post magnetrons are most commonly used for batch pro-
cessing, with the substrates arranged surrounding the source as shown in
Figure 29. For example, this configuration is used in the manufacture of
chromium photomask blanks for patterning semiconductor devices. The
current density is uniform over the cathode of a properly designed cylindrical
magnetron of the type shown in Figure 27 A. Typical values are about 20
mA/cm 2 which yield cathode erosion rates of about 20 nm/sec for metal
targets. See Equation 11. Total discharge currents are generally in the
range 1 to 50A. Operating pressures are typically about 1mTorr (0.13 Pa)
with discharge voltages in the 800V range. Because of the low pressures
the sputtered atoms undergo a near-collisionless, line-of-sight transport
to the sUbstrates. 146 Accordingly, deposition flux profiles at various radial
substrate positions can be predicted (a cosine emission is assumed).153 At
a typical substrate radial position equal to half the cathode length, a
thickness uniformity of about 10% can be achieved over an axial length
that is about half the cathode length. Thus a production coating machine
 Physical Vapor Deposition 385

CYLINDRICAL MAGNETRON
SPUTTERING SOURCE
SUBSTRATES /

VACUUM
I
CHAMBER
UNIFORM MAGNETICALLY CIRCULATING
CONFINED PLASMA SHEET EX B ELECTRON
CURRENT

Figure 29: Typical arrangement of su bstrates for batch processing with acyl in-
drical-post magnetron sputtering source.

with a 1m long cathode may yield acceptably uniform deposition over an

area of about 1.5m 2 . Deposition rates are typically in the 1 to 3 nm/sec
range. An advantage of cylindrical magnetrons is that they can be configured
with thick walled targets that provide a large inventory of coating material,
if the material is non-mag netic. 151 ,153 Fu rthermore, the target material is
used efficiently because of the uniform erosion along the cathode length.
A disadvantage is that cylindrical target fabrication from complex materials
may be difficult. See Section 5.10.
Planar and gun type magnetrons do not provide uniform deposition
over large areas. Therefore, substrate motion is generally used with these
devices. In the case of gun type devices, planetary systems of the type
shown in Figure 9 are commonly used. An important advantage of planar
and gun type devices, particularly for electronic related applications, is
their adaptability to apparatus configurations which incorporate several
sources for depositing multilayer coatings. Figure 30 shows a typical
commercial batch coating system which can be configured with three
rectangular planar magnetron sources. Up to 76 three-inch diameter
wafers, mounted on a vertical carrousel, can be coated with a thickness
uniformity of about ±5 0/o. Rectangular planar magnetrons are particularly
well suited to in-line systems in which the substrates are transported in a
direction perpendicular to the long axis of the target. Axial uniformity can
be obtained by using cathodes of sufficient length or apertures. Figure 31
shows deposition rate profiles for a typical rectangular planar magnetron.
Figure 32 shows a schematic drawing of an aperture configuration.
In-line planar magnetron sputtering systems with automated cassette-
to-cassette wafer handling are becoming widely used for semiconductor
386 Semiconductor Materials

Figure 30: Typical batch type sputtering apparatus which mounts three pla-
nar magnetron sputtering sources. (Photo courtesy of CHA Industries, Menlo
Park, CA.)
 Physical Vapor Deposition 387

PLANAR MAGNETRON
RECTANGULAR (127 mm x 380 mml

DISCHARGE CURRENT = 3.0A

DISCHAnGE VOLTAGE = 500V
AHGON pnESSURE =' 0.13 Pa Z = DISTANCE ABOVE TARGET
ALUMII'JUM

~
E. 3
UJ
r-
<t:
0:
Z
o
~
en 2-
oQ.
UJ
o

200 150 100 50 0 50 100 150 200

POSITION (mm)

Figure 31: Deposition rate profile for rectangular type planar magnetron sputter-
ing source on the long axis (A-A) at various distances from the cathode surface.

SUBSTRATES

\
r- - - - - - - - t/;t}.j\\\8\:;t??r------J.kS\t"ft:3fE,(j- - - - -----.,
,
I

,
I
,
------ \
\

I
\I

---J,------
I
-------1---
t
f
\
\
,,
,

\ I

~------- --------~

DEPOSITION
PROFILE

SHAPE IS ONE HALF OF

INVE RSE TO DEPOSITION
PROFILE

Figure 32: Schematic illustration showing the use of an aperture to improve the
axial uniformity of the deposition flux which reaches the substrates from a pla-
nar magnetron sputtering source.
388 Semiconductor Materials

metallization in wafer fabrication lines. Figure 33 shows a schematic

drawing of a typical system, which includes provisions for substrate heating,
sputter cleaning, and the deposition of a multilayer metallization. Figure
34 shows a commercial microcomputer controlled in-line sputtering system
which incorporates rectangular planar magnetron sources. Most wafer
processing systems mount the sputtering sources and wafers vertically in
order to sputter sideways and thereby avoid the accum ulation of debris on
the target and deposition su rfaces. Vertical substrate mou nti ng is used for
the apparatuses shown in Figures 29,30, and 34.
Planar magnetrons are typically operated at the same total cu rrents as
cylindrical magnetrons, 1 to 50A. However, the planar magnetron current
densities are higher, 50 to 300 mNcm 2 , because the plasma is magnetically
confined to a limited region of the target surface. Substrates are generally
placed within 2 to 6 cm of the source so that metal deposition rates are
typically 10 to 30 nm/sec. Thus planar magnetrons coat substrates sequen-
tially and at high deposition rates, while cylindrical magnetrons coat larger
numbers of substrates simultaneously at a slower rate but with a comparable
total sputtered flux. Planar magnetron working gas pressures are typically
in the range from 1 to 5 mTorr (0.13 to 0.65 Pa), with discharge voltages in
the 400 to 800V range. Targets for planar magnetrons are limited to a
thickness of about 1 cm by the req uirement that the magnetic field overthe
front su rface be of sufficient strength to confine the plasma. In addition, the
target material is eroded only under the plasma ring and is therefore used
inefficiently. Typically only about 25 to 30% of a rectangular planar magne-
tron target is consumed before the target must be replaced. Sometimes
relative motion between the target and the magnetic field pattern is used
to improve the efficiency of target consu mption. 161 Another approach uses
target inserts under the plasma ring.
The substrates in magnetron systems are generally located beyond
the magnetically confined plasma. If bias sputtering is to be used, the usual
procedure is to move the substrates into the plasma or to use an auxiliary
plasma generated in the vicinity of the substrates. 162 However planar
magnetron magnetic field configurations have recently been examined
which are particularly effective in providing high fluxes of low energy ions
at the substrate surface, while preserving the basic performance of the
magnetron source. 162a
The substrates in cylindrical magnetrons are usually free from plasma
or primary electron bombardment. However, substrate bombardment by
neutralized and reflected ions is especially important in cylindrical-post
magnetrons, because atoms undergoing reflections of considerably less
than 180°, and therefore having relatively high kinetic energies, pass in the
direction of su bstrates. 153 See Section 5.2. Thus coatings deposited at low
pressures, where these atoms lose little kinetic energy in transport, can
incorporate a considerable concentration of working gas. See Figure 21.
The primary sources of substrate heating in cylindrical magnetrons
are (1) the heat of condensation, (2) the sputtered atom kinetic energy, (3)
plasma radiation, and (4) energetic working gas atoms which are reflected
at the cathode. 163 The contributions from the kinetic energy of the sputtered
atoms and the reflected working gas atoms increase with the atom ic mass.
 ENTRY
LOCK

CASSETTE
BIN
J VACUUM BAKE
MODULE
ETCH SPUTTER
CASSETTE
BIN
MODULE MODULE

, .
'1J
::T
'<
en
SUBSTRATE
o·
TO VACUUM ~
HEATER COUNTER PLANAR MAGNETRON PUMPS SUBSTRATE
ELECTRODES SPUTTERING SOURCES WAFERS ~
"'0
o
o""""
CD
"'0
o
en
;::::+:
o·
::J

Figure 33: Schematic illustration of in-line sputtering system configured for depositing multilayer metallization onto semicon- c.v
ductor wafers. ex>
<0
 VJ
<0
o

en
CD
3
o·
o
::J
a.
c
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.-+
o
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~
~
.-+
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~

55·
ar

Figure 34: Cassette-to-eassette in-I ine sputtering system designed for semiconductor wafer processing. (Photo courtesy of Ma-
terials Research Corporation, Orangeburg, NY.)
 Physical Vapor Deposition 391

Typical substrate heating fluxes vary from 15 to 25 eV/atom for Iig ht metals
to over 50 eV/atom for heavy metals with moderate sputtering yields. See
Table 7. Substrates in radiation equilibrium with the heating flux are
projected to reach temperatures in the 100-200°C range at a typical
deposition rate of 1.7 nm/sec. 151
Substrates in planar magnetrons are generally placed close to the
sputtering sources and therefore may be subject to modest plasma bom-
bardment. Energetic electrons moving along magnetic field lines may
bombard the substrates if these field lines intersect the substrate
plane. 153,154 Substrates positioned in front of planar magnetrons are sub-
jected to less bombardment by energetic reflected working gas atoms,
because the most energetic atoms(those reflected at angles considerably
less than 180°) pass to the side and miss the substrates. 154 Accordingly,
planar magnetron substrate heating rates typically have a greater contri-
bution from the plasma and a lesser contribution from the reflected
atoms. 164 However, typical planar magnetron heating rates for sputtered
metals are comparable to those for cylindrical magnetrons. See Table 7.
Magnetrons have become the primary sputtering method for depositing
metallic coatings. Magnetron sources can be used to sputter magnetic
materials. However, when a sputtering target composed of a magnetic
material is used, it must be saturated magnetically so that its magnetic
behavior is suppressed and a field of the desired shape can be maintained
over its surface. 153 Thus, as a general rule, the allowable magnetron target
thicknesses are limited for magnetic materials. Reference 165 describes
several magnetron configurations specifically designed for sputtering
magnetic materials.
Magnetron sources driven by rf power are also becoming widely used
for depositing poorly conducting and insulating materials. However, the
magnetron is essentially a dc concept, and its performance as an rf
sputtering source is limited compared to its behavior as a dc source. 154
See Section 5.8.

Table 7: Representative Substrate Heating Rates for Cylindrical and

Planar Magnetron Sputtering Sources

.Heating Flux per Deposition Atom (eV/atom).

Cyl indrical Magnetron Planar Magnetron
Metal (Reference 163) (Reference 164)
Aluminum 13 11
Chromium 20 16
Copper 17 12
Molybdenum 47 42
Indium 20 15
Tantalum 68
Tungsten 73 98
Platinum 48
Gold 23
392 Semiconductor Materials

5.7 Ion Beam Sputtering

Glow discharge sputtering technology is limited, in the sense that the
target current density and voltage cannot be independently controlled
except by varying the working pressures. An exception is magnetron
systems in which the magnetic field is provided by an electromagnet and
the voltage can be varied at a fixed current by varying the field strength.
Ion beam sputtering permits independent control overthe energy and
current density of the bombarding ions. 166 A typical ion beam sputtering
system is shown schematically in Figure 35. The sputtering target is
arranged to obliquely intersect an ion beam of given energy and flux
density that is created by an independent ion source. Substrates are
suitably placed to receive the sputtered flux, as shown in the figure. In
addition to independent control over the ion current and voltage, ion beam
sources permit sputtered coatings to be deposited at very lowworking gas
pressures, ~O.1 mTorr, onto substrates which are not in contact with the
plasma. Su itable neutral ization of the ion beam perm its insu lati ng targets to
be sputtered without the use of an rf potential. Furthermore, since no
potential is applied to the target, secondary charged particles (electrons
and negative ions) are not accelerated away from the target and toward the
substrates. However, ions will be neutralized and reflected at the target.
See Section 5.2. Accordingly, substrate placement is important, since the
ratio of the sputtered to the reflected ion flux will depend on the angular
position of the substrates relative to the target.
The ion source shown in Figure 35 is one of the simplest and most
commonly used configurations. 167 A plasma discharge is sustained be-

SUBSTRATE

FILAMENT SCREEN
CATHODE GRID

ION
BEAM

------ -----
+ NEUTRALIZER

ANODE

Figure 35: Schematic drawing of ion beam deposition system with discharge
chamber having axial magnetic field.
 Physical Vapor Deposition 393

tween the thermionic cathode and the anode. Electrons emitted from the
cathode must cross the axial-magnetic field to reach the anode. As in the
magnetron case, the magnetic field strength is made large enough so that
the electron cyclotron radius is small compared to the distance from the
cathode to the anode. Thus the electrons suffer many collisions with the
working gas atoms, and hig h ionization rates can be ach ieved. Axial losses
of electrons are minimized by maintaining the screen and chamberwalls at
cathode potential. Consequently, ion (electron) densities in the 10 10 cm- 3
range can be maintained at low, ~1 mTorr, working pressures in the
chamber. Anode-cathode voltages are typically about 40V. The plasma
potential is typically a few volts above the anode potential. The anode is
maintained above the ground potential of the vacuum coating chamber by
an amount about equal to the desired ion energy. Typical values are +500
to 1000V. The accelerator grid is maintained at a potential that is about
1OOV negative relative to the ground potential. The accelerator grid controls
beam divergence and provides a negative potential barrierwh ich prevents
the passage of electrons from the beam plasma backwards into the
positive discharge plasma. A thermionically emitting hot filament supplies
electrons to neutralize the positively charged beam of ions.
The ions are extracted from the plasma by the electric field which is
produced because of the potential difference between the screen and
accelerator grids. The acceleratorgrids are typically fabricated from graphite,
with grid hole diameters of about 2 mm. Screen-to-accelerator grid spacings
are typically 1 to 2 mm. Typical beam current densities are 1 to 2 mA/cm 2 ,
with 500 eV ion energies and beam sizes of 5 to 10 em.
A large number of other apparatus config urations have been developed
to improve certain aspects of the performance. 167 In the mu Itipole magnetic
field configuration, the walls of the discharge chamber are covered with
anodes located behind localized magnetic fields produced by permanent
magnets. The bulk of the discharge chamber is field free, so that the ion
production and density are relatively uniform throughout the chamber.
Multipole devices are effective for producing large diameter beams, 15 to
30 em, with relatively uniform ion current densities. In the single grid
configuration the screen grid is omitted and the acceleration distance in
this case is simply the thickness of the plasma sheath. Current densities of
about 1 mA/cm 2 can be achieved in such systems at ion energies as low as
20 eV.
Ion beam sputtering systems cannot, in general, compete with magne-
trons as large scale production sources. However, the control that they
provide makes them very attractive for research studies and for special
applications. Ion beam sources are also used for providing controlled ion
bombardment during coating growth. In this case, an ion beam sputtering
or evaporation source provides a source of coating flux.168-170 The secondary
ion beam is arranged to bombard the growing coating in orderto modify its
properties as discussed in Section 6.4. In another method, called primary
ion beam deposition, an ion beam of the depositing material itself is
directed at the substrate. This technique provides a high degree of control
over the depositing film and has been used to produce unusual film
properties such as diamond-like carbon, 171 and to implement semiconductor
394 Semiconductor Materials

doping in deposition by molecular beam epitaxy. See Section 4.4. In

reactive ion beam sputtering the target is bombarded with a beam of
reactive ions. Thus, for example, silicon nitride coatings can be produced
by bombarding a silicon target with nitrogen ions. 172 A nitride layer forms
on the target, as discussed in Section 5.9, and species sputtered from this
are deposited onto adjacent substrates. Ion beam sources also play an
important role in microcircuit patterning via ion beam etching. Recent
reviews of ion beam deposition and etching are provided in references 173
through 175.

5.8 RF Sputtering
Direct current methods cannot be used to sputter nonconducting
targets because of charge accumulation on the target surface. 57 This
difficulty can be overcome by using radio frequency(rf) sputtering. Asingle
rf sputtering apparatus can be used to deposit conducting, semiconduct;'lg,
and insulating coatings. Consequently, rf sputtering has found wide appli-
cation in the electronics industry. Examples of nonconducting and semi-
conducting materials which have been deposited by rf sputtering are given
in Table 8.
Many of the phenomena which occur in glow discharge plasmas are a
consequence of the large difference in mass between the electrons and ions.
Thus, in the absence of strong magnetic fields, the electron flux from a
plasma to a surface will tend to be significantly higher than the ion flux
because of the larger thermal velocity of the electrons. Consequently, an
insulating surface will accumulate a negative charge which causes it to
float at a potential that is negative with respect to the plasma.57-132 The
variation in potential between the conducting plasma and the floating
surface will occur in a sheath region adjacent to the surface. The magnitude
of this floating potential will be just sufficient to retard the electron flux to
the point where it matches the ion flux. Values depend on the electron
temperature and the ion/electron mass ratio, but are typically in the range
-5 to -3QV and too low to produce a significant sputtering rate.
Now let an electrode be placed behind the insulator and let an rf
potential be applied to the electrode. Two things happen. First since the
capacitive impedance varies inversely with frequency, an rf-current can
now pass through the insulator. However, since the dc current must still be
zero, the total electron and ion current flux during each complete cycle
must balance to zero. Accordingly, the second consequence of applying
such an rf potential is that the insulator will develop a voltage bias that is
negative with respect to the plasma potential. The situation is very similar
to the floating potential case described above. However, in the rf case the
bias potential that develops is just sufficient to equalize the accumulated
electron and ion currents which pass to the electrode during each complete
cycle. The magnitude of the voltage bias will approach the zero-to-peak
voltage of the applied rf power, with values that are typically several
hundred volts. Accordingly, ions passing across the sheath to the surface
will accumulate sufficient energy to cause sputtering. This is the basis of
the rf sputtering method. 59 ,128,193-197
 Physical Vapor Deposition 395

Table 8: Typical Nonconducting and Semiconducting Compounds Which

Have Been Deposited by RF Sputtering

Target Sputteri ng Source Reference

Si0 2 planar diode 176
planar magnetron 177
AI 20 3 planar magnetron 178
cylindrical magnetron 179
Nb 20 S planar diode 180
Ta20S planar diode 181
ZnO planar diode 182
In203/Sn02 planar diode 183
LiNb0 3 planar diode 184
BaPb 1 _x Bi x 0 3 planar diode 185
Si 3N 4 planar diode 186
SiC planar diode 187
Si planar diode 188
GaAs planar diode 189
(Hg, Cd) Te triode 190
CdSiAs 2 planar diode 191
PvZr03-PbTi03 planar magnetron 192

Figure 36 shows a schematic drawing of an rf planar diode sputtering

system. The target is attached to one electrode and the substrates are
placed on the other one. The electrodes reverse cathode-anode roles on
each half cycle. The discharge is operated at a frequency that is sufficiently
high so that the ion charge accumulation during each cycle is not large
enough to significantly influence the voltage. 53 ,5? Frequencies greater
than about one M Hz are required. Most apparatuses are operated at a
frequency of 13.560 MHz. since this is the frequency in the 10 to 20 MHz
range that has been allocated by the Federal Communications Commission
for industrial-scientific-medical pu rposes. Operation at another frequency
will require careful shielding to assure compliance with FCC regulations
on radio interference.
At M Hz operating frequencies the massive ions tend not to follow the
temporal variations in the applied potential; however, the electrons do.
Thus the cloud of electrons that constitute the electron component of the
glow discharge plasma can be pictured as moving back and forth at the
applied frequency in a sea of relatively stationary ions. As the electron
cloud approaches one electrode, it uncovers ions at the other electrode to
form a positive ion sheath. This sheath takes up nearly the entire applied
voltage, the same as in the dc case. A large electron current flows to agiven
396 Semiconductor Materials

TARGET

SUBSTRATES

VACUUM
CHAMBER

Figure 36: Schematic drawing of rf planar diode sputtering system with single-
ended drive showing impedance matching network.

electrode as the electron cloud makes contact. Thus the electron cloud
need approach a given electrode for only a small fraction of a half cycle for
purposes of supplying sufficient electrons tofulfill the anode requirement;
i.e., to balance the entire ion flux through the cycle. Accordingly, in the
steady state both electrodes develop a negative dc bias relative to the
plasma potential, such that the electrodes approach or exceed the plasma
potential (become anodes) only for very short portions of their rf cycle, 59 as
discussed previously. Because of their inertia, the motion of the ions can
be approximated as if they follow the dc potential and pass to both
electrodes throughout the cycle. The electron cloud spends most of its
ti me near the center position between the electrodes. Visually, the discharge
looks like a dc discharge with a cathode dark space over each electrode.
Functionally, sputtering occurs very much as in the dc case, but at both
electrodes.
RF discharges in planar diode apparatuses can be operated at consid-
erably lower pressures than can dc discharges. Typical operating pressures
are 5 to 15 mTorr (0.67 to 2 Pa). There are several reasons for this.
Collisional interactions between the oscillating electron cloud and the
working gas provides an energy exchange mechanism, not present in the
dc case, which can contribute to the production of ionization. Secondary
electrons capable of producing plasma ionization are generated at two
electrodes, rather than just one. Finally, the positive space charge sheaths,
which are present at both electrodes during most of the rf-cycle, tend to
prevent the loss of at least the low and modest energy electrons.
Effective power transfer from the rf power supply to the plasma
discharge requires that the load impedance be adjusted to match the
output impedance of the power supply. Most 13.56 MHz power supplies
are designed to operate into 50 ohm resistive loads. The impedance
introduced by the plasma discharge and the sputtering target is primarily
capacitive. In fact, the development of an rf self bias on the target requires
 Physical Vapor Deposition 397

that there be no dc current flow. Thus a "blocking capacitor" (C b in Figure

36) is generally added, to make the system insensitive to variations in the
target capacitance, or to allow metal targets to be used. 57 A matching
network is used to match the capacitive impedance of the load to the
power supply. A typical matching network consists of a variable inductor in
series with the load, and a variable capacitor in parallel with it, as shown in
Figu re 36. These elements provide the two deg rees of freedom necessary
to convert any load to a specific value of series resistance. 133,134 In
combination with the load, the matching network forms a resonant circuit. 198
When the load is matched, the circuit is in a state of resonance, with large
circulating reactive currents. The matching network should therefore be
placed as close as possible to the discharge chamber to avoid excessive
power losses from these circulating currents. Manycommercial sputtering
sources monitor the "reflected power" from the load as an index to how
effectively the matching network is adjusted. The reflected power should
be minimized. Often this is done automatically. RF electrical systems are
discussed in References 133, 134, 135, 195.
It has been noted in the above discussion that both electrodes in an rf
planar diode apparatus have positive space charge sheaths throughout
most of the rf cycle and that sputtering tends to occur contiually at both.
Thus, referring to Figure 36, an asymmetry must be built into the system so
that sputtering occurs at one electrode and deposition at the other. This is
usually done by making the substrate or"counter" electrode much larger
than the target electrode. The counter electrode is often grounded as
shown in Figure 36. Systems of this configuration, with the power supply
connected between a "powered" or"driven" target electrode and a grounded
chamber or counter electrode, are said to be "single-ended". Sputtering
systems are occasionally configured in a double-ended arrangement,
where two identical target-mounting electrodes are positioned to sputter
material onto electrically floating or grou nded sUbstrates. 196 Such systems
are stabilized by placing the center tap of the rf power supply inductive
coupling (shown in Figure 36) at ground potential. Since the centertap is at
zero potential relative to the rf voltage, no rf currents can flow to grounded
elements. 59
An approximate theoretical analysis 197 predicts that the voltage division
between the sheaths on two planar electrodes of areas A 1 and A2 will obey
the relationship V1/V 2 = (A 21A 1)4. The analysis is based on the assumptions
(1) that the current desities to both electrodes are uniform and equal, and
proportional to V 3/2 /d 2 (Child Langmuir Law where d is sheath thickness);
(2) that the sheath capacitances are proportional to Aid; and (3) that the rf
voltage is capacitively divided between the two sheaths so that V1/V 2 =
C 2 /C 1.57 However, experimental resu Its suggest that for most real systems
the relationship is closer to V1 IV 2 rvA 2 IA 1 ' and that special care must be
exercised to minimize the sputtering on counter electrode surfaces. 199 A
recent and excellent discussion of the influence of the electrode areas is
given in Reference 200.
It is important to realize that the asymmetryof an rf discharge system is
not influenced by the fact that one electrode is grounded. The variation in
potential between two identical equal-area electrodes on a single-ended
398 Semiconductor Materials

rf system is shown in Figure 37 A. The plasma potential, Vp' tends to be

slightly more positive than that of the most positive surface in contact with
the plasma. 132 Thus the plasma potential relative toground varies with time
such that the time-average potential difference between the plasma and
each electrode is equal, and equal sputtering occurs at both electrodes. In
the case of unequal electrode areas shown in Figure 378, the average
sheath voltage variations (potential variations between the plasma and
the electrodes) are unequal, as discussed in the previous paragraph.
Typically, the grounded electrode is made the larger one, with a size
sufficient so that the sheath voltage drop is below the sputtering threshold.
Consequently, the plasma potential remains close to ground, and the self-
bias discussed previously assumes the form of a near-dc voltage offset
with respect to ground on the smaller electrode as shown in Figure 378.
This dc offset voltage is generally measured with an oscilloscope and is
one of the primary parameters which is used to specify deposition conditions
in rf sputtering. In some cases circuit elements are placed between the
substrate electrode and the grounded end of the powersupply, so that bias
sputtering bombardment can be induced at the substrates.133134135
The above discussion has been presented in the context of planar
diode sputtering systems. Magnetron sputtering sources can also be
operated with rf power. However, some problems are encountered. 154
Magnetron sputtering technology is basically a dc concept with specific
configurations and orientations of the cathode and anode with respect to
the magnetic field. Effective double-ended rf magnetrons can be provided
for some geometries. These configurations provide independent traps for
both electrodes but allow magnetic coupling between them so that the
electrons leaving one trap can diffuse freely to the vicinity of the other. 154
However, most magnetron configurations must be driven with single-
ended arrangements. These magnetrons operate in hybrid modes with
current-voltage characteristics which are not symptomatic of true magnetron
behavior. This can be seen in Figure 28 by comparing the dc and rf planar
magnetron I-V characteristics. RF driven magnetrons yield deposition
rates that are typically a factor of three greater than are obtained with rf
planar diodes, but far below the factor of twenty-to-thirty improvement in
deposition rate which dc magnetrons provide over planar diodes when
sputtering metals.
It should be noted that the performance of rf-driven planar diode and
magnetron systems for sputtering poorly conducting materials is limited
not by the capabilities of the plasma, since high rates have been achieved
with planar diodes 201 , but by the power densities that can be passed into
the target without causing damage. Ring type magnetrons, such as the
planar magnetrons shown in Figures 270, G, H,and I, are particularly
vulnerable in this respect because the power input is concentrated in the
region of the plasma ring. Therefore, RF driven magnetrons are generally
used not to provide high deposition rates, but to achieve large area
deposition and to reduce substrate electron bombardment and heating.
Special precaution should be taken in magnetron systems to avoid unwanted
sputtering at counter electrodes, since the magnetic confinement produces
gradients in plasma densitywhich can yield sheaths with elevated voltage
drops at the counter electrodes.
 Physical Vapor Deposition 399

VOLTAGE

DRIVEN GROUNDED
ELECTRODE ELECTRODE

• EQUAL ELECTRODE AREAS

A
VOLTAGE

DRIVEN GROUNDED
ELECTRODE ELECTRODE

• UNEQUAL ELECTRODE AREAS

B
Figure 37: Schematic representation of the potential variation between the elec-
trodes of rf glow discharges with equal electrode areas (A) and unequal electrode
areas (8). A nonconducting target or blocking capacitor is assumed to be present
in the unequal area case so that unequal space charge "sheath II voltage drops
develop.
400 Semiconductor Materials

5.9 Reactive Sputtering

Reactive sputtering is that process where at least one of the coating
species enters the system in the gas phase. Thus reactive sputtering is
similar to the process of reactive evaporation which was discussed in
Section 3.6. Examples of some reactive sputtered compounds, that are
important for electronic-related applications, are listed in Table 9.
The advantages of reactive sputtering are that (1) many complex
compounds can be formed using relatively easy-to-fabricate metallic
targets; (2) insulating compounds can be deposited using dc power supplies,
although rf power is sometimes used; and (3) coatings with graded compo-
sitions can be easily formed. The difficulty in the reactive sputtering
process is the complexity which accompanies its versatility.
Reactive sputtering differs from reactive evaporation in that, in addition
to the reactions which occur at the substrate, reactions can also occur on
the target surface, following which the reacted material is sputtered. At
high working gas pressures reactions can occur in the gas phase, but this
situation is unusual.
When sputtering with a re"',ctive-gas/argon mixture, one should be
aware that the relationship between the film properties and the reactive
gas injection rate is very nonlinear, and strongly dependent on the apparatus
geometry and the history of its operation. There are two reasons for this.
First, the condensing film can be considered as an additional pump forthe
reactive gas, and the sticking coefficient or speed of this getter pump

Table 9: Examples of Compounds Which Have Been Deposited by

Reactive Sputtering

Target Reactive Gas Film Sputtering Source Reference

AI O2 AI 20 3 planar magnetron 202
Ti O2 Ti0 2 ion beam 203
planar magnetron 204
Ta O2 Ta20s planar magnetron 204
Cu O2 CU20 planar magnetron 205
Zn O2 ZnO planar magnetron 206
In-Sn O2 In203/Sn02 planar magnetron 207
cylindrical magnetron 208
AI N2 AIN planar magnetron 209,210
Ti N2 TiN planar magnetron 211,212
Zr N2 ZrN planar diode 213
Si N2 Si 3N 4 planar diode 214
Cu H 2S CU2S cyl indrical magnetron 215
Cd H 2S CdS cyl indrical magnetron 216
Cu-In H 2Se Cu InSe2 planar magnetron 217
 Physical Vapor Deposition 401

depends in a complex way on the growth rate, composition, structure, and

temperature of the growing film. Second, reactions at the target surface
can change the rate at which the metal species are sputtered. In the case
of diode systems, where the target is also the cathode, target surface
reactions can also influence the plasma discharge.
The overall performance of a reactive sputtering system is dependent
on the deposition area compared to the size of the chamber, and on the
getter pumping effect of the sputtered flux compared to the speed of the
physical pumps. These relationships are identical in principle with those
discussed in Section 2 from the standpoint of wall outgassing. See Figure
3. Thus if the getter pumping effect dominates, the reactive gas injection
rate is a particularly relevant parameter. This is the situation in most
production coating systems. If the physical pumping dominates, the reactive
gas partial pressure is the more useful parameter. It should be noted that
most papers on reactive sputtering describe the process in terms of the
reactive gas partial pressure priorto ignition of the plasma discharge. This
pressure is proportional to the flow rate and is not the true partial pressure
during the reactive sputtering.
Figure 38 shows the composition dependence of the sticking coefficient
for N 2 incident on a growing Ti film. 218 As the number of gettered N 2
molecules per Ti atom approaches 0.5 (stoichiometric TiN), the sticking
coefficient drops by more than two orders of magnitude. This is a general
trend which applies for all materials, because the number of unoccupied
surface absorption sites decreases as a stoichiometric composition is
approached. Thus in the Si/02 reactive evaporation case discussed in
Section 3.6, an oxygen impingement rate about two orders of magnitude
larger than the Si impingement rate was required to form Si0 2 coatings.
See Figure 14.
In reactive sputteri ng the relatively hig h reactive gas partial pressu res
that are needed to produce the required high impingement rates at the
substrates also generally cause high impingement rates at the target. The
target reactions are stimulated by the fact that many of the incident ions
are reactive gas species. In addition, active radicals, such as dissociation
products, reach the target from the adjacent plasma where they are
produced. Consequently, target surface compounds with reduced sputtering
yields can form, as discussed in Section 5.4. These target reactions can
also limit the range of coating compositions that can be achieved.
The general concepts discussed above are illustrated in Figure 39.
The figure shows the variation in discharge voltage and deposition rate
with O2 injection rate, at a constant discharge current, for Cr-0 2 reactive
sputtering in a cylindrical magnetron sputtering system in which the getter
pumping capacity of the sputtered flux is large compared to the physical
pumping system. 6 At low 02 injection rates virtually all of the 02 is getter
pumped by the condensing Cr coating. Consequently, the 02 partial
pressure remains relatively low, and the cathode process remains primarily
one of simple Ar sputtering of Cr. The coatings deposited under these
conditions are metallic in nature, but possess an oxygen content that
increases almost linearly with the 02 injection rate and may exceed the
equilibrium solubility of oxygen in Cr. As the 02 injection rate approaches
402 Semiconductor Materials

1 .........- - - - -....- - - - - - . .

~ 10- 1
u
I..L.
I..L.
w.J
o
u
~
z
~
u
i= 10- 2
V)

10-3~ ~ - - - _.....

10- 2 10- 1 1
N2 MOLECULES SORBED/sec
Ti ATOMS DEPOSITED/sec
Figure 38: Sticking coefficient measured during the continuous deposition of
titanium as a function of the ratio of the gettered nitrogen flux to the titanium
deposition fl ux. Data from Reference 218.

that required to produce a stoichiometric chromium oxide, the 02 partial

pressure rises because of the reduced getter pumping rate, analagous to
the example shown in Figure 38. As a consequence, the target cathode
develops a su rface oxide, and the sputteri ng process undergoes an abru pt
transition into a mode in which the metal sputtering rate, and therefore the
reactive compound deposition rate, are reduced. Beyond this transition,
coatings of Cr 2 0 3 are deposited. In some cases the transitions are very
abrupt while in other cases they appear as a long-term, tens of minutes,
drift in operating parameters. The reactive gas injection rate which produces
the transition tends to increase linearly with the disch~rge current. The
phenomenon of forming such a su rface layer on the target is often referred
to as target poisoning.
The nature of the surface layer on a poisoned target depends on the
metal-gas combination and the reactive sputtering conditions. The reduction
in sputtering rate results because the atom binding energies are often
higher in these surface layers and because the mass of the reactive gas
ions may make them less effective than Ar as sputtering agents. In addition,
 Physical Vapor Deposition 403

the surface layers often have higher electron secondary emission coeffi-
cients, which result in a reduction in both the discharge voltage, as seen in
Figure 39, and the ion component of the discharge current, for discharges
driven at constant currents. Thus in the case of a Au cathode, where no
surface oxide forms, the discharge voltage and the deposition rate are not
significantly influenced by the 02 injection rate. See Figure 39. Very
pronounced losses in deposition rate are seen for oxide reactive sputtering
of materials such as AI (36X), Ti (14X), and Cr (4X), which form surface
compounds with high interatom binding energies and increased electron

1000,....-----------------.

-----~---~-------------~~~-----.
900
•
CYLINDRICAL-POST MAGNETRON
CHROMIUM (ARGON: 1.0 mTorr - 0.13 Pa)
~
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~ 800

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~ DISCHARGE
c:{ VOLTAGE

600

~ __ CHROMIUM
::I: 500 e--::--

~ el-.-e]e--e-
400

REVERSE HYSTERESIS
TRANSITION EFFECT

300
TOTAL SPUTTERING RATE "-' 0.2 Torr-liters/sec

w
....c:{
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a: 0.8
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0 DEPOSITION
t= RATE
CATHODE
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...J
w COATING
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OXYGEN INJECTION RATE (Torr-liters/sec)

Figure 39: Transition in steady state operating mode of cylindrical-post mag-

netron sputtering source because of cathode poisoning. Data from Reference 6.
404 Semiconductor Materials

secondary emission coefficients. 154 The decrease in deposition rate is

generally less for materials such as nitrides (2X for NbN) and sulfides.
The decrease in deposition rate which occurs with poisoning is relatively
independent of the cathode geometry.154
The cathode surface processes in the poisoned mode produce an
energetic fl ux of high ly reactive gas atoms and molecu larfractions (reflected
atoms, sputtered chemisorbed atoms and sputtered surface compounds)
which accom pany the sputtered metal atoms to the su bstrates. It is th is large
flux of reactive species that promotes the formation of stoichiometric
coatings and makes the reactive sputtering process so effective for pro-
ducing a wide range of compounds. Thus sputtering sources can often
be operated in the poisoned-target mode to produce stoichiometric coatings
under conditions that are not particularly sensitive to the reactive gas
injection rate.
Once formed, the target surface layer will remain until the working gas
is made sufficiently lean in the reactive species so that a net sputter
removal of the layer can occur. This is the origin of the hysteresis effect,
which is shown in Figure 39 for the discharge voltage, but which also
applies to the deposition rate. These target surface layers are often very
similar to the materials being deposited, with thicknesses that depend on
the compound and the sputtering conditions, i.e. current density and
reactive gas partial pressure, but which are typically in the range from 5 to
100 nm. 202 ,219,220 The hysteresis effect can therefore be used as a method
for controlled and reproducible deposition of ultrathin metal oxide lay-
ers. 220 ,221 Typical uses are for metal-insulator-semiconductor or Josephson
tunneling junctions. The method consists of first operating the sputtering
source under given conditions for sufficient time to generate a poisoned-
target surface layer of given thickness, with the substrates shielded. The
target is then sputtered in pure Ar with the substrates exposed. The
surface layer is therefore sputtered from the target and deposited onto the
substrates, with a smooth in situ transition being made from the ultrathin
compound to the metal as the target surface is returned to the pure metal
state.
The poisoning effect introduces two practical problems. One is the
loss in deposition rate. Thr second is that during the poisoning transition
the material being deposited often passes abruptly from a metal to a
nearly full-stoichiometric compound. Intermediate materials such as sub-
oxides therefore become difficult to deposit. The losses in deposition rate
can be very large (X 30 for AI, as noted previously). Often coatings with the
desired stoichiometry and physical properties are formed right at the
transition. Examples are NbN coatings with the maximum superconducting
transition temperature,222 In20 3/Sn0 2 coatings with the optimum combin-
ation of optical and electrical properties, 207 and V0 2coati ngs wh ich exh ibit
a maximum resistivity change in the thermally driven semiconductor-
metal transition. 223
Consequently, considerable effort has been directed toward develop-
ing methods for operating sputtering sources right at or very near to the
transition point. For many years these attempts met with little success.
However, considerable progress has been achieved over the past few
 Physical Vapor Deposition 405

years using (1) computer driven control systems, and/or (2) apparatus
configurations which provide the maximum possible separation between
the target sputtering process and thefilm growth reactions at the substrates.
Ring type plasma devices such as planar magnetrons (Figure 27H) have
proven to be particularly effective, as compared to uniform cu rrent density
devices. The higher current density under the plasma ring makes these
devices capable of operating at higher reactive gas partial pressures
without the occurrence of target poisoning. Target surface layerformation
begins at the edges of the sputtering region underneath the plasma ring
and closes in on the region as the reactive gas partial pressure increases. 224
The difficulty of the control problem depends on the nature of the
surface layer. 225 Thus transition point control is generally more difficult for
oxide than nitride deposition. Figure 40 summarizes the performance of a
planar magnetron source which was used to deposit AIN coatings by
sputtering an AI target in an Ar/N 2 working gas. 209 ,210 A microprocessor
was used to provide feedback control to parameters such as the N 2 flow
rate and the discharge current, voltage, and power. The figure shows data
for cases in which (a) the flow rate was controlled at a constant power, (b)
the power was controlled at a constant flow rate, and (c) the voltage was
controlled at a constant flow rate. Cases (a) and (b) yielded abrupt cathode
poisoning transitions and hysteresis effects, with metallic films formed
from F-D and nitride films from A-C. The voltage hysteresis in case (a) is
essentially identical to that shown in Figure 39, which corresponds to
similar operating control. In case (c) the computer adjusted the current to
maintain the voltage at the programmed value. No abrupt transitions or
hysteresis effects were encountered. Stable operation was continuously
obtained at all degrees of target surface coverage. The effectiveness of
voltage control has also been found in depositing V0 2 coatings with large
semiconductor-metal resistivity transitions. 226
In most cases of oxide deposition, special efforts must be made to
create controlled conditions at the cathode and substrates. The most
common approach is to use one or more of the following: (1) a planar
magnetron with a high current density as the sputtering source, (2) a gas
baffle surrounding the target or substrate to increase the reactive gas
partial pressure gradient between the target and substrate regions, and/or
(3) an auxiliary plasma discharge at the substrate to enhance the reaction
by creating active species. 226a
Figure 41 shows a schematic drawing of an apparatus configuration
with a reactive gas baffle. The sputtered metal flux that condenses within
the baffle housing acts as a getter pump which reduces the reactive gas
partial pressure at the target. The flow impedance introduced by the baffle
permits maintenance near the substrate of reactive gas partial pressures
which are several times the values for the case without a baffle. This is
shown by the data given in Figure 42a. The transition to an oxidized target
occurs at a lower flow rate when a baffle surrounds the target, compare
Figures 42 band 42c, apparently because the baffle reduces the pumping
speed provided in the vicinity of the target by the combination of the getter
effect and the vacuum system diffusion pump.227
The exact reaction mechanisms that are promoted at the substrate by
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012 o 300 600 200 300 400 ('")
..-+0

N 2 FLOW RATE (cc/min) POWER (W) CATHODE VOLTAGE (V) o.,

~
_ 1.5 •A 0)
_ ·400tF (b) 1 (0) ..-+0

?
ca
~ .,
CD
\0.
~ . ~ 1.0
05·
w • I E
~300 D(/·' W
~ 300 ::>
t-
:1

t· ··.~D
<t
t-
...J ...... s····c
en
~ 0.5
•8

...J
o c-······ S.... •A o ex:
>200 ~ ,c
> 200
• , ! ,I
A: N D ·····E
'-.. .. f
012 o 300 600 ZOO 300 600
N 2 FLOW RATE (cc/min) POWER (W) POWER (W)

E•
Dt!··
...... s:::"c

o 300 600
POWER (W)

Figure 40: Variation of AI/N 2 reactive sputtering parameters during various modes of computer controlled operation using
planar magnetron sputtering source. Data from Reference 209.
 Physical Vapor Deposition 407

REACTIVE GAS
INJECTION

SPUTTERED
FLUX

GETTER
SUFACE

PLANAR MAGNETRON
AI TARGET
SH IELD

Figure 41: Schematic drawing of planar magnetron reactive sputtering apparatus

with gas baffle to assist in isolating the reactive processes at the target and the
substrate.

a plasma discharge are still a subject of research. 228 However, the role of
such discharges in reactive sputtering is undoubtedly very similar to their
role in the plasma-assisted reactive evaporation case discussed in Section
3.6. Auxiliary discharges are obviously not required in apparatuses such as
plcnar diodes, which place the substrates within the sputtering plasma.
However, a substrate bias may be used in such cases.
The baffle reduces the metal flux reaching the substrate. However, this
reduction is more than compensated for, iffilms of the desired composition
can be deposited in the absence of cathode poisoning. Thus reactive
sputter deposition ofTa 20 s at 18 nm/sec,224 Ti0 2at 11 nm/sec,224 and AI 20 3
at 2.5 nm/sec 229 has been achieved using this method. The use of baffles
and auxiliary substrate discharges has proven very useful in depositing
transparent conducting oxide coatings with optimum combinations of
optical transmission and resistivity on low temperature substrates. Ex-
amples are ZnO,227 Cd 2Sn0 4,229 and In 20 3 doped with Sn. 207 In these
cases it was necessary to operate very close to the poisoning transition
point. Control of the discharge is often facil itated in such cases by a voltage
maximum which forms at reactive gas injection rates just below the values
that produce poisoning, because the target compound layer closes in on the
plasma ring. 224,23o The baffle technique has also been used to deposit high
quality AI 20 3 optical waveguides by reactive sputtering at reasonable
deposition rates. 231
In considering the reactive sputtering process it is important to recog-
nize the importance of the overall apparatus surface chemistry in achieving
408 Semiconductor Materials

a
co
0.07 I-

.
~

- .
..
~ 0.05 BAFFLE
w
cc
Cl.

.-:a:: .....
<t:
Cl.
0.03 - .. . .
NO
BAFFLE
0
N

0.01 ~
..... ... ........ ....
••• : •••
.
I

BAFFLE b
700 _I I , , I , : : :
.
.

600 - .
~
w
e"
<t:
......J
o
500 -
\
...........
>
w
o
o NO BAFFLE c
~
<t:
700 ."a:::::·:·············· ..
u
600 ""'

500 ~

• • p .

o 2 4 6
o FLOW RATE (cc/min)

Figure 42: Oxygen partial pressure and cathode voltage vs oxygen flow rate for
Zn-02 reactive sputtering, both with and without a baffle surrounding the target.
Argon partial pressure was 0.74 Pa. Data from Reference 227.

steady state operation. Clear evidence has been reported, for both Ta/0 2220
and Cu/H 2S232 reactive sputtering, which shows that the equilibration time
for steady state operation at a given reactive gas injection rate depends on
the initial state of the substrate and chamber wall surfaces as well as the
surface of the target. Equilibration times of several ampere-hours of target
operation have been encou ntered. 217 Consider the following case history.
A series of experiments were conducted to develop a reactive sputtered
coating. In each experiment a few test substrates were positioned sur-
rounding a cylindrical-post magnetron source of the type shown in Figure
29. Once operating conditions which yielded the desired coating properties
had been determined, a trial production run was made with the entire
 Physical Vapor Deposition 409

chamber filled with substrates. Deposition under the prescribed conditions

in this run produced coatings with very different properties than had been
obtained with the test substrates. This occurred because the load of fresh
substrates had significantly changed the state of the overall chamber
deposition surfaces. Reliable production deposition conditions were subse-
quently established in a series of experiments in which a fresh load of
substrates was introduced for each deposition run.
The problem of low substrate sticking probabilities for many reactive
gases can also affect the composition of coatings deposited by sputtering
from compound targets. Thus, as discussed in Section 5.5, coatings sput-
tered from oxide targets are often found to be deficient in oxygen, because
oxygen released from the target by sputteri ng or thermal decom position is
not incorporated into the growing coating and is lost in the chamber
pumps. A common practice in such cases is to introduce "make-up"
oxygen in the gas phase. This, then, is anotherform of reactive sputtering.
Finally it should be noted that when a batch processing chamber is
brought up to air for the purpose of introducing substrates, a thin oxide
layer will form on the target. Experiments with a Cr cathode indicate that
this layer is very similar in its sputter-removal characteristics to the one
that forms during reactive sputtering in the poisoned mode. 6 Thus a target
that has been exposed to the atmosphere must undergo a target clean-up
"reverse" transition similar to that shown in Figure 39 before metal coatings
can be deposited. This requires that the chamber be pumped for sufficient
time so that the outgassing flux entering into the plasma and deposition
region is less than the critical flux for permitting the reverse transition at
the target current density being used. If the outgassing flux exceeds the
critical value, the target will not "clean up," and a dielectric coating will be
deposited. For materials such as aluminum, the critical flux is relatively low.
This has led inexperienced workers, using devices operating at low cathode
current densities, to conclude that aluminum cannot be sputtered.

5.1 0 Target Fabrication

Targets can be formed by an almost unlimited variety of methods,
ranging from vacuum casting of metals, to hot pressing of powders, and to
forming composite targets by placing wires, strips, or discs of one material
to cover a portion of the surface of another material. However, caution
must be exercised. Poorcoating quality orconsistency can often be traced
to an inadequate target.
Target cooling is important, particularly at the high current densities
used with magnetrons. If the target material is a metal of good mechanical
integrity, direct water cooling can usually be provided on the rear surface.
Mechanically weak or nonconducting targets must be attached to a metal
backing structure which serves as the vacuum seal and, for nonconducting
targets, as an electrode. The attachment is usually made with a low-
temperature metal or alloy, or a conducting epoxy. If target purity is critical,
it is important to assure that the attachment medium does not diffuse into
and contaminate the target material. In the case of nonconducting targets,
the sputtering rate is limited by heat transfer within the target. 201 In some
410 Semiconductor Materials

planar magnetron designs the backing plate is a permanent part of the

cathode structure. Ring type metal targets for gun-type magnetrons
(Figure 271) are designed to make contact with the support structure by
undergoing thermal expansion.
A number of suppliers offer a wide selection of high purity metal and
compound targets, particularly in the disk form used by planar diode and
small ring type magnetron sputtering sources. The compound targets are
generally formed from powders by hot pressing. As noted previously, hot-
pressed targets are particu larly vul nerable to contam ination. It has, in fact,
been recom mended that si ntered targets be avoided if coati ngs with bu Ik-
type properties are desired. 233 For critical applications it is wise to measure
the composition of new targets prior to placing them in service. It is also
im portant to note that the pu rity levels quoted for most metal targets do not
generally include gaseous impurities such as oxygen.
In the cylindrical magnetron case, targets of common engineering
materials can be easily fabricated from commercially available tube and
rod stock. The tubular form possesses sufficient strength so that high
pu rity targets have been cast using materials as soft as Cd. Very soft metals
such as In, or compounds such as CdS, are generally attached to tubular
sections that contain the vacuum seals.
Reference 234 contains lists of suppliers of both sputtering equipment
and sputtering targets as well as general vacuum equipment and evapora-
tion systems.

6. THIN FILM GROWTH AND PROPERTIES

6.1 Coating Nucleation and Growth

The literature on nucleation and growth is very extensive. The discussion
here is necessari Iy selective and brief. The reader is encouraged to consu It
References 95 and 235-240 for more detailed reviews.
6.1.1 Condensation. The two main processes involved in condensa-
tion are the arrival of the coating atoms, or molecules, at the substrate
surface and the motion of these atoms on the surface. Coating atoms
incident on the surface of a substrate orgrowing coating can (1) bounce off
the su rface, (2) adsorb for a fin ite ti me, or (3) adsorb and stick permanently.
The probability of reflection is lowfor most practical cases of interest. Thus,
even energetic sputtered atoms will generally transfer sufficient energy to
the substrate on their initial encounter so that they become loosely
bonded species known as adatoms. 95 The adatoms diffuse over the surface,
exchanging energy with the substrate atoms and other adsorbed species,
until they either are desorbed, by evaporation or sputtering, or become
trapped at low energy sites as indicated schematically in Figure 43.
Two coefficients are used to describe the condensation process. The
accommodation coefficient provides a measure of the energy exchange
process and is defined as

(12)
 Physical Vapor Deposition 411

COATING FLUX - R

i i\
ADSORPTION SITE

Figure 43: Schematic illustration of condensation process that occurs during

film growth.

where T j is an effective temperature describing the kinetic energy of the

incident atoms, Ts is the substrate temperature, and Te is the temperature of
atoms evaporati ng from the su bstrate. For deposition by vacu um evapora-
tion, and probably also for most cases of sputter deposition,95 the accom-
modation process is so fast that there is negligible probability of an atom
re-evaporating before it reaches equilibrium, and a can be taken as unity.
The second coefficient is the sticking or condensation coefficient. It is
defined as the fraction of incident atoms which adhere and remain on the
substrate. Sticking coefficients are commonly less than unity, and in cases
where the adsorption energy is low and/or the substrate temperature is
high, can be very low. It should be noted that at high substrate temperatures
atoms accommodated to the substrate temperature can have a high
probability of loss by evaporation. Thus the sticking coefficient can be zero
even though the accommodation coefficient is near unity.24o
The mean residence time for desorption by evaporation depends on
the adsorption binding energy, Ea , and substrate temperature, T (absolute
degrees), and is given by

(13)

wherer 0 is a characteristic ti me approximately eq ual to the lattice vi bration

time, rv 10- 13 sec.
Under steady state conditions, where the rates of adsorption and
desorption are equal, an incident rate R of coating atoms per unit surface
area per second leads to an adatom surface density nA:

(14)

The exponential term in Equation 13 makes T R and therefore nA

strongly dependent on the adsorption binding energy and substrate temper-
ature. A typical deposition rate of 2 nm/sec (1200 Nmin) with unity
condensation coefficient corresponds to a flux of about 10 16 atoms/cm 3 -
412 Semiconductor Materials

sec for a representative material. The atom or site density on a metal

surface is about 10 15 atoms/cm 2. An Ea of 1 eVon a surface at 200°C leads
to a residence time of about 5x1 0- 3 sec and a flux of 10 16 atoms/cm 2-sec
yields an equilibrium adatom density that covers about 5% of the surface
sites. By contrast, an E a of about 0.15 eV (typical of Cu on clean glass) on a
surface at 200°C leads to a T R of about 5x1 0- 12 sec and an equilibrium
surface density of only about 5x1 0 4 atoms/cm 2. These calculations neglect
the interactions between the adatoms themselves and between the ad-
atoms and the surface sites (see next section). They are given simply to
provide a feeling forthe magnitudes involved and the importance of Ea and T.
6.1.2 Nucleation. As the coating process progresses, the condensed
adatoms must combine to form a coating. This nucleation process is
controlled by three parameters: Ea, the adsorption energy between the
adatoms and the substrate or growing coating; Ed' the surface diffusion
energy required to transfer an adatom to an adjacent adsorption site; and
Eb, the binding energy between coating atoms. Actually there are a set of E b
values depending on the degree to which the coating atom in question is
surrounded by, and bonded to, other coating atoms. In the following
generalized discussion, Eb will refer to the overall set of binding energies
unless specifically stated otherwise.
Thus the evaporation rate from a condensed deposit is given by
(15)

where Ebb is the sublimation or average surface atom binding energy for
the bulk condensate and 'l'e is a rate constant (typical units-atoms/cm 2-sec).
The adatom site-to-site hopping frequency is given by

1
v = - exp (-Ed/kT) (16)
To

The nu mber of sites visited by an isolated adatom du ring the residence

time, T R, that it is adsorbed on the surface is therefore
(17)

A random-walk diffusion distance before desorption can be written as

(18)

where a o is the mean distance between adsorption sites (see Figure 43).
However, it is important to realize that the adatoms do not necessarily
move uniformly over a real surface, since the migration rates are dependent
on the substrate crystallographic directions and surface topography.239
The collision rate between adatoms migrating overthe surface is given
by 237

(19)

Various regimes can be defined in terms of the parameters listed

above. If one assumes an ideal substrate with No (cm- 2) absorption sites of
 Physical Vapor Deposition 413

equal energy, then for R > Nov, the arriving atoms stay essentially where
they arrive. 239 If the atoms have directional bonds the layer will tend to be
amorphous. For materials with nondirectional bonds, such as metals, this
condition will lead to very fine-grained polycrystalline films. This regime of
low adatom mobility is encountered at low substrate temperatures.
At elevated substrate temperatures and low R, such that R < Re, no film
buildup can occur, although a monolayer of coating material may form on
the substrate for the case where Ea > E b. The most common regime of film
growth (R > RJ is one in which the substrate temperature is high enough
to produce considerable surface diffusion. The substrate is usually differ-
ent from the coating material, so that Ea is considerably different from the
various values of Eb. If Ea>E b, the first arriving atoms will condense as a
single monolayer. If Ea< Eb and 'r R is small, growth can occur on a uniform
substrate only through adatoms combining to form nuclei, which will tend
to be three dimensional as shown in Figure 44. There is said to be a
nucleation barrier to growth. 24o At low deposition fluxes, J (Equation 19)
may be too small to permit nuclei formation. Thus one has the concept of a
critical condensation flux to produce coating growth under given condi-
tions. 8 ,95 The stability of the nuclei depends on a balance between the
surface and volume free energies. 236 Thus nuclei that reach a critical
radius, such that subsequent growth decreases the free energy, survive
and can grow together to form grains as shown in the figure. The critical
cluster size varies inversely with Eb . 2 39 The condition Ea< Eb is commonly
encountered for metal condensing on insulators.
Most engineering substrates are characterized by a heterogeneous
distribution of sites of preferred nucleation. On such substrates the collision
rate of adatoms with these nucleation sites is generally higher than the
collision rate among adatoms themselves [J in Equation 19]. Therefore,
these sites tend to dominate the nucleation process. In fact at high
temperatures or low coating fluxes, such that J is small, nucleation will
essentially be impossible except at these sites. Thus, controlling the
density and distribution of the nucleation sites is an important considera-
tion in controlling coating properties such as grain size.
Once a continuous coating is formed, or when the condensate and
substrate are a common material, Eaand the various Eb values will depend
on the number of nearest neighbors at the atom site in question. However,
Ea(isolated adatom) will always be less than Eb. For conditions that yield a
low surface adatom density, nA' the growth rate will be limited by the
nucleation process as discussed above. Forconditions that yield a high nA'
there will be no impediment to condensation, but the atoms will tend to
group as clusters, since the atoms in the cluster have more nearest
neighbors (higher EJ than isolated adatoms.
All stages of the growth described above are greatly affected by
impurity atoms. Thus, for example, the deposition of Cd on clean W
represents a case where Ea> Eb' and layer growth occurs with no nucleation
barrier. However, the presence of less than one monolayer of oxygen on
the tungsten has been found to reduce Ea by a factor of more than two and
to yield evidence of a nucleation barrier. 239 Energetic particle bombard-
ment,such as ion bombardment, can dramatically affect the nucleation
 ~
~

HIGH ENERGY
TOTAL FREE SURFACE en
(1)
ATOMS
ELECTRONS COATING ENERGY ENERGY 3
o
FLUX I n"
o
o o I ::J

SITE I \ \
GROWTH
NUCLEI
/
I
I
I 0-
C
(')
r-+
o
GENERATION
/ .,
I
~
/ OJ
/ r-+

/
/ .,
(1)
/ ~.
ICC _ I '( _ RADIUS fij
/
..... ,
NUCLEATION SITES
", \

COLUMNAR \
GRAINS \

I \
\
\
\
\
\
VOLUME
ENERGY

Figure 44: Schematic illustration of film nucleation and growth.

 Physical Vapor Deposition 415

and growth process through the removal of impurity atoms, the creation of
nucleation sites, and perhaps even by influencing the effective mobility
of the adatoms and nuclei. 38 ,241 (See Section 6.4)
A special case of importance for many device applications is the
growth of single crystal films by the phenomenon of epitaxy.95,236,238,239
The term epitaxy means the oriented or single-crystalline growth of one
material upon another, such that there exists a crystallographic relation
between the overgrowth and the substrate. 235 Epitaxy may be classed as
either isoepitaxywhere the coati ng and su bstrate are the same material, or
heteroepitaxy, where the coating and substrates are different materials.
On single crystal substrates, crystallographic edges and steps of
atomic dimensions offer preferred growth sites. Layer-by-Iayer growth
from these sites yields epitaxial coatings. Growth can also occur via the
nucleation of clusters of the type described previously. If the clusters
can adjust to a common orientation during coalescence, a single crystal
film can be produced. 95 ,236,239 Epitaxial growth conditions involve clean
surfaces, modest deposition rates, and elevated substrate temperatures.
See Section 6.2. Such conditions are apparently required to suppress the
formation of unoriented nuclei or growth at unfavorable sites. There is
evidence that energetic particle bombardment improves epitaxy. Possible
mechanisms include removing impurity atoms, causing a higherdensityof
nucleating sites and hence a relatively slow growth rate of each cluster,
and increasing the cluster mobility.239 However, this is a controversial
subject of continuing research. See Section 6.4.
6.2 Evolution of Microstructure
Once a continuous coating is formed the growth continues, as des-
cribed above, but with the surface of the growing coating serving as the
substrate. Thus the properties of vacuum deposited coatings are determined
largely by adatom surface diffusion processes which are made evolutionary
by the way the state of the coating surface changes as the coating grows. 241
However, there are two additional processes that can affect the evolution
and growth of the coating microstructure. These are bulk diffusion and
atomic shadowing. Bulk diffusion affects the coating structure at elevated
temperatures, because atoms incorporated into the coating can readjust
their positions within the lattice by bulk diffusion processes. Any process
that causes a systematic nonuniformity in the arriving coating atom flux
over the substrate surface can have a drastic effect on the evolutionary
growth process. Shadowing, a simple geometric interaction between the
roughness of the growing surface and the line-of-sight directions of the
arriving coating atoms, provides such an effect. 241 ,242 The shadowing
effect is most pronounced at low substrate temperatures. At highertempera-
tures the shadowing can be compensated for by surface diffusion; i.e., if the
surface diffusion is large enough, the point of arrival of a coating atom
loses its significance.
For many pure metals the adatom binding energies and the activation
energies for both surface and bulk diffusion are related and proportional to
the melting point. 243 Thus the basic mechanismsofcoating growth, Le., surface
diffusion, bulk diffusion and shadowing, can be expected to dominate over
416 Semiconductor Materials

different ranges of T/T m' and to manifest themselves as differences in the

resulting coating structures (where T is the substrate temperature and T m
is the coating material melting point-both in absolute degrees). Such is
the basis for the structure zone models.
One of the first and most important zone models was developed by
Movchan and Demchishin from a study of thick evaporated coatings of Ti,
Ni, W, Zr0 2, and A1 20 3 .244The model, which related coating microstructure
to T/T m' has been extended to sputtering, in the absence of ion bombard-
ment, by adding an additonal axis to account forthe effect of the sputtering
gas. 241 ,245 See Figure 45. Recent studies have been found to be in basic
agreement with the mode1.246-249a The numbered zones correspond to
those suggested by Movchan and Demchishin. The transition zone (Zone
n was not specifically reported by Movchan and Demchishin for their
evaporated coatings.
The Zone 1 structure results when adatom diffusion is insufficient to
overcome the effects of shadowing. It therefore forms at low T/T m and is
promoted by an elevated working gas pressure which causes coating
atoms to be gas-scattered and therefore to arrive at oblique angles.
Oblique deposition and substrate surface roughness also contribute to
the shadowing effects. The Zone 1 structure usually consists of tapered
crystals, with domed tops, which are separated by voided boundaries and
tend to point in the direction of the arriving coating flux. 250 The crystal
diameter increases with T/T m' Shadowing introduces open boundaries,
because high points on the growing surface receive more coating flux than
valleys do, particularly when a significant oblique flux is present. The
coating surface roughness can result from the shapes of initial growth
nuclei, from preferential nucleation at substrate inhomogeneities, from

20
ARGON
PRESSURE
(mTorr)

Figure 45: Schematic representation of the influence of substrate temperature

and argon working pressure on the structure of metal coatings deposited by sput-
tering using cyl indrical magnetron sources. T is the substrate temperature and T m is
the melting point of the coating material in absolute degrees. See References 241
and 245.
 Physical Vapor Deposition 417

substrate roughness (most common), and from preferential growth. The

Zone 1 crystals are generally much larger than the crystallographic grain
size. In fact, Zone 1 structures can occur in amorphous as well as crystalline
deposits. 242 ,251,252 The internal structure of the crystals is poorly defined,
with a high dislocation density (see below).244
The transition structure, Zone T, consists of a dense array of poorly
defined fibrous grains. It is a columnar Zone 1 structure with crystal sizes
that are small and difficult to resolve. 241 Itforms the internal structure of the
Zone 1 crystallites. Coatings with structures approaching the Zone T form
grow under normal incidence on relatively smooth homogeneous substrates,
at T/T m values that permit the adatom diffusion to largely overcome the
roughness introduced by the substrate and the initial nucleation. 241 ,253
The Zone 2 region is defined as that range of T/T m where the growth
process is dom inated by adatom su rface diffusion.241 The structu re consists
of columnar grains separated by distinct dense intercrystalline boundaries.
Dislocations are primarily in the boundary regions. 244 Grain sizes increase
with T/T m and may extend through the coating thickness at high T/T m.
Su rfaces tend to be faceted. Coati ngs with platelet structu res and whisker
growth can also grow under Zone 2 conditions of high surface diffusion. 241
The Zone 3 region is defined as that range ofT/T m where bulk diffusion
has a dominant influence on the final structure of the coating. 241 The grains
may be columnar or equiaxed. Coatings tend to growwith columnar grains,
as indicated in Figure 44. Recrystallization into equiaxed grains may be
expected if points of high lattice strain energy are generated throughout
the coating during deposition. Large columnar grains can grow from
columnar as-deposited grains by strain-induced boundary motion and
grain growth. 241 In general, coatings adopt bulk-like behavior as T/T m is
increased into the Zone 3 region.
The general concept of the zone model shown in Figure 45 appears to
apply to a wide range of materials and deposition processes. However, the
most detailed use of the model has been in the deposition of metals. Thus
reference will be made to the model in formulating guidelines for semi-
conductor device metallization. See Section 7. Alternative versions of the
zone model are given in References 247 and 255.
The conical nature of the low-mobility Zone 1 structure is a consequence
of the evolutionary nature of the coating growth process. In addition to the
evolution of dominant physical structure there is an apparent repetition of
honeycomb-like features throughout the film thicknesses.247-251 This self-
similarity in the structural evolution, and the universality of the physical
structure of various materials, suggest a common origin, and it has been
suggested that the self similarity may be fractal in nature. 254
It has been observed that an optimum occurs in the structure-sensitive
properties, surface smoothness, crystallographic order, and charge mobility,
for coatings of many compounds of electronic interest at a substrate
temperature that is within a few percent of 1/3 T b, where T b (absolute
degrees) is the boiling point of the compound. 256 ,257 See Figure 46. It has
been estimated that T/T b~ 1/3 is that point at which evaporation from
amorphous intergrain regions becomes significant. Thus it has been
proposed that film quality improves with increasing substrate temperature
 ~
....t.
OJ

MATERIAL To/Tb
(f)
Se 0.32 CD
ZnSe 0.31 3
QUALITY OF BULK-TYPE
ZnTe 0.33 o·
AMOUNT OF FILM PROPERTIES 0
CdS 0.30 ::J
DISORDERED
MATERIAL I RATE OF
CdTe
PbS
PbTe
0.34
0.32
0.31
0-
c
()
...+
0

I
~

RE-EVAPORATION SnTe 0.32

PbSe 0.34 ~

Y
p.)
...+

\{;( ,/
CD
~

m·
en
' " '~;/
I,,,
EVAPORATION

-~
~1-----
,.. ............. I 'CRYSTALLINE

~ I ----- Ts/Tb
CRYSTALLIZATION
REGION

AMORPHOUS
REGION
AMORPHOUS REGIONS
WITHIN FILM

NEARLY COMPLETE
\ SURFACE
ROUGHENING

EVAPORATION OF
DISORDERED MATERIAL SUBSTRATE

Figure 46: Schematic illustration of Vincett-Barlow-Roberts structure/property relationship for vacuum deposited coatings.
See References 256 and 257.
 Physical Vapor Deposition 419

up to 113 Tb because the existence of such amorphous regions decreases

and because slight evaporation from these regions creates vacancies and
promotes crystallization and recrystallization. 256 At higher temperatures
the more complete evaporation from the amorphous reg ions can make the
films rough and voided. This, coupledwith a lossofvolatilespecies, leads to
degraded coating properties. Thus an optimum structure occurs at TIT b'V1 13.
Covalently bonded materials, such as tetrahedral semiconductors,
yield coatings with amorphous structures at low substrate temperatures,
polycrystalline structures at higher temperatures, and epitaxial single
crystal structures under some conditions of high temperature deposition.
Figure 47 shows a type of zone diagram which is useful for delineating the
TIT m and deposition rate cond itions under wh ich these phases a~e fou nd. 258
!

6.3 Growth of Compound Semiconductors from

Multicomponent Vapors
Compound semiconductors, such as the III-V materials, are composed
of constituents having widely different vapor pressures, so that direct
evaporation is difficult. 13,14 Thus, as was discussed in Section 3.6, multi-
source evaporation is commonly used. A method called three-temperature
evaporation is particularly effective. The method, which is shown schematic-
ally in Figure 48, was originally conceived for two-component materials,
with the two evaporation sources maintained at different temperatures
and the substrate at a third temperature. 259 However, the features of the
process are far more general than the name three-temperature-evaporation
would imply, and form the basis for much of the technology used in
Molecular Beam Epitaxy. See Section 4.

10
UQ)
AMORPHOUS
~
~
...w
<{
a:
...
J:
s:
0
a:
C)

10. 1

o 0.2 0.4 0.6 0.8 1.0 1.2

T/T m

Figure 47: Phase and crystallographic-order transitions in germanium. Data from

Reference 258.
420 Semiconductor Materials

Figu re 48 shows a schematic plot for the deposition of a com pou nd AS

by the three-temperature method. The figure shows the total substrate
condensation flux as a function of the incident flux of type A constituent,
with the flux of type S constituent maintained constant and with the
substrate maintained at a sufficiently elevated temperature so that the S
flux cannot condense. Thus, at low fluxes of the type A material, no
condensation occurs because both the A and S fluxes are below the
critical values for nucleation. See Section 6.1. However, as the flux of type
A material is increased, a point is reached where a reaction of A and S
adatoms to form AS nuclei results. This occurs before the flux of type A
constituent is large enough to condense as elemental type A material.
Thus there exist deposition conditions where the only condensate that
can survive on the substrate is the compoundAS. Subsequent increases in
the A flux increase the condensation rate until it becomes rate-limited by
the available S flux. If the A flux is further increased to the point where A
nuclei form on the growing AS surface, then a two-phase structure consisting
of elemental A and AS can result, as indicated in the figure.
The most important present aplication of the general three-temperature
principle is in molecular beam epitaxy. Figure 49 shows a schematic
illustration of the substrate processes that are believed to occur in the
MSE growth ofGaAs.26oThe processwill be described in some detail, since
it illustrates the complexity that can accompany the surface interaction
between the vapor fluxes. Ga is supplied as the monomer by evaporation
from the liquid. As can be supplied as AS 2 or As 4 . The GaAs surface
composition is defined as being "As-stabilized" or"Ga-stabilized" accord-
ing to whether the lattice is terminated by As or Ga atoms respectively.261
Most MSE GaAs growth is done under conditions in which the GaAs
surface is Ga-stabilized. It is this case that is considered in Figure 49,
where the upper drawing refers to growth from Ga and AS 2 fluxes, and the
lower drawing to growth from Ga and AS 4 fluxes.
The Ga atoms have a binding energy of about 2.5 eV and a near unity
sticking coefficient at typical substrate temperatures of 600 o e. The AS 2

SUBSTRATE (T3)

Figure 48: Schematic illustration of three-temperature evaporation method. See

Reference 259.
 Physical Vapor Deposition 421

Ga STABALIZED SURFACE
AS 2 STICKING COEFFICIENT ~ 1

AS4 STICKING COEFFICIENT ~O.5

Figure 49: Schematic illustration of MBE growth of GaAs from Ga and AS 2 fluxes
(upper) and Ga and AS 4 fluxes (lower). See Reference 260.

molecules are adsorbed in a weakly bonded, physisorbed, adatom precursor

state. They diffuse over the surface, and desorb after a short lifetime
(r R <1 0- 5 sec) unless they encounter a Ga atom. The AS 2 molecules can
also be lost by an association reaction which produces AS 4 molecules
which subsequently desorb. The AS 4 desorption is a first order reaction.
This implies that the rate-limiting step is not the surface diffusion of pairsof
AS 2 molecules to adjacent sites, since this would lead to a second order
process, but rather the actual associative interaction or the desorption
step itself. 262 AS 2 molecules encountering Ga atoms undergo a first-order
dissociative chemisorption. The sticking coefficient of AS 2 molecules is
therefore simply proportional to the Ga flux and tends toward unity on Ga-
rich surfaces. Excess AS 2 is lost by re-evaporation, and stoichiometric
GaAs is grown.
AS 4 molecules also are adsorbed in a weakly bonded precursor state.
The bond energy is '"'-'0.4 eVa Under typical deposition conditions the AS 4
molecules have a short residence time (r R<1 0- 5 sec) and become chemi-
sorbed only if they encounter a Ga atom underthe right conditions. 263 The
maximum sticking coefficient is only 0.5. In particular, pairs of AS 4 molecules
must undergo a second order reaction on adjacent Ga sites to yield four
chemisorbed As atoms and a desorbed AS 4 molecule, as indicated in
Figure 49. This requirement for a pairwise interaction can result in a higher
concentration of point defects for films grown with AS 4 .260
Similar growth behavior is observed for most III-V combinations of AI,
Ga, and In with P, As, and Sb. 260
422 Semiconductor Materials

The stoichiometric (AB) region is shown as a single phase region in

Figure 48. However, it should be divided into two sub-regions, one where
the growth is rate-limited by the available A flux, and one where the growth
is rate-limited by the available B flux. The detailed microstructure and
electrical properties of the coatings grown in these two sub-regions can
differ. Consider the case of CdS deposition onto elevated temperature
(250°C) substrates by reactive sputtering from a Cd target in an H 2S
working gas. 216 Data are given in Figure 50. The general three-temperature
model applies, since at the Cd flux and substrate temperature used, no Cd
condensation occurs in the absence of H 2S injection. The S flux rate-
limited region yields a film characterized by S vacancies, while the Cd rate-
limited region yields a film characterized by Cd vacancies. In doping was
effective in the S rate-limited region, but of limited utility in the Cd rate-
limited region because of compensation by Cd vacancies. 216
References 264 to 266 provide a more detailed review of semiconductor
crystal growth by sputtering. Compound semiconductors which have been
successfully deposited epitaxially include III-V compounds such as InSb,
GaSb and GaAs; II-VI compounds such as CdS; IV-VI compounds such as
Pb 1_xSn xTe; nitrides such as AIN; and special materials such as Bi 2Te 3 .
Other semiconductors produced in polycrystalline form include InN, GaN,
(Cdln)S, lnS, CdSe, CdTe, Cd x H9 1_xTe, lnO, Cu 2S, CulnS 2 and CulnSe 2.
6.4 The use of Ion Bombardment for Substrate Cleaning
and to Influence Coating Growth
Sputter cleaning is that process where the surface of a substrate is
subjected to ion bombardment for purposes of sputter-removing oxide
layers, or other surface contamination, before depositing a coating. Often
from 20 to 500 nm of material are removed using current densities of 0.5 to
5 mA/cm 2and ion energies in the 1 00 to 1 000 eV range. Sputtercleaning is
commonly used in sputter deposition processes and occasionally in evapora-
tion processes. 267 ,268 The usual method is to create a glow discharge
plasma at the substrates and to provide movable shields to collect the
sputtered flux. Sputter cleaning is easily executed in planar diode sputter-
ing sources of the type shown in Figure 19, because the substrates are in
contact with the plasma. It is more difficult to implement in magnetron
devices, because of the plasma confinement,and in evaporation systems.
In such cases an independent discharge must be sustained at the substrates.
In some circumstances these discharges can be implemented by designing
the substrate holder so that, in concert with the substrate, it forms an
efficient magnetron electrode. 162 See Section 5.6. Rf power is required if
the substrates are nonconducting. Ion beam sources are commonly used
for sputter cleaning in MBE systems. See Section 4.3.
The controlled use of ion bombardment of a growing film during
deposition has been shown to affect all stages of crystal growth, ranging
from the initial stages of nucleation discussed in Section 6.2 to the micro-
structure evolution discussed in Section 6.3. Low energy ion bombardment
has proven very effective in removing impurities from the surface of a
growing coating.269-271 There is considerable evidence that low energy
ion bombardment also affects the effective surface mobility of adatoms
 RESISTIVITY
DEPOSITIOI\J RATE
.............................
S-FLUX
::::::::::::::::::::~::: A 10 6
1.1
RATE !
1.0 LIMITING J

105

0.9

0.8 ~ilt:t:': Cd-~ 104

E
£
0.7
o
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w
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a:
•i~t'~;;tiII~ E
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Q
z ~ 10 2
Q 0.5
I-
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Vi ~
a (I)

Cii
~ 0.4 ~ 10 '1J
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(j)
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0.2 <
m
'0
0.1 10. 1
o.,

0
0 0.1
L
••
0.2 0.3 0.4 0.5 0·.6 0.7 0.8 0.9 1.0 10.21 ! !
DOPED WITH 1 ATOMIC PERCENT In.
! I ! }}}:::::::::::::::l ! ! !,
o
o
CD
'0
(j)
H2S INJECTION RATE (Torr - liters/sec) o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ~ ~ ;::+
H S INJECTION RATE (Torr· liters/sec) 0"
2 ~

Figure 50: Deposition rate and resistivity for CdS undoped and In-doped films deposited by reactive sputtering from Cd and ~
Cd-In cyl indrical magnetron targets u~ing a H2 S/Ar working gas. Data from Reference 216. r\)
UJ
424 Semiconductor Materials

and nuclei and may contribute to lowering the epitaxial tempera-

ture. 38 ,239,272 In addition, high energy ion bombardment can create nuclea-
tion sites. 267 ,268 Accordingly, the effect of ion bombardment on coating
properties, such as the grain size, appears to be strongly dependent on the
ion energy. The parameter T/T m is also important, since crystallographic
damage produced by ion bombardment can be removed through the
diffusion processes that are active at elevated substrate temperatures. It
has, in fact, been concluded that any chosen film property, whether
physical, chemical or electrical, will be modified to some extent by contact
with a plasma and application of a bias. 273
The term bias sputtering is used to refer to the specific process of
maintaining a negative bias on substrates in orderto induce ion bombard-
ment during sputter deposition. Bias sputtering is particularly effective
when the sputter cleaning process is simply continued, often at reduced
bias potential, after the deposition process has been initiated. The term
"ion plating" is also used, generally to refer to the case where concurrent
ion bombardment is used during film growth in evaporation systems. 267
However, an appreciation for the control over coating properties that can
be achieved through the use of ion bombardment is increasing, so that
current applications extend far beyond simple evaporation and sputtering
systems. Examples are in MBE (Section 4) and in ion beam deposition
(Section 5.7).
The uses of ion bombardment to modify the properties of concurrently
deposited coatings can be divided generally into cases of low energy ion
bombardment, where the objective is to remove impurity species, or
otherwise influence the coating composition, and higher energy bombard-
ment, where the objective is to modify the coating structure. The effec-
tiveness of low energy «200 eV) ion bombardment in removing loosely
bonded impurity atoms 269 ,271 is a consequence of the fact that such atoms
have a relatively high sputtering yield,68 as discussed in Section 5.2.
Figure 51 shows the oxygen content as a function of substrate bias for
GaAs coatings which were deposited from a GaAs target using an rf driven
planar diode sputtering source of the general type shown in Figure 19. 274,275
Data are also shown for room temperature Hall mobilities. The figure
clearly shows the effect of modest substrate bias t:=: 150V) in reducing
oxygen contamination in the films and thereby raising the mobility into the
range found in bulkGaAscrystals. Higherbiases(~200V) caused trapping
of accelerated oxygen containing ions, or forward sputtering of oxygen
species adsorbed on the surface, with the consequence that the oxygen
content of the films increased and the electron mobility decreased. Increas-
ing elemental incorporation probabilities is, in fact, another important
application of ion bombardment. 38 Figure 52 shows an example of using
substrate bias to increase the incorporation of sulfur dopant in GaAs films
deposited using the same planar diode apparatus. At low biases (~50V)
the ion bombardment suppressed the doping process by sputterremoving
S atoms from the surface of the growing film before they could be incorp-
orated. However, at a higher bias (~200V), the sulfur content of the GaAs
film was significantly increased.
The sputter removal of contamination may be one of the primary
mechanisms bywhich ion bombardment reduces epitaxial temperatures. 239
 Physical Vapor Deposition 425

4000 ...- -.....- -.....- - - . . - - - - . . - - - - . 1 . 0

....
III

'2
U 3500 0.75 :::>
~ ~
I
~
<-
/~\
N :0
2
E S
Z
>-
I- 0
:J \
I t=
3000 I 0.50 <t
Cii \ I a:
0 I-
~
Z
0
a::
\
\
\
\
/
•I

/e
z
w
u
z
/ 0
I-
u
w
\
, 'A___ A"''''---' u
Z
...J -'" w
w 2500
GaAs
0.25
"x>-
0
RF PLANAR DIODE
TARGET VOLTAGE = 1000V
Ar PRESSURE = 2.67 Pa (20 mTorr)
SUBSTRATE TEMPERATURE = 600 o e·
2000 0
0 50 100 150 200 250
APPLIED SUBSTRATE BIAS (Volts)

Figure 51: Room temperature electron mobil ities and relative oxygen concen-
trations in GaAs films as function of applied substrate bias during film growth.
Data from Reference 275.

Thus in the sputter deposition ofGe films, there is evidence that the use of a
substrate bias suppressed the detrimental effects of an oxygen background
pressure and permitted epitaxial temperatures comparable to those
achieved in ultra high vacuum systems. 276 However, it should be noted that
even in ultra high vacuum MBE systems it has been found that the growth
required to obtain single crystal Si films on both Si and sapphire substrates
was reduced when small fractions of the incident Si beam were ionized and
accelerated. 277 ,278
One of the exciting new developments in sputter deposition is the
growth of single crystal metastable semiconductors such as (GaAs)1_xSix'
(GaSb)1_xGex' and InSb 1_xBi x' which have unique physical properties. 275,279
The growth of these materials in very controlled environments could be
considered to be a sputtering analogue to MBE. It appears that a critical
aspect of the growth of such materials is the use of low-energy ion
bombardment of the growing film to simultaneously modify the elemental
sticking probabilities and effective adatom surface mobilities. For example,
one way that ion bom bardment apparently assists in the formation of these
materials is in inhibiting the formation of second phases by preferential
sputtering of incipient precipitates. Thus, for both (GaSb)1_xGex and
(InSb)1_xBix films it was found that ion bombardment increased the growth
temperature at which single phase epitaxial alloys could still be obtained. 275
426 Semiconductor Materials

A recent investigation has been made of the mechanisms that charac-

terize the growth of epitaxial films of GaAs by rf sputter deposition in the
presence of a substrate bias. 280 The sputtering apparatus was of the same
rf planar diode type, with a GaAs target, that provided the data shown in
Figures 51 and 52. An effusion cell was arranged to deliver an excess AS 4
flux at the substrates, wh ich were single crystals of GaAs. The investigation
showed that the film growth rate depends not just on the Ga beam flux, as in
the MBE growth described in Section 6.3, but also on the bias voltage, the
AS 4 flux(J As ), and the substrate temperature(T J. The growth rate is limited
by resputteting of Ga from the substrate surface and is coupled to J As and
4
Ts because these parameters determine the AS 4 surface coverage and
thus the average binding energy and sputtering yield of the Ga atoms on
the GaAs surface. It is important to note that, despite the difference in
growth mechanisms, these sputtered coatings, which were grown at sub-
strate tem peratu res of ~600°C with substrate biases of typically from 100
to 200V, yielded carrier mobilities comparable to those obtained using
liquid phase epitaxy and MBE. See Figure 51.
Intense substrate ion bombardment during deposition can suppress
the development of open Zone 1 coating structures at low TIT m. See Figure
45. This has been demonstrated for both conducting 281 ,282 and nonconduc-
ting deposits. 283 The ion bombarded deposits produced at low TIT m have
structures similar to the Zone T type and appear to be free of nodular
defects. Ion bombardment on uncooled substrates yields structures typical
of high TIT m. 284 As a general rule, the suppression of Zone 1 structures at
low TIT m requires thatthe ion flux be of such magnitude and energy that it is
capable of back-sputtering a significant fraction of the arrivi ng coating flux
(Le., 30-60 0/0).284
Figure 53 schematically illustrates the kinetic processes by which
concurrent ion bombardment is believed to influence the microstructure
of vacuum deposited coatings. Thus ion bombardment may cause the
erosion of surface roughness peaks and the redistribution of material into
valleys. The general knock-on behavior discussed in Section 5.2 can
cause a large number of atoms within the coating to be relocated by recoil
displacement reactions. These processes often lead to the formation of
coatings with significant compressive internal stresses. See Section 6.5.
Point defects can be generated which promote rapid internal diffusion
within the coating or between the coating and the substrate. 38 Inert gas ions
with energies greater than about 100 eV tend to become trapped in the
growing coating, as discussed in Section 5.2. At high ionfluxes, the entrapped
inert gas can have concentrations of sev~(al atomic percent and may cause
blistering in subsequent annealing. 284,286 Inert gas incorporation is generally
greater in amorphous than in crystalline materials. Concentrations of Ne,
Ar, and Kr of from a few to 30 atomic percent have been obtained in
amorphous GdCo and CdCoMo films deposited using an rf substrate bias. 287
Inert gases generally evolve during deposition at TIT m greater than about
1,13 to 1,12 and are therefore not entrapped.
Caution must be exercised when using ion bombardment during the
deposition of any multicomponent material, since the composition may be
modified by preferential sputtering, as discussed in Section 5.5.
 Physical Vapor Deposition 427

20 _ - - -.....- - - - . . - - - - - . - - - -..
GaAs
RF PLANAR DIODE
TARGET VOLTAGE = 1000V
Ar PRESSURE = 4 Pa (30 mTORR)
H 2S PRESSURE = 1.3 x 10-3 Pa (1 x 10-5 Torr)
SUBSTRATE TEMPERATURE = 570 0 C

2
o
i=
<t
a:
t-
2
w
U
~ 5
u
a:
::>
u..
...J
::>
CIJ

2 ... ... ..... '- -.11

o 50 100 150 200

APPLIED SUBSTRATE BIAS (Volts)

Figure 52: Sulfur concentrations in as-deposited GaAs films as function of the

applied substrate bias during film growth. Data from Reference 275.

SPUTTER DEPOSITION
INTO SHADOWED AREAS

SPUTTER REMOVAL
OF PEAKS

SHADOWED
AREAS ION ION

RECOIL INTERFACE
ENHANCED MIXING
DISPLACEMENT DIFFUSION

Figure 53: Schematic illustration of kinetic processes by which concurrent ion

bombardment influences the microstructure of a vacuum deposited coating. Suf-
ficiently intense ion bombardment can remove the shadow-induced columnar
structure as implied by going from left to right in the figure.
428 Semiconductor Materials

It has been noted above that ion bombardment during deposition can
promote interdiffusion within a film or between a film and substrate. In a
new process called ion-beam mixing, post-deposition bombardment of a
thin film structure by very high energy ions is used to cause interdiffusion
and reactions within the structure. 288 The reaction-mixing mechanism in-
volves collision cascades of the type discussed in Sec. 5.2. In many cases, the
process proves to be remarkably efficient, with the numberof mixed atoms
greatly exceeding the number of bombarding ions. Two examples are
illustrated schematically in Figure 54. In the case shown at the top,
multiple layers of Ag and Cu, 20 nm thick, were first deposited on Si0 2 with
the thickness adjusted so that the average compositions varied between
A9 20 Cu 80 and A9 80 CU 20 • The films were then mixed using 300 keV Xe+ ions,
at a dose about equal to the surface atom density (2x1 0 15 cm- 3), with the
samples held at liquid nitrogen temperatures. The resulting coatings were
fcc cubic metastable solid solutions of Ag and Cu atoms with lattice
parameters wh ich obeyed Vegard's lawfor ideal solid solutions. In the case
shown at the bottom of Figure 54, a30 nm thick Ni film was caused to react
with a Si substrate by bombardment with 300 keV Kr+ ions. 29o The reacted
zone consisted of a Ni 2 Si phase which increased in thickness with the
square root of the ion dose. Ion doses larger than those required to
consume all of the metal yielded amorphous structures. This is in contrast
to the thermal diffusion case, where the Ni 2 Si transforms to NiSi after all of
the metal has been consumed.

300 KeV Xe+

(Dose - 2 x 1015/cm-2)

a:
w
I- 4.08 A
W
:E
c:{
CC
<
Cl.-
UJ
U

...<~
..J 3.62 A
Cu Ag
ATOMIC % Au

300 keV Kr+

x oc (DOSE) 1/2

Figure 54: Schematic illustration of interfacial compound formation by ion beam

mixing. See References 288 and 290.
 Physical Vapor Deposition 429

6.5 Internal Stresses

Virtually all coatings deposited by evaporation and sputtering are in a
state of stress. The total stress is composed of a thermal stress, due to the
difference in the thermal expansion coefficients between the coating and
substrate materials, and an intrinsic stress due to the cumulative effects of
atomic forces generated throughout the coating volume by atoms which
are out of position with respect to the minimums in the interatomic force
fields. 291
The parameter T/T m is particularly important in determining the state
of internal stress in a coating. At low T/T m' the intrinsic stress dominates
over the thermal stress. At T/T m exceeding ~0.3 (Zone 2 in Figure 45) the
intrinsic stresses are significantly reduced by recovery292 during coating
growth. The thermal stresses are dominant for coatings deposited at high
T/T m and cooled to room temperature. Thermal stresses can also be
important for coatings deposited at low T/T m and then subjected to pro-
cessing or use at a higher temperature.
The thermal stress in thin films with thicknesses less than 10-4 times
that of the substrate, where plastic flow within the substrate can be neglected,
is given in a one-dimensional approximation (neglecting Poission effect)
by 95,293

(20)

where Et is Young's modules, at and as are the average coefficients of

thermal expansion for the film and substrate, Ts is the substrate temperature
during deposition, and Ta is the temperature at the time of measurement. A
positive value of a th corresponds to a tensile stress. Table 10 gives elastic
constants and thermal expansion coefficients for several metals commonly
used in electronics related processing. Large thermal stresses can be
induced by typical processing conditions. Consider an AI coating (at =
2.4x1 0-5 °C-1) deposited on a Si substrate (as = 7.6x1 0- 6 °C- 1) at a temper-
ature of 150°C and then annealed at 400°C as part of a device processing
step. A compressive stress of about 0.26 GN/m 2, which is larger than the
yield strength of AI (0.11 GN/m 2), is predicted.
The intrinsic stress has been defined as that component of the total
stress which cannot be attributed to the thermal stress. 291 Intrinsic stress
magnitudes can approach the yield strength for the coating material. The
coating/substrate bond must withstand the interfacial forces associated
with the accumulated internal stresses throughout a coating. In contrast
to the thermal stress, the contribution of the intrinsic stress to this force
tends to increase with the coating thickness. Therefore, premature inter-
face cracking and poor adhesion, forcoatings with thicknesses exceeding
values as low as 100 nm, can often be attributed to high intrinsic stress
levels.
For low melting point materials such as AI, T/T m exceeds 0.3 fortypical
deposition conditions (see Table 10), and both the thermal and intrinsic
stresses tend to relax by internal diffusion. 294 Accordingly, what we
encounter is not the mechanical consequences of the stress, such as
ad hesion fai lures, but the consequences of the stress driven diffusion. The
430 Semiconductor Materials

Table 10: Properties of Several Metallic Coating Materials Commonly Used

in Electronics Related Processing

Young's Yield Thermal

Melting Nodulus Strength Expansion
T/Tm")'r
Materials Temp. (oC) ~ CPa Coef.(oC- 1 )**

Aluminum 660 0.40 63 0.11 2.4x10- 5

Titanium 1668 0.19 113 0.14 0.85x10- S

Chromium 1875 0.17 260 0.16 0.68xlO- 5

Copper 1082 0.28 120 0.32 1.68x10- 5

Molybdenum 2610 0.13 300 0.84 0.49xlO- 5

Palladium 1552 0.20 115 0.31 1.18xlO- 5

Tantalum 2996 0.11 190 0.35 0.67xlO- S

Tungsten 3410 0.10 351 1.8 0.43xlO- 5

Platinum 1769 0.18 150 0.16 0.90x10- S

Gold 1663 0.19 81 0.21 1.43xlO- 5

Lead 327 0.62 16 0.009 2.94xlO- 5

resulting material flow can lead to the formation of hillocks or holes,

depending on whether the stresses are compressive or tensile. Hillocks
have been observed to grow extensively in AI, 295 AU,296 and Pb 297 films'under
conditions of high compressive stress, such as in the numerical AI/Si
example given above. Surface growths of this type present obvious
problems in the deposition of subsequent coating layers during device
processing.
In the case of high melting point materials, T/T m is generally less than
0.3 at typical deposition temperatures. See Table 1O. Accordingly, intrinsic
stresses usually dominate in these materials. Therefore, intrinsic stresses
are particularly important in the refractory-metal device metallization dis-
cussed in Section 7. The intrinsic stresses, in contrast to the thermal stresses,
are strongly dependent on the deposition conditions. Therefore, intrinsic
stresses will be the subject of the remaining discussion.
The following generalizations can be made regarding the intrinsic
stresses in metal coatings. 95 ,222,293 (1) The intrinsic stress is not strongly
dependent on the substrate material. (2) The intrinsic stress is relatively
constarlt throughout the coating thickness for thin films «500 nm thick).
(3) The intrinsic stresses in evaporated metal coatings are almost exclusively
tensile, and most evaporated dielectric coatings also exhibit tensile stresses.
(4) Coatings subjected to significant energetic particle bombardment
during or following deposition generally exhibit compressive stresses.
 Physical Vapor Deposition 431

Therefore, sputtered coatings are often in a state of compressive

st ress. 154,298,299
Figures 55 and 56 illustrate the effect of ion bombardment on internal
stress. Figure 55 shows the internal stresses, as a function of substrate
bias voltage, for Mo coatings deposited using an rf planar diode. 298 The
stresses are seen to be much larger than the estimated thermal stress for
the substrate temperature, and to be tensile at low bias voltages and
compressive at higher bias voltages. Note that the maximum stresses are
comparable to the yield strength of Mo(~O.8 G Pafm 2). Figu re 56 shows the
results of experiments in which the influence of concurrent ion bombard-
ment on the internal stresses in evaporated Cr coatings was investigated. 301
Coatings deposited at low ion doses were in tension, as would be expected
for evaporated coatings. Above a critical dose of about 45 eVfCr atoms, the
coatings were in a state of compression.
Tensile intrinsic stresses are generally explained by some type of void
network, such as grain boundaries, which place the coating in an under-
dense state.254-257,302-305 It is believed that the compressive stresses are
generated by an atomic peening mechanism where incident energetic
particles strike the growing coating and drive surface atoms into the
interior by recoil displacement reactions. Thus the coating is densified,
and the surface is smoothed, via the mechanisms discussed in Section 6.4
and shown in Figure 53. The upper curve in Figure 56 shows that the coating
reflectance does indeed undergo a significant increase at the ion bombard-
ment dose that produces compressive stresses. Thus tensile stresses are

MOLYBDENUM
COATING THICKNESS - 280-350 NM
SUBSTRATE TEMPERATURE "-' 100°C
1.5.... RF PLANAR DIODE -

~
~I
1.0-- /-\ -

0.5 - • -

~ ~t .~ 0 \ T_~~~~~~~ __
~z
~~
•
-0.5 - \ -
2 ~ •
~ -1.0>- \ -
8 •
-1.5 ~ -
I I I I I I I I

o -50 -100 -150 -200

APPLIED SUBSTRATE BIAS (volts)

Figure 55: Variation of internal stress with substrate bias for molybdenum coat-
ings deposited using planar diode sputtering source. Data from Reference 300.
 E 70 ~
~ I w
~ I ~

BOMBARDING IONS - Xe+ AT '1.5 KeV

~w
u
2
60 .1'"
I I .
M
•~
.'' - •--
(J)
m
ION BOMBARDED REFERENCE u~.. _----'- I
I \
n~.
SUBSTRATE SUBSTRATE ~ I gQ
7r
u.. I

~
~ 50 I REFLECTANCE AT 560 nm Q.
I Q

II
1 1\
1\
I:
/ I
2.01- I
I
~
~

I \ II z • I CD
--;; 0 · 1 ~.
~\ ~I c..
/ 27 0 I \ " 250 I ~
C/) ~ 1.0 ., .,
I I \ l I

\
~ CRITICAL DOSE
C/)
I I \ 120 mm I I W
I I I 0:
t- I 45 eV/Cr ATOM
/ 1\/ C/)

I H'0 0 \ ,
I ~
..J O~---------~-------/-----
I \ I u..
\ I W
1\. /e
ie. /•
\
\ I
/
"<!
0:
w
z
o
en -1.0 t I, /-
I
,
••-.
<! ~
> ESTIMATED:.
ION
SOURCE

CHROMIUM
I ~
~
8 -2.0
0.01
ERROR BARS

0.1
I
I
I
1 10 100
EVAPORATION
SOURCE DOSE (Bombarding Ions per 100 Condensing Atoms)
Figure 56: Influence of concurrent ion bombardment on the internal stress in evaporated chromium coatings. Data from Ref-
erence 301.
 Physical Vapor Deposition 433

generally found in the low density Zone 1 region of Figure 45 and com-
pressive intrinsic stresses in the relatively dense Zone T region. 222
In the case of triode and magnetron sputtering sources operating at low
working gas pressures, the growing coatings are subjected to bombard-
ment by energetic working gas atoms which originate at the target as ions
that are neutralized and reflected. See Section 5.2. These species are as
effective as ion bombardment in producing compressive stresses. 154,298
The stresses in such coatings therefore depend in a seemingly complex
way on those deposition parameters that determine the flux and energy of
the reflected atoms which are incident on the substrate.
Figure 57 shows the influence of the argon working gas pressure on
the interface force per unit width (integrated stress) that developed in 200
nm thick coatings of several materials deposited at normal incidence on
near-room-temperature substrates using cylindrical magnetron sources.
This general behavior has been observed for more than ten metals ranging
in mass from AI to W306 and for amorphous Si.7 7 It has also been observed
for coatings deposited using rectangu lar planar magnetrons 31 0and small
gun and ring type planar magnetrons.311-314

CYLINDRICAL POST MAGNETRONS

NORMAL ANGLE OF INCIDENCE
ARGON WORKING GAS j:
i7 .
200 COATING THICKNESS -- 200 nm
DEPOSITION RATE"" 1 nm/s A
z

E
o
en
~ 1M.
/\
~ I- 100
:r:: /
l-
e NICKEL ~ /'
~
t::
z
o ~~~:~~~/e- -----i---------
::>
a:::
w
a..
/ / I
w
U Z 100
CHROMIUM ......._ -'
/ A I
J
~ 0
u.. en
en
(MASS_52)~
w
a:::
c.. e_ / I
~
U
200
- - :
STAINLESS STEEL
MOLYBDENUM
(MASS-96)
II

.- -.-- --.---------
(MASS"" 56)

300 I £
- .......
4~
400 .... ........................._ ............._ - . . _............. ..........._ ............_ ......--.....
0.2 0.4 0.6 0.8 1.0 2 4 6 8 10 20 40

PRESSURE (mTorr) .

Figure 57: Force per unit width at coating/substrate interface as a function of

argon pressure for metal I ic coatings of various atom ic mass wh ich were deposited
using cyl indrical-post magnetron sputtering sources. Data from References 306
to 309.
434 Semiconductor Materials

It is believed that the transitions from compressive to tensile stress

shown in Figure 57 can be explained in terms of acompetition between the
bombarding effects of the reflected atoms and those factors that tend to
promote an open Zone 1 structure. The flux and energy of the reflected
atoms increase with the atomic mass of the target relative to that of the
working gas.7 8 Increasing the argon working gas pressure at a fixed
discharge current causes a reduction in discharge voltage and therefore
in the energy of the neutralized and reflected ions. An increase in Ar
pressure also leads to gas phase collisions which both attenuate the
energy of the reflected species that reach the substrate, and scatter the
sputtered atom flux so that the coating atoms approach the substrate at
oblique angles. The latter effect promotes the formation of a Zone 1
structure as discussed in Section 6.2. The energy attenuation of the
reflected species reduces the effectiveness of these atoms in suppressing
the formation of a low density Zone 1 structure. Figure 58 shows the
influence of the average coating flux angle-of-incidence, measured from

1.0
z STAINLESS STEEL
~ CHROMIUM ,........ (MASS-56)
N z (MASS-52) ~,'...... .. \
E ~ 0.5 I...... /~.
zQ. . ' "'e,
I '

~ lo------~l--------i--~=~~~--
w
~ , •
~"""I fY
.--.-;....
~, •

/Y
<t I
ffi> en~-0.5 .._ , I ~
~
I TANTALUM
« ~ __/ /' (MASS-181)

8 -1.0 MOLYBDENUM.'
(MASS-96) ............... .'
I /'Y
I -'Y
-1.5 J
I

.------. I

CYLINDRICAL-POST
MAGNETRONS
-2.0
Ar PRESSURE = 0.13 Pa

0° 300 600 90°

NORMAL ANGLE OF INCIDENCE GRAZING

Figure 58: Coating stress as a function of the coating flux angle-of-incidence for
coatings of various atomic mass which were deposited using cylindrical-post
magnetron sputtering sources. Data from Reference 315.
 Physical Vapor Deposition 435

the substrate normal, on the internal stresses in 200 nm thick coatings of

the materials shown in Figure 57. The coatings were deposited onto near-
room-temperature substrates, using cylindrical-post magnetron sources
operated in Ar at 0.13 Pa (1 mTorr).315 Again, it is seen that the presence of
an oblique coating flux promotes an open structure and tensile stresses.
The oblique flux effect is suppressed, and compressive stresses are formed,
up to flux arrival angles which appear to depend on the target mass and
therefore on the flux and energy of the neutralized and reflective ions.
Figure 59 shows the transition pressure, belowwhich Mo coatings are
in a state of compressive stress, as a function of the deposition rate. Data
are given for coatings deposited using a planar magnetron of the type
shown in Figure 27H, and cylindrical magnetrons of the uniform plasma
type shown in Figure 27 A and the ring plasma type shown in Figure
27E.316,317In all cases the transition pressure exhibits a general increase
with deposition rate. The cause is believed to be associated with the
discharge voltage, and therefore with the energy of the energetic working
gas atoms which originate at the target as neutralized and reflected ions.
The transition pressure is seen in Figure 60 to be a very sensitive function
of the discharge voltage.
Figure 61 shows the transition pressure as a function of the target-to-
working-gas mass ratio. The data appear to su pport the proposition, stated
above, that large mass ratios produce large energy fluxes of reflected
species and thereby delay the trend toward forming a low density Zone 1
structure at higher pressure, or larger oblique angles, Figure 58.
It wi II be noted in Figu res 59 and 61 that the transition to tensile stress
occurs at lower working gas pressures for planar than for cylindrical-post
magnetrons. This is believed to occur because the reflected atoms leave
the target surface at different angles than do the sputtered species.

Molybdenum Targets Cylindrical Magnetron

Ref. 267 .~~~.
Cylindrical Magnetron ~~~~~/.
1.0 Ref. 266 ""~",, ~.

.
ro
~"".~
0..
\.
'\.. ..~
....~:::::-- ~
......... ~. Planar Magnetron
~ Ref. 267
•

Deposition Rate (nm/s)

EFFECT OF DEPOSITION RATE

Figure 59: Argon transition pressure, below which sputtered molybdenum coat-
ings deposited with cyl indrical-post and planar magnetron sputtering sources are
in a state of compressive stress, as a function of the deposition rate.
436 Semiconductor Materials

Molybdenum Targets
t Reduced B-Field

ro 1.0
~
I t
Q)

~ 0.6
~
a..
I
I
1-----t
'--~
o
c • 1--~
:~c 0.3
co
;: •
I Cylindrical
Magnetron

I
Planar
Magnetron

0.1- .J.. -"-~~_~

100 300 600 1000

Discharge Voltage (V)
EFFECT OF DISCHARGE VOLTAGE

Figure 60: Variation of transition pressure with discharge voltage for cylindrical
and planar magnetron cases. The open circle data points refer to cyl indrical mag-
netron cases where the magnetic field was decreased in order to increase the dis-
charge voltage from initial operating conditions near the transition value, as indi-
cated by the dashed Iines. The arrows indicate that resultant coatings were all in
high compression, signaling that the transition pressures were significantly higher
than the pressures (indicated in the figure) under which the experiments were
conducted. Data from Reference 317.

Reflection at angles less than 180°, i.e., small angle scattering, is most
probable. Substrates placed directly in front of a planar magnetron will be
bombarded only by atoms reflected at approximately 180°, while atoms
which are scattered at smaller angles and possess larger energies will
pass off to the side. The symmetry of the cylindrical-post magnetron case
causes the substrates to be bombarded by the atoms that undergo small
angle reflections. Therefore, it is believed that the substrates in cylindrical-
post magnetrons are subject to bombardment by a larger energy flux of
reflected atoms. 153 Support for this point of view has been provided by
experiments in which special shield configurations were used to isolate
the particle flux which left cylindrical-post magnetron sources at oblique
angles, from the fl ux wh ich left at more normal angles,?7,78,309 Coatings that
were deposited in the presence of the oblique flux exh ibited larger com pres-
sive stresses, and contained more entrapped working gas, than coatings
grown in the presence of only the normal flux.
It was noted in Section 5.2 that the energetic reflected working gas
species can become entrapped in sputtered coatings deposited at low
pressures. The amount of entrapped working gas exhibits the same general
trend as the stress data, increasing with the target-to-working-gas mass
ratio as shown in Figure 21, and decreasing with increased pressure.
 Physical Vapor Deposition 437

10~ """""'''''''''''''''''''''~'''''''''''''''''''''''''''''''''''''''''''''
FILM STRESS TRANSITION PRESSURE
AR SPUTTERING UNLESS NOTED

4
/'"
CYLINDRICAL - POST T a . Pt
2 MAGNETRONS
,., @~
.....
"\. '" '" '" '"/ ' (a ~.c:. MoINe
ORh , . " QGd
Nb ,.,'"
o ,.,'"
Z~O@Mo
c;- V .,,'"
~
w 0.4 Ti °O~}""''''
.
a: Cr/Kr AI ........ O ....OSS
::J RECTANGULAR
~ ~9~ @Cr -Mo
..... ." .... Mo/Xe PLANAR MAGNETRONS
~ 0.2 TENSION
~
"
0.1
t
t
COMPRESSION

0.04 .Cr

/
0.02

0.01 ~ ...
o 2 3 4 5
MASS RATIO (Mt/M g )

Figure 61: Argon transition pressure, below which sputtered coatings deposited
with cyl indrical-post and planar magnetron sputtering sources are in a state of
compressive stress, as a function of the target-to-working-gas atomic mass ratio.
Data from References 306 to 310.

However, the compressive strains within the coatings remained invariant

over large changes in the amount of entrapped working gas. Therefore, it
has been concluded that the entrapped gas is a consequence of the atomic
peening produced by the reflected species, but not the cause of the
compressive stress, at least for metal coatings deposited using magne-
tron sources. 309
The above experiments illustrate three important points: (1) the forma-
tion of coatings with compressive stresses and entrapped working gas is a
common occurrence in sputter deposition at low pressures where the
neutralized and reflected ions do not lose theirenergyvia collisions in their
passage to the substrates; (2) the angular dependence of the reflected ion
flux emitted from the target makes the substrate bombardment dependent
on the shape of the target 309 and the positioning of the substrates relative
to source; 103,300 and (3) the dependence of the stress-producing mechan ism
438 Semiconductor Materials

on the energy of the incident particles makes the tendency to produce

compressive stresses a strong function of the discharge voltage. Of
course, these effects lose their significance for coatings deposited at high
T/T m ·

7. METALLIZATION OF SEMICONDUCTOR DEVICES

7.1 Introduction
The metallization of semiconductor devices is one of the primary
applications of physical vapor deposition. Metallization fortypical devices
mu"~ provide (1) metal to silicon contacts, (2) gate contacts, (3) interconnects
between various points on the chip, and (4) compatible bonding pads for
packaging and assembly operations. Aluminum is the most widely used
metallization material. It can be used to form low resistance ohmic contacts
to highly doped p± and n±-type Si and also to meet the interconnect
requirements in both bipolar and MOS integrated circuits.
In early circuit manufacture much of the AI was deposited by evaporation.
The present trend is toward usi ng AI-Cu-Si alloys contai ning typically 2 to 4
wt.%Cu and 1 to 2 wt.%Si. The Cu improves the electromigration resistance
and the Si improves the stability of the AI/Si interface. Therefore, sputtering
is coming into increased use because of its capabilities for reliably depositing
such multicomponent materials with controlled stoichiometry.
The more exacting requirements of VLSI will necessitate new metalli-
zation systems that permit shallower junctions, reduced contact resistances,
the use of dry etching processes, and multilevel interconnection schemes.
These requirements will necessitate the increased use of refractor metals
and their silicides, i.e., materials that can be deposited effectively by
sputtering. Therefore, the trend toward sputtering, which has resulted in its
use for perhaps 95% of the new wafer fabrication lines started in the past
few years,318 is expected to continue.
The reader is referred to References 319 to 323 for more detailed
discussions of the metallization of semiconductor devices. An excellent
multi-volume bibliography on metallization materials and techniques for
silicon devices has been prepared by J.L. Vossen of the RCA Laboratories
and is available from the American Vacuum Society.324

7.2 Metallization Materials Considerations

Ohmic contacts of AI on Si are generally formed by depositing the AI
onto the Si, and then annealing at a temperature in the 450 to 525°C range
for 15 to 30 minutes in N 2 or H 2, to consume the native oxide on the Si and
form an AI/Si alloy at the junction. 27o The solid solubility of Si in AI at the
annealing temperature is about 1 at.%. Therefore, Si diffuses into the AI,
leaving pits in the Si which are filled by AI to form spikes which can penetrate
deep enough to short shallow p-n junctions. One solution is to add Si to the
AI metallization material to form an alloy with reduced solubility for externally
supplied Si. This suppresses the spiking problem. However, another prob-
lem is introduced. During cooling to room temperature the AI becomes
supersaturated with Si. The Si can precipitate at the junction and result in
 Physical Vapor Deposition 439

the formation of a layer of p-type AI-doped Si. This leads to erratic barrier
heights on Schottky diodes and non-ohmic contacts on n-type substrates.
An alternative solution is to deposit a silicide film, such as PtSi or Pd2Si,
between the AI and Si to stabilize the junction. 325 Unfortunately, AI reacts
with such silicides at 400°C and is able to penetrate through the silicide
and reach the Si to repeat the spiking problem. 322 Therefore, a diffusion
barrier is needed in addition to the silicide. Examples are Cr322 and Ti-W.320
The general application of such barrier layers is reviewed in Reference
326.
Silicide layers such as PtSi can be formed by evaporating orsputtering
Pt films onto the Si and annealing at 400-600°C to cause the silicide
reaction. However, when shallow contacts are desired the Si is added
externally. This can be done by depositing Si- Pt bi-Iayers by evaporation or
sputtering, and then an neali ng them to cause silicide formation. In another
approach homogeneous layers can be formed directly, by co-evaporating or
co-sputtering from Pt and Si sources, or sputtering from a Pt-Si target, and
then annealing to form the desireq silicide.
Polycrystalline Si, deposited by chemical vapor deposition, has been
the primary interconnect material used at the gate level. However, the
resistivity of polysilicon is too high for the cross sectional areas that are
available in VLSI circuits with their shrinking line widths. Consequently,
excessive RC time constants and losses in circuit speed result. 319 Refrac-
tory metal-silicides, such as TiSi 2, MoSi 2, TaSi 2, and WSi 2, offer low resistiv-
ities, low contact resistances to Si, stability against oxidation in contact
with Si0 2, and stability against reactions with AI and AI alloys. Accordingly,
these materials are being investigated as gate metallization layers.
It is projected that the shrinking lateral features ofVLSI will require the
use of anisotropic plasma etching methods such as ion beam or reactive
ion etching. 319 Such etching processes tend to produce radiation damage
that cannot be annealed out at temperatures compatible with AI metalli-
zation (see Section 7.4). A possible solution is to form contacts using
refractory materials capable of withstanding annealing temperatures in
the 600°C range. Promising candidates are again the refractory metals
such as Ti, Mo, Ta, and Wand their silicides. Since the refractory metals
and silicides do not meet requirements for wire bonding to the chips, it is
envisioned that the uppermost layer would again be a material such as
AI. In some cases a diffusion barrier such as Ti N may be requ ired between
the refractory base layer and the aluminum top layer. 326
Refractory metals are also used on some conventional devices to
eliminate the corrosion problems associated with AI.
As noted previously, Cu is added to AI to improve the electromigration
resistance. The Cu apparently improves the electromigration resistance
by segregating in the grain boundaries. 327 The composition, resistivity, and
microstructure of these films depends strongly on the deposition technique
and affects the reliability of their performance as contacts and inter-
connections. 328 It has been argued that the larger grains produced by
electron beam evaporation yield greater electromigration resistance,329
particularly for the small line widths used in VLSI.330 However, others have
argued that electron beam evaporation is not well suited to controlling the
440 Semiconductor Materials

composition and microstructure, and that stable homogenous small grain

size films of a type easily produced by sputtering are required to fabricate
reliable VLSI interconnections. 328 ,331
Multilevel metallization interconnections will be used in VLSI to improve
circuit performance by minimizing signal paths and enhancing the utilization
of chip area. These consist of two or more metallization layers separated
by suitable dielectric layers. The principal candidates for interlevel dielec-
trics are oxide films such as Si0 2 and AI 2 0 3 prepared by low pressure or
plasma-assisted CVD. A typical VLSI multilevel system is

PtSi/Ti-W/AI-Cu/Si0 2/ AI (21 )

where PtSi forms the ohmic and Schottky contacts, Ti-W acts as a
diffusion barrier, AI-Cu provides the first-level metallization, Si0 2 serves
as the interlevel insulator, and AI serves as the second level interconnection.
It has been suggested that second-level metallization layers will be depos-
ited primarily by bias sputtering to provide step coverage, as discussed in
the next section. 319

7.3 Step Coverage

Step coverage is a critical consideration for most device metallization
applications. The basic problem is the geometric-shadowing and angle-of-
incidence effects on coating growth and microstructure that were discussed
in Section 6.2. Thus when coating a step, even deposition conditions
produce a dense Zone T structure on a flat surface, yield a porous Zone 1
structure on the step side walls, and an open boundary or cusp emanating
from the base of the step as a result of self-shadowing. See Figures 62 and
64a.
The techniques used to improve step coverage can be classified into
the following broad categories: (1) source geometry adjustments, (2) step

COATING FLUX

DENSE ZONE T
STRUCTURE
\ I \\I \ I \ ,

•
SUBSTRATE STEP
~'

Figure 62: The effect of substrate surface steps on the microstructure of coatings
deposited at low TIT m .
 Physical Vapor Deposition 441

geometry shape adjustments, (3) substrate temperature control, and (4)

bias sputtering.
Source geometry considerations are based on the fact that coating
atoms approach a substrate surface in directions that are dependent on
the geometric configuration of the deposition apparatus. In the case of
evaporation, the atoms pass essentially line-of-sight from the source to the
substrates. Even in the case of sputtering at elevated pressures, the atoms
approach the substrate line-of-sightfrom the point of last collision, which is
nominally one mean free path from the substrate. See Equation 6. A typical
mean free path at 50 mTorr is of the order of 1 mm and therefore much
largerthan the step sizes. Thus the apparatus geometry in the case of high
pressure sputtering can be approximated as an extended source, with
cosine emission, located one mean free path from the substrate. Since the
coating atom mean free paths are long compared to local variations in the
substrate topography, these variations can affect the coating distribution
and structure by shadowing.
Small source systems, such as electron beam orfilament evaporators,
or small ring type magnetrons of the planar or gun-type, are generally
configured to use wafer motion to provide increased throughput capacity
and thickness uniformity, as discussed in Section 3.4. Often planetary
tooling of the type shown in Figure 9 is used. As the ratio of the translation
or rotation velocity to the deposition rate increases, the effect of the
motion approximates an extended-target sputtering system,332 and thick-
ness uniformity on the top surface improves. However, the extreme oblique
component in coating flux that is produced by an extended source or by
planetary motion can actually exacerbate the open self-shadow boundary
or cusp that emanates from the base of the step.332 That is, the tooling that
provides the most uniform coating over a flat wafer may not provide the
best step coverage. 333
Large source magnetron systems are of increasing interest because
of their capacity for large production volumes and their compatibility with
in-line processing systems. See Section 5.6. In a recent study, measured
erosion rates from a rectangular planar magnetron were used with computer
modeling to stimulate step coverage for substrates that were rotated on a
single axis aligned with the long axis of the magnetron. 334 The deep cracks
at the base of the steps, that are typical of small sources with planetary
tooling, were not predicted. The reason was traced to the shape of the
vapor emission profile from the magnetron source. Measured step cover-
ages, for AI-2 wt.% Cu sputtered at a pressure (1.5 mTorr) that yielded line-
of-sight transport, were in good quantitative agreement with the calculated
deposition profiles. More modeling studies of this type can be expected in
the future as the step coverage capabilities of large area magnetron
sources are explored.
Step geometry shape control is one of the most effective methods for
reducing the geometric shadowing problems associated with step coverage.
For example, a step slope of 30° from the normal, and suitable substrate
motion, can eliminate cusp formation because of shadowing. 332 Unfor-
tunately, the shrinking lateral size features in VLSI will leave no space
available to taper steps.319
442 Semiconductor Materials

Increased substrate temperature increases the adatom surface diffu-

sion which tends to negate the effects of self-shadowing, as discussed
in Section 6.2. Thus, Zone 2 structures, in which surface diffusion dominates
over shadowing, can be produced on smooth substrates at TIT m ~ 0.5.
However, for the more extreme case of overcoming the shadow bou ndaries
induced by substrate steps, TIT m ~ 0.6 is recommended. 332 This corresponds
to a temperature of about 300°C for aluminum.
The combination of planetary or other substrate motion, tapered
steps, and substrate heating has proven adequate for providing acceptable
aluminum metallization on most conventional devices. However, as noted
above, tapered steps cannot be used for VLSI. In addition, it is projected
that VLSI metallization will require refractory metallayers. 319 See Section
7.2. The condition TIT m ~ 0.6 cannot be satisfied for refractory metals. For
example, the melting point ofWis341 0°C(3683°K). TIT m = 0.6 corresponds
to a temperature of 2209°K or 1936°C, which is above the melting point of
Si (141 O°C). See Table 10. Thus it is anticipated that bias sputtering will be
required to provide step coverage on VLSI devices. 319
In the bias sputtering method, improvements in surface coverage are
achieved by resputtering material previously deposited. 335 ,336 Thus some
of the material deposited at the bottom of a step is resputtered at small
angles and redeposited on the side walls of the step, as shown schematically
in Figure 63a. The process can also be enhanced by the "forward sputtering"
produced by ions striking at an oblique incidence relative to the surface of
the step, as shown in Figure 63b. The bias voltage and current must be
selected to provide a proper balance between the deposition and resput-
tering processes. Figure 64, drawn from SEM micrographs,336 shows the
effect of bias voltage in contouring Si02 films at a step. At -60V the bias has
successfully eliminated crevice formation from the base of the step. The
sputtering rate is greater at oblique ion incidence, as discussed in Section
5.4. Thus at a bias of -120V, the fast erosion of the angularsurface overthe
step is clearly apparent. Recent experiments have demonstrated that

ARGON IONS

DEPOSITED SPUTTER-ERODED
SPUTTER-ERODED
COATING SURFACE MOVES
SURFACE MOVES
TO RIGHT
TO LEFT
a b
Figure 63: Schematic drawing showing effect of ion bombardment, due to sub-
strate bias, on coating th ickness distribution over substrate step.
 Physical Vapor Deposition 443

COATING

BIAS VOLTAGE = 0
SUBSTRATE~~. 1
STEP
BIAS VOLTAGE = -60V

8 b

BIAS VOLTAGE = -90V BIAS VOLTAGE = -12QV

c d
Figure 64: Drawing, based on SEM micrographs from Reference 336, which
shows the effect of substrate bias on the thickness distribution of sputtered Si0 2
over a substrate step.

excellent step coverage of Si0 2 over straight edge profiles can be obtained
with a combination of rf sputtering from a planar magnetron source and an
rf bias applied to the substrates. 337 ,338 Furthermore, it has now been shown
that proper programming of the deposition and re-sputtering will permit
surface insulator layers to be leveled in anticipation of subsequent layers
of metallization.339-34oa
It is important to note that the use of bias sputtering can eliminate
porosity and improve the coating microstructures, as well as improve the
step coverage. See Section 6.4. However, it should also be remembered
that bias sputtering of a multi-component material can cause composition
changes because of preferential sputtering.

7.4 Radiation Damage

Electrically active defects can be produced in semiconductor surfaces
by(1) ion or other heavy particle bombardment, (2) electron bombardment,
and (3) x-ray and ultraviolet radiation. All three of these elements are
present in conventional planar diode sputtering sources, and numerous
examples of anomalous junction behavior have been reported for sensitive
semiconductor interfaces formed using sputter-related technologies. 341 -
344 The significance of the defects depends on the nature of the electronic
device. MOS devices are particularly sensitive to such defects, and the
fabrication of MOS capacitors has been one of the primary methods for
evaluating the tendency of various processes for producing radiation
damage.
444 Semiconductor Materials

Filament- and induction-heated evaporation sources (see Figure 6)

have the advantage that they produce none of the radiation effects cited
above, but the disadvantage that the controlled deposition of refractory
metals and stoichiometric alloys such asAI-Si-Cu is difficult. Therefore, the
use of these sources for device production has become limited. However,
they are effective for fabricating test devices that can serve as comparative
references in judging the damage produced by other deposition methods.
In the case of electron beam evaporation, reflected electrons can
cause device damage. Thus, it is reported that electron beam evaporation
of metal layers in the fabrication of MOS capacitors introduced defects
in Si0 2 that yielded threshold voltage instabilities which could not always
be removed byannealing. 345
Substrate bombardment by electrons and ions should be largely
eliminated in properly designed dcdriven magnetrons. There maybesome
bombardment by reflected and neutralized ions, particularly with cylindrical-
post magnetrons. However, detailed evaluations of this mechanism as a
source of device damage have not been reported. Studies of radiation
damage to MOS capacitors metallized using gun-type magnetrons (Fig.
271) have shown that trappi ng levels are created that can not be completely
annealed out at temperatures up to 500°C.346,347 The cause was concluded
to be uv radiation. Photons with energies that are greater than the Si0 2
band gap C::::::8 eV), and therefore that can produce radiation damage, are
emitted by the plasma. The damage could be eliminated by precoating the
wafers with a 300A thick layer of evaporated AI using an induction heated
source. Because of the strong attenuation of uv photons in such layers, it
has been concluded that this radiation should not present a problem in
many device metallization appl ications. 346 In fact, it has been reported that
post-metallization annealing to remove damage was not required for MOS
structures that were metallized in magnetron systems at substrate temper-
atures of about 300°C.348 A recent study reports damage introduced during
dc magnetron sputter deposition of Ti-W onto n-Si. 348a
The primary occurrence of heavy damage is during sputter cleaning
and dry etching processes such as reactive ion etching. Defects created in
the Si surface layer during ion beam etching can arise from three sources:
(1) radiation damage arising from the impact of the ions in the beam, (2)
implantation of the ions in the beam, and (3) implantation of impurities in
the beam. 349 Impurities are a particular problem because they cannot be
removed by annealing. A study of damage induced in Si by Ar ion milling
and reactive ion etching indicates that the interface states are strongly
dependent on the bombarding ion energy and the etching gas. 350 Recent
studies have identified a trivalently bonded Si defect as the probable
source of interface states at the Si0 2 /Si interface of MOS capacitor
structures fabricated on ion beam etched and reactive ion etched Si. 351
Clearly this is a contemporary area of research. However, as noted in
Section 7.2, it is generally agreed that VLSI circuit fabrication using dry
etching methods will require annealing, and that the temperatures will be
in the 600°C range, or perhaps higher.
 Physical Vapor Deposition 445

REFERENCES
1. R. Giang, R.A. Holmwood, and J.R. Kurtz in Handbook of Thin Film Technology,
L.1. Maissel and R. Giang ed., McGraw-Hili, NewYork(1970) pp. 2-1 to 2-142.
2. J.F. O'Hanlon,A User's Guide to Vacuum Technology, Wiley, NewYork(1980).
3. G.L. Weissler and R.W. Carlson, editors, Vacuum Physics and Technology- Vol.
14, Methods of Experimental Physics, Academic Press, New York (1979).
4. J.F. O'Hanlon, J. Vac. Sci. Technol., A1:228 (1983).
5. W.M. Brubaker, in Vacuum Physics and Technology- Vol. 14, Methods of Experi-
mental Physics, G.L. Weissler and R.W. Carlson ed., Academic Press, New York
(1979) pp. 183 to 192.
6. J.A. Thornton, "Considerations Relating to Pumping Requirements for Sputter-
ing Metallic Coatings onto Plastic Substrates," Proceedings 20th Annual
Technical Conference of the Society of Vacuum Coaters, Atlanta, GA (April
1977) p. 5.
7. B.B. Dayton, in Handbook of Vacuum Physics, A.H. Beck ed., MacMillan, New
York (1964) p.3 to 32.
8. L. Holland, Vacuum Deposition of Thin Films, Chapman and Hall, London (1966).
9. R. Giang, in Handbook of Thin Film Technology, L.1. Maissel and R. Giang ed.,
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7
Diffusion and Ion Implantation in Silicon

Richard B. Fair
Microelectronics Center of North Carolina
Research Triangle Park, NC

INTRODUCTION

As it becomes necessary to achieve higher levels of integration in IC

manufacturing, so too does it become necessary to better understand the
interrelationships among processing steps. Knowledge of the mechanisms
involved in ion implantation and diffusion are basic to obtaining this
understanding.
The focus of this chapter is on impurity diffusion and ion implantation
in silicon. Because of the large solid solubility of Group III and V doping
impurities in silicon, diffusion proceeds by interactions with point defects
in the silicon-vacancies and silicon self-interstitials. Each high temperature
processing step has the potential for changing the number of vacancies
and self-interstitials, and therefore, the properties of impurity diffusion. We
can understand these effects at two levels-the atomic level and the
continuum level. Thus, discussion of diffusion from both points of reference
is provided.
The process of introducing impurities into silicon is called predeposition.
Chemical predeosition is described in terms of a solution to the diffusion
equation and also in terms of ion penetration into silicon, distributions of
implanted impurities, lattice damage, etc. Finally, useful curves for designing
implanted junctions with a single annealing step are provided to assist in
the selection of implant dose, energy and dopant.

455
456 Semiconductor Materials

CONTINUUM THEORY

According to the Continuum Theory of diffusion, matter will flow in a

mannerwhich will decrease all concentration gradients in an inhomogenous
single phase alloy undergoing annealing. The physics governing diffusion
are described in two equations. The first is Fick's First Law which states
that there will be a flux of atoms whenever a concentration gradient exists,
and that flux is related to a constant that is a fundamental material
property. In one dimension Fick's First Law becomes 1

de
J =-D- (1)
x dx

As an example, Figure 1 shows a plot of the concentration of an impurity

distributed in a host lattice as a function of x-the depth into the material.
From Equation 1 the flux of this impurity during diffusion is related to the
concentration gradient. Figure 1b shows the flux calculated at 2 points-x 1
and x 2 . From Figure 1c, if LlX is small,

The net increase in matter in the volume is

Differentiating Equation 1 and substituting into Equation 3 gives Fick's

Second Law:

(JC iJ
-;- = iJx
I0;-acj
For the special case where D is constant and the surface concentration of
the impurity that is diffusing is fixed, then Equation 5 results:

a2c
D-=-
ac
(5)
ax2 at

Fick's Second Law is a continuity equation which describes the time rate of
change of the impurity concentration. The diffusion constant D is in units of
cm 2/sec. and the concentration C is usually in units of atoms/cm 3 .

Special Cases
Predeposition. Under the special case where D is constant, the surface
concentration of the diffusing impurity is fixed, the concentration of the
impurity at x= is C( ,t)=O for all time, and the concentration at any point
00 00

in the crystal at t=O is C(x,O)=O, then underthese conditions the solution to

Equation 5 is given as: 2
 Diffusion and Ion Implantation 457

(a)
c

(b)

---~--
I
I
I
J

(c)

1- -I Ax

Figure 1: (a) Plot of an assumed concentration as a function of depth, (b) the

flux J(x) for this plot and (c) the element of volume with the flux J 1 entering
and J 2 leaving.
458 Semiconductor Materials

C (x,t) = Co erfc 12~ 1·

If C( 00 ,t) = C B and C(x,O) = C B, then

C (x,t) = Co erfc !2~ 1:t CB,

where C B is the background doping concentration in the semiconductor.
Thus, for the boundary conditions described above the impurity concen-
tration as a function of space and time is given by a complementary error
function whose argu ment is x/y4[)t The complementary error fu nction is a
tabulated function and is described in Equations 8 and 9. A plot of the
complementary error function if given in Figure 2. If we form the inverse
complementary error function of Equation 6 and set the concentration
equal to the background concentration in the host lattice we can solve for
the depth of ajunction with that background concentration. This is given by
Equation 10.

10- 4 L.--...L...-.....I----J.....---L-----II..-...L-....l---Io---L.----I-L-~------
o 1.0 2.0
xf.J4Bt
Figure 2: Normalized Gaussian and complementary error function curves.
 Diffusion and Ion Implantation 459

erfc y =1 - erf y (8)

(10)

Example: forC o=5x1 0 18 cm- 3 and diffusion of arsenic in silicon at 1200°C,

what diffusion time is necessary for the arsenic concentration to decrease
by a factor of 1000 in 5x1 0- 5 cm (0.5 microns)?

a) C (x,t) = Co erfc (x/{JJDi )

C (XJl t ) -3
b) - - - = 10 ; x/2JDi = 2.32 (from Fig. 2)
Co
2
c) t =-Xj- : D = 2.2xl0-13 em 2/sec; t = 528.4 sec.
21.5D

Figure 3 shows the complementary error functions plotted as a function of

time on linear and semilogarithmic scales. It can be seen that the junction
depth increases as the Vt when the surface concentration is equal to a
constant value.
Diffusion processes that are performed with a constant surface concen-
tration are normally referred to as predeposition steps. Predepositions are
usually done in N 2 furnace ambients with a small percentage of 02' and the
doping species is introduced into the furnace in gaseous form. The dopant
concentration in the gas N 2 stream is varied to change the su rface concen-
tration in the silicon. Typical predeposition temperatures are in the 900-
1000°C range, and times are usually 30-60 minutes. There are a wide
variety of sources of dopants including liquids, solids and gases.
For the predeposition of boron the most prevalent species in the gas
phase in the furnace is 8 2°3. Once the 8 2°3 is deposited on the silicon
surface there is a reaction of this oxide with the silicon to produce doping.
This is shown as Equation 11.

(11)

The production of 8 2 °3 may come from either one of the reactions described
in Equations 12 or 13,

(12)

(13)

The source of the boron nitride in Equation 13 may be in the form of disks
460 Semiconductor Materials

1.0

0.8

0.6
0
~
u

0.2

x (p)

10- 1

10- 2
0
~
U

10- 3

Figure 3: The complementary error function (erfc): normal ized concentration

vs. distance for successive times.

about the size of a silicon wafer which are placed next to the wafers in the
diffusion furnace.
By varying the partial pressure of the gas phase of the dopant in the
furnace, it is possible to change the concentration of impurities in the
silicon. Henry's Law relates the concentration of dopants that are introduced
in the furnace to the surface concentration:

(14)

Co - dopant surface concentration

H .. Henry's constant
P, - partial pressure of dopant gas

Figure 4 shows Henry's Law plotted. It can be seen that once the solid
solubility of boron in silicon is reached, Henry's Law no longer applies.
Thus, most predeposition steps operate with a high enough partial pressure
in the dopant gas phase that solid solubility of the dopant is achieved in the
silicon. This provides a natural control for reproducible diffusion results.
 Diffusion and Ion Implantation 461

Solid solubility of
- - -at....... --------......--
Bin Si °c
1100 ./ ""
~- --
/
/
/
/
2
/
/
/
o
o /
Line corresponds to Henry's law,
with H E! 2 X 1()25 atm/cm3

0.5 1 1.5
Ps (Torr)

Figure 4: Surface concentrations of boron in silicon as a function of the partial

pressure of 8 2 0 3 in the ambient at 1100°C.

For the predeposition of phosphorus the predominate species in the

gas phase is P205' The doping reaction with P205 is shown in Equation 15:

(IS)

Sources of P2 0 5 vapor are solid P2 0 5 , red phosphorus, POCI 3 , PBr3 ,

NH 4 H 2 P0 4 or PN.
For the predeposition step the goal is to deposit some number of
atoms/cm 2 in the silicon substrate, Q(t). The way in which that number is
calculated is to integrate the total concentration percubic centimeterfrom
o to as shown in Equation 16.
00

Q (t) = f C (x,t) dx
o

00

=Co J erfc (x/2..fDt) dx

o

(16)

Once the predeposition is completed with Q atoms/cm 2 the next step is to

redistribute the atoms to g-ive the desired junction depth.
Redistribution or Drive-in. If Q atoms/cm 2 are deposited on the
semiconductor surface with the following boundary conditions: 2
462 Semiconductor Materials

C (~,t=O) = QB(x)
C (CO,t) = 0

then the distribution of impurities after diffusion for a time t is given by a

Gaussian function solution to Equation 5:

C (xtt) = -Q- exp -

J;f5t 4Dt
l-x j2
. (17)

This distribution is shown plotted in Figure 2 on normalized axes. The

Gaussian distribution can be used to describe the impurity profile that
results from a drive-in with no dopant gas in the furnace. The drive-in
step is performed in several types of ambients: dry oxygen, steam, nitrogen
or argon. The drive-in temperatures range from 900-1 200°C.
Example: arsenic was prede~osited and the resulting Q equals 1x1 0 14
cm 2 . How long would it take to drive-in the arsenic to a junction depth of
1x1 0- 4 cm (one micron) in a background doping of 1x1 0 15 cm- 3 ? T =
1200°C.

- exp 1-(10- )2]

14 4
lxl0
C (X,t) = 1xl0IS = -
J;Dt 4Dt

The solution to the equation above must be graphed and is shown where
the left-hand-side of the equation intersects the righthand side of the
equation in Figure 5. Note that if x = 0, the surface concentration Co
decreases as 1/Vt as shown in Equation 18. The junction depth can be
found by taking the log of both sides of Equation 17:

C (t) = _Q-
o J;f5t (18)

(19)

Normalized Gaussian concentration profiles versus distance are shown in

Figure 6 for successive times both on linear and semilogarithmic scales.
Under certain conditions the Gaussian solution to the Second Law
can be used in conjunction with short predeposition steps provided that
the following condition applies:

112
Dt (drive-in) I > 4
I Dt (l'redep)
Otherwise, a more complex solution is necessary, and under these condi-
tions the solution is
2Co J.L exp (-Bel + p.2))
C (x,t) =- J 2 du
(20)
1T 0 1+j.L
 Diffusion and Ion Implantation 463

exp (-- Xf /4Dt)

10- 3
-;;
0
~
N._
)(

~
Q.
)(
cu
0

~..
0
10- 4

t (sec)

Figure 5: Graphed solution to the equation cited in the example in the text.

where

1/2 2
Dt (predep) 1
IJ.=
1Dt (drive-in)
B _I :x 1
2 [01 (predep)+ Dt (drive-in)]l12

The decision as to when the Gaussian solution is appropriate can be

determined by plotting Equation 20 for various ratios of the product vm
for the predeposition and diffusion. These results are shown in Figure 7.

Diffusion Coefficients
Diffusion coefficients are based upon the atom ic behavior of the atom
in a host lattice. Diffusion coefficients obey an analytical form as described
in Equation 21.
464 Semiconductor Materials

1 x 105

0.8

I 0.6
E
~
0 0.4
U
0.2

2 3
x (JJ)
105

104

103
'~E
~
0
U 102

10

o 2 3
x (J.L)

Figure 6: The Gaussian function: normalized concentration vs. distance for suc-
cessive times.

where Do is the prefactor (cm 2 /sec), EA is the activation energy in (eV), k is

the Boltzmann constant and T is the temperature CK). Typical diffusion
coefficients of Group III and V elements in silicon are shown in Table 1.
There is remarkable similarity between the diffusion coefficients of these
elements in silicon. The activation -energies for Group III and Group V
elements are in the 3.5 to 4 eV range. A discussion of the origin of these
energies and prefactors is provided in the next section.

Table 1: Diffusion Coefficients of Dopants in Silicon

Impurity P As Sb B Al Ga In

J)o 10.5 0.32 5.6 10.5 8 3.6 16.5

EA .1.69 3.56 3.95 3.69 3.4; 3.5 3.9

 Diffusion and Ion Implantation 465

1.0

0.8

2- 0.6
~c.
= 1.0
ur
........
u
0.4
Y!(Dt)Predep/(Dt)drive

0.2

0
0 2 3
x/2V(Dt)drive

Exact

~--""""'-Uncoupled
10- 3 ~_.&--......L----a._.a...--A----a... ..lto._......- ........._.a..-~

o 1 2 3
x/2 V (Dt)drive

Figure 7: Comparisons between exact and uncoupled solutions to the drive-in

diffusion equation for several values of Ot (drive-in)/Ot (predep).

ATOMIC THEORY OF DIFFUSION

Diffusion Mechanisms
The atomistic theory of diffusion is concerned with describing how an
atom gets from one part of a crystal to another. The lattice sites in a crystal
are generally taken as the fixed location of the atoms making upthe crystal.
It is known that the atoms oscillate around these lattice sites which are
their equilibrium positions. These oscillations lead to finite chances that
an atom will move from its lattice site to another position in the crystal.
There are several ways by which atoms can move from one site in the
crystal to another. These mechanisms are

• the vacancy mechanism

466 Semiconductor Materials

• the interstitial mechanism

• the interstitialcy mechanism

These mechanisms are illustrated in Figure 8.

00000 0000
00000 00~0
00-. 00 0000
00000 (b) The interstitial diffusion mechanism.
(a) The vacancy diffusion mechanism.

0000
OpOO
0000
(c) The interstitialcy mechanism.

Figure 8: Illustration of the dominant diffusion mechanisms in silicon.

Thermodynamic considerations require that some of the lattice sites

in the crystal are vacant and that the number of vacant lattice sites
generally is a function of temperature. When a lattice atom moves into an
adjacent vacant site, th is process is called the vacancy diffusion mechan ism.
In addition to occupying lattice sites, atoms can reside in the space
between the lattice sites. These interstitial atoms can readily move to
adjacent interstitial sites without displacing the lattice atoms. The interstitial
atoms may be impurity atoms or atoms of the host lattice, but in eithercase
they are generally present only in very dilute amounts. These atoms,
however, can be highly mobile and are the dominant diffusion species in
certain cases. A mechanism related to interstitial diffusion is the interstitialcy
mechanism. In this process an interstitial atom moves into a lattice site by
displacing the atom on that site onto an adjacent interstitial site. Although
several other diffusion mechanisms may exist in semiconductors, in silicon
the three dominant mechanisms are those just described.

The Flux Equation in Diffusivity

The number of atoms which cross a unit area in unit time is known as
the flux. In one dimension the atoms only move to the right or leftwhen they
 Diffusion and Ion Implantation 467

change position along the x axis indicated in Figure 9. The atoms in this
simple case are taken to be located in planes at X o and X o + a o as shown in
the figure. The flux J is simply the concentration C times the velocity v:

Jx =C v (22)

The net flux is the difference between the flux to the right and from the left:

1
Jx = - v
2
(c; -ex + a )
0 0 0 (23)

where Cx and Cx +a are the concentrations at x = Xo and X o + ao respective-

ly. A factor of 112 occ~ rs in Equation 23 because at anyone plane, half of the
atoms move in the +x direction and the other half moves in the -x direction.
When ao approaches 0,

and Equation 24 becomes:

1 de
J = --
x 2
vac -
dx
.

Figure 9: Flux in the x direction through the unit area in unit time. The planes
of the unit area are located at x == X o and x = X o + a o .
468 Semiconductor Materials

For motion by discrete jumps between planes a o apart, the velocity is the
number of jumps per second, f, times the distance a o of each jump.
Equation 25 may now be written as

1 2 de
Jx = - - ao r-.
2 dx

and the quantity (.!..; r) is called the diffusivity or diffusion coefficient 0:

2
1 2
D = - a r
2 0 (27)

Equation 27 shows that for diffusion by a particular mechanism, calculation

of the diffusivity is reduced to the calculation of the jump frequency f. The
jump frequency by the vacancy mechanism is

(28)

where w is the frequency at which an atom and an adjacent neighboring

vacancy exchange, and Xv is the probabil ity that the adjacent site is vacant.
From statistical thermodynamics the vacancy atom fraction is given by
Equation 29, where ~Sf is the entropy of formation of the vacancy and ~Hf
is the enthalpy of vacancy formation.

Xv = exp (~Sf/k) exp (-AHf/kT) (29)

These terms are related to the Gibbs free energy change for vacancy
formation through the equation

~Gf = AH f - TASf = -kT In Xv. (30)

It is far more difficult to derive the frequency, w, from fundamental

principles. Nevertheless a discussion of the physics involved in evaluation
w provides useful insights into the quantities that affect diffusion.
In self-diffusion by the vacancy mechanism a lattice atom moves from
a normal lattice site to a vacancy. As shown in Figure 10, the atom must
move from the normal lattice site in 1Oa to the saddle point position in 1Ob
to reach the vacancy at 1Oc. The energy at the saddle point is greater than
at the equilibrium lattice sites, and atoms must be sufficiently activated in
order to move to b and then c. The fraction of the lattice atoms activated to
the saddle point is related to the Gibbs free energy change between
positions 10a and 10b. In the same manner as for the atom fraction of
vacancies, the atom fraction of activated atoms is

(31)

where ~Sm and ~Hm are called the entropy and enthalpy of motion
respectively.
Now, the frequency, w, at which an atom and an adjacent neighboring
vacancy exchange can be written
 Diffusion and Ion Implantation 469

Activated atom

o ~OO-O
(a)
o (b)
0000 (c)

(a) (b)
(d)
Figure 10: The sequence of (a), (b), and (c) show the movement of the atom
from a normal lattice site to an adjacent vacancy. Part (d) shows the variation of
free-energy as the atom moves from (a) to (c).

(32)

where the frequency, Y, is generally nut known and is usually taken as the
lattice vibrational frequency of an atom about its equilibrium site, which is
of the order of 1 Q13/ sec -1. Now, from Equations 28,29 and 31 and 32 the
jump frequency for vacancy self-diffusion is

r = y exp !Cf.Sf + f.Sm)/k Iexp !-<f.Hr + f.Hm)/kT I· (33)

Experimentally it is found that diffusivity is given by the Arrhenius expression

where EA is the activation energy. Thus, the diffusivity is

1 2
D = ;- 80 l' exp [(A5r + ASm)/k] exp [-(AH r + ~Hm)/kT] • (35)

Comparisons of Equations 34 and 35 gives the prefactor Do as

Do = -1 2
~ y exp [(AS r + ~Sm)/k]
2
and
(37)
470 Semiconductor Materials

From the above discussion it can be seen that diffusivity is basically

the product of the lattice vibration frequency, vacancy concentration and
activated lattice concentration:

(38)

Also the activation energy for vacancy diffusion depends upon the energy
necessary to form the vacancy and to move the lattice atom into an
adjacent vacancy.

Multiple Charge State Vacancy Model

From the previous discussion it can be seen that the process of
diffusion depends upon the concentration of point defects in the crystal
such as vacancies or self-interstitials. Therefore, if one can find ways of
raising or lowering the point defect concentrations then one can effect
diffusion coefficients.
Forthe vacancy mechanism, the single vacancy in silicon is known to
exist in fou r charge states: V+, VX, V- and V=, where + refers to a donor level,
x a neutral species and - an acceptor level. 3 ,4 The creation of a vacancy
introduces a new lattice site, and thus four new valence band states in the
crystal. These states are available as acceptors but are not shallow. The
lattice distortion associated with the vacancy will split states from the
valence and conduction bands of the surrounding atoms a fewtenths of an
electron volt into the forbidden gap. States split from the valence band will
become donors and those from the conduction band will become acceptors.
At low temperatures there should be one deep donor level, V+, a fewtenths
of an eV above the valence band edge, a single acceptor level, V- near
midgap, and a double donor level v= very near the conduction band edge
(see Figure 11 ).5 The levels depicted in Figure 11 represent a best guess
based on experiment. 6 -8

1.2 Si AT O~K
CB
O.lleV =
1.0 TV 0.44eV
-
:>

-GJ
0.8
1 v-
>-
t.:)
Q: 0.6
u.J
Z
L.6.J
0.4

0.2
--L v+
V+ <0.05 eV OR v++~O.l6 eV
0 VB

Figure 11: Estimated vacancy energy levels in the silicon band-gap at OOK.
 Diffusion and Ion Implantation 471

It has been experimentally verified that both silicon self-diffusion and

the diffusion of Groups III and V impurities in silicon depend upon the
Fermi-level position. The initial assumption in thevacancydiffusion model
of self-diffusion is that an observed diffusivity arises from the simultaneous
movement of neutral and ionized vacancies. Each charge type vacancy
has a diffusivity whose value depends upon the charge state, and the
relative concentrations of vacancies depend upon the Fermi-level. 9 Calcu-
lated changes in relative concentrations of charge species versus Fermi-
level, Ef, are shown in Figure 12a at T=3000K and in Figure 12b at
T= 1400° K.5Whereas at lowtemperature VXwill bethe dominantspecies in
intrinsic silicon, at high temperatures both V+ and V- would be more
numerous. There is no value of Ef forwhich vx dominates. Another important
concept is that every time an ionized vacancy is formed the crystal must
return the neutral vacancy population back to equilibrium by generating
an additional vacancy. In this way, as the doping becomes more n-type or
more p-type, the total vacancy concentration wi II increase with the increasing
population of ionized vacancies. Since impurity and self-diffusion coeffi-
cients depend upon the concentration of vacancies, the diffusion coefficients
will also increase with doping. Such concentration-dependent diffusion
can occur when the doping level exceeds the intrinsic electron concen-
tration, n j at the diffusion temperature. An illustration of concentration
dependent diffusion is shown in Figure 13.

T=300 0K T=1400oK
6 6

4 4

2 2

,..,
......, 0
C
~

C)
0
-"" -2 -2

-4 -4

-6 -6

-8 -8 ~--'-----"""----'
o 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6
E V E F(eV) EC EV EF{eV) EC

(a) (b)
Figure 12: Calculated changes in the ratios of ionized to neutral vacancies at (a)
0 o
300 K and (b) 1400 K.
472 Semiconductor Materials

u
WJ
V)
.........
N
E
-e
H
u INTRINSIC ~
g DIFFUSION
~

EXTRINSIC
DIFFUSION

n·I
LOG(n) ELECTRONS/em 3
Figure 13: Donor impurity diffusion coefficient vs. electron concentration show-
ing regions of intrinsic and extrinsic diffusion.

THE ROLE OF POINT DEFECTS IN SILICON PROCESSING

The Silicon Processing Balancing Act

Silicon oxidation and diffusion of impurities are quite related since
they both occur at high temperatures and they both involve point defects
such as vacancies or self-interstitials. The first level of process design
involves the concept of doping and junction formation, threshold voltage
control, or the gain control of the transistor. Another goal of doping is to
achieve low sheet-resistance. For oxidation the primary goal is to grow
controlled layers of Si0 2 . Th ings of concern in oxidation include the growth
of stable oxides with electrical integrity, etc. If one is creating a non-planar
structure it is necessary to worry about the viscous flow characteristics of
the oxide and whether the viscosity is low enough to release stress. The
process engineer in general spends a lot of time dealing with these first
order requirements. However, the rest of the time is spent in trying to
balance things that are generally not well understood. The point defect
balancing act diagram is shown in Figure14. All of the arrows in the figure
indicate the directions of interactions. For example diffusion may change
the concentration of point defects, and point defects themselves can
affect diffusion. Oxidation produces point defects and point defects can
affect oxidation. The balancing act involves point defect generation and
the effect of this generation on these major processes. Diffusion may
introduce strain into the lattice which can affect surface quality. Oxidation
 Diffusion and Ion Implantation 473

Figure 14: The point defect balancing act in silicon processing.

can influence surface bonding which also affects surface quality. As these
processes produce point defects it is possible that extended structural
defects can grow in the silicon. Point defects can also influence the
precipitation of oxygen. Oxygen is incorporated into the crystal during
crystal growth, and precipitates during subsequent heat treatments. It is
known that these precipitates create good internal gettering sites for
metal impurities with subsequent impact on junction quality.

Point Defects
Point defects are defined as atomic defects. There are atomic defects
such as metal ions which can diffuse through the lattice as shown without
involving themselves with lattice atoms or vacancies. Another type of
atomic defect is the self-interstitial which in silicon is a silicon atom that is
bonded in a tetrahedral interstitial site. Examples of point defects are
shown in Figure 15.
One of the major controversies in solid state science currently is: what
is the dominant native point defect in silicon - the monovacancy or the
silicon self-intersitial? A brief review of the arguments for each species is
given below

The Monovacancy
From statistical thermodynam ics, it is known that if a vacancy is formed
by removing an atom from the crystal and depositing it on the surface, the
free energy of the crystal wi II decrease as the nu mber of vacancies created
increases until a minimum in this free energy occurs. Because a minimum
in the free energy occu rs for a certain vacancy concentration in the crystal,
the vacancy is a stable point defect. Other experimental observations
involving vacancies are listed below: 10

1. Electron paramagnetic resonance measurements only iden-

tify the existence of vacancies or vacancy complexes in Si
irradiated by electrons. The absense of Si self-interstitials
has been ascribed to rapid athermal migration even at
2°K.11
474 Semiconductor Materials

2. Diffusion phenomena as well as calculations of diffusion

entropy and enthalpy have been successfully explained by
ascribing multiple ionization levels to vacancies which are
the same as those observed for the vacancy in a low-
temperature irradiation experiment. 12 - 14
3. Theoretical esti mates of the heats of formation and entropies
of formation of vacancies correspond well with those of the
native defects observed in diffusion and quenching experi-
ments. 13,15-17
4. Channeling studies of impurity-defect interactions in Si
show that under helium ion bombardment the trapping
efficiency of impurities for radiation-produced defects is
very low near 30° K.17 Vacancies are not mobile in Si below
this temperature while interstitials still are. This implies that
the impurity-defect interactions involve vacancies.
5. Positron annihilation lifetime measurements which have
been performed on float-zone Si at high temperatures,
show that vacancy-like defects are formed. 18

Foreign interstitial atoms

Ca, Ni, Fe, Li, H

Self-interstitial I

Substitutional dopanu

B,AI, Ga P, As, Sb

p- n-type

Figure 15: Examples of point defects in the silicon lattice.

 Diffusion and Ion Implantation 475

The Silicon Self-Interstitial Atom

It is possible to perform a sim ilar consistent statistical thermodynam ic
analysis on the existence of self-interstitials and show that they are stable
point defects. Other arguments in support of the silicon self-interstitial are:

1. The great majority of dislocation loops and stacking faults

in Si observed by transmission electron microscopy are
judged to be of extrinsic or "interstitial" character. Though
there exist four proposed mechanisms by which extrinsic
type dislocations may be formed without any self-interstitials
being present, 10 most workers feel that self-interstitial pre-
cipitation is the dominant mechanism.
2. The picture of self-interstitials in Si developed by Seeger
and Frank 19 is consistent with observations indicating self-
interstitial migration at low and high temperatures.
3. Evidence for the liquid drop character of B-swirl defects in
Si comes from the observation that upon melting, droplets
of liquid Si are formed in the interior of the solid phase. 2o
4. In n-p structures formed by sequential diffusions of Band P,
dislocation climb was observed to have occurred at the
same time that the emitter-push effect was seen in the B
layer. 21 This result implies that the same point defect is
responsible for both phenomena.
5. Stacking fault growth P diffusions and enhanced buried
layer diffusion have been observed to occur simultaneously.22
6. Total energy calculations show that self-interstitials form
and migrate in Si with a total activation energy roughly the
same as that of self-diffusion. 23

After reviewing the balance sheet of pros and cons surrounding the
question of the native defect in Si, one is still left with the question: what is
the native defect responsible for impurity diffusion and defect growth in
Si? So far we only have clues. However, the majority opinion currently is
that both types of point defects are important. Thermal equilibrium concen-
trations of point defects at the melting point are orders of magnitude lower
in Si than in metals. Therefore, a direct determination of their nature by
Simmons-Balluffi type experiments 24 has not been possible. The accuracy
of calculated formation and migration enthalpies appears to be within ±
1 eV but do not help to distinguish whether vacancies or interstitials are
dominant in diffusion. The interpretation of low temperature experiments
on the migration of irradiation-induced point defects is complicated by the
occurrence of radiation-induced migration of self-interstitials. 25 ,26In addition,
there are indications that the structure and properties of point defects may
change from low to high temperatures. 27 The observation of extrinsic type
dislocation loops in dislocation-free, float zcne Si showed that self-inter-
stitials must have been present in appreciable concentrations at high
temperature during or after crystal growth. 28 ,29 However, it is unclear
476 Semiconductor Materials

whether these self-interstitials were present in thermal equilibrium or

were introduced during crystal growth by non-equilibrium processes.
In view of the uncertainties regarding the native point defect in Si, it is
necessary in discussions of self and dopant diffusion to take account of
both types of defects.

Point Defect Models of Diffusion in Silicon

Underthermal equilibrium conditions, a Si crystal will contain a certain
equilibrium concentration of vacancies, Cv' and a certain equilibrium
concentration of Si self-interstitials, C,. In diffusion models based on the
vacancy, Cv»C, and dopant as well as self diffusion can be explained as 13

where D j is the measured diffusivity and D(, D j-, D j= and D j+

are the intrinsic diffusivities of the species through interactions with
vacancies in the neutral, single acceptor, double acceptor ordonorcharge
states respectively. These individual contributions to the total measured
diffusivity were described in a previous section.
Analogous to the vacancy model, Si self-interstitials can be assumed
to be dominant such that C1> >Cv' For such a model, dopant and self-diffusion
are assumed to occurvia an interstitialcy mechanism. 3D Mobile complexes
consisting of self-interstitials in various charge states and impurities are
assumed to exist.
In principle, both vacancies and self-interstitials may occur simulta-
neously, and somewhat independently. Indeed, any relationship that may
exist between Cvand C, may be dominated by the Si surface which can act
as a source orsink for either species. If a local dynamical equilibrium exists
between recombination and spontaneous bulk generation, vacancies and
self-interstitials would react according to

v+I ~ 0, (40)

where 0 denotes the undisturbed lattice. The law of mass action under
equilibrium for this reaction is

(41)

For sufficiently long times and high temperatures Equation 41 turns out to
be fulfilled. 31 ,32 However, it has been reported that a substantial amount of
time may be required for dynamical equilibrium to occur. 32 This would
make vacancy/self-interstitial recombination an activated process. In
addition, under point-defect injection conditions, Equation 41 may no
longer be valid.
If both types of point defects are important, diffusion processes may
involve both types:
 Diffusion and Ion Implantation 477

where Djl is the interstitialcy contribution and Djv is the vacancy contribution
to the total measured diffusivity, OJ' One way in which vacancies and self-
interstitials could cooperate in affecting impurity diffusion is the Watkins
replacement mechanism 34 shown in Figure 16. Interstitial dopant impurities
can be created by the exchange between a self-interstitial and a substitu-
tional dopant atom. The newly created interstitial impurity would migrate
until it finds a vacancy. Then, it is free to diffuse again as a substitutional
impurity.
It is evident now that both vacancies and self-interstitials can exist in
equilibrium with each other in the silicon lattice. Each species can be
decribed by equilibrium equations of the type:

(43a)

(43b)

For silicon self-diffusion, the total diffusion coefficient could be expressed

as

DSi =f y Dy ~ + f 1 ~ cf

where f v and f j are the fractional contributions of vacancies and self-

interstitials to self-diffusion. There currently is substantial debate as to
what the values of these fractional coefficients are. A diagram of the
spectrum of the debate currently underway in the literature is shown in
Figure 17. The concept that impurity diffusion was dominated by vacancies
on Iy was held until1968 when Seeger and Ch ick 35 proposed that both self-
interstitials and vacancies could contribute to diffusion in silicon. However,
the concept of vacancies and interstitials coexisting in silicon leads to
several unresolved questions such as-is there dynamic equilibrium between
self-interstitials and vacancies and what is the time required to establish
this dynamic equilibrium?

Experimental Observations
In order to understand whether vacancies or self-interstitials are

000000
0,tf06'- a
000000
Figure 16: A schematic diagram of the Watkin's Replacement Mechanism.
478 Semiconductor Materials

V Only Vand I

Questions:
.I+V~O
'1 0 0
• C,C v =C,C v
• Time to equilibrium?
In 0

lIT
Figure 17: A diagram of the spectrum of the vacancy vs. self-interstitial debate.

involved in diffusion, there are numerous indirect observations that we

must rely upon. A partial list of these types of experiments is shown in Table
2.
For example, during oxidation, enhanced diffusion of phosphorus, boron
and arsenic are observed as well as retarded diffusion of antimony. However,
if direct nitridization of the silicon surface occurs, the inverse effects are
observed, Le. enhanced antimony diffusion and retarded phosphorus
diffusion. There also is a doping dependence associated with oxidation-
enhanced diffusion. As either p or n-type doping concentration increases
above n i, the effect of oxidation-enhanced diffusion diminishes. If chlorine
is introduced into the oxidizing ambient oxidation enhanced diffusion is
likewise diminished.
Not only is enhanced impurity diffusion observed during oxidation but
also increased stacking fault growth. A stacking fault is a plane of dislocated
material that may intersect the silicon surface but which also has a
bounding partial dislocation. These faults grow if sufficient numbers of
self-interstitials are generated such that the concentration of self-interstitials
in the lattice is higher than the concentration of self-interstitials on the
bounding partial dislocation core. This process is illustrated in Figure 18.
Since oxidation is a process that generates excess self-interstitials, stacking
faults grow during oxidation.
 Diffusion and Ion Implantation 479

Table 2

Which Mo~el is Operatin2 in Silicon?

For insight we need indirect observations from numerous
different experiments:
• Oxidation - enhanced/retarded diffusion
.backside oxidation
role of Si 3N4 surface films
retarded diffusion of Sb
doping dependence of OED/ORD
effeet of chlorine
CZ versus FZ Si

• Doping effect on OSF shrinkage

• Effect of diffusion on 0 precipitation
• Codiffusion studies
!t TEM studies of precipitates/defects
• Cr vs. n in doped layer
• Profile 1vfodeling
• Role of stress
• Doping dependence of oxidation

Other experiments that have been performed include irradiating uni-

formly doped silcion wafers with protons and observing the diffusion of the
dopant after irradiation has occurred. Additional discussion of these effects
will follow.

DIFFUSION IN THE PRESENCE OF EXCESS POINT DEFECTS

Oxidation-Enhanced Diffusion
As it was mentioned in the above discussion, oxidation generally
enhances the diffusion of Group III and Group V elements except for
antimony. These results are summarized in the Figure 19. In this figure
oxidation- enhanced diffusion is generally observed by depositing a silicon
nitride mask on the silicon surface which will prohibit oxidation in the
regions that it covers. Then oxidation is performed in a window opened to
the silicon surface, so that differential changes in junction depth can be
observed. In orderto explain these results, HU 36 proposed a model whose
essential points are:

1. Oxidation of Si at theSi/Si0 2 interface is usually incomplete

to the extent that approximately 1 Si atom in 1000 is
unreacted.
480 Semiconductor Materials

PARTIAL
DISLOCATION

__- - c I C
L
(4F)L
/ ci = EXP RT
C0 ---.::...--L.----=---'--t~
I DISTANCE

Figure 18: A model of self-interstitial diffusion from the bulk to the partial dis-
location bounding a stacking fault. Under non-oxidizing conditions the concen-
tration of self-interstitials at the fault line, C, L, is greater than the equilibrium
bulk interstitial concentration, C,a. Under oxidizing conditions, C, is greater
than C, L until the retrogrowth temperature is reached.

Enhanced diffusion Retarded diffusion

more point defects
l'l::: less point defects
l'l:::

S, Ga, In, AI; P, As Sb

~ J
I Supersaturation V Reduction

Figure 19: Experiments that illustrate oxidation-enhanced and oxidation-re-

tarded diffusion of dopants in silicon. The supersaturation of self-interstitials
associated with the oxidation process drives both effects.
 Diffusion and Ion Implantation 481

2. The unreacted Si becomes mobile, severed from the lattice

by the advancing Si/Si0 2 interface. These atoms enter the
Si lattice interstices, causing a flux of self-interstitials away
from the interface.
3. Growth of oxidation-induced stacking faults will proceed by
the absorption of the generated self-interstitials. Oxidation-
enhanced diffusion can occur as a result of the presence of
the excess interstitials via the Watkins 34 replacement
mechanism or by an interstitialcy process.

If the Watkins replacement mechanism is ignored, the diffusivity of an

impurity atom under conditions of non-equilibrium point defect concentra-
tions is

where C and Cv are the non-equilibrium self-interstitial and vacancy

1

concentrations. Defining the fractional interstitialcy factor as 32

we can write

Calculations of the fractional interstitialcy components for B, P, As and Sb

are shown in Table 3. 31 ,37,38-40 A significant spread in the values of f j is
obtained. The value of f j has been correlated with the amount of energy
required to make a substitutional dopant atom become interstitial. Interstitial
formation energies in Si are shown in Table 4. Thus, the larger the interstitial
formation energy the smaller is the fractional interstitialcy component of
diffusion.
It is observed that the diffusion of Sb is retarded during oxidation of the
Si surface. 31 Thiscan be explained byassuming Sbdiffuses predominantly
by a vacancy mechanism, and the self-interstitials generated at the oxidizing
surface combinl.~ ,,vith vacancies to reduce their concentration. Recent
data from nitridation experiments suggest that f j for P is greaterthan 0.7. 41

Table 3: Fractional Interstitialcy Components of Diffusion Via

o
Self-Interstitials in Silicon at 1000 -1100°C

<------------ f·1 -= D~ID~

1 1 --------- >
Element Fair [37] Antoniadis [32] Matsumoto [39] Gosele [38] ~fathiot [40]

B 0.17 0.32 0.41 0.8-1.0 0.18

Al 0.2 0.6-0.7
P 0.12 0.40 0.35-0.5 0.5-1.0 0.19
As 0.09 0.43 0.45-0.75 0.2-0.5 0.16
Sb 0.13 0.15 0.02
482 Semiconductor Materials

Table 4: Estimated Interstitial Formation Energies in Sil icon

Element Interstitial Formation Energy

Si 2.2eV
A1 2 + 2.21
B 2.26
P 2.4
As 2.5

Experiments that use the backside of the silicon wafer to inject self-
interstitials and thus observe diffusion on the frontside of the wafer are
illustrated in Figure 20. 42 ,43 On the wafer surface, films of Si 3 N4 or Si3 N4 on
Si0 2 are deposited over previously diffused layers. On the backside a
window is opened whose distance from the frontside surface can bevaried
by etching. It can be seen in the figure that the backside oxidation can, in
fact, influence the diffusion of dopants on the frontside surface. The ratio of
the junction depth under the oxidized portion to the non-oxidized portion
versus distance from the backside oxidizing surface is shown in Figure 21
for boron-phospohorus and antimony. These results were obtained in float
zone (FZ) silicon with no oxygen incorporated in the silicon. It can be seen
that self-interstitial diffusion lengths of the order of 200-300 microns were
obtained. These backside oxidation experiments show:

1. Oxidation-enhanced diffusion of Band P and oxidation-

retarded duffusion of Sb involve the same point defects
generated by an oxidizing Si surface.
2. The diffusion length of these point defects increases with
diffusion time in FZ Si.
3. Long-range(>1 00 p,m) oxidation enhanced/retarded diffu-
sion does not occur in Czochralski Si (CZ Si).
4. A Si 3 N4 1ayer on the Si surface is not a sink for point defects.

Doping Dependence of Oxidation-Enhanced Diffusion

Tanaguchi et al 44 found that oxidation-enhanced diffusion decreases
as the concentration of the diffusing impurity increases beyond the point
where concentration-dependent diffusion occurs. This effect was explained
in terms of the reduction of oxidation produced self-interstitials by recom-
bination with the increasing supply of vacancies. Fair 45 assumed that the
equilibrium vacancy concentration is unaffected initially by the self-inter-
stitials generated at the oxidizing surface. But, the quasi steady-state
value of interstitial supersaturation is inversely proportional to the vacancy
concentration which increases with doping above n j• The oxidation enhanced
dopant diffusivity, De' is then
De:le DS1 +ADo (48)
-DlCv/C~) + Di f i (CI/cf)i(C~/CV)'
 Oiffusion and Ion Implantation 483

BNaarea BO....rea

XJBO

Figure 20: Experiments illustrating the use of the backside of the silicon wafer
to inject self-interstitials in order to observe diffusion on the frontside of the
wafer (after Mizuo)"

where(C/C10)j is theself-interstitial supersaturation under intrinsic doping

conditions, and Cv/Cvo is the vacancy enhancement that occurs when
doping exceeds n j" This equation is divided into the contributions to
substitutional impurity diffusion under non-oxidizing conditions, 0SI' and
the enhanced contribution due to oxidation, dOo' The data ofTanaguchi et
al 44 are shown in Figure 22 for oxidation-enhanced diffusion of P and B
versus the total number of dopant impurities per cm 2 , Or The calculated
values of 0SI and dO o are shown in comparison with the data. Reasonable
agreement is obtained. Thus Tanaguchi's model of self-interstitial recom-
bination with vacancies is consistent with the high concentration diffusion
models of Band P used by Fair in his calculations.

Effect of Chlorine on Oxidation-Enhanced Diffusion

If chlorine is added to oxygen in the furnace in sufficient concentrations
such that stacking fault retrogrowth occurs,46 oxidation-enhanced diffusion
will become negligible. 47 Th is resu It is believed to be due to the generation
 484 Semiconductor Materials

1.5

1.0 ~ - - - - - - - -
_--::::;~'-=----------j
_
"..,-"'-
~

e/
A
/'

0.5 oL-----'-1...Loo---2o:1:-o----=:3o~0
-----:-;40~0--~500

Figure 21: The ratio of the junction depth under the oxidized portion to the
non-oxidized portion of the wafer vs. distance from the backside oxidizing
surface.

g3.0xl0- L I
-0 --0- - .1)_ - - ,

~ \
3 '\ DSI CALCULATED

• (a)
", ~6 00 CALCULATED
........ 0
1.0 .........

O~-----I------~t---------t
10 14 10 15 10 16 10 17
TOTAL IMPURITY DOPING, QT(cm- 2)

3.0xl0- 15
DSI CALCULATED
--0-------0----, ••
\0
2.0 \
.\
(b)
'\
1.0 ""<.. ~. DO CALCULATED
DATA FROM TANIGUCHI etal ...... 0 ......

Figure 22: Measured and calculated values of boron and phosphorus diffusivity
as a function of total impurity doping. Data are divided into contributions to
substitutional impurity diffusion under non-oxidizing conditions, DS 1 and the
enhanced contribution due to oxidation LiDo.
 Diffusion and Ion Implantation 485

of vacancies at this Si/Si0 2 interface when Cl reacts with Si atoms on lattice

sites to produce SiCI by the reaction

Si + 1J2Cl:r-+SiC1 +v.

The vacancy generated is then available to recombine with a Si self-

interstitial produced by oxidation:

I +V --+0. (50)

As a result, the supersaturation of self-interstitials in the silicon surface

and the bulk is reduced or eliminated, inhibiting stacking fault growth and
enhanced diffusion. This effect is diagrammed in Figure 23. The effect of
adding HCI to 02 on stacking fault length after oxidation of silicon is shown
in Figure 24.

CHARACTERISTICS OF SILICON SELF-DIFFUSION

In order to satisfactorily explain the self-diffusion of silicon, one must

reconcile the experimental results obtained by three techniques in three
temperature ranges:

1. high temperature radio-tracer measurements

2. precipitation in quenched crystals at temperatures less than
850°C

(Hel oxidation)

Si
•
¢:=== OSF shrink

Figure 23: Diagram of SiCI formation during oxidation with the subsequent in-
jection of vacancies. The vacancy injection reduces the concentration of self-
interstitials in the bulk and causes oxidation stacking faults to shrink.
486 Semiconductor Materials
20

E
-=
~

t; 6
z:
"'"
-'
~

:5
c
4
"-
T=1100°C
Co:'
z: t=2 HR.
;::
Co.)
c
o ·SHIRAKI
~
U')

l'---_ _ -----.l_ _......L-------.l_...L..._-L.-...I...--'~...I._ . . . I . __ _L.__...L..._.__L_____I._.._J._.............~

10- 1 10 0 10

PERCENT HCI IN 02

Figure 24: The effect of adding Hel to O 2 on stacking fault length after oxida-
tion of silicon.

3. electron paramagnetic resonance measurements during

the low temperature annealing (1 OO°K) of radiation-induced
defects.

Silicon self-diffusion data over the range 850 to 1380°C are shown in
Figure 25. 35 ,48,49 The high temperature data show an activation energy of
5.02 eV while the lower temperature show a 4.25 eV energy. Watkins and
Corbett 50 reported an activation energyforself diffusion in Si of 3.9 eV. This
result was obtained from low temperature annealing of E-centers, impurity-
vacancy pairs at 100° K. The cause forthe continual decrease in activation
energy with decreasing temperture has been ascribed to different charge
state vacancies dominating self-diffusion in the various temperature
ranges. 13,51 ,52 Th us at very low tem peratu res neutral vacancies may dom inate
self-diffusion. At high temperatures, both donor and acceptor vacancy
diffusion was considered important. An alternate view was expressed by
Seeger and Chik 35 who suggested that in Si at low temperatures, self-
diffusion mainly occurs via vacancies, whereas at high temperatures it is
dominated by the interstitialcy mechanism. Their observations indicate a
change in the self diffusion mechanism and/or in the entropy and enthalpy
of self diffusion as a function ,of temperature. The change in entropy with
temperature can be accounted for by assuming that the form of the self-
interstitial changes with temperature. For example, the entropy would
increase due to a spreading out of the self-interstitial over several atomic
volumes.
 Diffusion and Ion Implantation 487

TEMPERATURE (OC)
10-12 1300 1200 1100 1000 900

CALCULATED (As-DOPED TO 8xl0 19 cm- 3 )

- QSi = 3.96eV

10- 15

~.-....--CALCULATED (B-DOPED TO
\
2.5xI0 cm- 3 )-QSi =4.78eV
19
"
,,
CALCULATED '
(INTRINSIC)
10- 18 • INTRINSIC Si (HETTICH,
etal)
o Ni IN INTRINSIC Si(SEEGER
& CHIK)
A B·DOPED Si (HETTICH, etal)

• As ·DOPED Si(FAIRFIELD & MASTERS)

• P-DOPED Si(SANDERS &DOBSON)
c INTRINSIC Si (KALINOWSKI, etal)
10- 21

10- 22 '-- ...J..- ......L- ---'- "'"-~_ _~

6 7 10 11

Figure 25: Self-diffusion data in intrinsic and heavily doped nand p-type silicon.

The self-diffusion data in Figure 25 shows that Si diffusion is different

in heavily doped n-type or p-type silicon. In orderto see how the contributions
from vacancies in various ionization states can describe this effect, we will
write the intrinsic self-diffusion coefficient as

(51)

where Dv is the vacancy diffusivity, n H is the number of sites in the crystal,

and [V] i is the intrinsic vacancy concentration. In extrinsic silicon where the
488 Semiconductor Materials

doping concentrations exceed the intrinsic electron concentration, n i,

mass action effects cause changes in ionized vacancy concentrations as
shown in Figure 12. These curves obey the relations

[vl n [V1
-------
[V~ ni [vi
Using the relation D Si = 1/(2n H)D)VJ i, where the one-half term is the
correlation factor for the diamond lattice and n H is the number of lattice
sites, the Si self diffusion coefficient becomes

0Si -
x
DSi -I I
+ 0Si ~
D =
+ °Si [n ]2 + °Si+ I- : 1•
nj
Di
(53)

The calculated curves shown in Figure 25 use Equation 53 with thefol-

lowing intrinsic diffusion coefficients

D:i = 0.015 exp (-3.8geV/kT). (54a)

D~ = 16 exp (-4.54eV IkT). (S4b)

D~ = 1180 exp (-5.0geV/kT). (S4c)

The expression for DSi = cannot be obtained by analyzing the data in Figure
25. The values of the activation energies for each term are consistent with
the formation enthalpies, migration enthalpies and average free ionization
energies associated with each vacancy.53 Thus, at temperatures below
600°C Equation 53 predicts that Q Si approaches 3.8geV as the neutral
vacancy dominates self-diffusion. This agrees with the low temperature
value observed by Watkins and Corbett. 50

DOPANT DIFFUSION IN SILICON

Group III and V elements as solutes in Si are unique in their ability to

form strong covalent bonds with the lattice atoms. The result is they exhibit
very high substitutional solubilities in Si. An important consequence of this
is that it has led people to believe that these elements diffuse predominatntly
via vacancies of self-interstitials. Thus, one would expect similar activation
energies and pre-exponential factors for Group III orV elements in Si and
for Si self-diffusion. In fact, both the pre-exponential factors and the
activation energies of impurity diffusion are lower by a significant amount.
To explain this phenomenon using the vacancy mechanism asan example,
HU 54 has proposed that there must exist a long-range vacancy-impurity
interaction potential which would cause impurity-point defect pairing to
occur. Thus, the vacancy and the impurity atom would diffuse as a pair and
the additional energy required forcomplete dissociation would not have to
be supplied. If no pairing occurred, the vacancy would have to disappear
 Diffusion and Ion Implantation 489

into the lattice, and this would be the rate controlling mechanism as it is for
self-diffusion. Therefore, the difference between the activation energy for
self-diffusion and Group III or V impurity diffusion is less than the impurity-
vacancy pair binding energy, Eb. This is illustrated in Figure 26 where a
particular long-range interaction potential is assumed. The potential energy
between a vacancy at a third coordination site and one infinitely removed
from the impurity atom is ~Q. Thus the activation energy for impurity
diffusion, Q" is proposed to be

OJ - QSi .. ~Q. (55)

Equation 55 is based upon an impurity displacement cycle which sees

the vacancy first partially dissociate from the impurity atom, and go at least
as far as the third coordination site to close a path around the impurity
atom. If the long-range interaction potential is assumed to be Coulombic,
this complements the multiple charge state vacancy model where the
diffusion of donor atoms is dominated by acceptor type vacancies, etc.
Experimental evidence exists in support of coupled point defect-
impurity diffusion in Si. For such a model, chemical pumping effects
involving vacancies or self.. interstitials would be negligibly small. Thus, for
a system such as Si where the diffusivity of the solute differs considerably
from that of the solvent, a vacacny or self-interstitial flux will be induced by
the solute fluxes. 55 According to the chemical pump model, the influx of a
fast diffusing impurity such as P or 8 in Si will cause an eflux of lattice
vacancies or a flux of self-interstitials in the same direction as the solute
atoms. However, it is observed that buried clumps of 8 or P approximately 5
microns from the Si surface will undergo isotropic enhanced diffusion
(uniform broadening towards the surface and into the bulk) during the

-'
~

>-~
~z:
-L.t.J
o::~
==>0
Q..o...

~z:
>'0
u;::
Zu
ex: c:x:
UQ:::
ex: L.t.J
>fooo-
Z

012345678
VACANCY SITE ON COORDINATION
SHELL ABOUT THE IMPURITY
Figure 26: A schematic diagram showing a long range vacancy-impurity interac-
tion potential which could account for the lower activation energy of impurity
diffusion compared with self-diffusion in silicon.
490 Semiconductor Materials

diffusion of a high P concentration at the surface. If a chemical pumping

effect were important, one would expect a buried clump of impurities to be
skewed in one direction or the other depending upon whether vacancies
or self-interstitials were dominant. This is not observed. This experiment is
diagrammed in Figure 27.
Other types of experiments such as proton-enhanced diffusion have
been used to support the notion of coupled impurity - point defects in pair
diffusion. For example, consider a uniformly doped sample that is irradiated
with high energy protons (see Figure 28a). The production of vacancies
and self-interstitials occurs mainly in a region near the average projected
range of the protons, R p (see Figure 28b). These point defects diffuse into
the bulk and towards the surface. This in turn produces a non-uniform
redistribution of the dopant atoms in the Si as shown in Figure 28c. 56 The
initially uniform B or P doping shows a dip centered at R between two
smaller peaks. Thus the dopant atoms diffuse in the same direction as the
diffusing point defects.
Two known mechanisms can account for these results. Either the
dopant atoms respond to the chemical pumping of a self-interstitial flux, or
they become tightly bound to either type of point defect and diffuse as a

I
-+t-
I
: ~ Jp
+-1,
I

-+-I (INTERSTITIAL
J
I
FLUX)
I

PHOSPHORUS .....+-
I
JS'I
EMITTER I
c I
!
• J8
I
I ___ BURIED
.... ,, LAYER
,,
~
,,~~
',,~t

x
Figure 27: A schematic diagram showing the expected redistribution of a buried
layer under the influence of a flux of self-interstitials chemically pumped from
the surface by a phosphorus diffusion.
 Diffusion and Ion Implantation 491

(a)

VACANCY AND SELF-

INTERSTITIAL
FLUXES
~
(b)

X
P
/ PROFILE AFTER
IRRADIATION
u
z
o
...
C.)

z
c: (c)
G-
o
o

Rp

Figure 28: Proton-enhanced diffusion experiments supporting the notion of

coupled impurity-point defect pair diffusion in silicon. (a) initial distribution of
dopant in silicon, (b) production rate of vacancies and self-interstitials due to
proton irradiation, (c) dopant concentration after irradiation.

dopant atom-point defect pair. 37 From our previous discussion the chemical
pumping effect is unlikely. Thus the question remains: which type of point
defect is more Ii kely to pair up with the dopant atoms? The answer appears
to depend in an unpredictable way on the type of dopant atom. For that
reason, the following sections will describe what is known about each of
the important dopants in Si.

Arsenic Diffusion Models

Arsenic is believed to diffuse primarily via a vacancy mechanism. In
this section the current understanding of As diffusion via a vacancy
mechanism will be reviewed. The characteristics of As diffusion as inter-
preted by this model are summarized in Table 5. The entropy of diffusion of
the As+V- pair is much larger than the entropy of the As+90Vx pair. 13 So, in
spite of the larger activation energy (OAs=4.05eV and 0As=3.44eV), the
As+V- pair dominates As diffusion above 1050 o e, as shown in Figure 29.
Diffusion of As+V= pairs is less important than in the case of P. This is due to
a smaller pair binding energy (1.37eV). In an oxidizing ambient little
492 Semiconductor Materials

Table 5: Characteristics of Arsenic Diffusion

(Vacancy Model Interpretation)
Property Result

As+V- pair diffusion dominates

at T > 1050·C
As+V= binding energy is Fewer As+V= pairs than P+V=
-0.25 eV less than P+V= 8. Less gettering of metal donors
b. No emitter push above 700°C
c. No effect on [OJ precipitation
v~ pair binding energy 1. Significant [V As2 ] form at
= 1.6 eV n ( = 2xl020cm-3 at lOOO·C
2. Reduces n solubility
3. Causes retarded base diffusion
in some cases
2.5 eV required to make As Little oxidation-enhanced diffusion
interstitial

enhanced diffusion of As occurs because 2.5eV (Table 5) is required to

create an As interstitial atom. Thus diffusion continues to be controlled
primarily by the local vacancy concentration rather than by the Si self-
interstitial supersaturation created by the oxidizing surface.
It can be seen in Figure 29 that As diffusivity can be enhanced when
diffusion occurs in heavily doped n-type Si. This concentration dependence
is further described in Figure 30 where DAs versusAs concentration curves
are plotted. The implication of such a concentration dependence is shown
in Figure 31. The As impurity profile no longer is described by an erfc
solution to the continuity equation for diffusion. An approximation to this
solution will be given in a later section.
Another feature of the As profile in Figure 31 is that the total As curve
deviates from the measured free electron concentration curve. It has been
proposed that this discrepancy is due to As clustering at high temperatures. 57
Thus, much of the study of As diffusion in Si has centered around the
clustering pheno.menon. The most recent contribution by Guerrero, et al 58
suggests that clustering involves As atoms along with one negative charge
(electron or V-). This result was obtained by fitting various models to room
temperature free-electron concentration versus total As data such as that
shown in Figure 32. The functional dependence of n on CT (total As
concentration) depends upon the source of As (implantation or diffusion)
and temperature. Other authors have tried to fit similar data with calculations
and have arrived at different conclusions regarding the chemical and
electrical form of the As cluster.
 Diffusion and Ion Implantation 493

TEMPERATURE (DC)
10- 11 _---:~-1.....,2~0..:....0 __I""T""10_0_ _1--,00_0_ _---.900

ARSENIC

EXTRINSIC DATA

Di (3.44 eV)

o GHOSTAGORE
• MASTERS AND FAIRFIELD
• ADDA
A FAIR AND TSAI
o BALDO et al.
• WEBER et al.
x CHAN AND MAl

10 -18 L . . . - - _ - . l_ _ -----L_ _ ~_ ____'__ _--Io- _

6 6.5 7.5 8 8.5 9

0~4)CK-l)

Figure 29: Arsenic diffusivities in intrinsic and extrinsic n-type silicon.

The clustering reaction can act to reduce As diffusion. Consider one

model in which the As cluster is a vacancy with two As atoms-VAs 2 .57 The
reaction is

V = + 2As + = VAs 2 0

Then, the total As concentration is

(57)
494 Semiconductor Materials

IOOO'C ra 02
'L- N2
A N2
1050C 6 02
{
o WET 02
1100'C • 02 •
1200:C • 02

10- 15 ,--_~---:,---,-",-~I . . I...;..i

. . "--_.J..---l-~--'--~~ __ ,","---_~--""""""--"
10 18 10 19

Figure 30: Arsenic diffusivity vs. total arsenic concentration. The solid curves
are calculated. The data represent diffusions in various furnace ambients.

where the formation of V-As+ and V=As+ pairs are included. By writing
down the equilibrium reactions forthe formation of each species in Equation
57 and setting CAS = n, then CT becomes

(58)

where K(l)'s are the equilibrium constants. Equation 58 can be used to

describe the data in Figure 32.
 Diffusion and Ion Implantation 495

The effective diffusion coefficient of As is defined as

(59)

which is Fick's First Law. If J is the flux of monatomic As, CAs' with a linear
concentration-dependent diffusivity, then

CAs (jC.As
J=-Di - --.
ni ax

=-Di -
CAs acAs
- - --.
CJCr
. Dj CJCr ox
Substituting Equation 58 and solving for DAs yields
D j (n/nj)
D,As = 3
4Kc(T)n
1+---- 2
(62)
1 + 3K b(T)n

900 0e
2020 MIN .
• -C
T

I
E
u
---
0::::
o
.-
u

10 19 ~ _ _---"' ----L ~ --"" ---"

o 0.1 0.2 0.3 0.4 0.5

DEPTH (Jjm)
Figure 31: Total arsenic CT and free electron profiles in silicon following an
arsenic diffusion.
496 Semiconductor Materials

10 22

CALCULATED

1M PLANTED-DIFFUSED
~-
~.,
SOLUBILITY
L1MIT(1050 C)
E ~
(..)

c: "'- CHEM ICAl SOURCE

10 2C
CHEM ICAL [A
MUROT A. eta I
SOURCES • FAIR
IMPLANTEDf o lxl0 115 cm- 3 (1050 C)
SOURCES L~~ 2xl0 1E cm o3 (1100 C)

Figure 32: Electron concentration vs. total arsenic for chemical source arsenic
diffusion and diffusion of an ion-implanted arsenic layer with the same inte-
grated concentration.

oAs is the effective diffusivity of As in Si that results when monatomic As+

diffuses substitutionally while inactive, stationary As complexes (VAs 2) are
forming to reduce the flux of diffusable ions. Equation 62 is plotted in Figure
33 and is compared with measured data of 0 As versus C-p The reduction in
oAs when clustering occurs is evident.
The individual components that make up Equation 57 are shown plotted
in Figure 34 at 700°C and 1000°C. At 700°C the contribution of V=As+
becomes significant. This also corresponds to the temperature at which As
diffusion becomes greatly enhanced, much like P diffusion at highertemper-
atures.

Phosphorus Diffusion Models

The characteristics of P diffusion in Si are summarized in Table 6 using
the vacancy model of diffusion for interpretation. As a result of the large
diffusion entropy of P with neutral vacancies, ~Sdx, low-concentration P
diffusion is dominated by the availability of VX vacancies. 13 At high concen-
trations (C> > n j ) the P+V= dominates diffusion. Thus, the diffusivity shows
 Diffusion and Ion Implantation 497

CT C
T=34 T =38
I

/ hR o
0
ni

.y
/
o
CALCULATED

° KENNEDY AND MURLEY

~] FAIR AND WEBER

DI =1 .4x10-15~2
o

SEC
T= 1000°C

CTO = 8.5x 10 20 ATOMS/em 3

10- 15 L...-.._----JL-.----L..---J_I-...L.~...J-I, _ _~_ __'____L._..&..__L_............ ~

10 19 10 20
C (ATOMS/em 3 )
T

Figure 33: The effect of diffusivity of arsenic vs. total concentration for dif-
fusions into p-type sil icon at 1000°C.

~ 10 21 J------4-----~---_+_----t_---_1
C"")

Ie 5110 20
~
c:: t~c..

CVAs2,Cr
10 20 J---------+------f--.:::::...--t-------f"lI"--------~
~

7e 5110 20
~
c::

10 20 L..-...L.-~~..LU....---JL..._J......L...L.J..LLL~.:::I......L...L....&...I_I..u..L..____I""__I_ ~._..
......................&-.-....&._..............

10 16 10 18 10 19
CONCENTRATION (em -3)

Figure 34: Arsenic and arsenic-vacancy pair concentrations vs. electron concen-
trations at two temperatures.
498 Semiconductor Materials

an n2 dependence for n»n j • The relative unimportance of P+V- pair

migration to the total P diffusivity is due to the small size of the P atom. The
small covalent radius (rc = 1.1 OA) causes the pair migration entropy, i1S pv '
to be very small.
The diffusion coefficients that have been attributed to P+VX,P+V- and
P+V= pair migration are shown in Figure 35. The Fair-Tsai 12 model uses these
three diffusion coefficients to explain the unique shape of the high concen-
tration P profile shown in Figure 36. Features of this profile include:

• a difference between total P and free carrier concentration

near the Si surface
• a kink in the profile
• a tail region of enhanced diffusivity
Two more majorfeatu res associated with P diffusion in Si are defect gen-
eration and supersaturation of point defects. Because the tetrahedral covalent
radius of P is smaller than that of Si, contraction of the host lattice can occur
at sufficiently high doping concentrations, leading to the generation of misfit
dislocation arrays. The generation of excess point defects and, thus, the
formation of a tail on the P profile has been proposed to be a result of the
dissociation of P+V= pairs. 12 At P concentrations above 10 20 cm- 3 the
dominant diffusing species is thought to be the P+V= pair. According to the
Fair-Tsai theory, these pairs dissociate when n drops below 10 20 cm- 3 at the
diffusion front. The vacancy then changes charge state (E c-E f =0.11 eV is
the second acceptor level of the monovacancy), and the binding energy of
the P+V= decreases. The probability for dissociation is thus enhanced. The
resulting vacancy flux is shown in Figure 37.
The correctness of the Fair-Tsai theory has recently come into question
as a result of experiments in which a high concentration of P was diffused

Table 6: Characteristics of Phosphorus Diffusion

(Vacancy Model Interpretation)

Property Result
X
Large AS~ (11.6k.) Diffusion via V is dominant at low concentrations
Large P+V= pair binding p+V= pair dominates high concentration diffusion
energy (1.57 eV) a. P+V= pairs compensate monatomic p+
b. Gettering of donor metal ions .... P+M-
p+V= dissociation Q,t 1. Emitter push effect
2. Defect shrinkage near junction
3. Reduced [Oil precipitation
Small covalent radius 1. Misfit strain
8. Gettering by misfit dislocations
b. Reduced diffusivity through band gap
narrowing

2. ASp-v < ASAs-V

 Diffusion and Ion Implantation 499

TEM PERATU RE (DC)

1300
10 -11 ~I~_12~0_0_1'""'l""'10_0_1_0.,.-00_ _9-r0_O_ _8....,00

0-
10 -12 : Of} FAIR AND TSAI
• MAKRIS AND MASTERS
• GHOSTAGORE
10- 13, --

• TSAI
• o MATSUMOTO
10- 14 ....--of = 3.85 exp (-3.~; ev)
Co.)

N
LoU
V)
..........
10- 15
0
_ (-4-.0 ev)
Dj = 4.44 exp -k-T-
E
u
0'
10- 16

44.2 exp (
-4.37
kT
eV)

10 -19 L...-_-~_....o.-.. --"'-" -"'"' __

I 6.5 7.0 8.0 9.0 9.5

6.25
( It) ('Kj-l
Figure 35: Phosphorus diffusivities in intrinsic silicon.

into an epitaxial layer grown over an Sb buried layer. 59 ,6o The point-defects
generated by the P surface diffusion retarded the diffusion of the buried Sb
layer. Retarded diffusion of Sb has also been observed under an oxidizing
surface in which Si self-interstitials are generated. 31 ,32
Recently these experiments were repeated in which the P diffusions
were characterized and the surface concentrations were above the solid
solubility limit. Over the temperature range 900-1150°C, reduced and en-
hanced diffusion of buried Sb or As layers respectively was observed. 22 In
addition, extrinsic stacking faults over the buried layers were observed to
grow at the same time. Thus, the generation of self-interstitials seems to be
associated with supersaturated P diffusion. Along these same lines, Nishi
and Antoniadis 61 have shown that oxidation-induced stacking faults (OSF)
grow fasteror shrinkslowerwith increasing phosphorus/cm 2 both within the
P-doped layer and below this layer. The P was introduced from a supersatu r-
ated chemical deposition system. Plots of P diffusion junction depth and
change in OSF length reduced by Vt are shown in Figure 38 versus
500 Semiconductor Materials

/ TOTAL PHOSPHORUS
ELECTRON PROFILE

T = 1000uC
t = 60 MINS.
M
10 20 POCI3
I
E
~
z
2
~
e:t:
0:::
~
Z
~
U
z
0 10 19
u

10 18 L--_~_~_'-""- ~

o 0.4 0.8 1.2 1.6 2.0

DEPTH (fAm)
Figure 36: Total phosphorus and electron concentration profiles obtained by
secondary ion mass spectrometry and differential conductivity measurements,
respectively.

phosphorus dose, Qp' These data were extracted from Nishi's work Note
that the doping conditions which create rapid growth of OSF's in the Player
did not enhance the P junction depth. This may be due to P precipitation or
the recombination of generated self-interstitials with vacancies which P
needs to diffuse.
Two recent experiments have yielded considerable support for an
interstitialcy mechanism for P diffusion. Fahey, et a/ 41 have observed that
direct nitridation of Si produces a supersaturation of vacancies such that P
diffusion is substantially reduced below the surface and Sb diffusion is
enhanced. Estimates of the fractional interstitialcy component of P by these
authors are 70-100 0/0. Results are shown in Figure 39.
In another experiment, Nishi, et a/ 51 have observed stacking fault growth
beneath P diffused layers which had surface concentrations below solid
solubility. This experiment provides strong evidence that the point defect
injected by P diffusion is the self-interstitial. No quantitative model exists to
explain this result. However, calculations of the self-interstitial supersaturation,
C/C,o, caused by high concentration P diffusion are shown in Figure 40.
These calculations are based upon measured stacking fault growth beneath
P diffusions.
 Diffusion and Ion Implantation 501

TOTAL PHOSPHORUS CONCENTRATION

(PV) - O(n~
Do<n 2 ELECTRON CONCENTRATION, n
ns -------

p+ V= PAIR DISSOCJATION REGION

_ ne1------., (PV)- ...... (PV)x + e-
z:
o (PV)x~P+ + V-
t=
c
a::
~
z:
L.\J
U
z:
o
~ EXCESS VACANCY

I
/ --- --- L CONCENTRATION
----
/ TAIL REGION
/
I D = CONST. x n~ ----...
/ EMITTER DIP
/
/ EFFECT
/
/
~ (V)----..

o
Figure 37: Ideal ized phosphorus profile and vacancy generation model (after
Fair and Tsai). P+V= pairs formed in the surface region dissociate when the elec-
tron concentration drops to n = n e . At th is concentration the Fermi- level coin-
cides with the second acceptor level of V=. The freed vacancies diffuse until they
recombine with p+ atoms in the tail region.

Boron Diffusion Models

The vacancy model for B diffusion assumes that under non-oxidizing
conditions, B diffuses exclusively by exchanging with V+ vacancies. 62 This is
because the B-V+ migration energy is approximately 0.5eV lower than for
other impurity/vacancy pairs. As a result its diffusivity is enhanced if p> njand
is reduced if p<n j• A summary of the characteristics of B diffusion are shown
in Table 7.
Diffusion coefficient data for B are shown in Figure 41 for intrinsic
diffusion and extrinsic diffusion in both p+ and n+ Si. 62 Boron is unique in that
its diffusivity can be reduced by up to a factor of 10 when it diffuses in n+ Si. 62
Additional data showing this effect are shown in Figure42 where DB normalized
to OJ (intrinsic diffusion coefficient) is plotted versus p/n j• In B-doped Si
compensated by donor dopants, p/n j:::; 1. Calculated curves that fit these
measu red data show that the energy level of the V+ vacancy is 0.05 eVabove
the valence band of Si.
The importance of this effect is illustrated in Figure 43. Measured B
profile data are shown for a B implant into Si with an As background doping of
5 X 10 19 cm- 3 . 62 After annealing at 1050°C for23 min. the B has diffused less
502 Semiconductor Materials

20
(0
15
~
x
10
'$!.
u
CD
~ 5
E
....
----- .. ------
u
t LL
Cf)
0
.:-----
....J
<] -5 C - -
0
6-, -10
x
-15

Qp (cm- 2)

Figure 38: Phosphorus diffusion junction depth and oxidation stacking fault
length change as a function of integrated phosphorus concentration (Nishi,
et al).

10 r---------------------~

o p
~ As
8
X Sb

e 1\
6 T
-~'j;-- - - - -_ ""L

o
~
4 /
/" 1 -r---x-----J
~ L I
v
~I
l ;_-------6-----1'::.------1'::.
- -o~ - - - - - - - - - - -- - --
''-,- ......T
0

\
~
4 -l'--- - ----1--- }i- -- __ 0

0
::{ 6
* ~
0

10
1 10
Time (min)

Figure 39: The effect of direct silicon nitridation on phosphorus, arsenic and
antimony diffusion. The nitridation process creates a supersaturation of vacan-
cies which substantially enhances antimony diffusion, partially enhances arsenic
diffusion, and reduces phosphorus diffusion.
 Diffusion and Ion Implantation 503

Anneal Time
(minutes) =

1015
Phosphorus Dose (em -2)

Figure 40: Calculated self-interstitial supersaturation vs. integrated phosphorus

concentration (after Nish i, et al).

Table 7: Characteristics of Boron Diffusion

(Vacancy Model Interpretation)

Property Result
B-v+ migration energy is ... 0.6 eV Relatively fast diffuser dominated
by [Vi
Small tetrahedral covalent radius 1. Small diffusion entropy
2. Misfit strain
a. Dislocations
"b. Good gettering
c. Reduced diffusivity
226 eV required to make B Oxidation enhanced diffusion
interstitial
Forms stable oxides - B20 J and HB02 Segregration into growing Si02
from Si
504 Semiconductor Materials

10- 12

g 10'13

10- 14

• ANTONIADIS. etal
10- 15 • WAGNER
• TSAI
a KURTZ & YEE

o.[FAIR & PAPPAS} n~1.5xl020

CROWDER. etal em-)
o p~5x101~em'3

10- 17 '--------""---'----'----~---'"--.....
6 6.5 7.5
10 4 / T ( K· I )

Figure 41: Boron diffusivities in intrinsic and extrinsic nand p-type silicon.

10

.0
---
.... -- --
• 870C
• 950 C
o 1000'C
0. 1050C
.1 Q 1100C
Ev- = 0.05eV(l000 C) .. 1150'C
o 1250 C

.0 1' " - _ . . L . . - - ' - -..........

....J-l..J-LJ,_ _ I.....-..l--~....I..-l... ........._~_~--J..~1-I-I
.01.1 10

Figure 42: Normalized boron diffusivity vs. p/nj. The solid curve is calculated
with the vacancy donor level at Ev + 0.05 eVe The dashed curve is calculated with
the vacancy donor level at Ev + 0.35 eV.
 Diffusion and Ion Implantation 505

10 21

10 20

CN=
2X10 19 cm' 3
5Xl0 19
lXI0 20
10 19 1.5Xl020

~
z
o
;::
et:

~
L.I.J
10 18
• SIMS B DATA
w T = 1050°C
Z
o t = 23 min.
w

10 17

1016 ---....._ _.-....-_----'-_ _-"---_----' ~

o .1 .2 .3 .4 .5 .6 .7

DEPTH (JAm)

Figure 43: Calculated boron profiles as a function of n-type background doping,

CN . Experimental SIMS data of a 10 15 boron/cm 2 , 50 keV implant diffused at
1050°C for 23 minutes in N 2 in an n-type background doping of 5 X 10 19 cm -3.

than if the background As were 2 X 10 19 cm- 3 and more than if higher As

concentrations were present.
Theresults of experiments utilizing oxidation, direct nitridation of Si
and the emitterpush effect in the presence of high concentration P diffusion
show that B diffusion is enhanced in the presence of self-interstitial super-
saturation. It is reasonable to expect, therefore, that B diffusion occurs to
some degree by an interstitialcy mechanism under non-injecting conditions
as well. Estimates of the fractional interstitialcy component of B diffusion
range from 17 % -100 % •

DESIGN CONSIDERATIONS FOR IMPLANTED-DIFFUSED LAYERS

In this section useful curves and equations are developed to allow

designers to estimate diffusion temperatures and times for establishing
junctions from ion implanted layers in Si.
506 Semiconductor Materials

Arsenic Diffusion
For surface concentrations»n i, the diffusivity of As is

2Di C
DCC)= -
Di (63)

The continuity equation that must be solved with Equation 63 is

(64)

No exact analytical solution exists, but an approximate solution is

(65)

where

Equation 65 is plotted in Figure 44 on normalized scales and compared

with data.
Equation 65 can be solved for the junction depth, x J ' when C = O. Thus,
for ion-implanted layers that are diffused;

(67)

Use was made of the result obtained by integrating Equation 65 to give the
"dose" of arsenic, Or:

(68)
o

Equation 68 is shown plotted in Figure 45 and compares well with measured

data from As implants that were diffused at the temperatures shown.
Equation 67 is shown plotted in Figure 46 and is compared with measure-
ments.
Example: A3 X 10 15 As/cm 2 implant is performed in Si at50 keV. What isthe
junction depth after an 11 OO°C, 1 hour anneal in a N 2 furnace ambient?
Using Equation 67:

OrDit ]1/3
XJ=2
I
--

I
Dj
1/3
1 2
lIC:21C3XI015 em -2) C2xlO- -t em /sec.) (3600 sec.)
lxl0 19 em- 3

-=O.57xlO-4 em.
 Diffusion and Ion Implantation 507

1.0.--~_& NUMERICAL SOLUTION FOR

5xl0 1S cm- 2(1050 CC, 15 MIN.)
{
AND CHEBYSHEV POLYNOMIAL

~ NUMERICAL SOLUTION FOR

lxl0 1S cm- 1 (10500C, 30MIN.)
• • GAUSSIAN

0
~

~
.1
u QT(cm- 2 ) T(GC) t(HR.) AMB.
0 2x 10 15 1200 l2 O2
2/ O2
0 5xlO 15 1200 3

..
t::. 2xl0 1s
2xlO 16

• 5x10 1s
1000
1200
1000
2
2/ J
O2
O2
Nz

• lx10 16 1050 r2 O2
• 1xlO 16 1050 1

.
2 STEAM

• lxlO 16 1050 ~
STEAM

.01
0 .2 .4 .6 .8 1.0
YIY J OR XIX J
Figure 44: Normalized total arsenic profiles of implanted-diffused layers of sili-
con. The exact numerical solutions to the diffusion equation are compared with
the polynomial approximation for two different implant doses.

The surface concentration after anneal is

Cs = 1.9 Qr/xJ
::::: 1 X 1020 em- 3

Substitution of Equation 67 into 68 and solving for C s gives

508 Semiconductor Materials

10 21

o ~

o 0

o
t-
•
U

~.

eTC = l. 9 Or I XJ

Figure 45: Total arsenic surface concentration vs. average doping.

10 1

0
t-
U
q o

0 10°
.- I X 101~ cm- 2
E ~-2x 101~
::1..
.., o-5xI01~
X
• - I X 10 16
o-2x10 16
SUBSCRIPT *-STEAM AMBIENT

I0- 1~_-L_-L--.J....-L-.L..-L..~I--_-.L._~-'--~L.-I-~
10- 1 10° 10 1
1/3
Qr OJ t
) (J-Lm)
nj

Figure 46: Time, temperature and dose dependence of the junction depth of
arsenic implants after diffusion.
 Diffusion and Ion Implantation 509

Thus, C s decreases during annealing of an implanted As layer as t-%.

Sheet resistance measu rement can be used to characterize hig h dose
As implanted layers after diffusion:

(70)
o

where Rs is the sheet resistance (ohms/square) and the effective bulk

carrier mobility in the diffused layer. It has been shown that Equation 70
yields

(71)

and the time dependence of Rs is

Equation 71 is plotted in Figure 47 and compared with measured

electrically active surface concentration data. Equation 72 is a useful
design equation and is shown plotted in Figure 48 for various As implant
doses. The times and temperatures required to achieve a given sheet
resistance for a given dose are shown. Using Figure 48 in conjunction with

1021
,,
""
" Dt
"
" e

""
O-IOOOOC "'"
t
o ·-1025°C
U
eX b.-I050 0C DIFFUSION
o-II000C TEMR
e- 1200 0C
*- DATA FOR WHICH
CA. SOL < CTO

1019~_~_~.....L.-J..-L.~-L..I.. _ _...L.---.L---L--J.."""""'~
10- 4 10- 3 lQ-2
P = Rs XJ (ohm-em)

Figure 47: Electrically active arsenic surface concentration vs. average layer
resistivity.
510 Semiconductor Materials

10 1

X J AT O. 1 C s (I.un)

Figure 48: Sheet resistance vs. junction depth for implanted arsenic layers dif-
°
fused in N 2 or 2 .

Figure 49 allows one to design a simple one-step process. The procedure

is:
1. From Figure 49 pick the As dose required to give the
desired Rs and x J values.
2. From Figure48 pickthetimeandtemperaturecombination
that intersect with the Rs and dose values specified.

Phosphorus Diffusion
As pointed out earlier, high concentration P diffusion is complicated by
multiple species diffusion mechanisms. Thus, no simple solution exists to
the diffusion equation. However, some useful curves have been generated
for designing ion implanted P layers with a single step anneal.
 Q=

t~-:~-'~~--,~.;..~-,:~~"-··_-_.- ··~+·:"';;.;..~-J.--,+-,~1~-' T ::::;:':-:-~':~·_·11xl015cm-2

2x 10 15
c 3x 10 15
2 ----4xl01~
~ 10ll:......,..;..-l.+--:-r--:-:-:-~ "':';"rl-c."..-_:~':"';':""""'::---:"'f--- •• '+';-_':':- ";"'··---ro-i·,-"-·;-;':'~"-+~!-;-__ +._,_.,-.,,_ ~_.:.~.-.,-;-,-~ 5xl0 15
a:: :.L-,2.,.. _.,4-~ 7xl0 15

l:~:':::::'-':~'-:::':;:':'_:j.:;::':.:::::~. f:::)h',,:::q: ':":::::r"::'::>:J~j

1 xl 0 16

~~:4~~rn~~~~~~~;i~~~tD~UW~4~~~~_~:~~~~~2Xl016
1:~~~~-~CI·:;~:;~i:~;;:::;::i·=':~'~: ~ .~. :j.~;-;:'~~::~=:·:i;:::!~~~~~- ~:~ :.. ~~t:J·.:·::.:j·~:t-~~f~:::~-:t1-~~:~1:~::!" :::~~t·~~;~::-r~t-t~jj"~~~~-:-j~~~i~~j::j·.;t::::Ij 3x 10
16 o=+;
-+-
c
en
10 3 10 4 10 5 10 6 10 7 o·
TIME (SEC)(1000'C) ::J
Q)
::J
TIME (SE C){ 1050: C):' . : r.:~:+· :-:::-'!~::~:';:. :L:~::, ...._ ... +. .::::.~j:: i 'r ....
c..
10 2 10 3 10 4 10 5 o
::J
TIME (SEC)(1100:C):· ,.j '.;. ._._~ .... i
3
10 2 10 3 10 4 10 5 "0
c
n;-
TIME (SEC)(1200 C), ::J
----------------------------
10 2 10 3 10 4 10 5
.-+
Q)
.-+

TIME (SEC)(1250°C) _ o·
::J
10 2 10 3 10 4 10 5

C1J
~

Figure 49: Time, temperature and arsenic dose dependence of sheet re~istance (diffusions in N2 or 02). ~
512 Semiconductor Materials

Calculated curves of Rs versus x J for various P implant doses are

shown in Figure 50. These curves are similar to the As curves shown in
Figure 49. The times and temperatures required to achieve a given sheet
resistance for a given dose of P are shown in Figure 51. The design
procedure is similar to the procedure described in the As section.

ION IMPLANTATION

Ion implantation is the introduction of ionized atoms into a silicon substrate

with sufficient energy to penetrate beyond the surface region. This requires
that the ions have energies above 3 keV if they are either boron, phosphorus
or arsenic. Such an energy will allow these atoms to penetrate beyond any
surface layer of native Si0 2 • Therefore, any barrier effect of the surface
oxide on impurity introduction is avoided.

0.1 1.0 10 1 10 2
X J AT 10 17 cm- 3 (pm)

Figure 50: Sheet resistance vs. junction depth for implanted phosphorus layers
°
diffused in N2 or 2 -
 Diffusion and Ion Implantation 513

The advantages of using ion implantation as a predeposition technique

are:

precise control over impurity dose, depth, profile and area

uniformity
excellent reproducibility
wide choice of masks; Si0 2, Si 3 N4, polysilicon, photoresist,
etc.
low temperature processing
small lateral spreading of dopant (self alignment)
vacuum cleanliness

The disadvantages of ion implantation are:

expensive, complicated equipment

junctions are not automatically passivated

Some typical parameters for ion implantation of dopant atoms in

silicon are:

implanted ions: phosphorus, arsenic, antimony and boron

dose: 1011/cm 2 to 10 16/cm 2
energy: 5 keV to 2 MeV
depth of implant: 100 angstroms to 1 micron
reproducibility and uniformity: + or - 5 0/0
temperature: usually room temperature

Example: a 50 microamp beam of high energy ions implanted into a3 inch

wafer is equivalent to a dose rate of 6 X 10 12 atoms/cm 2 per second. The
dose is calculated by the equation
1 (amps)
Q-r= 2
q
A Ccm )

For comparison, a chemical predeposition of arsenic from a doped oxide

sourcewith a surface concentration of 5X 1020/cm 3 and ajunction depth of
0.1 micron gives a total deposited dose from Equation 68 of

01-= 0.53 Cs x J
= 2.6xl0 15As/cm2
Therefore in applications where low predeposition dose is needed (less
than 1015/cm 2), ion implantation has a natural advantage and should be
used over chemical source predepositions. Ion implantation is also useful
at higher doses for dopant control. Masks can be made of any convenient
material used in VLSI fabrication. As a result ion implantation has become
the primary doping source in the following applications:
 01
......
~
QT =
~
1xl 014 cm -2 C/)
CD
3
n·
102~:-:J~;L0:,_ . :m' ::<;~m::-_-W:J mjm_:lj~-"~·~·-.~._._:.I 5x 10 14
0
::J
c..
~-~-1,-H-:-:+~:+-~i 1xl0 15 C
()
o --~- _.- ro+
0
~ 2xl0 15
""'"
V\
cr: ~
3x 10 15
Ol
ro+

5xl0 15
CD
7x 10 15
""'"
iii·
_~ ....-.--..- .. -~·-_-··-~·.-.>·:·----=_=r.::~=-~-=~~~i'~ :·.-4-'-·----~·-1
_"""'"""'.-:----.. . ,. - . --~'----,:;_'~-_. -.'.::2·:::~b:=±t-·=-·t=±:--=-1-~·:-·~;~~_i;: j
lxl0 16
en
TIPIVTfUI="RV;";:-I'~-:;:-----;--'- '·:i.~

2X\016

3x10 16

.:....;.-=~~~:.::::-=-=S.2~~:.-:..2~~~..!J~~~L---=fu:Gl~[lili11.rtIill
1

1 .. --,

.... : . : : : : I
1
1 ; ;-

10 2 103 104 10 5 106 10 7

TIME(SEC)(900°C)

TIME (SEC)(1000°C) .. :::: .~ ... f::..-';"-!O::'~~"~:::';:: ·;'::~::r :~: T::T··r·r·~:::

102 103 104 10 5
TIME (SEC)(1 050°C) ~~-~:~}~: :T-::':::·l·::·:~:::>~:~::'~::::J1~-=~-ii r: .;:.. ':::~ :":::::f::r}i-t:-:~~~TT+::: :':::::B::::t::+.
\0 2 \ 03 104 10 5
TIME (SEC)(1l00~C) ,.!--:!':!' j

\0 2 103 t 04 10 5
TIME (SEC}(1200 c C) ~L::T:::::T:·~·:-::l':::: '.:;:~.::::::~:: ::::T::::::: :·~;::~::::Tl~_.~:·:-:~::: :f'E:::~=:~::::l:':~:,:~.}-~:;

t 02 \ 03 10 4 10 5
Figure 51: Sheet resistance vs. time, temperature, and dose for phosphorus-implanted, diffused layers in silicon.
 Diffusion and Ion Implantation 515

base regions in bipolar transistors for precise gain control

high value ion-implanted resistors
MOS threshold voltage adjustment
p and n wells for CMOS devices
emitters and bipolar transistors
source/drains in self-aligned MOS

Ion Implant System

A drawing of an ion implantation system is shown in Figure 52. 63 The
important features of this system are:

(1) Gaseous source of vaporizable material such as BF 3 or

AsH 3 at high accelerating potential. A valve controls the
flow of gas to the ion source.
(2) A power supply to energize the ion source and accelerate
the ions into the mass separation mechanism.
(3) An analyzer magnet that selects only the ion species of
interest and rejects other species.
(4) Beam sweeping electrodes with sawtooth voltages applied
to raster the beam and give a uniform implantation across
the wafer.
(5) A target chamber consisting of an area defining aperture,
Faraday cage for measuring current and a wafer feed
mechanism.

Simple Range Theory

An understanding of the mechanisms which govern the slowing down
of ions in silicon is of considerable importance in achieving controlled and
reproducible dopant distributions in ion implantation. Factors such as ion
energy and ion species, the crystal orientation and temperature of the
implant all influence the range distributions obtained. There is, therefore,
the possibility of a much greater controlled variation of the distribution of
dopants introduced into the substrate than exists in the case of chemical
predeposition.lf the implantation behavior is well understood, as a function of
ion energy and dose etc., it is feasible to program these parameters to
achieve almost any desired distribution, and in practice this processing is
highly automated.
Before considering the ranges of ions it is appropriate to discuss the
differential functions (dE/dx), known as the stopping power or specific
energy loss. Here E is the ion energy and x is the distance into the crystal,
usually measured along the direction of incidence of the ions. It is customary
to distinguish between two major processes of energy loss; 1) due to
elastic Coulomb interactions between the screened nuclear charges of
the ion and target atom and the other due to in elastic interactions of the
ion with bound or free target electrons.
 Acceleration 01
...L
Tube ())
Analyzer
Magnet Y Scan
Plates (J)
(1)
'1\jafer 3
X Scan (Target o·
Position)
o
Ion Beam Plates ::J
a.
c
(')
r-+
o
.,
~
tu
r-+
.,
(1)

Source m·
C;;
Deff
Pump

Ion Wafer
Source Beam Line & Feeder
End Station
Diffusion Pumps

Gas
Source

Figure 52: A schematic diagram of a typical commercial ion implant system. (After Varian-Extrion, DF-3000 brochure.)
 Diffusion and Ion Implantation 517

The total specific energy loss is taken to be the sum of two separable
components - nuclear and electronic:

where the units of dE/dx are eV/cm, and Sn(E) is the nuclear stopping
power( eV cm 2 ), Se(E) is the electronic stoppi ng power (eV cm 2 ), and N is the
target atom density which is 5X 1 Q22/ cm 3 for silicon. The variation of these
two components is shown schematically in Figure 53. It can be seen that
both increase with energy, reach a maximum, and then decrease again. At
the lowest energies nuclear stopping dominates and is responsible for
most of the angular dispersion of an ion beam. At higher energies electronic
collisions are the most important, and in slowing down to rest from these
energies the bulk of the particle energy is dissipated in the form of
electronic, rather than nuclear motion.
Reference coordinates for the important ion implantation parameters
are shown in Figure 54. The projected range, Rp ' is derived from the total
range of the incident ions. The total range can be calculated from Equation
73 if Sn and Se are known. Thus, rearranging terms in Equation 73 and
integrating gives Equation 74.

R 1 Eo dE
R=J dx=-J
o N 0 ISn(E) + Se(E)] (74)

Note that R will be the average total range and we would expect a
distribution of R, Rp and the transfer straggle Rr Such typical distributions
are shown in Figure 55 in which the depth distribution of implanted ions in
an amorphous target are shown for two cases-first relating to when the
incoming ion has a mass smaller than the target, and the second-
referring to the case where the incoming ion has a mass greater than the

X Electronic
"C
-...
W
"C Nuclear

Ion Velocity v

Figure 53: Behavior of the nuclear and electronic contributions to the specific
energy loss d E/dx as a function of ion velocity B.
518 Semiconductor Materials

Incident
Ion Beam

~~~~~~IIf""Ir""'I~~~~~-""~~~~~~~~ ,-Target
Surface
~~'''ll'_ll.''''';a..;l~~ -/ I~~lro~""~~'~~~."~
1\

xl
Y /
/ I \
/ t \
/ I \ Projected

, t ~ Range

t~peak
Standard
Deviation
of Projected _----11"--_

Range of Concentration
I Profile

I~ I ~I

Transverse
Straggle

Figure 54: Reference coordinates for the important ion implantation parameters.

Ion E Substrate
Beam • •
Z" M,

c:
o
.~
C'O
~
~
c:
~
c:
o
U

Depth Depth
Figure 55: The depth distribution of implanted atoms in an amorphous target
for the case in which the ion mass is less than or greater than the mass of the
substrate atoms.
 Diffusion and Ion Implantation 519

target atom mass. In general, the lighterthe ion relative to the su bstrate the
broader the distribution of implanted impurities will be. Thus:
LightIons Heavylons
~ Rp fl Rp
- - is large - - is small
Rp Rp

Nuclear Stopping
The specific energy loss due to collisions of the ion and a target
nucleus is derived by considering these as independent elastic two body
interactions. The energy transferred during a two body scattering process
depends upon the interaction potential between the two particles. Assuming
a Born-Mayer interaction potential it can be shown that a useful approxi-
mation for the nuclear stopping function is 64

(75)

where Sn is the nuclear stopping power independent of E, Z1 is the ion

atomic number, M 1 is the ion atomic mass, Z2 is the substrate atomic
number (14 for silicon), M 2 is the substrate atomic mass (28 for silicon) and

Electronic Stopping
When moving at velocities greaterthan the K shell electron velocity, an
ion will have a high probability of being fully stripped of its electrons. The
theory of energy loss under these circu mstances derives from the work of
Bore who carried out classical calcu lations. The electron ic stoppi ng function,
therefore, is dependent upon the velocity of the atom simply expressed
as 64

(77)

where v is the velocity of the ion, C 1 and K are constants. K depends on both
the ion and the substrate as shown in Equation 78.

(78)

(79)

47TEoaM 2
CE =----- (80)
ZtZ2q2(Ml +M 2)
520 Semiconductor Materials

and a is the bore radius. For an amorphous silicon substrate, K is approxi-

mately independent of the ion and assumes the value

Critical Energy

.
Note that in the above equations, Sn is independent of energy and S e
Increases with energy. There does exist, therefore, a critical energy at which
these two functions are equal:

Ec is the critical energy at which nuclear stopping and electronic stopping

are equal in magnitude and can be expressed as

-.fEe= Sn/K
14Z M
= 14 - - - -1 - - - -1 - (81)
[(14)2/3 + Z12/3]1/2 M1 + 28

The following values for Ec have been determined:

(1) Ec is approximately equal to 10 keV for boron (Z1=5 M 1=1 0)

(2) Ec is approximately 200 keV for phosphorus (Z1=15 M 1=30)
(3) Ec is greater than 500 keV for arsenic and antimony.

Therefore boron tends to be stopped by electronic interactions in the

typical energy ranges used in implantation and phosphorus, arsenic and
antimony tend to be stopped by nuclear collisions.
If E is much, much less than Ec then,

dE
- = NS n•
dx

Thus the range, R, can be expressed as

113
Z1 M1 +M 2
R == O.7A - - - - - E (83)
Zl~ M1

This expression is useful for arsenic, antimony and sometimes phosphorus.

If E is much, much greater than Ec then

dE 1
12
- = NKE •
dx

The useful expression for the range then becomes

R ::::: 20JE (A) (85)

 Diffusion and Ion Implantation 521

Projected Range
The discussion thus far has dealt with the total pathlength of the ion
implanted into the substrate, called the range R. A typical ion stops at a
distance normal to the surface, called the projected range, Rp . Statistically
speaking other ions encounterfewer scattering events in a given distance
in the target and come to rest beyond the projected range. Some ions that
may have more than the average number of scattering events come to rest
between the surface of the su bstrate and the projected range. The fluctuation
or straggle in the projected range is dR . The relationship between Rand
Rp is shown in Figure 56. The statistical clistribution of implanted impurities
with Rp and dR p were shown in Figure 55. The relationship that exists
between Rand Rn is shown in Equation 86 where b = 1/3 for nuclear
stopping and M 1 > M 2 Le. forantimonyand arsenic. Thevalue of b issmaller
for electronic stopping (B,P) but 1/3 is still a reasonable approximation to
first order.

Example: for arsenic M 1 = 75. Therefore R/R = 1.12.

The projected range corrections for calcu Fating Rp from R are shown in
Table 8. Useful calculations of the distribution parameters and concentra-
tions are shown in Equations 87-90.

-----iE~----------___t~-~ Distance into

~----- Rp - - -........1 Crystal

f
Target
Surface
Figure 56: Relationship between total range, R, and the projected range, Rpe
522 Semiconductor Materials

Table 8: Projected Range Corrections Rp/R

Ion Substrate RplR values Rule-of-thumb

value
20 keV 40 keV 100 keV 500 keV (1 + M /3M )-1
2 1

Li Si 0.54 0.62 0.72 0.86 0.4

B 0.57 0.64 0.73 0:86 0.54
P 0.72 0.75 0.79 0.86 0.77
As 0.83 0.84 0.86 0.89 0.89
Sb 0.88 0.88 0.89 0.91 0.93

(87)

Qr
cMAX-
-2.5ARp
--
(88)

I
(X-RP)2j
Ox) = C MAX exp - - -
2ARp2

1
O:x) = - CMAX @x=Rp±2ARp (90)
10
1
C(x) = - CMAX @x=Rp:t:3ARp
100
5
C(x) = 10- CMAX @x=Rp:t:4.8ARp

The depth distribution or profile of stopped ions can be approximated by a

symmetric Gaussian distribution function. The concentration of implanted
ions as a function of position is given in Equation 89, where the maximum
concentration occurs at x = Rp . The integral of Equation 89 is the dose, 0T'
and the maximum concentration is given by Equation 88.
Calculated curves of projected range(microns) as a function of implant
energy (kiloelectron volts) shown in Figure 57 for four important silicon
dopants. 55 As expected, the lighter boron atoms penetrate farther for a
given energy than the heavier phosphorus, arsenic or antimony ions.
Calculated curves of projected standard deviation, AR p' in microns as a
function of implant energy are shown for the four same dopants in Figure
58. As was stated earlier, the ARp/R p ratio is larger for light ions than for
heavy ions.

Implantation Masking
The goal of masking ion implantation is to allow the doping of the
substrate to occur in selected areas of the wafer. The ability of a given
 Diffusion and Ion Implantation 523

1.0r---------------------~---~

en
c:
eu
iQ)

cr.Q. ~ .1
cr.
"'0
~
u
Q)
'0
et

100 1000
Energy (keV)

Figure 57: Calculated projected range in microns as a function of implant energy

in kiloelectron volts for four important sil icon dopants.

material to act as a mask depends upon the ion stopping power of the
material as well as the thickness of the material. Three commonly used
masks in integrated circuit technology are Si 3 N4 , Si0 2 , and photoresist.
The minimum masking thickness of each of these materials is shown in
Figure 59 as a function of ion energyforthree dopants. 64 Forexample, 100
keV boron implantation requires a silicon nitride mask thickness of at least
0.4 microns, an Si0 2 thickness of at least 0.55 microns, and a minimum
photoresist thickness of 0.7 microns. One problem in using photoresist as
a mask is that at dosesgreaterthan 1015/cm 2 , the resist mask may become
difficult to etch. The chemical changes that the bombardment creates can
depolymerize the resist, causing swelling and thickness changes by up to
40%.
In order to understand the sensitivity of mask thickness on the percent
of ions that may penetrate that mask, reference is made to Figure 60. 66
Here, photoresist thickness is plotted as a function of ion implantation
energy in a family of curves showing the percent ion penetration through
the mask as a parameter. Increasing the mask thickness from 0.45 microns
524 Semiconductor Materials

1.0r---------------~

.1
c:
o

Ic:
o
":;
r:r:.o.~

~ )
"0

'0
et .01

.001 L . - - --4-- -----'

10 100 1000
Energy (keV)

Figure 58: Calculated projected standard deviation in microns as a function of

an implant energy in kiloelectron volts for four important sil icon dopants.

to 0.6 microns can reduce the ion penetration percentage from 100/0 to
0.01 0/0 at 100 keV.
Energetic ions penetrating masks can "knock" atoms of the mask into
the underlying silicon. Thus, the role of the mask in the ion implantation
process is not necessarily a neutral one. This knock-on effect may nucleate
damage in the silicon. An example for phosphorus into Si 3 N4 is shown in
Figure 61. Concentration profiles of implanted phosphorus and recoiled
nirtogen in silicon are shown as a function of the thickness of the Si 3 N4
mask. It can be seen that the measured nitrogen profiles form an exponential
d,istribution whose surface concentration is approximately 1X 1020 atoms/
cm 3 . This concentration is many times above the solid solubility of nitrogen
in silicon at high temperatures. Thus the excess nitrogen has the potential
for nucleating damage which may grow during high temperature annealing.
Another example of knock-on damage caused by implantation through a
masking layer is shown in Figure 62. This shows a schematic diagram of
oxygen recoil damage caused by implantation through an Si0 2 layer. 57
Areas where recoil damage can occur are at tapers in the Si0 2 edges and
where the oxide is very thin. In both cases recoiled oxygen can penetrate
 Diffusion and Ion Implantation 525

(a)

~M~Sk I
L J
I

'.0 (b)
Phosphorus
Boron
.0,.L--_....L.-_~~--&....1-_.....&-_--L ...............--'
10 100 1000
Energy (keV)
ell
c:
E 2.0 tj
.3 (c) :.c
l-
NO.'
ell 1.0 o
c:
tj Cii
:.c E
:;,
l-
E
cc 'c
u.
I- ~
~

E
:;,
E
'c
~
0.11------~---I..---------I .0 '1L..---.J.-&.-L...-JI--&-..a...4..L..I,u.---..'---..Io--......-_....""":"000
10 '00 1000 0 00 1
Energy (keV) Energy (keV)

Figure 59: Minimum masking material thicknesses for the ion implantation of
boron, phosphorus and arsenic.

0.01%

1.0

o. 1 1--_---L._......L---J,.---li....---+._.L--..L.-..L.-L.-1.......L-_ _L..----.1._...L-...L-_..L.-~
.....................1_'__&

10 100 1000
Energy (keV)

Figure 60: Percent of S+ ions penetrating photoresist VS. energy.

526 Semiconductor Materials

6 480 A Si 3 N 4

• 650 A

x 1200 A
20
10 ---
-)(.

-
6_X.

-- .lC..
6-
-fIiI..

]. 10 19 _
-
6-./
c:
o -
6_
)( 6

-
I
u

dY N

-
I:!.

I:!.
10 17 1.--_-L'_----L'_-JIl--_l--'_..1-'_-l-'_---J
0.1 0.2 0.3 0.4 0.5 0.6
Depth (J.i.m)

Figure 61: Concentration profiles of phosphorus and recoiled nitrogen in sili-

con for ion implantation through silicon nitride of 480,650, and 1200A thick-
ness at 160 ke V to a dose of 1 X 10 16 ions/cm 2 .

• Implanted Atom
o Oxygen Recoil Atom

Thick
Oxide

Thin
Oxide

o
) LD Silicon

Recoil Dam age t Implant Damage t t

Recoil
Damage Free

Damage

Figure 62: A schematic diagram of oxygen recoil damage caused by implanta-

tion through a silicon dioxide masking layer. Taper at Si0 2 edges can cause
knock-on of oxygen atoms. Damage regions may result and any metallic precipi-
tation in these regions will cause degradation of junctions.
 Diffusion and Ion Implantation 527

into the silicon substrate. The high concentration of recoiled oxygen

atoms in the substrate may cause the atoms to precipitate during high
temperature processing which can nucleate the growth of extrinsic dislo-
cations around the oxygen precipitates. 68 If the ion implanted dopant
forms a junction whose space charge layer intersects this damage, leaky
or shorted junctions may result.

Ion Channeling
Until about 1960 it was tacitly assumed that ion penetration in crystal-
line substrates would not differ substantially from that in amorphous
solids, and there was little or no experimental evidence to suggest that the
regular structure of a crystal lattice was significant in atomic stopping. It is
now known that low-index crystal axes or planes present large open or
transparent avenues for the incident ions, and fewer atoms are exposed to
the bombarding particles, resulting in the reduction of the number of
atomic collisions 64 . An example of this effect is shown in Figure 63 where
views are presented of the <11 0> direction (open channels) vs. a random
direction viewed at 10° from the <110> direction. Thus, if an ion beam is
aligned along the <110> direction one would expect a much deeper

(110)

10° off (110)

Figure 63: Atomic configuration in the diamond-type lattice (a) along the <110>
direction, and (b) viewed along a "random" direction at 10° from the <110>
direction.
528 Semiconductor Materials

penetration by that ion. Once the ion is inserted into a channel, the atomic
potentials become operative and steer the ion towards the center of the
open space or channel. The ion can be guided along the channel over
considerable distances. Examples of channeling are shown in Figure 64
for potassium implanted into tungsten in the <111> direction and for
phosphorus implanted into silicon in various orientations of the crystal off
the <110> direction. In Figure 64a the portion of the curve labeled A
represents the region of the crystal where the implanted ions strike
surface atoms and no channeling occurs. Region B is where partial chan-
neling and Region C is where full chaneling occurs. Channeling is purposely
avoided in most devices because it is difficult to accurately control. Thus
implants are usually performed with the wafer tilted to get random "amorph-
ous" like profiles. As an example, a 7° tilt off the <110> axis allows more
than 99% of the ions to be stopped, as if the silicon were amorphous.

Modeling Implanted Dopants in Silicon

The Lindhard, Scharff and Schiott(LSS) range theory65 can predict the
ranges of implanted ions into solids under conditions in which the target is
amorphous or oriented in a random ordered crystal lattice direction which
appears amorphous to the incident ions. 69 -72 Prediction of the range of
ions which are either initially channeled or become channeled is difficult.71 -73
Rigorous calculations using the Boltzmann's Transport Equation and the
Monte Carlo Method, which calculate individual ion trajectories, have
been found to be insufficient for complex and fine structured targets.7 5 In
addition, implant profiles are difficult to calculate due to dynamic anneal
effects and time-dependent amorphization of the substrate. As a result, in
order for modeling calculations to reasonably represent implanted profiles,
either the silicon substrate should be amorphous prior to implantation
(especially for boron) or the modeling should be modified to use experi-
mental data. Modeled profiles have been calculated by su mming a Gaussian
distribution and an exponential rJistribution. The exponential function was
described by parameters extracted from as-implanted (unannealed) profiles.
Theoretical predictions for implanted ions served as a basis for graphing
the profile parameters as functions of implantation conditions. Formulae
for the profile parameters were then derived from the graphs. These
equations were incorporated in computer programs which calculated as-
implanted concentration profiles of As ions implanted into <100> and
<111> crystalline Si, for Band BF 2 ions implanted into < 100> and < 111 >
crystalline Si and for P ions implanted into <111> crystalline Si.
The basic shape of the desired concentration profiles for As, Band P
as-implanted profiles is the sum of the two distributions:

I' 1-
C=Cpeak exp
I
--<X-RP)2j
2~Rp2 +Ctail exp -K(x-XtaiI)em
3
(91)

The Gaussian distribution describing the distribution of ions implanted

into amorphous Si is characterized by three parameters, Cpeak, Rp and
~ Rp. The exponential distribution is characterized by three parameters,
 Diffusion and Ion Implantation 529

(a)

42 K into Tungsten
(111) direction

" Amorphous"
Range

!
A = no channeling
(strike surface atoms)
B = partial channel ing
C = full channeling

Depth

(b)

-c
Q)

~ 10- 1
E
o
..s
c:
o
.~

~
.....
c:
Q)
u
c:
o
U
a..
10- 3

Depth

Figure 64: Examples of ion channeling for (a) potassium implanted in a tung-
sten in a <111> direction and (b) phosphorus implanted into silicon in various
orientations of the crystal off the <110> direction.
530 Semiconductor Materials

Xtail, Ctail and K, and is assumed to describe the impurity profile of the
"tail" region.7 4 ,76-79 Figure 65 illustrates the method by which the estimated
values of key parameters which characterize the Gaussian and exponential
distributions of ion implanted profiles were extracted from published
figures.
The ranges of implanted ions vary sublinearly or linearly with implant
energy as shown in Figure 58. Xtail is the depth at which the channeling tail
is estimated to begin. Figures 66a and 66b are plots of the extracted Xtail
value as a function of implant energy for Band P respectively. Empirical
expressions were derived from the data and are shown drawn in the figu res
as Xtail.
Ctail is the parameter corresponding to the concentration of implanted
ions at the beginning of the tail. The normalizing ratio Ctail/Cpeak isshown
as a function of implant dose orenergy in Figures67a and 67bfor Band P.
This ratio is an indicator of the occurrence of chanelling. As channeling
occurs, Ctail approaches Cpeak. Therefore, the normalizing ratio Ctail/
Cpeak will increase. The figures indicate that an increase in dose or
increase in energy decreases the ratio Ctail/Cpeak. This agrees with
theory since crystal damage is directly proportional to the number of ions
implanted. Channeling will be minimized if the damage is sufficient for the
substrate to become amorphous. Thus, more channeling is likely at lower
doses and Ctail can approach Cpeak. With heavy ions, such asAs, the dose
to amorphize the substrate at room temperature, is approximately 2x1 0 14
ions/cm 2 . Higher doses are necessary for lighter ions such as boron and
phosphorus.

Gaussian
Cpeakt----",.._.

C peak/2.35 C t---7''---+-t-\.
tai1

Log C(x)
Concentration

o Rp DoR
/ "-X X
p tail
Depth

Figure 65: Illustrations of extracted parameters wh ich characterize the d istribu-

tion of an ion implanted impurity profile in crystalline silicon.
 Diffusion and Ion Implantation 531

1.0

Boron Xtail
0.8

0.6
o
Xtail (em x 1E-4)
0.4
o
o
0.2

o L-----l"-----L_---A-_--I-_~_--J

o 100 200 300

Energy (keV)

1.0

0.8

Phosphorus Xtail
0.6
Xtail (em x 1E-4)
0.4 o
o
o
0.2

O'--_L.----J,_---'-_---+.._.......L-_ _
o 100 200 300
Energy (keV)

Figure 66: Xtail vs. energy for (a) boron implants and (b) phosphorus implants
in <100> silicon.

The B data was not sufficiently regular to fit an equation. The average
values of Ctail/Cpeak are shown for the dose ranges indicated in the
figure. Again, for low dose ranges, Ctail/Cpeak is large indicating occurrence
of ions entering open channels.
Figure 67b shows the estimated curve of Ctail/Cpeak versus log dose
for P for a dose 2:: of 1x1 Q14 c m- 2 . Since data were unavailable for implant
doses < 1x1 Q14 cm -2, a constant value was used for Ctail/Cpeak in the
modeling programs. The data substantiate the relationship that Ctail/Cpeak
decreases as dose increases.
A large value of the exponential slope function, K, corresponds to a
steep concentration gradient in the tail region, indicative of less channeling.
Figure 68 is an illustration of the effect of an increasing slope value on the
concentration profile.
532 Semiconductor Materials

0.8
I::.. Boron <100> & <111>
0.7
I::..
0.6 Dose < 2E13 0
~
0

0.5 0
Ctail/Cpeak 0.4 II

L ~ Dose < 1E15

0
0.3 I::..
1::..0 2E13 I::..

0.2 0

I::..~ Dose> 1E15 v

0.1 /
0
~s 'I
0 100 200 300
Energy (keV)

0.3 0
Phosphorus <111 >

0.2 0

0
Ctail/Cpeak

0.1

0'-----£-----I...------J1-..---~L-----1

12 13 14 15 16 17
Log Dose

Figure 67: The normalized ratio of Ctail/Cpeak as a function of implant dose or

energy for (a) boron and (b) phosphorus.

The observed exponential tai I is due to random scatteri ng of ions along

open channeling directions of crystalline Si substrates. For low mass ions
and low energy implants, more channeling will occur. This can be understood
by noting 70 the critical channeling angle, l/J c a E1/4 for low energies and at
higher energies, l/J c a E1/2. Therefore, at lower energies the critical channel-
ing angle is larger, allowing more ions to channel. K is both a function of
dose and energy. For low implant doses, less crystal damage occurs
allowing ions to penetrate the su bstrate with fewercollisions. Therefore, at
low doses and at sufficient energy the implanted ions have a good chance
to enter an open channel. As dose increases, the crystal becomes damaged
or amorphous and less channeling occurs. K is larger for higher doses and
smaller for low doses. Low mass ions, such as B, have a greater probability
of entering channels since nuclear collisions are less likely to occur. Once
 Diffusion and Ion Implantation 533

Log Concentration

K2

o Depth (cm)

Figure 68: Illustration of the effect of an increasing exponential slope function

on the tail distribution of an implanted profile.

an ion has entered a channel the penetration is deeperfor ions with higher
energies. This corresponds to a smaller K value as energy increases.
Figures 69a and 69b relate the slope function versus implant energy
for As and B implanted ions, respectively. Figure 69a shows that for As ions
implanted into<1 00> Si, the Kvalue is more energydependentthanfor As
ions implanted into < 111> Si. The critical angle for channeling of 50 keV As
ion~ into <111 >'Si is4.4° and l/J c for< 100> Si is4.0°.7 2 The critical angle is a
measure of the steering action of the atoms that comprise the walls of the
channel. It is less likely for an ion in a channel in < 111> Si to leave than an
ion in a channel in <100>. The ability of an ion to remain in the <100>
channel at low implant energies is not as good as an ion in the <111 >
channel. Figure 69a shows calculated curves for K slope versus energy
which represent the best fit to the data for As <100> and As <111>
implants. In the case of the As <111> implants the best fit is a constant
value for K.
Figure 69b is a graph of K values calculated from B profiles as a
function of energy. The increase in K for B implants into < 100> Si fordoses
greater than 5x1 0 13 ions/cm 2 is a result of increased crystal damage and
dechanneling with increasing dose for a given implant energy. The critical
angle for channeling of a 50 keV B ions into <100> Si is 2.9° and l/Jc for
< 111 > Si is 3.2°.7 2 It can be seen that the K value is smaller for the < 111 >
Si and less dependent on implant energy than the <100> Si for implant
dose> 5x1 0 13 .
Curve fitting model parameters extracted from the experimental data
are summarized in Table 9 for B, P and As and in Table 10 for BF2 . Based
upon these parameters, representative profiles were calculated using
simple computer programs which now reside in the process simulation
program PREDICT. The calculated profiles using Equation 91 and a multi-
plicative smoothing function were compared with experimental profiles.
The smoothing function is an inverse exponential function used to join the
534 Semiconductor Materials

80 ~ Arsenic <100>

70
o Arsenic <111 >
60

K Slope 50
As<100>
(1/cm x 1E4) 40 ~~
0 ~
~
~As<111>
30
B
20
4

100 200 300

Energy (keV)

o Boron <100> dose> 5E13

40 ~ Boron <100> dose < 5E13
o
'V Boron <111> dose> 5E13
30
~B<100> Dose> 5E13
Dog
K Slope 20 ~B<111>

~--=: ~
(1/cm x 1E4)

10
B<100> Dose < 5E13

0'------.1----------'
o 100 200 300
Energy (keV)

Figure 69: K vs. energy for (a) arsenic implants into <100> and <111> crystal-
line silicon, and (b) boron implants into <100> and <111> crystalline silicon.

Gaussian distribution and the exponential distribution about the Xtail

point without having any discontinuities in the calculated profiles.
Figure 70 shows comparisons between calculated and experimental
data from published as-implanted profiles for As implanted into < 100> Si
for two doses. Examples of B implantation profiles into <111> Si were
compared by using published data80 in Figure 71.
Experimental errors on the model parameters may result from several
factors: (1) misalignment of the target 73 , (2) measurement variation in
equipment, and (3) dose rate effects. The misalignment error is illustrated
in Figure 72 using B profiles from an experiment performed by W.K. Chu,
et. al.7 3 The tilt and rotation angles of the waferwith respect tothe ion beam
 Table 9: Curve Fitting Model Parameters for Implanted B, P and As

Parameter EQuations

B p As

Rp(cm) 4.9XI0-6r:°..5-19.4XI0-6 (E< 100) 1.23XI0-7E 6.7XI0-Br:

7.24X10-7EO.783 (E<20)

~p(cm) 6.8Xl0-'t>.538 (E< 1(0) 6.4Xl0- 8E+ 4Xl0-7• <100> 9Xl0-¥·773

o
:::::h
S.8XI0- 7t>..538 (E<20) S.sXl0-8E. <111> C
en
o·
::J
ro
X
tai1
(cm) 4.2Xl0-6E°.5-7.9Xl0-6 (E<lOO) 2.2SXIO- 7E+ lXl0- 6 1.37Xl0-7E+ .03Xl0- 4 • <100> ::J
c-
o
::J
Rp + 6.5Xl0- 6 (E<20) 1.48Xl0- 7E-.OIXIO- 4, < 111 >
3
"C
iil
K(cm.. 1 ) 3.57Xl0SE-O.222(QT<SX1013. < 100» 2.2XloS(00r<3Xl0 14 • <100» 11.33Xl0~-O.708. < 100> ::J
r-+
ro
r-+
o·
.3.4XI0S(QT>3Xl0 14, <100>
::J
7.4XI0SE-O.222<00r>SXl013. < 100» 3XloS. <111>

01
SXl0SE-O.222(00r->SXl013. < 111» c.v
01
536 Semiconductor Materials

Table 10: Curve Fitting rv~odel Parameters for Implanted BF 2

Parameter Equation

Rp(cm) 5.6 x 10-7 (E x 0.22)°·844

ARp (em) 5.8 x 10-7 (E x 0.22)°.538 (~ < 2 x lOIS)
4.8 x 10-7 (E x 0.22)°.538 (Or > 2 x lOIS)
Rp + 4.2 x 10-6
7.7 x 105 (E x 0.22)-0·222 (Or > 2 x lOIS)
6.9 x 105 (E x 0.22)-0.222 (QT < 2 x lOIS)
2.5 x 106 (E x 0.22)-0·222 (E<4S)

le+20

le+19
Arsenic <100>
M
I le+18 100 keV, 7E15 Dose
o
E
~ le+17
o
~ le+16
'-
'E
~ le+15
r:::
o
U le+14

le+13 '---~-_&--~-~
o 0.1 0.2 0.3 0.4
Depth (,tm)
le+21

;)' le+20
I
E le+19 Arsenic <100>
o
---.2 le+18 100 keV, 7E14 Dose

~ le+17
E
Q)
o le+16
t:
o
U le+15

le+14

le+13 "- L--_~_~

o 0.1 0.2 0.3 0.4

Depth (ftm)

Figure 70: Examples of calculated profiles and extracted experimental data for
arnesic-implanted silicon.
 Diffusion and Ion Implantation 537

30 TA = 850°C
~ 50 t = 30 minutes
~i
p~ ,ao 150
12 2
{q, 0.7-2x10 /cm J
Ti-p.,..p +
~ , ! 200

\ ,r\~,
\
300 keV

\
M".. . \
I
E
~
Ol
c::
'0. 10 16
o
C

10 15 ~~~_"-----"---4-_"---&---4-_"---~--..L.-----"
o 0.2 0.4 0.6 0.8 1.0 1,2
Distance X (j-tm)

Figure 71: Example of modeled profile and extracted experimental data for
boron implants into crystalline silicon.

21

20

18
Log N

17

16

15
0~-~-:-----L.. _ _..I.-_-~--O....&..-5--

Figure 72: Example of modeled profile and extracted experimental data for
boron implanted at various orientations in crystalline silicon. Boron implant was
10 1 5 cm"""2, 45 ke V .
538 Semiconductor Materials

influence the implanted impurity profiles. Using the experimental data,

error measurements were calculated for the tail parameters using the
profile indicating the greatest channeling, (implantation into < 100> at 0°,
and the least channeling (random orientation at 5.5° tilt and 7° rotation).
The percentage difference in the Xtail parameter is 12%, the Ctail percentage
difference is 92%, the Ctail/Cpeak percentage difference is 89.5% and the
slope percentage difference is 33.2%.
The effect of implantation beam current was not considered in formu-
lating the models. However, this is an important factor in the channeling
effect since an increase in dose rate (or beam current) will cause an
increase in substrate temperature. 80 ,81 An increase in substrate tempera-
ture will affect the "tail" of the concentration profile by annealing out
damage occuring in the crystal. As the substrate temperature increases,
the ions which have managed to enter channels can travel deeper due to
the presence of fewer interstitial atoms which cause dechanneling events.7°

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15. J.A. Van Vechten: Lattice Defects Semicond., 1975, 1:(1974).
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17. M.L. Swanson, J.A. Davies, A.F. Quenneville, F.W. Saris, L.W. Wiggers, Radiation
Effects, 35:51 (1978).
18. S. Dannefaer, G. Hogg and D. Kerr, to be published.
19. A. Seeger, W. Frank, Conf. Ser.-Inst. Phys., 16:262 (1973).
20. J. Chicawa, S. Shirai, J. Cryst. Growth, 39:328 (1977).
21. H. Strunk, U. Gosele, B.O. Kolbesen, Appl. Phys. Lett., 34:530 (1979).
22. R.B. Fair, J.C.C. Tsai, D.G. Schimmel and W. Maszara, to be published.
23. S.T. Pantelides, R. Car, P.J. Kelly, and A. Oshryama, Amer. Phys. Soc. Meeting,
Detroit, March, 1984.
24. R.O. Simmons, R.W. Ballufi, Phys. Rev., 125:862 (1962).
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 Diffusion and Ion Implantation 539

26. G.D. Watkins, J.R. Troxell, A.P. Chatterjee, Cont. Ser. -Inst. Phys., 46:16 (1979).
27. A. Seeger, W. Frank, U. Gosele, Cont. Ser. -Inst. Phys., 46:148 (1979).
29. P.M. Petroff, A.J. R. deKock, Cryst. Growth, 30: 117 (1975).
30. U. Gosele, H. Strunk, ApI. Phys., 20:265 (1979).
31. S. Mizuo, H. Higuchi, Japan, pn. J. Appl. Phys., 20:39 (1981).
32. D.A. Antoniadis, I. Moskowitz, J. Appl. Phys., 53:9214 (1982).
33. T.Y. Tan, U. Gosele, Appl. Phys. Lett., 40:616 (1982).
34. G.D. Watkins, Effects Des Rayonnements Sur Les Semiconductors, Dunod,
Paris, 1965.
35. A. Seeger, K.P. Chik, Phys. Status Solidi, 29:455 (1968).
36. S.M. Hu, J. Appl. Phys., 45:1567 (1974).
37. R.B. Fair, J. Appl. Phys., 51 :5828 (1980).
38. U. Gosele, T.Y. Tan, Defects in Semiconductors II, edited by S. Mahajan and J.W.
Corbett, North-Holland Press, Amsterdam, 1983.
39. S. Matsumoto, Y. Ishikawa, T. Niimi, J. Appl. Phys., 1983, to be published.
40. D. Mathiot and J.C. Pfister, J. Appl. Phys., 55:3518 (1984).
41. P. Fahey, G. Barbuscia, M. Moslehi and R.W. Dutton, Appl. Phys. Lett., 46:784
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43. S. Mizuo, H. Higuchi, Japan. pn. J. Appl. Phys., 21 :281 (1982).
44. K. Taniguchi, K. Kurosawa, M. Kashiwagi, J. Electrochem. Soc. 127: 2243 (1 9aO).
45. R.B. Fair, J. Electrochem. Soc. 128:1360 (1981).
46. H. Shiraki, Japan. pn. J. Appl. Phys. 15: 1 (1976).
47. Y. Nabeta, T. Uno, S. Kubo, H. Tsukamoto,J. Electrochem. Soc. 123: 1416 (1976).
48. L. Kalinowski, R. Sequin, Appl. Phys. Lett. 35:211 (1979)
49. G. Hettich, H. Mehrer, K. Maier, Int. Cont. Defects Radiat. Eff. Semicond. 500
(1978).
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51. D. Shaw, Phys. Status Solidi B. 72:11 (1975).
52. R.B. Fair, Semiconductor Silicon 1977, edited by H.R. Huff and E. Sirtl, The
Electrochem. Soc., 1978.
53. R. B. Fair, Impurity Diffusion and Oxidation of Silicon, edited by D. Kahng,
Academic Press, New York, 1981.
54. S.M. Hu, Phys. Status Solidi B, 60:595 (1973).
55. F. Seitz, Acta Crystallogr. 3:355 (1950).
56. P. Baruch, J. Monnier, B. Blanchard, Castaing, C., Appl. Phys. Lett. 26:77 (1975).
57. R.B. Fair, G.R. Weber, J. Appl. Phys. 44:273 (1973).
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60. R.M. Harris and D.A. Antoniadis, Appl. Phys. Lett. 43:937 (1983).
61. K. Nishi and D.A. Antoniadis, unpublished.
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63. After Varian-Extrion, DF-3000 brochure.
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66. G. Baccarani and K.A. Pickar (unpublished 1970).
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and O.K. Brice (Plenum Press, New York, 1976) p. 319.
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(1979).
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540 Semiconductor Materials

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 8
Microlithography for VLSI

R. Fabian Pease
Stanford University
Stanford, California

INTRODUCTION
The high resolution patterning of material for the fabrication of VLSI
circuits is one of the key pacing technologies in the evolution of micro-
electronics. Feature sizes are now approaching the wavelength of light
while the patterned area extends up to 1 cm 2 for a single chip and up to 150
cm 2 over a wafer. Thus, the pattern complexity is equivalent to ten thousand
television images. However, these patterns are required to be defect free,
with feature size control of about 0.25 um. To make acomplete circuit, up to
a dozen such patterns must be overlaid with an accuracy of 0.25 um.
Projections of scaling of integrated circuit devices indicate that dimensions
may shrink by another factor of four.
For most VLSI circuits making jLJst one such pattern calls for many
steps. First a mask, a pattern of chromium on a glass substrate, is formed,
usually by electron beam lithography. After etching the pattern in the
chromium film, the mask image is projected onto a resist-coated wafer.
Following development of the resist, the pattern is transferred into the
underlying circuit material. By"lithography" we mean the generation of the
pattern in the resist. Transfering the pattern from the resist to the circuit
material is usually done by etching which is described in other chapters.
Thus, two lithographic steps are required to generate each level on the
wafer, the first to generate the mask pattern and the second the wafer
pattern.
Each lithographic step has several processes;

( i) Spin coating the workpiece with a thin (0.1-2 um) film of resist

541
542 Semiconductor Materials

(ii) Formation of the appropriate, high resolution, aerial image

through the use of a focused electron beam in the case of mask
making and an ultra-violet image of the mask forwaferexposure.
(iii) Interaction, both physical and chem ical, of the aerial image with
the resist in the exposure process.
(iv) Development of the resist pattern by selectively dissolving
away the exposed (for a positive resist) or unexposed (for a
negative) regions of the resist film.

In the sections below we describe these processes. We first describe

mask making in considerable detail because of its relative simplicity and
then go on to describe the more complex processes forwaferexposure.ln
the case of wafer exposure the aerial image can be formed by contact or
proximity printing but these techniques have largely been supplanted by
projection. A final section is a brief litany of emerging new technologies
together with a list of references where the reader can pu rsue these topics
further. The main thrust of this chapter is to present an account of today's
mainstream lithographic technologies.

FORMING THE RESIST FILM

Both negative and positive electron beam resist are widely used for
mask ma~ing. Because the image is built up by scanning a focused beam
sequentially over each address, the process is slow. Therefore, there is
considerable emphasis on resist sensitivity which is usually, unfortunately,
quantified as the dose in C/cm 2 required to bring about the desired
chemical change.
Negative resists are long chain polymers containing groups which, on
electron bombardment, form crosslinks between adjacent chains. 1 Such
groups include:

(1) Vinyl - CH + CH2

(11) Allyl - ClI + CH- CH 2

(iii) Epoxy - CH- CH 2

'0/

Those portions of the film that are crosslinked are insoluble in a suitably
chosen developer. Typical required doses range from 10-7 to 10- 5 C/cm 2 for
1a keV electrons.
Positive electron resists are also long-chain polymers. However, positive
resists contain groups which, on electron bombardment, cause chain
scission and hence locally reduced molecular weight. The exposed regions
are now selectively soluble in a suitably chosen developer. Examples of
such materials are poly (methyl methacrylate) (PM MA)2 and poly(butene-1
sulfone) (PBS)3. The chain scission process also results in gas evolution
which may also promote the selective solubility of the exposed regions.
 Microlithography for VLSI 543

Typical required doses are somewhat higher than those for negative
acting resist and range from 10-6 to 10-4 C/cm 2 for 10 keV electrons.
The resists as purchased are solutions of the above polymers in
volatile solvents. A few ml. of the solution are dispensed onto the center of
thewaferwhich is spun at a pre-determined rate while the solvent evaporates
to leave a polymer film of predictable thickness. The theory of the spinning
action is quite complicated because some material is lost through cen-
trifugal action and the viscosity of the remaining material changes during
evaporation of the solvent. 4 Often the thickness, t, of the remaining film is
given by the expression:
t + ks 2 /1W

where k is a constant related to viscosity

s is the solids content in the solution expressed in percent by weight.
w is the angular velocity.
For mask making the surface of the substrate must be quite flat, much
lessthanO.1 fLmoverdistancesofupt01 cmandlessthan1 fLmoverall.The
minimum thickness of the resist is set by the maximum allowable defect
density, less than one per square inch. Although there exists little quantitative
information on defect density versus resist thickness, the minimum value
is usually 0.4 um. Unlike masks, the surface of wafers may contain step
heights exceeding 1 fLm due to previous patterning steps. Resistfilm thick-
nesses of up to 2 to 3 fLm may be required to coat these surfaces uniformly.

GENERATION OF THE AERIAL IMAGE FOR

ELECTRON BEAM MASK MAKING

The image is formed by focusing a writing electron beam onto the

resist film and scanning the beam across the film in the appropriate pattern.
In general, mechanical scanning of the workpiece supplements the elec-
trical scanning of the beam. One advantage of this arrangement is that
large area electrical scanning becomes less important and makes it easier
to maintain the focus and positional accuracy of the deflected beam. The
writing strategy and a schematic view of the most widespread commercial
instrument, "EBES" developed at Bell Laboratories 5 , is shown in Figures 1
and 2. The choice of the convergence sem i-angle a is important. Too large
a value resu Its in unacceptably large beam diameters due to aberrations of
the final beam forming lens. Too small a value results in unacceptably low
beam currents due to limits of source brightness and space charge. These
limits are discussed in detail elsewhere 6 and are summarized in Figure 3.lt
should be noted that if the electron energy is increased then the beam
current can be increased proportionately. The specifications for the current
version of EBES, Perkin-Elmer's MEBES 3, are shown in Table 1. The
writing rate is 80 M Hz, or 8x1 0 7 exposed addresses per second. A rough
calculation of the exposure time indicates that at a 1/4 fLm address size the
rate comes to 2 cm 2 /minute. Also note that the optimum value of a is about
10- 2 radians. Although beam diameters of less than 5 nm have been used
544 Semiconductor Materials

~--t-- 128 Jlm

WRITING PATH WAFER

(Table motion)

(a) WRITING STRATEGY

BEAM BLANKING

LASER
BEAM DEFLECTION
INTERFEROMETER
------- -----,

~
I
I
,I
I I
I I
I .. --J
I I
I
I
I
I I

:----1 TABLE POSITION

I
I I
I
I
I
I
~~
I
POSITION ERROR
I--J
COMPUTER -1 WRITING POSITION I
(b) SCHEMATIC VIEW

Figure 1: (a) Writing strategy used in Bell Laboratories Electron Beam Exposure
System "EBES": a single stripe of the circuit pattern is read out repeatedly from
memory then is written on to each chip site. (b) Schematic view of EBES. The
feedback system employs beam deflection to compensate for table position errors
(After D.R. Herriott et al. s ).
 Microlithography for VLSI 545

L V--l . . .~--- ELECTRON SOURCE (at -V)

~ ~- ELECTRON LENS

I I· BLANKING ELECTRODES

~ DEFLECTION COILS

II~ FINAL LENS

APERTURE

BEAM OF SEMI-ANGLE
'- OF CONVERGENCE a

" ' - - WORKPIECE

Figure 2: Schematic view of an electron beam column employing two lenses

which focus a demagnified image of the source onto the workpiece. The beam
can be blanked, swept away from the aperture, by energizing the blanking elec-
trodes. The deflection coils serve to scan the beam across the workpiece while
the aperture serves to control the convergence semi-angle a. Larger values of a
lead to increased current but at the expense of larger aberration disks.

for specialized patterning 8 most mask generation is carried out with

beams diameters in the range of 0.1 to 0.5 /Lm, respective currents of 5 nA
to 300 nA and an electron energy of 10 keV.

INTERACTION OF ELECTRONS WITH THE WORKPIECE

The electrons entering the resist film not only bring about the chemical
effects alluded to earlier, but are also scattered by the film and substrate so
that the lateral extent of the interaction can exceed the diameter of the
impinging beam. This effect is known as the proximity effect and has been
the subject of large numbers of papers. The effect lends itself well to
546 Semiconductor Materials

ELECTRON-ELECTRON
INTERACTIONS
1= 1fLA
CHROMATIC
DISK DIA

de: Cc T~E a

E
c
c:
'E
"'0

CATHODE
CURRENT
DENSITY
FOR I : 10 nA

a (rad)
Figure 3: Contribution to focused electron beam diameter as a function of semi
angle of convergence a. Often the total beam diameter is estimated by adding in
quadrature the contributing diameters. The electron energy, E, is 10 keV with
energy spread ~E = 3 eV, chromatic aberration coefficient 4 em, spherical aber-
2
ration coefficient Cs = 10 ems, cathode current density 10 A/cm , and column
length 66 ems.

Table 1: Outline Specifications of a CommerciallY Available

Electron Beam Pattern Generator "MEBES 3" Manufactured by
the Perkin Elmer Corporation

Address and Beam Diameter 0.1 um to 1.1 ~m

Naxiamum WrIt ing Area 6 .1" x 6 .1"

Level-to-Level overlay Position Accuracy 0.12 um

Electron Energy 10 keV

Writing Rates 40 MHz, 80 MHz

Required Temperature Control ± O.l°C

 Microlithography for VLSI 547

modelling by a Monte-Carlo technique which has been verified byexperi-

ment. 9 ,10 Monte-Carlo simulations of 10 keV and 20 keV electrons are
shown in Figure 4. Qualitatively the extent of scattering of the electrons is
much less for the lower energy 10 keV electrons, however, the 20 keV
electrons are scattered less by the resist so that there is a sharper
concentration of energy dissipation around the point of impact. Fortunately,
for making photolithographic masks with minimum dimensions of 1.5 to 2
p,m, the use of 10 keV electrons and 0.4 p,m resist is a reasonable compro-
mise and is a widely used combination which does not require elaborate
correction for proximity effects. If either thicker resist or finer dimensions
are required, then higher electron energies and some form of local dose
variation for correction of proximity effects may become desirable. How-
ever, for most of today's mask making, the above combination of 10 keV
electrons and a resist thickness of 0.4 p,m allows us to treat the proximity
effect asjust another contribution to beam diameter. The magnitude of the
contribution can be determined by simulation 11 or by experiment 9 ,10 to be

r2
J(r) + J(o) exp (- ---2)
rp

where J r is the current density at radius r, and rp = 0.2 p,m ± 0.1 p,m forthe
case depicted in Figure 4a. At higher voltages two gaussian terms are
needed for an adequate description.
The chemical effect of electron bombardment has already been des-
cribed as generating crosslinks between adjacent polymer chains to
create an insoluble gel. We can invoke a simple model to describe quanti-
tatively the resist's behavior in terms of the parameters, sensitivity and
contrast.
The starting point of the model is to assume the following:

x- pm X - - pm
2 0 2 3 2 0 1 2 3

0
PMMA
Si
E
::t

2 2
N

3 3

4 4
(a) 10 keV (b) 20 keV

Figure 4: Trajectories of electrons scattered by a typical target comprising 0.4

pm polymeric resist on a silicon substrate. Substitution of glass as the substrate
material would give rise to a sl ightly greater extent of scattering. I I
548 Semiconductor Materials

(i) The local rate of generating crosslinks is proportional to the

local power dissipated by the electron beam.
(ii) When two or more molecules are crosslinked together they
form an insoluble group.
(iii) The number of crosslinks per unit volume obeys a Poisson
distribution.
(iv) There are many crosslin king sites per chain such that only a
negligible fraction form crosslinks at the lowest exposure
needed to crosslink virtually all molecules.
(v) Associated with each chain is a volume, Vm' within which a
crosslinking event results in a bond to a neighboring chain.
(vi) The effect of the resist material on the incoming beam is
unaffected by crosslinking, Le. the distribution of powerdissipa-
tion is constant during exposure.
(vii) The energy A(z) where z is the depth into the resist. We shall
initially assume that A is constant with depth.

For very low exposures, only isolated pairs of molecules are crosslin ked
together. On development, these pairs per se may not be dissolved, but all
the surrounding uncrosslinked material is dissolved and washed away so
that no resist remains after development. At some critical dose enough
chains are crosslinked together so that a skeletal gel is formed which
remains after the developing solvent has leeched out the uncrosslinked
polymer chains. Beyond this exposure level, we assume that each crosslink
that bonds a previously uncrossl inked molecu Ie contributes that molecu Ie
to the gel. The fractional thickness, Tn' of resist remaining after develop-
ment is equal to the fraction of (identically sized) molecules, each with the
same volume, Vm' that have at least 1 crosslink to neighboring molecules. If
Nc is the mean local concentration of crosslinks then the mean number of
crosslinks per volume Vm is NcVm. The fraction of molecules with no
crosslink to neighboring molecules is, from the Poisson distribution, exp
(-VmN c). Therefore, the local fractional thickness remaining is
Tn + 1 - exp(-VmNc)
for doses in excess of the critical dose and

where Q is the local dose (in C/cm 2 )

g is the number of crosslinks generated per eV dissipated (the
sensitivity of the resist material)
q is the electronic charge
Tn + 1 - exp(-V m Ag Q/q)
Therefore, a plot of Tn versus log10 Q can be drawn (Figure 5). The general
form is clear and understandable. At doses below the critical dose Tn = O.
 Microlithography for VLSI 549

(/)
(/) 1.0 ,.._---1
w '-
z
~
u 0.8
:r o
.... o
~ 0.6 o
-....J ....c o
u.. o
....J 0.4
~
z
0
.... 0.2
u
<
0:
U.
10- 7 10- 6
2
EXPOSURE (C-cm- )

Figure 5: Fractional thickness remaining after development Tn as function of

exposure for PGMA-co-EA negative electron resist (COP) for V = 10 kV. The
sol id Iine is the model, the circles are experimental points (Reference 12).

At increasingly higher doses, increasing numbers of molecules are cross-

linked until virtually all molecules are crosslinked together so that continued
exposure adds virtually nothing. However, the shape of the curve in Figure
5 can also be used to quantify two resist parameters. One is the sensitivity
or dose required to bring about the required value of Tn' Thus, for Tn = 0.5,
-V m Ag Q/q = In 0.5.

O.7xl.6xlO- 19
Q ... V Ag C/cm 2
m

This looks quite reasonable since when the required dose is reduced for
largerV m' a film made of larger molecules requires a smaller concentration
of crosslinks to bond them all together. Also, at large values of A the energy
dissipated per incident electron per unit depth, and g, the number of
crosslinks per eV dissipated will also tend to lower Q.
The other parameter is the contrast, or gamma, which is a measure of
the minimum ratio of exposures needed to bring about a required difference
in Tn (often a to 50 0/0). If we approximate the curve if Figure 5 as three
straight line segments (shown dotted) then the slope of the central portion
is the contrast (y) defined 'as dTn/d(log 1o Q). If this slope is equal to the
maximum slope of the solid curve then we can quantify y as

1
+ elog e + 0.85
10

Note that this value is independent of g, A, Vm . According to this simple

550 Semiconductor Materials

model the contrast of negative acting, crosslinking resists is about 0.85

and independent of their constituents. As it happens a great many negative
acting electron beam resist materials do have approximately this value of
contrast. Of course, a high value is desirable because this means that less
contrast in the aerial image is needed to bring about a given relief image in
the resist. A number of materials are reported to have values of up to 1.6.
There are a number of possible explanations. One is that those few
materials with abnormally high values are the most attractive and hence
are selected for intense study. Another is that the above simple model may
not apply so well to these few materials. For example, a highervalue of y is
obtained if we postulate that more than 2 molecules must be crosslinked
together to form an insoluble gel. Nonetheless, the simple model above
accounts for the main features of negative acting, crosslinking, electron-
beam resist. It is quite straightforward to embellish the simple model. A
spread in the values of molecularweight can be modeled as an equivalent
spread in the values of Vm . It can be determined, as has been reported
experimentally13, that this will give a lower value of y than a material with a
single value of Vm or molecularweight. A non-uniform value of A can also be
accounted for by describing each elemental layer according to the above
model. It so happens that for the case we are concerned with, 10 keV
electrons exposing 0.4 urn thick resist the assumption that A be uniform
throughout the resist thickness is not a bad one.
The negative resist most frequently used for mask making is poly
(glycidyl/methacrylate-co-ethylacrylate) referred to colloqu ially as COP.13
It has a contrast of about 0.9, close to the value predicted by ou r model, MW
of 180,000 and a g value of .01 crosslinks per eV. Determining Vm is tricky
but if we take Vm as the mean volume occupied per molecule and the
specific gravity as 1 gm/cc, then Vm ~ 2x1 0- 19 CC. From experiment and
from simulation of electron scattering, a 10 keV electron, on the average,
dissipates 1/3 of its energy in a resist film 0.4 um thick;

10t OOO 8
whence A + -4 + 10 eV/cm/electron
3xO.4xlO

whence for Tn + 0.5 Q + 3.6xlO-7 C/cm 2

This is remarkably close to the value shown in Figure 5 although a figure of

2x10- 7 C/cm 2 is usually recommended for this material.
To determine the 2-dimensional relief image obtained as a result of 10
kV electron beam of known diameter exposing a 0.4 p,m-thick negative
resist, we can employ a crude model in which the local thickness after
developing is given by the original thickness multiplied by the value of Tn
corresponding to the local energy dissipated throughout the thickness of
the resist. In practice neither this nor any other model is yet used because
the negative crosslinking resists used swell considerably on developing. A
doubling of the thickness during development has been observed. Even
with a developing solvent mixture optimized to minimize swelling the
shape of the image is set by the rheological behavior of the resist in the
developing and rinsing solvents and in the subsequent post-development
 Microlithography for VLSI 551

bake. Some example of images in negative electron resist are shown in

Figure 6. Thus these particular materials do not lend themselves either to
useful modelling or to high resolution, steep-sided patterns. For making
patterns of minimum critical dimensions of 4,um or greater, however, such
materials are in widespread use because of their sensitivity, ease of use
and adhesion.
For mask making the subsequent pattern transfer step is accomplished
by: wet etching of a 60 nm thick chromium film with a buffered ceric
ammonium nitrate solution. Thus good adhesion is necessary but a steep
sided resist profile is not.
The most frequently used positive resist material for electron beam
mask making is poly (butene 1-sulfone) ("PBS").3 The repeat unit of the
chain is:
HH
I I
-C-C-S02-
I I
H CH 2 CH 3

On irradiation by electrons, the predominant chemical reaction is chain

scission accompanied by the evolution of S02 gas. The exposed regions
can be selectively dissolved away in a solution of water and methyl iso-
amyl ketone (MIAK). The curve of Tn versus dose of 10 keV electrons
(Figure 7) indicates that the minimum require,d dose is Bx1 0- 7 C/cm 2 and
that the contrast is about 1.5. The curve shown in Figure 7 depends
critically on the development process since considerable swelling occurs
on development, though to lesser extent than with COP. Thus, a model of
the exposure and development process that has some theoretical basis
and that also reliably predicts the resulting relief image does not yet exist
for this material. To compound the issue, it is not always easy to obtain
good SEM micrographs of PBS patterns because the material is believed
to deform as a result of the electron irradiation in the SEM. At the minimum
exposure level, feature edges have very shallow slopes (Figure B), although,
with much higher exposures (20 ,uC/cm 2 at 20 kV) and modified developing,
crisp submicron features have been reported. 14 In practice, masks with
controlled feature sizes down to 1 ,um are produced using 0.4,um thick PBS
resist and 10 keV electron exposure. The linewidths have a standard
deviation of less than O.OB,um and defect densities are adequately low. As
with COP, the subsequent pattern transfer step is·wet etching of a 60 nm
chromium film with a buffered solution of ceric ammonium nitrate. Examples
of portions of chromium mask made in this way are shown in Figure 9.

EXPOSURE AND DEVELOPMENT OF

PHOTORESIST ON SEMICONDUCTOR WAFERS

We must now expose the resist on the wafer in accordance with the
mask pattern. The simplest way of accomplishing this is by contact printing
or proximity printing. The formertechnique allows excellent resolution but
is prone to defects especially when many contacts are needed to assure
accurate alignment. Thus, contact printing is not in widespread use for
 01
01
I\)

(j)
co
3
n°
o
:J
a.
c
()

0"
~

s:
~
.-+
CD
~

~
(J)

a b
Figure 6: SEM photograph of PCMS negative electron resist pattern (a) exposed with a 0.5 J.1m diameter electron beam, (b)
exposed with a 0.1 J.1m diameter electron beam (courtesy of H.S. Choong).
 Microlithography for VLSI 553

c
....
<.:)
z
z
«
:2
w
a:
en
en
w
Z
~
U
J:
....
....J 0.5
«
z
o
i=
u
«
e: 10-8

EXPOSURE - C/cm 2

Figure 7: Fractional thickness remaining after development versus exposure for

poly (butene l-sulfone) resist exposed with 10 kV electrons (Reference 3).

Figure 8: SEM photograph showing end view of an image formed by electron

exposure of PBS resist (photograph courtesy of E. Crabb and G. Eiden).
554 Semiconductor Materials

Figure 9: Two views of chromium masks made with electron beam exposure of
PBS resist (photographs courtesy of D.H. Dameron and J.P. Ballantyne).
 Microlithography for VLSI 555

VLSI. The defect problem is alleviated by proximity printing in which a gap

of 15-30 ,urn exists between mask and wafer. Unfortunately, this gap
degrades resolution so that this technique is no longer the method of
choice for high density circuit manufacture. The method now adopted is to
project an image of the mask onto the wafer by means of a lens or mirror
system. There are two main classes of projection exposure tools also
referred to as"maskaligners". Thefirst is the scanning projection aligner in
which a doubly reflecting system (Figure 10) forms an erect image over an
arc-shaped field of view. The optics are such that overthe field of view there
are essentially no aberrations for numerical aperture values (NA) up to 3.
By mechanically scanning both the mask, containing the pattern to be
transferred to the wafer, and the wafer simultaneously through the illumina-
tion over the field of view an image of the complete pattern on the mask is
transferred to the resist on the wafer. This scanning projection technology
has been in use for about eig ht years and can be used for the manufactu re
of circuits with linewidths down to less than 2 ,urn. The specifications for
one such system, the Perkin-Elmer M icralign 660 HT® are outlined in Table
2. The other form of projection aligner is usually referred to as a "stepper"

ms

Figure 10: Schematic view of doubly reflecting optics used in scanning pro-
jection printing.
556 Semiconductor Materials

Table 2: Outline Specifications for the Perkin-Elmer "Micralign 660 HT"

Scanning Projection Printer

Throughput: )00 6-inch wafers per hour

Exposing Wavelengths: 240 nm to 436 nm

Resolution: 0.9 ~m to 1.25 ~m lines and spaces

Auto-Alignment: ± 0.25 um (98% of population)

Magnification Compensation: ± 2 ~m range ± 0.25 um precision

Machine-to-Machine Overlay: ± 0.45 (98% of population)

Uptime: In excess of 90%

because the image of the mask pattern occupies only a small portion (1 x 1
cm 2 ) of the wafer area and the whole area is filled up by stepping the wafer
mechanically and repeating the exposures. Refracting focusing is usually
used for the optics. With this technique, VLSI chips with feature sizes of 1
1/4 /Lm are being manufactured. The specifications of two such steppers
are shown in Tables 3 and 4. With these techniques both positive and
negative photoresist are used although the former is becoming the most
popular.

FORMATION OF THE AERIAL

IMAGE IN PROJECTION MASK ALIGNERS

In both the scanning projection and the stepping aligners the physics
of image formation is the same. An outline of the basic scheme is shown in
Figure 11. A mask is illuminated and the projection optics focuses an
image of the mask at the wafer surface. As with electron beam lithography

Table 3: Outline Specifications of the Ultratech Model 1000 Wafer Stepper

Throughput: 24 6-inch wafers per hour

Exposing Wavelengths: 390 nm - 450 nm

Numerical Aperture: 0.315

Effective Partial Coherence: 0.45

Resolution: [0.8A(NA) • 1.1 ~m lines and spaces]

Field Size: 20 mm x 7.6 mm (max. rectangle)

Machine Alignment ± 0.26 um ( 2-sigma)

Total RMS Overlay Precision: ± 0 .35 lJm

 Microlithography for VLSI 557

Table 4: Outline Specifications of the GCA Model 63008 Wafer Stepper

Throughput: 40 150 mm wafer/hour

Alignment Precision: ± 0.15 ~m TIR. Global

Numerical Aperture: 0.30

Resolution: (working) 1.1 ~m [O.8A(NA»)

Fi,eld Size: 20 mm diam.

Exposing Wavelength: 436 nm (g line)

Magnification: 1/5 X

FOCUSING SYSTEM
MASK (MIRROR OR LENS) WAFER
PATTERN \
/
I
I
I
ac I
I
I
I
I
ILLUMINATING
RAYS APERTURE IMAGE OF MASK
DEFINING a PATTERN OF
MAGNIFICATION M

Figure 11: Basic optics required for projection printing.

the semi-angle of convergence, a, is a critical parameter although for

somewhat different reasons. Because the optical engineer can arbitrarily
control the shape of the refracting or reflecting surfaces, the images are
virtually aberration-free over the field of view. The sharpness of the aerial
image is set by diffraction, provided that the wafer surface is in the plane of
best focus. When the illumination is in the form of a planewavefront and the
mask pattern is a 1-dimensional grating whose amplitude transmissivity is
a sine wave, then there is only first order diffraction. If a is large enough to
accept these diffracted beams then, according to the Abbe principle for
microscopic image formation,15 the image is formed with full contrast at
the wafer surface. The converse is true, that if a is too small to accept the
diffracted beams then there is zero contrast at the wafer and the grating is
558 Semiconductor Materials

"unresolved". The relation between a and the maximum resolved spatial

frequency v max at the wafer is
'J sin a
max + -A--

where A is the wavelength of the exposi ng radiation. The term n si n a, where

n is the refractive index of the space between the lens and resist, is the
"numerical aperture" of the lens (NA). The early projection aligners had
NA = 0.15 but values in excess of 3 are now common. Thus with the
illumination specified and with A= 404 nm, a frequently used wavelength
available in mercury arc lamps, v = v max (Figure 12, dotted line).
IIlu mination of the above type is referred to as "coherent" illu mination.
An alternative, incoherent, form of illumination is to have manywavefronts
impinging on the mask over a wide range of angles ±ac' greater than the
angle ±a/M subtended at the mask by the lens aperture, and with no
systematic phase relations between them. Now it is possible for a ray
whose direction is -aiM to give rise to a ray diffracted by+2a/M in that both
the undiffracted and diffracted ray are accepted by the aperture and give
rise to small, but non zero, contrast for spatial frequencies of 2 v max . For
smaller spatial freq uencies a greater fraction of the incident beam will give
rise to acceptable diffracted beams and so the image contrast will approach
one. For this, incoherent, illumination the coherence factor can be de-
scribed as a= MSinaJsina. When a= 0 we have perfectly coherent illumi-
nation (our first case), when a> 1 the illumination is usually regarded as
incoherent, and intermediate cases are partially coherent. In Figure 12 are
plotted values of image contrast as functions of normalized spatial fre-
quency v N == vAF where F, the "F number", is defined as 112NA. Most mask
aligners operate with 0=0.7 because this gives the necessary high image
contrast (> 0.6) for good relief images in most resist materials. Lower

1.0

0.8 CT=O

=LL O.E:'-
....
:E
= 0.4

0.2

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

NORMALIZED SPATIAL FREQUENCY =I1AF
Figure 12: Contrast (" MTP ") of image of a bar pattern of equal lines and spaces
as a function of normalized spatial frequency for 3 different values of coherence
factor a of the illumination (from Reference 16).
 Microlithography for VLSI 559

values of a give rise to the appearance of fringes at sharp edges which is

obviously undesirable.
Asa digression we might point outthatthe human eye respondswell to
very low contrast, down to 0.05, images. Hence, Iig ht microscopes operate
with high values of a so that spatial frequencies close to 2 v max can be
resolved. Thus a mask aligner with a = 0.7, A = 0.4 p,m and NA = 0.3 might
generate resist patterns with a maximum period of 1 Iv where
v = _0,;;.,..;..;.8;;......;,N_A_ = 0.6 j.Lm- 1

or 0.8 p,m lines and spaces whereas a high resolution light microscope
objective lens with a > 1, A = 0.5 p,m, NA = 0.5 might yield a visibly resolved
image corresponding to a spatial frequency given by 1.8 v max = 1.8 p,m- 1 or
0.25 p,m lines and spaces.
The reader should be cautioned against attempting to generalize the
response of the projection optics to arbitrary mask patterns for intermediate
values of a. For a value of a = 0, the system is linear with respect to
amplitude and for a= 00 it is Iinearwith respect to intensity. For intermediate
values, the system is non-linear and extension to patterns other than a
grating pattern is tricky.16 The curves in Figure 12 are for a square wave
object with sharp transitions between zero intensity and full intensity. It is
interesting to point out (from Figure 12) that light optics with a minimum
wavelength of 190 nm, set by the transparency of the mask substrate, and
NA = 0.5 can generate images with 10% contrast at a spatial frequency of
4 p,m- 1 or 0.125 p,m lines and spaces. Such a system in practice would
require resists of much higher contrast than are presently used and reflec-
tive focusing optics of very high numerical aperture. In practice contact
printing has yielded lines of 0.2 p,m widths. 17 So, the limits to the resolution
of optical lithography are not firmly set by diffraction but by increasingly
difficult practical problems in pushing the diffraction limit further into the
submicron regime.
In modeling the aerial image formation process, we usually assume a
grating pattern and use curves similarto those of Figure 13. We are usually
interested in spatial frequencies such that only the first order diffracted
rays are accepted and so the aerial image is a sine wave of contrast
indicated by Figure 13. We can also model the case of out-of-focus images
as might occurwhen the wafer is not flat and there is no dynamic correction.
Treatment of this case is beyond the scope of this chapter, and the reader
is referred to the monograph by King. 16 The most widely used modelling
program SAMPLE18 requires as inputs the values of A, widths of exposed
and unexposed lines, NA and, in later versions, the extent of defocus.

INTERACTION OF ULTRA-VIOLET LIGHTWITH PHOTORESIST

The most commonly used wavelengths are 436 nm, 404.7 nm or less
commonly 365 nm. All 3 lines are present in mercury arc illumination.
Because the energy of the photons is insufficient to directly cause cross-
linking orchain scission, a photoactive compound (PAC) is a third compon-
560 Semiconductor Materials

STEP 1

DIAZIDE PAC
-.-
AZIDONITRENE

STEP 2

DINITRENE

H H H H H H H H H H
STEP 3 -C = C-C-C -C = -C C-C-C-C=
H H H I H
NH
POLYMER { H H I
MOLECULES -C = C-C-C-C = R
I
H H H H H
NH
I H
-C=C-C- C- C =
H H H H
~
CROSSLINKED
MOLECULES

Figure 13: Outline mechanism of crosslinking in negative photoresist (after Blais,

Reference 19).

ent incorporated, the other two being the base polymer and the solvent,
into both negative and positive resists. In the case of negative photo-resist,
the PAC is a di-azide material which decomposes and bleaches under UV
irradiation to form nitrenes which bring about crosslin king of the base
polymer molecules (Figure 13). Positive photo-resist (PPR) also contain a
PAC with diazide groups which on UV irradiation bleaches and decomposes
to render the local base polymer, a novolak resin selectively suspectible to
dissolution by an aqueous alkaline solution.
We can model the exposure of both negative and positive photoresist
by embellishing the simple exposure model used for the exposure of
electron beam resist. The treatment follows that of Dill and co-workers. 2o -23
Initially we will treat the case where the resist is on a non-reflecting
substrate. The resist material when unexposed absorbs light quite strongly.
As the exposure proceeds, the PAC bleaches thus reducing the absorp-
tance of the resist. This effect can be seen by viewing the resist in a high
power light microscope in the reflection mode. After viewing the resist at
1000X magnification for several seconds, during which time the resist
becomes clearer, viewing the same area at 400X magnification will reveal
a small bleached area representing the area illuminated when at 1000X
magnification. Thus, unlike the case of the electron beam resist, we have
the complication that the local power dissipation varies both with depth, z,
and wi~h time, t. This behaviorcan be modelled by assigning an absorptivity
a(z,t) to the resist material, where a contains both a labile component
which decays on exposure and a non-labile component which is unaffected
by exposure.
Thus, across an elemental depth, 6,Z, the local intensity drop is given
by
I + 1 0 exp (-a~z)
 Microlithography for VLSI 561

The labile component is modeled as AM(z,t), where M is the normalized

concentration of the PAC compound and therefore, M = 1 at t = 0, at the
start of the exposure, and 0 at t = The non-labile component is a
00.

constant B. Thus
111 + I exp {[-AM(z,t) + B]~z}

We model the rate of decomposition of the photoactive compound as

being proportional to the local concentration and the local intensity such
that aM/at = l(z,t)M(z,t)C where C is a constant corresponding to the
instrinsic sensitivity of the material.
The parameters A, B, and C wh ich descri be the exposu re characteristics
of the resist can be determined by measuring the transmittance T == I(zo/I(O)
of a resist film of thickness Zo on a transparent substrate of matching
refractive index, real part. Note that 1(0) is the intensity just inside the top
surface of the resist and is related to the incident intensity, linc' by
1(0) + (I-R) line
where R is the reflection coefficient at the top surface of the resist.
Depending on the experimental arrangment a similar correction may have
to be made forthe emerging ray. For now, we will define I(zo) as the intensity
at a depth Zo just inside the resist film of thickness Zoo Because the
substrate and resist have matched refractive indices we will assume that
there is no reflected wave.
Determining A and B is quite straightforward as at t = 0

T + T(o) + exp [-(A+B)Zo]

and at t = 00

T + T(~) + exp [-BZ o ]

Determining C is a bit more tricky and involves measuring the initial rate of
change of T.
Zo
In general T + exp { - J [AM(z,t) + B] dz }

Z
°
dT(t) d
~ + - T(t) dt (
°
I AM(z,t)dz)
o
z
o 3M(z,t)
+ - T(t)A J at - dz
°
zo
At t + 0 ~~ - :~ I
t-o
+ -T(o)AC J
o
I(z,o)M(z,o)dz

Z
+ -T(o)ACl o J° exp[-Z(A+B)]dz
o
562 Semiconductor Materials

dT
dt
I +
-T(o)ACl o
A+B l-exp [-Zo(A+B)]
t-o

... C +
A+B
AI o T(o)[l-T(o)]
dT
dt
I
tao

Some values for A, B, C for a positive photoresist under different conditions

of treatment are shown in Table 5.

Table 5: Exposure Parameters A, B, C, for AZ1350 Photoresist

(Reference 21)

Exposure Wavelengths A 436 nm

Refractive Index (real) n 1.68

Labile Absorptivity A o .54 ~m-1

Non-Labile Absorptivity B 0.03 ~m-l

Intrinsic Sensitivity C 0.014 cm2 /mJ

Having determined the exposure parameters A, B, C, by measuring T

as a function of time, we can now describe the development behavior of
negative and positive photo-resists. In negative photoresist, following
Blais, 19 the fraction of azide groups decomposed after a given exposure is
1-M. If all the resulting nitrene groups have had time to react, then the
probability of 1 azide group in a diazide group bonding to a poly (isoprene)
molecule is 1-M and the probability of both azide groups bonding to
polymer molecules is (1-M)2. This implies that the bonding events are
independent. Thus the above double event corresponds to a single cross-
linking event between 2 polyisoprene molecules, assuming that the
number of crosslinking events between 2 portions of the same molecule is
negligible. We can complete our model using the treatment outlined for
negative electron resist in which any polymer molecule crosslinked to
another is assumed insoluble in the developer and vice versa. Note
however, the important difference is that to achieve Tn=1 we must have at
least as many diazide (PAC) molecules as polymer molecules. A detailed
treatment is not given here but the reader can develop the model independ-
ently by determining M(z) and then equating Nc(z) = [1-M(z)]2 X, the original
concentration of PAC molecules. Over the last 10 years there has been a
considerable decline in the popularity of negative resist. Most negative
photoresist swell considerably on development, which limits their resolu-
tion and, following postbake, exhibit sloping feature edges which are
 Microlithography for VLSI 563

unsatisfactory when dry etching is used at the following step. The thickness
versus exposure curve of a typical negative photo resist is shown in Figure
14. As with negative crosslinking electron resists, both the contrast and
the required dose are quite low, about unity and 5 mJ/cm 2 respectively.
Recently some newer materials, e.g. Selectilux®, have been reported to
exhibit better topographic characteristics. As a result, negative photoresists
may regain their popularity.
To model the development response of positive photoresist we have,
as yet, no satisfactory mechanism. We resort to an empirical determination
of the rate of etching away of the resist material as a function solely of M for
each material. The technique for measuring the etch rate, R, as a function
of M is described fully in Reference 22 and is described as
R + exp (E l + E2M + E3M2 )
Reliable and quick ways of determining developing rate37 are important
because the values obtained depend critically on many factors such as
temperature of the developer and the degree of agitation. Hence, quoted
values should only be used as examples. Some results are shown in Table 6.
Thus, we have characterized the interaction of ultra-violet light with
photoresist in terms of the resulting normalized concentration, M, of

0.8

0.6

0.4

I
100

Figure 14: Fractional thickness remaining, Tn, versus exposure for Kodak KMR
752 negative photoresist. Notice that Tn never reaches 1 suggesting that the ex-
tent of crosslinking is limited by the availability of photoactive compound (after
Blais, Reference 19).
564 Semiconductor Materials

Table 6: Development Parameter E 1E2 E 3 for AZ 1350° Photoresist

(Reference 22)
Development Process 1:1 AZ Developer: Water at 22°C

E1- 5.27

E2 - 8.19

E3 • 12.5

photoactive compound. We then described how this value of M is related,

in the case of negative resists, to the concentration of crosslinks and
hence, to Tn. In the case of positive photoresists, the etch rate in the
developer for given process conditions is treated as a unique function of M.

EXPOSURE AND DEVELOPMENT OF

PHOTORESIST FILMS ON REFLECTIVE SUBSTRATES

When the resist is on a strongly reflecting substrate, such as a metal

film, the amplitude of the reflected wave inside the resist can be comparable
with that of the forward wave. A standing wave pattern is set up with nodes at
the metal surface and at distances of integral numbers of AR/2 away from
the surface, where AR=A/N where N is the real part of the refractive index of
the resist. Thus, the resist will be preferentially exposed in layers separated
by AR/2. Because there is absorption in the resist, both the forward and
reflected wave decay as they proceed through the resist. So, the interef-
erence is strongest nearest the metal surface where the two waves have
approximately the same amplitude. This absorption can be described by
assigning to the resist material a complex refractive index ~ = n-jk, so that
k now refers to absorptivity and n is the real part of the refractive index. For
most resist materials n»k so that the n*I~I.
The case for a perfectly reflecting metal substrate is depicted in Figure
15. At each interface the relevant boundary conditions are that both
electric fields ~ and magnetic fields t1 must be continuous. The amplitude
reflection coefficient R can be determined from the true simultaneous
equation resulting from the two boundary conditions at the top interface:

1 + R+ E (l-e -j~)
2
1 - R + NE (l+e-j~)
2

where ~ + 4nZ o /A (n+jk)

l-exp(-jp) - nrl+exp(-jp)]
Whence R·to l-exp(-j~) + n[l+exp(-jep)]

The power absorbed in the film is simply 1-R2, the difference in powerofthe
incident and reflected wave, outside the resist. Thus, determining R is
 Microlithography for VLSI 565

important in knowing how much of the incident beam's power is absorbed

in the resist. Evaluating the above expression for R will indicate that as Zo is
increased IRI will be at a local maximum whenever Zo is an even multiple
of AR/4 and a minimum for an odd multiple of AR/4, anti-reflection case. The
reader may wish to check this independently for j = 0.02, N == 1.68, and
A= 404 nm. The significant conclusion is that as the resist thickness
changes by AR/4 (~ 60 nm), the power coupled into the resist can change
by a factor of 2 or 3. Thus, there are two serious effects of the reflected
wave; one is to cause a layered pattern to the exposure and the other is to
make the total exposure a very sensitive function of resist thickness.
Unfortunately, except at the first lithographic level, wafer surfaces are
rarely flat and the resist thickness varies greatly at steps in the wafer
surface, often resulting in serious variations in resist linewidth (Figure 16).
One way to alleviate the layering effect is to bake the resist after exposure
and before developing. This is thought to promote diffusion of the remaining
PAC and hence homogenize the developing rate. 24 Another effective
technique is to eliminate the reflected wave with a buffer layerof absorbing
material. This is described more fully in the section on emerging new
technologies.
In modeling programs such as SAMPLE,18 the case of reflecting
substrates can be handled and the resulting resist feature profiles pre-
dicted quite well. The first set of input parameters includes:

INCIDENT
WAVE

AIR E=1
H=H o
!E=R
H= - RHo

RESIST

METAL~~~-
~ Z-o

Figure 15: Schematic view of resist film on a perfectly reflecting metal film
(reflection coefficient = .1). The incident wave has unit amplitude and the total
ampl itude reflection coeffecient is R. At the air/resist interface both the elec-
tric field and the' magnetic field are continuous. Because of the principle of
superposition, we can treat the series of multiply reflected waves as two waves,
one traveling downwards and the other upwards. The complex phase shift ¢ =
41T ZoIA (n +j k ).
566 Semiconductor Materials

Figure 16: Linewidth variations in positive photoresist covering steps (Ref-

erence 25).

The linewidth and period of the mask pattern.

The wavelength, A, and dose in mJ/cm 2 •
The numerical aperture NA and coherence factor a of the
aligner.

The above will give the aerial image incident on the resist. We now must
supply the second set of parameters which includes:

The exposure parameters A, B, C of the resist material.

The thickness of the resist and of any underlying film (e.g.
oxide).
The complex refractive index of the resist, the underlying film
and of the substrate.

We can now determine M(z) for each value of x where x is lateral position
and Z in depth.
We now supply the parameters E1 , E2 , and E3 describing the developing
action and can determ ine the resist profile after a succession of developing
intervals. The advancing front of the etching process is controlled by the
parameters M(x,z), E1 , E2 , E3 and is modeled as a string of elemental
 Microlithography for VLSI 567

UNEXPOSED AREA EXPOSED AREA

--------------~-------------

PROF J LES OF EXPOSED AND DEVELOPED

PHOTORESIST I REFLECTING SUBSTRATE

(SI02/51)
DEVELOPING TIMES: 305 ---~""t-- .../
60s---""""'-::r4l

90
120s----.r

0.4 UM

.......l ~ ••••••••••••••••••••••••••••••••••••••••••••••• t",,:,.

Figure 17: Examples of simulated profiles of exposed and developed positive
photoresist on a reflecting substrate.

straight line segments. The point of each intersection of neighboring

segmerl~s advances a distance given by equation (1) in a direction which
bisects the angle between the normals of the two segments. 18
Some results, obtained using an early version of SAMPLE, are shown
in Figure 17. The effect of the reflecting substrate is obvious from the
scalloping of the profiles resulting from the layering of the exposure
maxima. A scanning electron micrograph, Figure 18, of positive photoresist
profiles clearly shows the scalloping of the edges obtained by exposing on
a reflecting substrate. Current versions of SAMPLE allow for multiple
wavelengths of exposing radiation, non-zero defocus, and a more sophisti-
cated description of the developing action. 26

EMERGING NEW TECHNOLOGIES

The research and development of microlithographic technologies is

an intense area of activity. Eye catching names such as "Natural Litho-
graphy", "Brushfire Lithography" and "Vote Taking Lithography" keep
emerging. Forthose wishing to study these developments the proceedings
of the annual International Symposium on Electron Ion and Photon Beams
is a good starting point. 27 Below we briefly review four of the most promising.
 568 Semiconductor Materials

Figure 18: Scanning electron micrograph of pattern in exposed and developed

positive photoresist on a reflecting substrate (courtesy of the Canon Corpora-
tion).

Multiple Level Resist 28

The principle of multiple level resist is illustrated in Figure 19. The first
level of resist is spun on in the standard manner and may indeed be a
standard resist. The action of spin coating with a thick(1-3 JLm) bottom layer
is to planarise the workpiece surface. The top surface of the bottom layer is
much smoother than the wafer surface. Thus, we can use a thin (0.4 p,m) top
layerto adequately coat the top surface. This layer is the only one sensitive
to the image of the mask pattern. Following the patterning of the top layer,
the pattern is transferred to the lowest layer by anyone of a variety of
techniques. One popular scheme is to use a thin intermediate layer such
as Si0 2 which can be easily plasma etched through the pattern in the top
level. This intermediate layer then acts as a very robust mask for ion
etching the much thicker first level. Some results are shown in Figure 20.
Although the multi-level resist structure was originally invented to
alleviate the problems of thick, sensitive, crosslinking resists in x-ray and
electron-beam lithography, it is particularly applicable to photolithography
because, in addition to allowing a thinner, more uniformly thick sensitive
layer, the lower layers can be rendered absorbing to eliminate the standing
wave effects. Thus we can now greatly improve the linewidth control at
 Microlithography for VLSI 569

AERIAL
.+ * ili
_---'-----'_ _---'---:.-_ _---'
+J t .:
I MAGE
TOP LAY E R

1 BOTTOM
\ LAYER
1'-7-r...,......,....-;--r"7~.....,........,-~

»//1:~/»/~;///:} SUBSTRATE

b)

Figure 19: Principle of multi-level resist. The spin-on bottom layer is much
thicker than any step height and presents a much flatter surface for the top
radiation-sensitive layer. Following patterning of the top layer, by the aerial
image, the bottom layer is patterned by some technique, e.g., ion beam etching,
not sensitive to variations in larger thickness. Often a 3rd intermediate layer
is used to provide a robust mask for etching the bottom layer.

Figure 20: A tri-Ievel resist pattern formed by electron beam lithography of the
top layer (PBS resist) followed by reactive ion etching of an intermediate (800 A
silicon) layer and then oxygen ion etching of the lowest layer of overbaked (200°C
for 30 min) AZ1470 resist (photograph courtesy of E. Crabbe and G. Eiden).
570 Semiconductor Materials

steps over reflecting substrates (Figure 21). The first reported manufactur-
ing appl ication of the multi-layer resist scheme was in the production of the
CPU chip for the Hewlett Packard 9000 computer. 29 Stepper projection
lithog raphy was used to generate the critical levels which have a half-pitch
of only 1.25 p.m.

Electron-Beam Direct Write 30

Electron beam pattern generators have been used to generate patterns
directly on resist-coated wafers since the mid 1960s. The advantages are
that no mask is needed and feature sizes and overlay errors can each be
less than 0.1 p.m. The disadvantage is that the throughput is very low. Thus
one obvious application has been in fabricating individual devices for
research.
Since 1975 this technique has also been used for the production of
chips that are only needed in limited quantity. The first machines used for
this application could expose twenty 21/4/-diameter wafers per hour. 31
This throughput was achieved by projecting a shaped beam onto thewafer
surface so that many address were exposed simultaneously. The draw-
backs were that the minimum feature was 2.5 p'm x 2.5 p.m and that
linewidth control was not particularlygood.ln more recent machines these
disadvantages have been overcome by a novel electron optical arrange-
ment in which the shape can be varied electronically. Typically, the shape

Figure 21: Optically exposed tri-Ievel resist covering aluminum steps. Note the
greatly improved linewidth control compared with that shown in Figure 16 (SEM
photograph courtesy of M.M. O'Tool, E.D. Liu, M.S. Chang) (Reference 25).
 Microlithography for VLSI 571

is a rectangle with dimensions that range from 0.5 x 0.4 p.m 2 to 2 x 2 ,um 2
with changes taking place is less than 1 ,uS.32 The specifications of a
recently announced commercial instrument are shown in Table 7.

Table 7: Outline Specification of the Perkin-Elmer AEBLE - 150 Electron

Beam Direct Write System
Writing Strategy: Vector-scant variable-shape beam

Electron Energy: 20 keV

Throughput: up to 30 4-1nch wafers per hour

Current Density: 200 A/cm 2 at minimum feature size

Minimum Feature Size: 0.5 ~m x 0.5 ~m

Overlay Accuracy: ± 0.15 ~m 3-sigma

Critical Dimension Accuracy: 0.08 ~m

X-Ray Lithography 33
This is an approach to combine sub-optical resolution with parallel
processing. The principle, outlined in Figure 22 is proximity printing with

MASK
A •

SUBSTRATE ABSORBER]

Figure 22: Principle of X-ray lithography. Because point projection is used the
sharpness of feature edges is set by penumbra as well as by photoelectron gene-
ration. Varying the mask-to-wafer gap will change the magnification and can be
used for correcting isotropic linear distortion but uncontrolled local variations
will cause placement errors.
572 Semiconductor Materials

Figure 23: Elimination of the effect of mask defects by vote taking: (a) micro-
graph of a grossly defective portion of reticle mask showing both positive and
negative defects, (b) micrograph of corresponding wafer resist pattern showing
effective correction by using four mask fields per chip field.
 Microlithography for VLSI 573

the mask consisting of a thin, x-ray transparent membrane supporting a

pattern of metal thick enough to absorb most of the incident x-ray beam.
One of the best known of the many variations is a mask membrane of boron
nitride and polyimide and an absorber pattern orO. 7 }lm-thick gold. The x-
ray wavelength is 4.36 Agenerated by electron bombardment of a station-
ary, water cooled, palladium target. The main problem is making a mask
which is defect free, distortion free and exhibits less than 0.1 }lm linewidth
errors in the 0.7 }lm - thick gold absorber pattern. Other problems have
been in developing an attractive combination of resist and source. The use
of chlorine in the resist greatly improves sensitivity to the 4.36 A-wave-
length radiation and the use of multi-level resist structures allows such a
resist to exhibit good Iinewidth control. Exposure times of less than 1
minute per wafer have been reported for this system. 34 The use of novel x-
ray sources such as plasma sources and synchrotron radiation is under
active study. Very intense sources allow a greater choice of resist without
sacrificing speed. In addition, synchrotron radiation, offers much better
collimation of the beam to reduce placement error. 35

Vote Taking Lithograph y 36

One of the drawbacks of any form of Iithog raphy that involves masks is
that defects in the masks themselves lead to degraded yield. In VTL, the
effect of random defects on the masks is effectively eliminated by building
up the exposure at each chip site by exposing with at least 3 identical
patterns in the mask. If, forexample, fourmask patterns are used to build up
the chip pattern then 1 random defect corresponds to a 25% perturbation
of the illumination at the wafer. The trick is to obtain excellent overlay
accuracy of the 4 mask patterns and to have resist with sufficiently high
contrast (at least 2) that a 25% perturbation in exposure level does not
result in a printed defect. Some encouraging results are shown in Figure
23, in which both negative and positive tone defects are apparent in one of
the fields yet the resu Iting printed patterns appears adequate. The overlay
accuracy obtained is better than the specification, 0.1 }lm, of the stepper
used (U Itratech ModeI90C). This is attributed to the fact that specifications
usually refer to the overlay between different machines at different times
What makes this approach to reducing the effect of defects interesting
is that it is the first reported attempt to employ some form of error correction
through redundancy in the mask. Hopefully, other imaginative approaches
to overcoming the vexing problem of lithographic defect on the wafer will
be forthcoming.

Acknowledgments

The preparation of this paperwas largely supported by

DARPA Contract Number MDA 903-84-K-0062. The use of
material from sources other than the author's is acknowl-
edged where appropriate.
574 Semiconductor Materials

REFERENCES

1. Materials for Microlithography, Ed. L.F. Thompson, C.G. Willson, and J.M.J.
Frechet, 1984 American Chemical Society Symposium Series 266.
2. I. Haller, M. Hatzakis, and R. Srinivason, IBM J. Res. Dev. 12:251 (1968).
3. M.J. Bowden et aL, in Microcircuit Engineering, Ed. H. Ahmed and W. C. Nixon, p.
p. 239 (Cambridge University Press, 1980).
4. A.E. Emslie, F.T. Bonner, L.G. Peck, J. Appl. Phys. 29:858 (1958).
5. D.R. Herriott, R.J. Collier, D.S. Alles, and J.W. Stafford, IEEE Trans. Elec. Dev.
22:1305 (1975).
6. R.F.W. Pease, Contemporary Physics 22:265 (1981).
7. H.C. Pfeiffer, Scanning Electron Microscopy 1972, p. 113 (liT Research Institute,
1972).
8. R.E. Howard et aL, J. Vac. Sci. Tech. B1 :11 01 (1983).
9. A.A. Iranmanesh, R.F.W. Pease, C.M. Horwitz, "A Direct Experimental Determin-
ation of the Lateral Extent of Scattering of Kilovolt Electrons in a Solid Target,"
Stanford Electronics Labs. Technical Report (1980).
1O. T.H.P. Chang, J. Vac. Sci. Tech. 12:1257 (1975).
11. D.F. Kyser and N.S. Viswanathan, J. Vac. Sci. Tech. 12:1305 (1975).
12. J.P. Ballantyne, J. Vac. Sci. Tech. 12:1257 (1975).
13. L.F. Thompson, J.P. Ballantyne, E.D. Feit, J. Vac. Sci. Tech. 12:1280 (1975).
14. D.C. Shaver, unpublished communication.
15. See any college-level textbook on optics.
16. M.C. King, IEEE Transactions on Electron Devices, ED-26, 711 (1979).
17. H.C. Craighead et aL, J. Vac. Sci. Tech., B1 :1186 (1983).
18. W.G. Oldham et aL, IEEE T-ED 26:717 (1979).
19. P.O. Blais, Proc. Kodak Microelectronics Conference 1975 p. 6.
20. F.H. Dill, IEEE Trans. Elec. Dev' ED-22:440 (1975).
l

21. F.H. Dill et aL, ibid p. 445.

22. K.L. Konnerth and F.H. Dill, ibid p. 452.
23. F.H. Dill et aL, ibid p. 456.
24. E.J. Walker, ibid p. 464.
25. M.M. O'Toole et aL, Proc. of SPI E Volume 275, Semiconductor Microlithography
VI (1981).
26. D.J. Kim, W.G. Oldham, and A.R. Neureuther, IEEE Trans. Elec. Dev., ED-31: 1730
(1984).
27. Proceedings from Electron Ion and Photon Beam Symposia for 1973, 1975,
1977, 1979, 1981, 1983, 1984 are published in the following respective
issues of J. Vac. Sci. Tech.,: 10 (Nov./Dec. 1973), 12 (Nov./Dec. 1975) 15
(May/June 1978), 16 (Nov./Dec. 1979),19 (Nov./Dec. 1981), B1 (Oct./Dec.
1983, B3 (Jan./Mar. 1985).
28. J.M. Moran and D. Maydan, J. Vac. Sci. Tech. 16:1620 (1979).
29. J.M. Mikkelson et aL, ISSCC 81 Technical Digest, p. 106 (1981).
30. See, for example S. Moriya et aL, J. Vac. Sci. Tech. B1 :990 (1983).
31. H.S. Yourke and E.V. Weber, Technical Digest IEDM 76:431 (1976).
32. D.E. Davis et aL, J. Vac. Sci. Tech. B1:1 003 (1983).
33. D. Maydan et aL, IEEE Trans. Electron Dev. ED-22:429 (1975).
34. G.N. Taylor, T.M. Wolf, J.M. Moran, J. Vac. Sci. Tech. 19:872 (1981).
35. W.O. Grobman, J. Vac. Sci. Tech. B1: 1257 (1983).
36. C.C. Fu'and D.H. Dameron, Electron Device Letters EDL-5:398 (1984).
37. "Resist Characterization Using a Multichannel Development Rate Monitor."
Paper presented by Perkin Elmer, Applied Optics Div., 7421 Orangewood
Ave., Garden Grove, CA at Sixth International Technical Conference on
Photopolymers, Ellenville (1982).
9
Metallization for VLSI Interconnect
and Packaging

Paul s. Ho
IBM Thomas J. Watson Research Center
Yorktown Heights, NY

INTRODUCTION

Over the past several years, a significant fraction of the resources of

the semiconductor industry has been focused on the development of
systems with very large scale integration (VLSI). For hardware, this consists
of primarily the development of device chips and packaging architecture.
Significant progress has been made in both areas with great improvement
in the circuit density and performance. Advances in chip development are
illustrated in Figure 1 where one can see that an exponential increase in
the circuit densityfor memory and processorchips has been achieved with
time. 1 At this time, dynamic memories of 256k bit density are available on
the market and plans for manufacturing memory chips of 1 M bit density
have been announced by several companies in the United States and
Japan. Comparable progress has been made in the development of logic
chips, such as microprocessors, which have more complex structures than
the memory chips. This trend, if sustainable, indicates that development of
the 4 M bit memory chip is to be expected in this decade. This will require
the development of ultra-large-scale integration with minimum device
dimensions in the micron or even submicron range. 2
Such progress is achieved largely through continuing reduction in
device dimensions. In the course of this development, the metallization
structures of the device and packaging have evolved into one with a high
degree of complexity. It is the objective of this chapter to discuss the
implications of VLSI on metallization and some of the basic problems.

575
576 Semiconductor Materials

t Number of transistor functions

10 7

106

10 5 Memories (RAM)

60 65 70 75 80 85 90
Year of Introduction -+
Source: Siemens

Figure 1: Progress in silicon chip technology since 1960 (Source: Siemens). Note
that the degree of integration quadruples about every 3 years. While the develop-
ment in microprocessors may show after the 32 bit level, the advance in dynamic
memories remains constant (Reference 1).

Before discussing specific issues of metallization, it is instructive to illustrate

the drastic change in the metallization structure by showing in Figure 2 two
bipolar devices manufactu red about a decade apart. 3 The early device has
only one active element in a chip with a dimension of about 2.5 mm by 2.5
mm. In contrast, the contacts in the recent chip have dimensions of about 3
micron by 3 micron. If the device density can be increased simply in
accordance with the dimensions of the contacts, the number of devices for
the lattercan be increased about300X300 times. Scaling of such magnitude
was not accomplished because interconnections had to be provided to
wire the devices. To fulfill this requirement, a very large portion of the area
of this chip had to be used for the interconnect structure. As a result, this
chip contains only about 1000 active elements which is about 100 times
less than the density allowed by scalling the contact dimensions. Even
with only 1000 elements, the overall structure required for this chip is
highly complex, evolving from a simple single-level structure to one with a
multilevel architecture.
In addition to device density, interconnect is important in determining
the performance of the device chips. For example, by comparing the
dimensions of the contact to that of the intercon nect of the multi layer ch ip,
one can see that its performance is probably not limited by the switching
speed of the contacts, but rather by the time delay for signal propagation
through the interconnect.
With the increased circuit density on the chip, more device functions
can be assembled onto a single circuit board. While this provides a high
 Metallization for VLSllnterconnect 577

Cr-Cu-Au
terminal pad

AI-Si

/
Thermal oxide
(P20S· Si0 2 )

Pb-Sn
sol~er pad Cu-Sn intennetallic
Phased Cr-Cu
Cr
3.8 ,urn Sial

Silicon

Figure 2: Schematics of interconnect metallization structure for (a) an early bi-

polar device and (b) a current advanced bipolar device. Note that the size of the
chip in (a) containing one transistor is about 0.25 cm by 0.25 cm while the con-
tact dimension in (b) is about 3 pm by 3 pm (Reference 3).
578 Semiconductor Materials

degree of flexibility for the functional design of the chip, to enhance the
performance and the level of integration of the whole system, new packaging
structures are required which can utilize the high density and performance
of the device chips. This has brought forth significant improvements in the
performance and level of integration of the packaging system. As indicated
by the statistics in Figure 3, the wiring density in packaging has grown
exponentially with time, but at a rate less steep than that of the device
density.4 Although this has not been as well recognized in the past, it has
become clear recently that packaging is an important issue, particularlyfor
the high end computer systems where performance is the prevailing
factor.
This can be illustrated bycomparing the IBM 3033 and3081 computer
systems. s As shown in Figure 4, the performance of the central processing
unit, as measured by system cycle time, can be divided into chip and
packaging portions. While the cycling time in the chip has been improved
about 20%, the improvement in the packaging portion is about threefold.
(The improvement in the circuit chips should not be measured by speed
alone since there is significant enhancement in the circuit density which is
not shown in Figure 4). The improvement is achieved primarily through a

500

200

100

50

20

:.f.l 10
";j
c
·5
'- 5
~
sc..
:;
0
............ 2
:;
c..
.E
2
0-1 10 10

Maximum circuits per package component

Figure 3: Progress in circuit density with time at the packaging module level.
The abbreviations associated with the data points represent different versions of
IBM packaging modules (Reference 4).
 Metallization for VLSI Interconnect 579

new design of the interconnect module and board in the packaging

system. The distributions of the wiring structure at different levels of these
two systems are compared in Table 1a. The new designs of the module and
board provide a high level of integration which makes it possible to
eliminate a large portion of the wiring cables in the 3033 system. This
greatly simplifies the wiring structure and provides significant improvement
in the reliability as well. It is instructive to compare the number of inter-
connects for the 3081 module and its equivalent in 3033 technology. As
summarized in Table 1 b, the high level of integration in the 3081 system
makes possible a reduction of about tenfold in the number of interconnects.
Thus interconnect metallization is important in determining both the
density and performance of the system. Since these are the general goals
ofVLSI, the optimization of the metallization structure becomes an essential
part of the VLSI technology. Careful consideration should be given to not
only the layout of the interconnect but also other aspects, such as material
characteristics, processing reliability and manufacturing cost. As the trend
continues toward device miniaturization, interconnect metallization will
become even more important.
In this chapter, several basic aspects of VLSI interconnect and
packaging will be discussed. It is divided into two parts: system requirements
and material characteristics. The discussion of system requirements focuses
on the wiring structure and the impact of device scaling. The wiring
structure is a complex but fundamental issue arising from the need for
interconnecting more devices when the device density increases. Device

Board and
cable

Card

Hoard and cahle

Module
TCM

Chip
Chir

Technology

Figure 4: Comparison of system performance of the IBM 3033 and 3081 cen-
tral processing units (Reference 14).
580 Semiconductor Materials

Table 1: Comparison of the IBM 3033 and 3081 Technologies

a. Percentage distribution of total wire length by packaging level (Ref. 5).

Packaging level 3033 Processor 3081 Processor

Chip 1.3 9.2

Module 41.9

Card 38.8

Board 12.9 31.1

Cable 47.0 17.8

100°;0 1000/0

b. Average number of logic interconnections between pac caging levels in ('wo

technologies (Ref. 14).

3033 Technology

equivalent 3081 Module

Chip-lo-module 22,560 4368

22,560
Module-to-card

Card-to-board 4,000
} 670 (no card)

Total 49,120 5038

scaling imposes certain requirements on the device structure and functions

which have to be fulfilled by properly matching the materials and design of
the interconnect structure. These two topics define the general requ irements
of interconnect metallization forVLSI. With the requirements clarified, the
material characteristics of interconnect will be discussed, with emphasis
placed on the thermal and electrical properties. This will be followed by
discussions of two material reliability problems: contact resistance and
electromigration. These problems are used to illustrate the impact of
scaling on specific interconnect functions. Some of the current approaches
to solve them will be indicated. It is not the intent of this article to review the
different metallization schemes, nor specific device structures and proc-
essing developments. Some of these subjects are reviewed in other
chapters and some have been discussed in the literature. 5 ,?
 Metall ization for VLSI Interconnect 581

WIRING STRUCTURE

In Figure 2, one can see that the interconnect structure on a device

ch ip serves four main fu nctions: contact to ju nction and gate, intercon nection
between device cells, interlevel insulation, and input and output signal
pads. In a computer system, interconnect structures have to be provided to
connect the device chips to form a central processing unit as well as to
interface with other functions, e.g. storage devices, printers and terminals.
While it is beyond the scope of this chapter to discuss the overall issues of
system integration, one can readily recognize that the design of the
interconnect wiring structure is very complicated. The complexity originates
from the combinational nature of interconnecting a very large ensemble of
elements. 8 This can be readily recognized using a simple estimate that for
N elements, there ar N(N-1 )/2 possible binary connections. So, when the
number of circuit elements increases beyond about 10k on a chip, the
wiring becomes very complicated. Such an estimate overprojects the
number of interconnects required since in practice devices are not wired
randomly. Instead, the circuits are grouped in specific ways according to
their functions and the placement of various types of circuits is optimized
to reduce the number of interconnections. The nature of this problem has
been investigated by treating it as a statistical optimization process of
interconnecting a certain number of device cells subject to some overall
layout of a functional block on a logic chip.9,1o The result follows the so-
called "Rent's rule" which specifies the number of connections (or pins) P
required to wire N devices cells in a system by the following relationship.
P=aN b (1)

where a and b are parameters with a between 2 to 3 and b about 1/2 to 2/3.11
This rule can be illustrated by the results obtained by Heller et al. 10
Using a statistical simulation method, they calculated the wiring r~quire­
ments for a logic chipas a function of the gate density. As shown in Figure5,
the number of wiring tracks required follows Rent's rule with b varying from
about 1/2 at low gate density to about 213 at high gate density. This example
shows the empirical nature of the Rent's rule since its parameters vary
with the device density. The increase in b with gate density shows that the
wiring requirements actually exceeds that predicted by Rent's rule based
on low gate density.
As device density increases, there is anotherfactor contributing to the
increase in the wiring requirements. This is the increase in the average
length of each connection. This altogether with the increase in the number
of con nections causes the total wire length to increase drastically, as seen
from results obtained by Heller et al. (Figure 6). These results can be used
to estimate semi-quantitatively the impact on the wiring requirements of a
bipolar chip as the device density increases. For example, when the
number of logic circuits increases from 100 to 1000, the number of
connections required increases from 13 to 20 while the total wire length
increases by a factor of about 100. Assuming the wire track width can be
scaled proportionally according to the numbers of circuits, Le. by a factorof
582 Semiconductor Materials

20
-.J
-.J
W
U
a:
w
Cl.
(f)
~

~
a: 15
t-
w
a:
i

10 1000
10 100
GATES/CHIP

Figure 5: Results of a numerical analysis showing the" Rent/s rule" for a logic
chip. This rule correlates empirically the number of wire tracks required per cell
to the device density on a ch ip (Reference 10).

~,the total wiring area would still have to increase by a factorof~. This
indicates that as device scaling continues, the circuit layout and the chip
becomes increasingly dominated by interconnect wiring. Eventually, it will
become impossible to use all the circuits on a chip simply because some of
them cannot be wired properly.
This can be seen from the statistics of a recent bipolar chi p 12 with a
surface area of 0.29 cm 2 and a gate count of about 1500. The total length
required for wiring is 4m. With a wire channel width, line width plus line-to-
line separation, of 6.5 /lm, the total wiring area is 0.26 cm 2 , which is about
90% of the surface area of the chip. Thus the structure of this chip is clearly
dictated by the wiring requirements of the interconnect.
In the layout of the wiring structure, several factors are important to
consider in order to optimize the device performance. First, the length of
connection should be minimized. This is equivalent to minimizing the RC
response time for optimum circuit performance. Second, the layout should
minimize the cross talk in order to reduce the level of inductance noise
coming from the random switching of individual circuits. Third, it is desirable
to keep all the connections as close to the average length as possible. This
reduces the random fluctuations of the switching voltage at the contact.
Fourth, the placement of circuits should distribute the power dissipation
evenly. This is to minimize the local heating, a problem particularly important
for driver circuits. And finally, the layout should facilitate detection and
correction of errors and defects.
 Metallization for VLSI Interconnect 583

w
z
:J
AVERAGE
'+
~---=--+++-+
:+~ I
100 10 3 104
CIRCUITS/CHIP

Figure 6: The average length of interconnect and the total wire length on a logic
chip as a function of device density. The lengths are measured in circuit pitches,
i.e. the square root of the area per circuit (Reference 12).

An effective approach in meeting these requirements is to employ

multilevel interconnects. The structure of the multilevel chip in Figure 2
gives an example of a 3 level design. In this structure, all the wire tracks in
one level run in one direction while those in the adjacent level run in a
perpendicular direction. Such a structure provides a simple means to
miminize the cross talk and the average length of the interconnects.
In the design of the mu Itilevel structure, many material and processing
requirements have to be considered in addition to wiring placement. For
example, the number of levels can be reduced by packing as many lines as
possible on one level. This demands high precision and good control of the
patterning processes, such as lithography and metal etching. The use of
multilevel interconnects can relax the wiring density requirements but
causes problems in other processing areas, such as planarization and
topography of interlayer contacts. The method of dealing with these
problems often depends on the overall objective of the system desig n, e.g.
performance or cost. These factors have to be optimized together with
wiring placement.
The design of the wiring structure for the chip is only the first step to
building the interconnections of the computer system. After the chip level,
other levels of interconnections are required for assembling the chips into
the central processor and for interfacing the processor storage and
peripheral equipment. As shown schematically in Figure 7, the packaging
system has to also provide mechanical support, power, cooling, etc. in
order to assume proper function of the system. 13 The complexity of the
packaging system depends on the functional requirements of the computer.
For high end systems where the design is driven by density and performance,
584 Semiconductor Materials

Figure 7: Schematic representation for the structu re of a computer package.

This structure contains thermal and mechanical supports for the chips as well as
the high-speed interconnections that permit information exchange between chips
and peripheral equipment (Reference 13).

packaging can become very complicated and usually requires a high level
of integration and optimization. This can be illustrated by the packaging of
the IBM 3081 system. This system contains two main levels of wiring
structure: the module and the board. The module is designated as the
thermal conduction module (TCM). Each TCM contains about 100 device
chips, each of which has about 2000 circuits. It is built into a ceramic
substrate of about 5.5 mm thick and 10 cm by 10 cm square (Figure 8). The
wiring structure in the board is designed for each board to support 10
modules. 15 It has a 20-layer structure containing about 6,000 connectins
with dimensions of 60 cm by 70 cm. The wiring complexity of this board is
comparable to that of the TCM.
It is interesting to estimate the wiring requirements forthe module and
the board on the basis of Rent's rule. Taking the parameter a to be 2.5 and b
0.6, the number of interconnects required for each chip is about 250
connections for the 2000 circuits. To support the 100 chips on one module
requires 16 times the I/O connections of an individual chip. This turns out
to be about 4,000 connections for each module. These requirements
evolve the module into a structure with more than 30 interconnect layers
 Metallization for VLSI Interconnect 585

Redistrihul ion
layers

b Signal
distribution
layers

Power
distribution
layers

Figure 8: (a) Exploded view of the thermal conduction module assembly. (b)
Schematic drawing showing the wiring structure of the multilayer ceramic sub-
strate used in the thermal conduction module (Reference 14).
586 Semiconductor Materials

as shown in Figure 8. In order to optimize this structure, the layers are

organized into three levels: the wiring redistribution layer, signal redistrib-
ution layers and power distribution layers. At the board level, to connect 10
such modules with a total of 40,000 interconnects onto one board requires
about 600 con nections accordi ng to the Rent's ru Ie. Com pared with Table
1b, these estimates of 4000 interconnects per module and 600 per board
are in reasonable agreement with the nu mber of intercon nections actually
used.
The complexity of interconnect wiring necessitates the use of sophisti-
cated computer-aided design techniques. It is beyond the scope of this
article to review this important and fast developing area except to point out
that advanced methods of statistical mechanics have recently been
employed forwiring placement. Forexample, Kirkpatricketal. 16 ~mployed
a novel approach of simulated annealing based on the Monte Carlo
technique. In such simulations, most of the interconnect requirements
mentioned above can be incorporated as boundary constraints. This
method can be applied to design wiring layout on a chip as well as
interconnects between chips in a package module. An example of the
application of th is method is shown in Figure 9 where the length distributions
for an interconnect structure calculated by various statistical methods are
compared. The results obtained by simulated annealing has a narrower
"peak" distribution, indicating the method is more efficient in comparison
with other methods in placing interconnects with an average length.

200

Q) 150 1- _ _ _ _ _ .,

c
c
~
L:.
U
c 100
co
E
)(
co
~ 50
.............4._ ..
........ _....

0
0 2 4 6 8 10
3 5 7 9
Channel position
Figure 9: Histogram of the maximum wire densities within a given channel cal-
culated using various methods of interconnect routing. The channel position
provides a measure of the length of the interconnect. The top dash line repre-
sents the results obtained by the simulated annealing technique (Reference 16).
 Metallization for VLSI Interconnect 587

IMPACT OF DEVICE SCALING

In general, the aim of device scaling is twofold: first, to improve the

device performance, particularly its speed and second, to increase the
device density. These goals impose certain requirements on the function
and dimension of various components in the device, which constitute the
so-called scaling rules. The scaling rules differ for field effect transistors
(FET) and bipolar devices because of their different operating principles.
Based on a constant field approximation, Dennard et al. 17 first derived a set
of scaling rules for MOSFET devices by assuming all dimensions can be
scaled linearly. They found that as the device dimensions were reduced by
a factor of k, its performance as measured by the delay per circuit may be
enhanced by the same factor if the dopant level increases by k while the
voltage and current are reduced by k. On this basis, one can deduce the
scaling factor for other parameters pertinent to interconnect metallization,
such as the resistance, capacitance, current density, power dissipation
and etc. These factors are listed in Table 2.

Table 2: Scaling Results for Some Device Parameters

Scaling Factor

Device Parame ter FET Bipolar

Device dimension t ox ' L, W 11k 11k

Delay timelcircuit 11k 11k

Doping concentration k k

Voltage 11k - 1

Current 11k l/k-l

Power density

Capacitance 11k 11k

Line resistance k k

Line response time -1

Line current density k

Scaling of bipolar devices is more complicated because its vertical

structure and operation principle do not allow similar linearscaling employed
for FET devices. Thewide spectrum of bipolarcircuit designsadds additional
complications to deducing a general set of scaling rules. Another parameter
588 Semiconductor Materials

relevant to the discussion of interconnect is the applied voltage. Since the

switching voltage can not be less than the voltage drop across a p-n
junction, which is usually about half of the bandgap of the semiconductor
(e.g. about 0.6 eV for Si), scaling of the voltage is restricted. Indeed, the
voltage level used in devices is usually set to be a constant, chosen as a
standard by the industry. Based on constant-voltage scaling, Tang and
Solomon 18 employed device simulation techniques to analyze the effect
of scaling on device parameters. They found that for an optimum power-
delay product, the current density increases about linearly with the reduction
in device dimensions. For 12 L type circuits, Prince 19 deduced separately a
set of scaling rules based on a linear scaling of delay time. He found that
the current densityvaries approximately with the square of the dimension.
Results of these two studies lead to somewhat different scaling of device
parameters which are summarized in Table II. There are certain limitations
as to how far the scaling rules can be extrapolated before encountering
difficulty in device processing or basic physics. For example, the minimum
switching voltage in FET devices is limited by the noise level and voltage
fluctuations generated by random switching and variations in line dimen-
sions. Th is restricts the lower bou nd that the voltage level in an FET can be
reduced. Usually, the gate voltage can not be substantially reduced below
0.5 Ev. This restricts the scaling of the voltage in FET devices to a level
similar to that of the bipolar devices. Line thickness is another parameter
that can not be reduced infinitely. Practical thickness is usually not less
than about 5000 A. There are additional limitations coming from basic
device physics. 2o Such problems will affect the scaling rules, particularly
for devices with dimensions in the submicron range.
In spite of these difficulties, the resultes summarized in Table II
provide some general guidelines to examine the requirements imposed by
device scaling on the interconnect functions. For FET devices, scaling of
the device dimensions and circuit delay by k requires the doping concen-
tration to increase by k while voltage and current decrease by k. On this
basis, the response time of an isolated interconnect line will remain
unchanged. (The implication of a constant line response time on the
system performance and complications due to interference between
conductor lines will be discussed in the next section.) In addition, the 1/k
scaling of the voltage and current is balanced by the k 2 increase in device
density. This results in a constant power density for the chip although the
current density increases by k. Thus to a first order approximation, scaling
of FET devices will not change the cooling requirements at the chip level in
spite of the increase in the device density. It does require, however, the
current-carrying capability of the line to be higher.
For bipolar devices, the fact that the voltage level cannot be scaled in
accordance with the device dimension causes increases in power density
and line current density exceed the scaling factor. Depending on the
desired performance level, these two parameters can increase as much as
k2 , making the requirements for cooling and current-carrying capabilities
significantly more severe than for FET devices. These factors plus the
intrinsic complexity of the device structure make the development of an
interconnect structu re for bipolar devices considerably more difficu It than
for FETs.
 Metallization for VLSI Interconnect 589

To illustrate quantitatively the increasing demands due to device

miniaturization, the values of several key device parameters are given in
Table 3 for three stages of device development. These highlight several
key areas for future concern, including the formation of shallow contacts
with high dopant concentrations, the reliability of very thin gate insulators,
the development of conductor lines with high electromigration resistance
and the design of efficient cooling structures. While some of these problems
will be discussed in the following sections, it becomes clear that scaling
brings forth a set of requirements in addition to those from wiring placement
for the design of VLSI interconnects. In general it is difficult to design a
structure optimizing all these factors. A practical approach is to choose a
certain combination of metallization and structure to optimize some
designed functions of the system. For example, for bipolar logic circuits
where speed and power dissipation are important, the metallization should
be of low resistance and with reasonable cross-sectional area to reduce
the current density and time delay. In contrast, for FET memory chips
where density and reliability are important, the line dimensions should be
minimized with the possibility of using thermally stable but resistive
refractory metals.

Table 3: Scaling Trends in Device Dimensions

Period Line Junction Oxide Current Density

Width Depth Thickness (105 A/cm 2 )

(Jlm) (Jlm) A FET Bipolar

J
1970 s 3-6 -1 -1000 0.2-0.5 0.5-1

1980-85 1.5-3 -0.25-.5 250-500 0.5-1 2-4

Late 1980's 0.5-1.5 -.1-.25 100-250 1-2 8-15

ELECTRICAL CHARACTERISTICS

When a signal pulse is transmitted through a conductor line, a certain

amount of time is required forthe signal level to rise from zero to its original
magnitude. This rise time corresponds to the wiring delay and can be
calculated by treating the conductor as a transmission line. For the usual
situation of long pulses, i.e. pulse lengths longer or at least comparable to
the wire lengths, the rise time equals 2.3 times the RC constant, where R
and C are the resistance and capacitance of the wire respectively. The RC
constant can be expressed as follows
590 Semiconductor Materials

pL
R = U;-'
"t m

c = tWL
t
ox

(2)
and

where p is the resistivity, L the wire length, W tile wire width, t m thickness of
the wire, f the permittivity, and t ox the thickness of the oxide. Equation 2
shows that if t m and t ox can be scaled in the same manner as L, the line delay
would remain cons~ant (see Table 2 also). Therefore, the line delay becomes
an increasingly larger portion of the total circuit delay as the device
dimension decreases. Eventually it can become a substantial part or even
dominate the system response time for very small dimensions. In practice,
linearscaling is difficu It to accomplish fordevices with submicron dimensions
since t m and t ox are usually limited to aboutO.5 p'm and 1OOA respectively. In
addition, L of all the interconnects does not scale uniformly as we discussed
previously in the wiring placement section.
In general, the effect of the line delay will become a problem when the
minimum dimension reaches below about 2 p.m. The impact is less for FET
memory circuits than for bipolar logic circuits because of the bipolar
circuits more complex wiring structure. For the 3-level bipolar chip with
about 2 p'm minimum dimension shown in Figure 2, the wiring delay
constitutes a sig nificant portion of the system processing time. In addition,
for VLSI applications, the chip dimension is usually enlarged in order to
accommodate the high device density which, when combined with a more
complx wiring structure, results in broadening of the overall length distri-
bution of the interconnects. This widens the distribution in the RC time
constants with substantial increases for the portion of the wires with long
lengths.
To minimize the RC delay, it is usually important to use materials with
low resistivity and perm ittivity to bui Id the interconnect structu reo In Tables
4 and 5 are summarized some of the physical properties forthe commonly
used conductor and insulator materials. 21 ,22 (The resistivities forthin films
of these metals are not given here since they depend in general on various
parameters, e.g. method of deposition and grain structure. They are about
20-40% higherfor pure and large grain films of AI and noble metals but can
be 2 to 3 times higher for impure refractory metal films.) Because of their
excellent conductivities, it is clearwhy AI, Au and Cu are the most commonly
used metals. However, in certain applications, because of processing
requirements (e.g. the annealing temperature) or device design (e.g., the
high-density self-aligned polycide gate), materials of lesserconductivities,
such as refractory metals, silicides and even highly dOrJed polycrystalline
silicon are used.
 Metallization for VLSI Interconnect 591

Table 4: Selected Properties of Metals

(Reference 21)
Bulk Coefficient
Electrical of Thermal Thermal
Melting Resistivity Expansion Conductivity
Metal Point(OC) (lO-8n-m) (10- 6 / o C) (W/mK)

Ag 960 1.6 19.7 418.4

AI 660 2.65 23.6 220

Au 1063 2.2 14.2 297.06

Cu 1083 1.7 17.0 393.29

Pd 1552 10.8 11.0 71.13

Pt 1774 10.6 9.0 71.13

Mo 2625 5.2 5.0 146.44

W 3415 5.5 4.5 200.83

Ni 1455 6.8 13.3 92.05

Cr 1900 20 6.3 66.94

Table 5: Selected Properties of Insulators

(Reference 22)
Thermal
Thermal Conduc-
Dielectric Expansion Strength tivity
Materials Constantt (10- 6 / o C) (KPSI) (CaS)

960/0 AI 2O) 9.3 6.4 46.0 0.06

92~o Al 2 0 3 8.5 6.5 48.0 0.04

Electrical
5.5 4.4 13.0 0.004
Porcelain

Si0 2 3.8 0.6 8.0 0.005

Si 3 N 4 6.0 3.0 85.0 0.08

AI N[8] 8.8 4.5 53.3 0.02

Glass-
7.5 4.2 42.6 0.01
Ceramic [7]

t Dielectric constant is defined as the ratio of permittivity.

592 Semiconductor Materials

For the insulators, Si0 2 is the universal material used to form the
dielectric layer on circuit chips. It has a low dielectric constant of 3.5 and
can be produced with extremely low defect density by oxidizing the Si
substrate to a thickness as small as 100-200A. This makes itwell suited for
gate insulator applications although for submicron devices, there is some
question regarding the integrity of Si0 2as a gate insulatorforthicknesses
below 100A.23 For interlevel insulation, silicon oxide up to 2 fLm thick
produced by sputtering or evaporation (often not of the exact Si0 2 stoichio-
metry) is often employed. Si 3N 4 is frequently used in combination with Si0 2
in spite of its high dielectric constants. Its excellent mechanical strength
makes it well suited to serve as a lithographic masking material. Examples
of the Si 3N4/Si0 2 combined layer can be seen in Figure 2.
For packaging applications, ceramics formed byvarious combinations
of oxides, particularly AI oxides and Si oxides, are common materials. For
example, the multilayerceramic moduleshown in Figure8 employs materials
of several oxide mixtures. The ceramic materials have relatively high
dielectric constants (about 7-8) and have to be processed at elevated
temperatures (above 1500°C). Special, and often complex, processes
have to be developed for the application of this type of material forforming
multilayer structures. For example, high temperature processing neces-
sitates the use of metals with high melting points, such as the refractory
metals. This increases the response time of the system due to the high
resistivity of these metals. To circumvent these difficulties, polymeric
materials are being considered to replace the ceramics in chips as well as
in packaging. 24 The main advantages of this class of materials are the low
dielectric constant (about 3.5, similar to Si0 2) and the low processing
temperature (usually below 400°C). Higr-temperature polymers such as
Polyimides are used to satisfy processing requirements where thermal
stability up to 400°C is required.
Some of the problems relating to wiring delays for VLSI applications
have been discussed by McGreivy.25 He has considered the change of the
access time for a static NMOS (N channel) RAM with decreasing design
rules. His results are shown in Figure 10. The access time decreases
continuously with shrinking device dimensions down to about 1.5 to 2 fLm.
Below that, the effect due to the RC delay of the interconnect becomes
observable and its magnitude depends on the resistivity of the material
used. For refractory metal gates with sheet resistivities of 1 ohm per
square cm (sheet resistivity equals p/t m), a decrease in the access time can
still be achieved below 1.5 fLm although the gain is very small. The access
time is doubled what one would expect to achieve in an ideal scaling
model. For resistive polysilicon gates with 20 ohm per square cm sheet
resistivity, corresponding to a 1 fLm thick gate with 200 ohm-cm resistivity.
The access time increases with decreasing geometry due to the RC delay.
The access time becomes about an order of magn itude more than the ideal
case in the submicron range.
He has also considered the problem of parasitic capacitance. His
resu Its for the variation of the capacitance components of intercon nect as
a function of line width are shown in Figure 11. Of the three capacitance
components, only the metal-to-substrate capacitance, Cms' decreases
 Metallization for VLSI Interconnect 593

ISO r-------------------------.~---_.,

-0c
o
u
~ 100
o
c
co
c
Q)

E
~
(J)
(J)
Q)
u
u
«

(1ohm/ O )
Refractory Metal G ate _-----
------,~~s~ii;g-
o L--O.L.5----..:.:~---.L..1 ------L.2 ----'-----'--~5--.6~7~8~9~IO
Gate Length (microns)

Figure 10: Variation in the access time of a 4k NMOS RAM with decreasing de-
sign rule for gate interconnects with different resistivity (Reference 25).

with scaling. The edge capacitance is relatively constant while th parasitic

capacitance C mm increases with decreasing line pitch. The net effect is for
the total capacitance to increase in the submicron range, similar to the
resistance component although the effect is less. The end result is an
overall increase of the system access time.
There are other electrical problems related to wiring interconnects.
The broadening of the distribution in wire length mentioned already is
particularly important. The presence of a fraction of long wires will increase
the overall time delay. The length variation also introduces nonuniform RC
response time. This disturbs the switch synchronization of the system,
wh ich can be a particu larly difficu It problem for bi polar log ic ci rcu its. As lin e
pitch decreases, inductance effect due to switching of adjacent lines
increases. This generates random voltage noise which can affect device
switching. Again, the problem is more serious for bipolar logic circuits.
Most of these problems can be reduced by using multilayer structures with
wiring running orthogonally in adjacent layers. This approach is particularly
effective if combined with a statistically optimized wiring placement design,
such aswas mentioned previously. Multilayerstructures, however, require
long and complex processing steps, so the advantages will have to be
balanced against cost effectiveness and the overall design objective~.
 594 Semiconductor Materials

,-----W m
, __ "1I 4
W
(s
t-- W
~l--- m ---1-.
I

tJ~--lm~/~_ _"\
t 1
fox
SiO
2
-'-(
--.--
I
me
--!.-c ms
--r-
!
_\-"C
----r-
!
'me

Substrate

(
mm
2.0

1.5
(apaci tance
(Relative
to (
ms
at 1 micron)

1.0

t ,t = Constant
m f ox

0.5
2C
me

C
o .... ..... mm
..... ~

0.5 1.0 1.5 2.0

W,W
m s
(microns)

Figure 11: Variation of components of interconnect capacitance with design

rules. The various components are defined in the upper figure (Reference 25).
 Metallization for VLSI Interconnect 595

MATERIAL REACTION

In the multilayer structure, various materials are integrated to serve

the designed function of the device. Interfaces are formed with different
combinations of materials, such as metal-metal, metal-insulator, metal-
semiconductor and semiconductor-insulator interfaces. In addition to the
interfaces, there are structural defects in thin films, such as grain boundaries
and dislocations. The close proximity of layers, the different material types
and the presence of structural defects are all factors contributing to mass
transport in the device structure. During processing or operation of the
device, atomic transport is further enhanced by the elevated temperature
as well as by the external driving forces, such as the applied voltage or the
current density. The resultant material reactions often change the device
characteristics, giving rise to reliability problems.
The concern for device reliability will become more important as
device dimensions are reduced and more complex multilayer structures
are used. For example, a reduction in the vertical dimension of interlevel
thickness will increase interfacial reaction which can result in junction
penetration as well as a change in the dopant profile at the contact.
Discussion in this section focuses on the characteristics of materials
reactions in multilayerstructures, emphasizing the roles of atomic mobility
and driving force as well as damage formation induced by flux divergence.
In a multicomponent solid, the atomic flux can be expressed generally
as

D.
J•. = c._IF.
IkT I
(3)

where c j is the mobile conc~ntration of the ith element characterized by a

diffusivity OJ at temperature T. The driving force Fj is derived from the
gradient of the chemical potential f.li as

(4 )

The chemical potential f.lj can be expressed as

where f.lj is written as originating from the concentration c j' the internal
chem ical free energy f.lj( c j), and other external contributions, such as those
from the stress a and electric potential ¢j; v j and qj are the atomic volume
j

and charge respectively. Consequently,

F.• = kT
-vc.-V{J!.(c.)}-D.e.-q.E. (5)
C • 1 1 1 I 1 1
j

where £j and E j represent the deformation strain and the electric field
respectively.
In th is form, the d riving force in a mu Iticomponent system can orig inate
596 Semiconductor Materials

from three types of sources. The first source is related to the concentration
gradient which is generally recognized as the diffusion term. The second
force comes from the internal chemical energy gradient representing the
driving force associated with the change in the chemical form of the ith
element, e.g. the compound phase or the composition in a concentrated
alloy. The last type relates to external constraints such as an applied stress
(Tj or an electric field E j•

Combining Equations 3 and 5, it is clearthat the existence of an atomic

flux requires not only that the atoms move, i.e., Di~O, but also that there is a
nonvanishing driving force. Thus the role of the driving force is as important
as the diffusivity although the present discussion will address mainly the
diffusivity issue since the variety of driving forces makes a systematic
discussion of the role of the forces difficult. (One exception is the later
discussion on electromigration.)
The existence of an atomic flux by itself is not sufficient to cause
damage formation. In order for that to occu r, a local depletion or accu mu lation
of materials is required. This condition can be expressed by the flux
continuity equation as

c.-c~
-v.J. + _1_ _
1 (6)
1 'T

where the rate of accumulation or depletion equals the negative flux

divergence plus the rate of dissipating the excess concentration cj-c?
from equilibrium (r is the time constant for the process). In a bulk solid, the
flux divergence is usually generated by gradients of macroscopic para-
meters, such as temperature and stress. In a multilayered device structure,
it can originate from two othertypes of inhomogeneities. One is associated
with the interfaces where two different materials join, and the other is due
to the presence of microstructural defects, e.g. grain boundaries and
dislocations. These two types of structural inhomogeneities provide high
diffusivity paths for mass transport wh ich often give rise to flux divergence.
Grain boundary triple points or abrupt changes in grain size are well-
known examples of structural inhomogeneities. (See, for example, the
discussion in Reference 26.) For multilayered devices, such defects are
usually more important than the macroscopic ones since their effect on
atomic transport is significantly higher. Structural imperfections will become
even more important as further device scaling produces steepergradients
in the structure as well as closer proximity of the interfaces.
The characteristics of diffusion in thin films have been reviewed by
Balluffi and Blakely27 and Gupta and H 0 28. The diffusivities via various
defect structures can be summarized as a function of a homologous
temperature TIT m' where T m is the absolute melting point, as shown in
Figure 12 29. Using this data, the relative contributions of different diffusion
processes in thin films can be estimated. For metallic films in the device
operating temperature range of 0.3-0.6 TIT m' diffusion is dominated by
grain boundaries and dislocations instead of lattice defects (Figure 13).
For nominal films with grain size L in the 1 JLm range, i.e. log(1 IL) ~ 4, grain
boundaries usually dominate.
 Metallization for VLSI Interconnect 597

-3
THE DIFFUSIVITY SPECTRUM
FOR F:C.C. METALS
-5

-7
'0
Q)

~
N
E
~ -9
0
0\
.2
-II t-
Z
5
Q.
(!)
-13 z
5
w
:E
-15 3.0
1.0 1.4 1.8 2.2
Tm/T

Figure 12: Summary of diffusivities via various types of structural defects. The
temperature scale is normal ized to the absolute melting temperature T m (Ref-
erence 29).

6 T/Tm =0.6 ~ - - --1 T/Tm =O.5 r- - --1

4 b b
~
E 2
s
en 0
~
~
0- -2 ..l d .L d
0
.....J
-4
-6

6 T/Tm=O.4 r- ----, T/Tm=0.3 r-----,

I
r::::;:"'1
4 I
E
S 2
en
0
~ b
~
C' -2
0
.....J ..l d
-4 d
-6
0 2 4 6 8 10 12 0 2 4 6 8 10 12

Log P, (cm- 2) Log D (cm- 2)

d rd
Figure 13: Regimes of grain size (g.s.) and dislocation density Pd over which lat-
tice diffusion (I), grain boundary diffusion (b), or dislocation diffusion (d) is
dominant. The calculation is based on steady-state diffusion through a thin film
specimen of an fcc metal as a function of the homologous temperature (TIT m)
(Reference 27).
598 Semiconductor Materials

The amount of grain boundary diffusion can be estimated from the

diffusion distance (Dbt) 1/2, where Db is the grain boundary diffusivity and tis
the time. Known values of Db have been summarized for metal films in
Figure 14.30 Between 0.3T/T m and 0.6T/T m' Db is approximately 10- 15 -10- 10
cm 2s-1, taking the thickness of the grain boundary 8 to be 10-7 cm.
Accordingly, for a period of 10 3 sec., the diffusion distance in the boundary
is in the range of .01 to 1 p,m. At highertemperatures, such as those used in
device processing, about 400°C, the diffusion distance can be one to
several orders of magnitude higher. Comparing these diffusion distances
with the dimensions of submicron device structures, the diffusion distance
as estimated shows that atomic transport via structural imperfections in
about 10 min. is sufficient to cause material reaction th roughout the device
structure. Thus it is clear that the high rate of diffusion is a basic reliability
problem in VLSI technology.
This has led to the use of diffusion barriers. 31 The general approaches
include the use of single-crystal or epitaxial films, the use of amorphous
films, stuffing the boundaries with impurities or second phase particles,
and by imposing a barrier with a high activation energy for diffusion, e.g.
nitrides, carbides or oxides. Except for the last approach which is close to a
true diffusion barrier, the others often achieve the results by changing the
nature of the structural defects instead of reducing the intrinsic rate of the
diffusion process. The use of refractory metallic compound, e.g. TiN, will be
described later as an example of a barrier for reducing material reaction at
junction contacts.
The correlation between diffusivities and the absolute melting point
shown in Figure 12 provides a useful calibration for the relative thermal
stabilities of various materials used in interconnect structures. For example,
comparing AI (T m' 933°k) and refractory metals (e.g., T m of Mo, 2983°k),
equivalent stability at 0.5 T m corresponds to 200°C for AI, but about 1200°C
for Mo. For device structures requiring high-temperature reliability, the
refractory metals are significantly superior than AI and are often used in
spite of their high resistivity.

METALLIZATION RELIABILITY
Junction and Gate Contacts
The scaling results in Table 2 indicate the impact on junction properties
is to increase the contact resistance while reducing the junction depth.
This problem affects both Schottky diodes and ohmic contacts although
these two types of junctions have different reliability requirements because
of their specific circuit functions. The problem of contact resistance has
been investigated by several groups32 and the results are shown in Figure
15. The variation of the specific contact resistance Rc with a dopant
concentration, No' is comprised of two regions: the charge transport is
mainly controlled by thermionic emission for No less than 10 19 percm 3, but
by tunneling for No more than 10 19 per cm 3. To reduce the contact
resistance, it is essential to operate in the tunneling region which requires
high dopant concentrations.
 Metallization for VLSI Interconnect 599

T(K) AS FRACTION OF Tm (K)

0.90.80.70.6 0.5 0.4 0.3

~
(Ni-BULK) Ni*(o)
(Pb-BULK) Pb*(b)
(Ag-BULK)Ag*(c)
"(~u-BULK)AuM(d) *
~Au-1.2 To BULK) Au (e)
(Au-1.2To BULK) Au*(i)
"~038 exp (-17Tm /T)

""
a "
~
'<~/AI-AES(fl

'\ "
-~Y~u *(g)
Au/Ag-AES(m) \ ",
- \ ~Au-0.86CO)CU-AES
28exp(-25Tm /T) ~~ (0)

(Ni -0.5Co)Au*(n)

4.5

T(K) AS FRACTION OF Tm (K)

0.90.8070.6 0.5 04 0.3

1.0 1.5 2.0 2.5 3.0

Tm/T(K)

Figure 14: Plot of the grain boundary diffusivity against the reciprocal normal-
ized temperature T mIT for (a) data obtained by sectioning techniques in thin
films and some bulk materials and (b) data obtained by permeation techniques
in thin films (Reference 30).
600 Semiconductor Materials

300 K
- - THEORY
• P t 5 i - 5i
a Al- 5,

E 10
- I

u
I
~

u -I
ex: 10

-3
10

-~
10

5 • 10 30
~ ( 10. 10 cm 3 / 2 )
~

Figure 15: Theoretical and experimental values of specific contact resistance.

Note that for doping level exceeding 10 19 per cm 3 , Rc is dominated by the tun-
nel ing process while for doping level of 10 17 per cm 3 , thermionic emission domi-
nates and Rc becomes constant (Reference 32).

To see the effect of scaling, consider a typical contact of PtSi on n-type

Si. Even for a high dopant concentration of 10 19 cm- 3 where conduction is
dominated by tunneling, the specific contact resistivity is about 10-6 0-
cm 2 • For a contact of 3 ,umX3,um dimension, the contact resistance is about
100. It will increase to 1 00 0 when the contact size is reduced to 1 ,umX 1
,urn. An increase in resistance of this magnitude can degrade the switching
time and reduce the voltage swing to affect the normal device operation.
Since the increase is nonlinear with scaling (see Table 2), the problem
becomes even more significant for submicronjunctions. The usual remedy
forthe problem is to increase the dopant concentration to ensure conduction
by the tunneling mechanism. For example, when the doping of the PtSi
contact is increased to 10 20 cm- 3 , the resistivity is reduced by about a
factor of about 10 5. Contact junctions with such hig h dopant concentrations
have many material problems, such as the stability of the dopant profile
during processing and interfacial resistance due to contamination. Thus
one can readily understand the extensive recent interest in studying the
formation of shallow contacts with high dopant concentrations.
The concern for the selection of a metallizaion scheme extends
 Metallization for VLSI Interconnect 601

beyond the initial formation of shallow contacts. Particularly important in

this regard are the thermal stability of the contact and the retention of
shallow junction profiles during processing. It as been recognized that the
usual method of using AI to form junction contacts has severe limitations
for VLSI applications. The difficulty arises from AI penetration of the
junction as a result of the formation of AI spikes caused by Si dissolution
into A133. This is a particularly significant problem for shallow contacts
since it induces leakage current which, in severe cases, can short the
junction electrically. The incorporation of Si into AI to alleviate junction
penetration proves to be ineffective for shallow contacts since the precipi-
tation of AI doped Si at the contact interface gives rise to high contact
resistance. 34
These probl~ms led to the use of silicides to prevent AI penetration of
junction contacts. Silicides are compound phases usually formed by
reacting a deposited layer of transition metal with Si,35 Silicides have two
important advantages for forming junction contacts. First, the formation of
a silicide establishes a silicide-silicon interface below the original metal-
silicon interface, thus producing a junction interface free of processing
defects and contamination. Second, the amount of silicon consumed can
be limited by restricting the annealing time in the formation of silicide
contacts to shallow implanted junctions.
Silicides have several other material characteristics useful for integrated
circuit applications. 36 ,37 First, some silicides have electrical conductivities
exceeding heavily doped polysilicon by several orders of magnitude. The
resistivities of silicides formed on polysilicon 38 are summarized in Table 6.
Second, it can be oxidized. And third, different metals form silicide Schottky
diodes with barrier height varying from 0.5 to 0.9 eV. The combination of
these material characteristics extends the usage of silicides beyond
contact metallurgy into otherVLSI applications. Notably among these are
the use of silicides for interconnecting lines, the formation of low and high
barrier diodes in Schottky transistor logic circuits and in combination with
polysilicon for self-aligned bipolar contacts and MOS gates. 39
The use of silicides is not free of metallurgical problems. Particularly
relevant are the thermal degradation of the silicide contact 40,41 and reliability
problems associated with stress generated due to silicide formation. 42
Thermal degradation is a particular concern for the AI/silicide/Si structure
when subjected to post-metallization annealing. This step is often required
for removing process-induced damage in the insulator or during deposition
of passivation layers. Depending on the process, the temperature can
exceed 500°C for an hour or longer. The basic problem which has been
recognized for some time 40 is caused by the phase instability of silicide in
contact with AI.41 The dissociation of silicide is driven by the formation of an
AI-transition metal compound with a higher thermodynamic stability than
the silicide. This precipitates the dissociated Si (p-doped by AI) on the
silicon substrate, causing changes in the junction characteristics. The
sequence of steps in the degradation of the AI/Pd 2Si/Si junction is illustrated
schematically in Figure 16. This mechanism of junction degradation is
similar to the degradation of AI(Si)-Si contacts. Thus, it appears that the
silicide serves only as a "sacrificial" barrier to delay the reaction between
 602 Semiconductor Materials

Table 6: Resistivities of Various Silicides Formed on Polysilicon

(Reference 38)
Method of Sintering Resultant
Silicide Formation Temperature Resistivity
(OC) (",O-em)

TiSi 2 Metal on Polysilicon 900 13-16

Cosputtered Alloy 25

ZrSi 2 Metal on Polysilieon 35-40

HfSi 2 45-50

VSi 2 50-55

NbSi 2 50

TaSi 2 900, 1000 60-70, 35-40

Cosputtered Alloy 900 or 1000 50-55

CrSi 2 Metal on Polysilieon 700 -600

MoSi 2 Cosputtered Alloy 1000 -100

WSi 2 1000 -70

FeSi Metal on Polysilieon 500 150-200

FeSi 2 700 >1000

CoSi 2 Cosputtered Alloy 25

NiSi 2 Metal on Polysilieon 900 -50

Cosputtered Alloy -50-60

Pt5i Metal on Polysilicon 800 28-35

AI and Si, leaving the nature 01 .junction degradation unchanged. The

thermal stability of the AI/sil icide/Si system has been reviewed recently by
Wittmer. 43
Ironically, this necessitates the use of another barrier to protect the
silicide layer from reacting with AI. Two approaches have proven to be
effective. One is to incorporate a thermally stable internlediate layer, such
as TiW 44 or TiN45 while the other is to use phase separation to form the
barrier layer during silicide formation. 46 For example, if a PdW mixed layer
is used to form the contact, Pd 2 Si will form at the contact upon annealing
due to its faster reaction kinetics and W will separate out to form a
protective layer. In addition to being a single-step process, the consu mption
 Metallization for VLSI Interconnect 603

SCHEMATIC PRESENTATION OF
AI/Pd 2Si/Si REACTION

Pd+Si

a) INITIAL STAGE

AI/Pd
COMPOUND
AI
DIFFUSION
Pd 2 Si

b) INTERMEDIATE STAGE

AI/Pd
COMPOUND
REGROWN
Si LAYER
(AI DOPED)

c) FINAL STAGE

Figure 16: Schematic presentation of the different reaction stages in AI/Pd 2Si/Si
junctions. Note that Si precipitate can reach the contact interface before the Pd 2Si
layer is completely consumed by passing through pinholes existing in the Pd 2 Si
layer as shown in b) (Reference 41).

of silicon can be limited by reducing the concentration of the reacting

element in the mixture. A structure making use of a TiW barrier in a bipolar
device with a PtSi contact is shown in Figure 17a.
The problems associated with gate metallization systems differ from
those of contacts because the metal is not in contact with Si. Since device
density is important for MOS devices, more emphasis is placed on the
patternability and geometrical aspects of the structure, such as edge
coverage. There is a need, in addition, to reduce the resistance of the
polysilicon gate line to improve the switching time. For this purpose, the
approach of using a silicide-silicon combined layer, polyicide, has been
604 Semiconductor Materials

B E c

n+ BURIED LAYER

(0)

(b)

Figure 17: Schematic cross sections of silicide contacts to (a) bipolar and (b)
MOS devices. Note also in (b) the combined use of sil icide and polysil icon for
gate metallurgy (from Reference 43).

widely accepted. 47 One can compare the resistivities of silicides in Table VI

to those of metals in Table 4. In Figure 17b, an example of a polyicide gate
used in a recent MOS device is shown.

Electromigration
Electromigration describes the movement of atoms in a metallic
conductor induced by the passage of a direct current. Its magnitude is
determined by the atomic diffusivity and the current density. Electromigration
induced damage in the form of opens or shorts in the interconnect lines is a
result of a local divergence of the mass flux. This divergence can be
generated by various types of inhomogeneities, such as those from grain
size variation local heating and stress gradients. 48
With regard to electromigration, the main impact of scaling is to
increase the current requirements of interconnecting lines. This problem
has two basic aspects, one from the increase in the current density and the
other from the reduction in device dimensions. 49 From Table 2, the current
density is seen to increase linearly with the scaling of MOS devices and
 Metallization for VLSI Interconnect 605

more than linearly for bipolar devices. This increases the driving force for
electromigration as well as the Joule heating generated in the conductor.
With the heating increase as j2 p, the effect can be significantly higher than
the driving force coming from the linear increase in j. The combination of
these factors can raise the conductor temperature giving rise to higher
atomic diffusivity and electromigration flux. This problem, together with
the increased power density, necessitates an improvement in heat dissipa-
tion during device operation. The combined effect of these factors will
inevitably cause the electromigration flux to increase beyond that caused
by the increase in current density alone.
The increase in the current density can be estimated based on the
trend in device dimensions. For present devices with dimensions of about
3 /Lm or larger, the current density can reach 2 X 10 4 and 5 X 10 4 A/cm 2 for
MaS and bipolar devices, respectively. For the next generation of devices
with minimum line dimensions in the range of 1.5 to 3 /Lm, j increases to
about 5-10 X 10 4 for MaS and 2-4 X 10 5 for bipolars devices. This trend
continues and can result in j exceeding 10 5 and 10 6 respectively, for
submicron MaS and bipolar devices. This is an increase of 10 2-1 03times in
the current density. Since an isolated metal wire can carry only about 10 4
A/cm 2 before melting, the Joule heating generated in a line carrying 10 5
A/cm 2 must be almost completely removed through the substrate and/or
the passivating overlayer. When the current reaches rv1 0 6 A/cm 2, any
imperfection in the substrate, such as processing defects or interfacial
barriers, can cause thermal ru naway to destroy the line. Even without such
a catastrophe, the heating effects of such high current densities will
increase the rate of electromigration, resulting in a significant reduction in
the lifetime. In practice, this is reflected by an increase in the exponent n in
the lifetime equation of t 50=Aj-n exp (ilH/RT) outside the normal range
between 1 and 2. This effect adds considerable difficulty in extrapolating
the lifetime under operating conditions for submicron lines from results
obtained in accelerated stress tests. 50
The other electrom ig ration problem due to size reduction is geometry-
related and caused by scaling into the submicron range. For metal films, it
is generally observed that the grain size is about the same as the film
thickness. For a 1 /L thick film, the common thickness of interconnecting
line, there will be only a few grains spanning across a 1-3 /Lm wide line. At
the device operating temperature, the electromigration flux is confined to
grain boundaries. With a small number of the grains across the line, each
individual divergent site in the grain structure becomes potentially more
damaging since a line can fail without requiring a statistical linkage of
several divergent sites, as would be the case of a line many grains across.
This shortens the conductor lifetime while increasing the randomness of
the failure statistics, i.e. increasing the statistical deviation ain the lifetime.
Both trends have been observed in lifetests 51 as well as in computer
simulation for linewidths down to about 2 /Lm52. This effect is significant
since the extrapolated lifetime for device operation can be significantly
reduced by an increase in a.
Another effect which results from the increase in the grain size-to-line
width ratio is a decreas~ in the role of the grain boundary in mass transport.
606 Semiconductor Materials

Particularly for multilayer structures, scaling in the line width causes a

reduction in the grain boundary area per unit line length relative to surface
and interface areas. This increases the relative contributions of surfaces
and interfaces 53 to mass transport. Since these structures have diffusivities
generally exceeding that of grain boundaries, the total electromigration
rate will be increased accordingly. Even though electromigration at surfaces
and interfaces has seldomly been studied, the effect can be estimated
from the respective diffusivities. As seen from Figure 12, at aboutO.5T m' the
surface diffisivity is about 1OX that of the grain boundary diffusivity. Thus,
the total electromigration rate can be substantially increased in the multi-
layer structure if the surface and interface contribute.
In addition to the two aspects of electromigration discussed already,
one new area of concern emerges, namely the behavior of device contacts
and step coverage. In certain applications, e.g. the emitter contact in
bipolar devices, performance enhancement in scaling requires as much
dimension reduction as possible. Consequently, the emitter contact can
be subject to current densities exceeding 10 5 A/cm 2. This problem is
complicated by two factors. First, the contacts are often formed using a
combination of materials such as silicides and polysilicon. And second,
current crowding usually occurs when current flow converges vertically
into a contact. The combination of these factors will change the nature of
the divergent site, Joule heating and the local electromigration flux.
Consequently, the formation of electromigration damage at these structural
elements can be basically different from that of a metallic conductor line.
Very few studies on this aspect of electromigration have been reported,
particularly for small geometries of interest to VLSI appHcations. Although
a recent investigation 54 of AI/Si contacts reported severe effects due to
current crowding cmd Joule heating.
Studies on electromigration and life tests have been reviewed. 48 ,50
While most of these investigations have focused on AI-based metallurgy
for line widths more than 2p,m, two systems have been developed for fine
lines below 2 p,m. One is based on a grain structure modification of the AICu
metallurgy.55 Using a low Cu concentration of 0.5wt. % and suitable anneal-
ing conditions, AI lines with "bamboo" like grain structure can be formed.
With the grain boundary placed normal to the current flow, grain boundary
electromigration is greatly reduced. Lifetime of such lines at 5 p,m was
found to improve by an order of magnitude overthe same material without
specifically oriented grains. The lifetime showed a significant upward
trend with the decrease in linewidth below 2 p,m although the corresponding
a seemed to increase. The observed increase in the lifetime is opposite to
other studies 51 ,52 and was attributed to an improvement in the uniformityof
grain structures in the line. The other approach taken was to incorporate
an AI-transition metal intermetallic sandwich layer in the AICu structure. 56
The intermetallic compound was formed by reacting AI with a thin layer of
transition metal, e.g. Cr and Ti. The intermetallic layerwas found to improve
the AICu grain texture and also serve as a barrier forvoid linkage to the top
and bottom AICu layer. Between 1-2 p,m, the lifetime was found to improve
50-100 times in comparison to AICu while a remained almost unchanged.
 Metallization for VLSI Interconnect 607

SUMMARY

In this chapter, the fundamental aspects of metallization schemes for

VLSI interconnects were discussed by considering system requirements
and material characteristics. To assess system requirements, the increase
in wiring complexitywas first explored as a statistical optimization problem.
With device dimensions approaching 1 p,m, wiring placement becomes
a dominant factor in the design of the chip layout and packaging structure.
For the design of VLSI interconnects, device scaling brings forth a set of
requirements in addition tothosefrom wiring placements. The impactwas
assessed by considering the scaling rules for FET and bipolar devices,
emphasizing the increasing demands on the functional requirements of
the interconnect metallization. The discussions on material characteristics
focused on the electrical and thermal properties with emphasis placed on
the basic parameters including electrical resistivity, dielectric constant
and diffusivity.
This was followed by a discussion of two important reliability problems
in metallization, junction contacts and electromigration. The projection
based on the scaling rules makes it clear that as the device dimension
approaches about 1 p,m, there will be serious materials problems for
junction contacts and electromigration. There are two aspects of the
problem. The first is material-related because of the use of new materials
and the other geometry-related. Some approaches used to deal with these
two problems have been described.
Compared with other factors which can potentially limit VLSI develop-
ment, such as those imposed by the basic physics of the devices, inter-
connect metallization seems to be of immediate concern and will become
increasingly important. The future development of VLSI may well depend
on how successfully these problems can be overcome.

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11. 8.S. Landman and R.L. Russo, IEEE Trans. Comput. C-20:1469 (1971).
12. R.W. Keyes, Proc.IEEE69:267 (1981).
608 Semiconductor Materials

13. W.O. Grobman, J. Vac. Sci. Technol. A3:725 (1985).

14. A.J. Blodgett and D.R. Barbour, IBM J. Res. and Develop. 26:30 (1982).
15. D.P. Seraphim, IBM J. Res. and Develop. 26:37 (1982).
16. S. Kirkpatrick, C.D. Gelatt, Jr. and M.P. Vecchi, Science 220:671 (1983).
17. R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous and A.R.
LeBlanc, IEEE J. Solid State Circuits SC-9:256 (1974).
18. D.O. Tang and P.M. Solomon, IEEE J. Solid State Circuits: SC-14, 679 (1979).
19. J.L. Prince, in Very Large Scale Integration: Fundamental and Applications, ed.
by D.F. Barbe, Springer-Verlag (1982). Chp. 2.
20. See, for example, B. Hoeneisen and C.A. Mead, Solid State Electronics, 15:819
(1972); ibid 15:981 (1972).
21. Metals Handbook, 8th Ed. Vol. 1, Am. Soc. for Metals (1961).
22. B. Schwartz in Electronics Packaging Materials Science, p. 49, (E.A. Giess, K.N.
Tu and D.R. Uhlmann eds.) Materials Res. Soc., Pittsburgh (1985).
23. D.J. McGreivy in VLSI Technologies (D.J. McGreivy and K.A. Pickar eds.) p. 211-
224, IEEE Computer Society Press, Los Angeles (1982).
24. D. D. S 3raphim, L.C. Lee, B.K. Appelt, and L.L. Marsh in Electronics Packaging
Materials Science p. 21, (E.A. Giess, K.N. Tu and D.R. Uhlmann eds.)
25. D.J. ~~cGreivy in VLSI Technologies (D.J. McGreivy and K.A. Pickar eds.) p. 185-
197, IEEE Computer Society Press, Los Angeles (1982).
26. F.M. d'Heurle and R. Rosenberg, Phys. Thin Films, 7:257 (1973).
27. R.W. Balluffi and J.M. Blakely, Thin Solid Films, 25:363 (1975).
28. D. Gupta and P.S. Ho, Thin Solid Films, 72:399 (1980).
29. N.A. Gjostein in Diffusion, p. 241, Am. Society for Metals, Metals Park, Ohio
(1973).
30. D. Gupta, D.R. Campbell and P.S. Ho in Thin Films: Interdiffusion and Reactions
(J.M. Poate, K.N. Tu and J.W. Mayer eds.) p. 161, Wiley, New York (1978).
31. P.S. Ho, Thin Solid Films 96:301 (1982); R.S. Nowicki and M.A. Nicolet, Thin Solid
Films 96:317 (1982).
32. C.Y. Chang, Y.K. Fang and S.M. Sze, Solid State Electronics, 14:541 (1971);
A.Y.C. Yu, Solid State Electronics 13:239 (1970).
33. T.M. Reith and J.D. Schick, Appl. Phys. Lett. 25:524 (1974).
34. H.C. Card in Meta/-SemiconductorContacts, Inst. of Physics Conf. Series No. 22,
Manchester, England (1974).
35. KN. Tu and J.W. Mayer, in Thin Films: Interdiffusion and Reactions, ed. by J.M.
Poate, K.N. Tu and J.W. Mayer, Wiley-Interscience (1978). Chp. 10.
36. B.L. Crowder and S. Zirinsky, IEEE J. Solid State Circuits 14:291 (1979).
37. S.P. Murarka, J. Vac. Sci. Technol. 17,775 (1980).
38. S.P. Murarka, D.B. Fraser, A.K. Sinha, and H.J. Levinstein, IEEE Trans. Electron
Dev. ED-27:1409 (1980).
39. C.M. Osburn, M.Y. Tsai, S. Roberts, C.J. Lucchese and C.Y. Ting in VLSI Science
and Technology/1982, ed. C.J. Dell'Oca and W.M. Bullis, The Electrochemical
Society, Inc. (1 982), p. 21 3.
40. C.J. Kircher, J. Appl. Phys. 47:6394 (1976); H. Grinolds and G.Y. Robinson, J. Vac.
Sci. Technol. 14:75 (1977).
41. U. Koster, P.S. Ho and J.E. Lewis, J. Appl. Phys. 53:7436 (1982); ibid 53:7445
(1982).
42. F.M. d'Heurle in VLSI Science and Technology/1982 ed. C.J. Dell'Oca and W.M.
Bullis, The Electrochemical Society Inc. (1982), p. 194.
43. M. Wittmer, J. Vac. Sci. Technol. A2:273 (1984); Thin Solid Films 107:99 (1983).
44. J.A. Cunningham, P.R. Fuller and C.T. Haywood, IEEE Trans. Reliab. 19: 182
(1970).
45. C.Y. Ting and M. Wittmer, Thin Solid Films 96:327 (1982).
46. K N. Tu, J. Vac. Sci. Technol. 19:777 (1981).
 Metallization for VLSI Interconnect 609

47. C.Y. Ting, S.S. Iyer, C.M. Osburn, G.J. Hu and AM. Schweighart in VLSI Science
and Technology/1982, ed. C.J. Dell'Oca and W. M. Bullis, The Electrochemical
Society, 1982, p. 224.
48. F.M. d'Heurle and P.S. Ho in Thin Films-Interdiffusion and Reactions, ed. by
J.M. Poate, K.N. Tu and J.W. Mayer, Wiley Interscience (1978). Chp. 8.
49. P.S. Ho, IEEE Proc. of 20th Sym. Reliab. Phys. San Diego, Ca. (1982), p. 288.
50. P.B. Ghate, IEEE Proc. of 20th Symp. Reliab. Phys. San Diego, Ca. (1982), p.292.
51. G.A. Scoggin, B. N. Agarwala, P. Peressini and A. Browillard, Proc. 13th. IEEE
Symp. Reliab. Phys. (1975), p. 155.
52. J.M. Schoen. J. Appl. Phys. 51 :513 (1980); K. Nikama. Proc. 19th IEEE Symp.
Reliab. Phys. (1981 ). p. 175.
53. H.L. Huang. J. Vac. Sci. Technol. A3:705 (1985).
54. S. Vaidya and A.K Sinha. IEEE Proc. 20th Sym. Reliab. Phys. San Diego, Ca.
(1982), p. 50.
55. S. Vaidya and A.K Sinha. Thin Solid Films 75:253 (1981).
56. J.K. Howard. J.F. White and P.S. Ho. J. Appl. Phys. 49:4083 (1978).
10
Characterization of Semiconductor Materials

Gary E. McGuire
Tektronix, Incorporated
Beaverton, Oregon

INTRODUCTION

Characterization of semiconductor materials frequently conveys the

image of analyzi ng the si ng Ie crystall ine su bstrate. However, sem iconduc-
tor materials include a broad range of high purity gases, solvents, metals,
organics, dielectrics and single crystalline substrates. The analysis of
these materials requires an extensive array of analytical tools in order to
fully characterize them. Even a brief introduction to this array of tools is
beyond the scope of this chapter. Instead, a short description of some of
the more popular analytical techn iques will be given with the major em pha-
sis being placed on thosetechniqueswhich provide physical and chemical
information.
The ultimate goal of semiconductor device production is to produce
components with the appropriate electrical properties. Due to the reduced
size of the electrically active region ofVLSI devices, the numberof impurity
and dopant atoms allowed is extremely small, quite often below the
detection limit of ma ly analytical techniques. Collectively, these elements
produce el~,. ,cronic states within the semiconductor band gap which
impact device performance, yield and reliability. The interaction of chemi-
cal impurities with physical defects can result in precipitate formation and
stacking fault generation, both of which influence the mechanical and
electrical properties of the substrate.
The presence, location and role of dopants and adventitious impurities
are highly dynamic. The substitutional or interstitallocations for impurities
are only two of the many possibilities that arise when impurities interact
with defects in the crystal lattice. Device processing, especially at elevated
610
 Characterization of Semiconductor Materials 611

temperatures, constantly changes the microstructure of the device which

can induce both desirable and undesirable electrical properties depending
on the location in the wafer.
As a result, characterization strategies must consider the nature of the
material, the impurity level and distribution, microstructure and electrical
properties. Since each analytical tool provides only a small segment of the
necessary information, a series of techniques may be required. This
chapter illustrates where some of the more popular analytical tools may be
applied and the type of information that may be obtained from them.

SURFACE ANALYSIS TECHNIQUES

Auger Electron Spectroscopy

Figure 1 shows an energy level diagram which depicts the Auger
Electron (AE) process. Incident photons, electrons or ions with sufficient
energy will create a core hole through the excitation of an ionizing photo-
electron. 1 The atom, left in an excited state, de-excites through the emission
of x-rays or Auger electrons which are characteristic of the energy levels

PHOTOELECTRON
OR AUGER EL~CTRON
IONIZING ELECTRON - (KL 1L2•3)

__.._-----t------+--- VACUU M
........--+"'I'-I-I--+HM'-+-~-+-/-,H-+o,t'-t'+++-t'"-, FER MIS URFA CE
I VALENCE BAND

~
CORE
LEVELS

EK----- ----K

AUGER ELECTRON; EKL,L2.3 =EK -EL1-EL2.3-ep

PHOTOELECTRON; EpE = h VI - EK - ~

X-RAY FLUORESCENCE: h V F = EK -E L,

Figure 1: Energy level diagram describing the process for the emission of Auger
and photoelectrons.
612 Semiconductor Materials

involved. For example, the kinetic energy of the Auger electron illustrated
in Figure 1 is typically described as

(1 )

where EK is the energy of the ionized core level, E L1 is the energy of the level
from which the electron originates to fill the initial core hole, EL23 is the
energy level from which the Auger electron originates and ¢ is the work
function. Multiple characteristic Augertransitions may be observed due to
the various core energy levels available for photoexcitation and the multiple
combination of energy levels available for de-excitation and Auger emission.
The Augerelectron is usually described by the three energy levels involved
in its emission. Figure 1 depicts the KL 1 L2 3 Auger transition.
The kinetic energy of the AE is independent of the excitation source.
As a result, the tendency has been to use electron beams in the 1-20 KV
potential energy range for excitation. Electron beams are the preferred
excitation source because they can be focused to a small spot size and
deflected to a region of interest on the sample.
The AE transition is characteristically a small feature sitting on a large
background of inelastically scattered electrons. 2 The most prominent
feature in the electron spectrum is the contribution due to backscattered
electrons from the primary beam. The data has been presented historically
in the dN(E)/dE versus E format as a means to enhance the Auger signal.
More recently the data has been presented in the N(E) versus E due to the
availability of computers for background subtraction.
Figure 2 shows a schematic diagram of an Auger spectrometer. The
optics for the primary beam are coincident with the cylindrical mirror

Compuler
Interface

Figure 2: Schematic diagram of a cylindrical mirror analyzer Auger spectrometer.

 Characterization of Semiconductor Materials 613

analyzer. In most modern spectrometers a LaBs filament is used to provide

high brightness. Spatial resolution of from 25-50 nm may be achieved by
sacrificing beam current and sensitivity. A secondary electron detector is
incorporated to facilitate locating the electron beam on the sample area of
interest.
The focal point of the electron optics and the electron spectrometer
are designed to be identical. 3 When a sample is positioned at the focal
point, the electron beam irradiates the surface, giving rise to the Auger
electrons which pass through the acceptance slits into the spectrometer.
A negative potential applied to the outer cylinder of the spectrometer
deflects the electrons through the exit slit onto the electron multiplier. By
sweeping the voltage on the outer cylinder, the electron energy spectrum
may be scanned.
The shallow escape depth or inelastic mean free path of electrons as a
function of energy is the factor which gives AES its surface sensitivity,
Figure 3. 4 In the range of interest, from 0-2000 eV, the inelastic mean free
path (IMFP) is only a few monolayers. Although many studies have been
conducted to more accurately determine the IMFP, there is still a large
uncertainty in this function.
Characteristic Augertransitions may be observed for all elements with
three electrons or more. As a result AES is often used to survey the surface
composition of materials. For example, Figure 4 shows an AES spectrum of
the surface of a Si wafer coated with an AI layer that is doped with
approximately 4% atomic Cu, after etching in a CCI 4 plasma. The plasma
etch removes the AI but leaves residual Cu since it does not have the same
volatility as AI. The Cu rich residue is only a few monolayers thick and as a
result can only be detected by surface analysis techniques such as AES.

100

E
c:
.s::."
Cii
Q. 10
Q)
Q)

it
c
nJ c:
~~
.~ 1
c;;

......
nJ
(i)
..=
0.1 a-....... .... ....._ _....
10 100 1000

Energy (eV)

Figure 3: Plot of electron inelastic mean free path versus energy which illustrates
the shallow sampl ing depth of the electron spectroscopies.
614 Semiconductor Materials

Si

CI

200 400 600 800 1000 1200 1400 1600 1800 2000
ELECTRON ENERGY ,eV

Figure 4: Auger spectrum of residue left after plasma etch ing a copper doped
aluminum layer in CCI 4 •

By combining the surface sensitivitywith ion sputtering, depth profiles

of the elemental composition may be generated. 5 This is accomplished
through the use of the ion gun shown in Figure 2. The ion gun bombards the
surface with a flux of inert ions in the 2-5 keV range, removing controlled
amounts of material due to the transfer of momentum from the impinging
ions to the surface atoms. By monitoring the Auger signal intensity of
selected elements as a function of sputtering time a plot can be generated
which represents the concentration as a function of depth. Figure 5 shows
the in-depth profile of a multilayered sample of chemically vapor deposited
SiXN y on thermally grown Si02 on a Si substrate. 6 For amorphous materials,
the profile of the bou ndary between succeeding layers can be qu ite sharp.
Artifacts of the sputtering process may arise due to a variety of factors,
however, the information gained as a result of an in-depth profile with a
resolution of 20-50A usually outweights the disadvantages.
Auger spectra usually contain featu res which are characteristic of the
surface chemistry of the system under investigation as a result of the
participation of the valence band electrons in the Auger process. These
features have been studied for many systems and may be used in combi-
nation with the elemental composition as a means to identify the chem ical
oxidation state. Figure 6 illustrates the change in the Ga L3 M4,5 M45 Auger
electron kinetic energy and line shape in two chemical different chemical
environments.? The Ga Auger peak is shifted by4.9 eVforthe oxide formed
on GaAs by anodic oxidation relative to the energy observed for the
underlying GaAs substrate. A similar shift of 5.8 eV is observed for the As
L3 M45M4 5Augertransition for As in the anodic oxide relative toAs in GaAs.
Chemica} shifts of this magnitude have been observed for most elements.
Since the spectral features are complex and the magnitude of the chemical
 Characterization of Semiconductor Materials 615

dE.~
dE
PEAK TO PEAK
HEIGHT

5 15 25 35 45 55
SPUiTERING TIME
(min)
Figure 5: Auger depth profile of chemically vapor deposited Si 3 N 4 on thermally
grown Si0 2 over Si.

L3M41 sr1 4/5

Go(GaAs) Go(Go203)

N(E)/E

1055 1080 1105

KINETIC ENERGY CaV)

Figure 6: Gallium Auger lineshapes for anodic oxide grown on GaAs.

616 Semiconductor Materials

shift relatively small it is not simple to determine the composition of

multicomponent systems.
Since the primary electron beam can be focused to a small spot and
rastered scanned over the surface, elemental distribution maps may be
obtained of the surface composition. This is accomplished by fixing the
pass energy of the spectrometer so that only one transition is being
monitored. If more than one element is of interest sequential elemental
distribution maps may be generated as shown in Figure 7. One typically
looks for inter-relationships in the maps as an indication of compound
formation, corrosion, etc. 8 When the Auger transitions exhibit features
which are indicative of certain oxidation states these may be mapped out
as well. Elemental orchemical oxidation state distribution mapping may be
combined with ion sputtering to generate a three dimensional picture of
the sample.
AES has been a powerful tool in the investigation of a wide range of
materials problems in the semiconductor industry. One application forwhich
AES is particularly well suited is the study of diffusion in thin films. Figure 8
illustrates schematically the three diffusion processes encountered in
thin polycrystalline films. Grain boundary diffusion transports material
from the underlying substrate through a thin polycrystalline film more
rapidly than bulk diffusion. Rapid surface diffusion then distributes the
material across the specimen. Surface analytical techniques like AES
have been used extensively in the investigation of diffusion in thin metal
cou pies used in the sem iconductor industry. This may be accomplished by
monitoring the surface composition while annealing the sample in-situ to
determine the arrival time and increase in concentration of the diffusing
species. By annealing at different temperatures, one can generate aseries
of curves of surface concentration versus annealing time from which an
Arrenhius type plot may be generated. 9 An alternate approach which has
been used is to anneal a series of samples at different times at a fixed
temperature then profile through the film to determine the extent of
interdiffusion. 10
AES has a detection limit of approximatelyO.1 % atomic or 10 18 atoms/
cm 3 in Si with a sensitivity variation of 50-100 across the Periodic Table.
Several handbooks of Auger data provide relative sensitivity factors forthe
elements which may be used to quantify experimental results. 11 There
remai ns extensive work that needs to be done, however, before AES is truly
a quantitative technique. In addition, even though AES has relatively poor
sensitivity, it is one of the more popular analysis techniques for the
evaluation of surfaces and interfaces.
AES may be utilized on a wide variety of materials, but due to the use of
an electron beam for excitation it does have limitations. The electron beam
and ion beam used for sputtering may induce sample decomposition. This
problem is accentuated by the high current densities that occurwith small
probe diameters. Insulating materials may be difficult to evaluate due to
sample charging effects. The inbalance of currents from the primary beam,
the secondary electrons and the sample result in a surface potential which
distorts the Auger electron energy.
 Characterization of Semiconductor Materials 617

Figure 7: SEM image and 0 and S scanning Auger maps of zone refined Fe foil.
The numbers indicate the approximate orientation of the surface normal of the
various grains.
618 Semiconductor Materials

SURFACE
DIFFUSION

GRA IN BOUNDARY
DIFFUSION

Figure 8: Schematic diagram of the diffusion paths in thin polycrystalline ma-

terials.

Photoelectron Spectroscopy
Photoelectron spectroscopy is a technique which has many similarities
to AES. Thesame energy level diagram used to describe the Auger process
may be used to describe the photoelectron process. 12 Excitation of the
ionizing photoelectron may be accomplished through the use of a variety
of energetic photons or charged particles. The pri mary focus in th is text wi II
be on monochromatic x-ray excitation of photoelectrons (XPS). Use of a
monochromatic excitation source is essential to this spectroscopy, since
the photoelectron's kinetic energy is directly dependent on the energy of
the excitation source. By knowing the energy of the x-ray with a high
degree of accuracy and measuring the kinetic energy (KE) of the emitted
photoelectron from the relationship:

BE = hv - KE + <t> (2)

one can determine the binding energy (BE) of any electron energy level
less than the photon energy.
A variety of electrostatic electron energy analyzers have been pro-
duced commercially. One of the most popular is the cylindrical mirror
analyzer, Figure 9, similar to that used for AES. A two stage, two cylindrical
mirror analyzers in tandem, device is employed to enhance the energy
resolution. An x-ray source, either an AI or Mg anode, mounted in proximity
to the sample is used for excitation. The x-rays flood a broad area of the
sample since they, unlike the electron source in AES, can not be easily
focused. The acceptance angle of the spectrometer determines the area
of analysis, which is typically a few millimeter diameter circle. With adjust-
able aperture slits the sampled area may be reduced to a few hundred
micrometers.
Figure 10 shows a schematic diagram of another common variety of
XPS spectrometer. It employs an x-ray monochrometer to enhance the
x-ray line width, eliminate satellite x-ray lines and focus the x-rays. The x-
 Cha~acterization of Semiconductor Materials 619

Figure 9: Schematic diagram of a two stage cylindrical mirror analyzer and x-ray
source used for XPS.

MONOCHROHATOR
CRYSTAL
HE~:I SPHERI CAL
h.~ALYSER

VACUUN

KATER

SYSTEM
CONTROL

Figure 10: Schematic diagram ofaXPS system utilizing a bent quartz crystal x-
ray monochrometer in conjunction with an electrostatic lens and hemispherical
analyzer.
620 Semiconductor Materials

rays from an AI anode are allowed to diffract off of a bent quartz crystal
before interacting with the sample. The natural AI x-ray linewidth is approxi-
matelyO.9 eVwhilethat of the monochromized source is approximatelyO.4
eV.13 The focusing properties of the monochrometer produce a spot size of
approximately 150 micrometers. 14 Due to the loss in x-ray intensity in
going through the monochrometer, most spectrometers of this type employ
an electrostatic lens to increase the collection efficiency of photoelectrons
going into the hemispherical analyzer and a position sensitive, multiple
array, detector to enhance the count rate.
Photoelectron spectrometers employ ion guns for in-depth profiling
as in AES. Since the area of analysis is much larger than in AES, the ion
beam is defocused in orderto generate a uniform ion flux. This reduces the
ion etch rate but does not prevent one from monitoring signal intensity as a
function of ion sputtering time. In addition, many XPS systems have both x-
ray and electron beam sources for combined multi-technique analysis by
XPS and AES.
Figure 11 shows the Ag3d photoelectron spectrum. The trace illustrates
the relative simplicity of the spectra. The spectral features are Gaussian-
like sitting on a low background. The spin-orbit splitting of the energy
levels, in this case the 3d 5 / 2 and 3d 3/2 , is well characterized and easy to
recognize due to the predictable intensity ratios. The spectra are usually
plotted in the N(E) versus BE format even though the energy analysis is of
N(E) versus KE. Each element exhibits a unique set of photoelectron (PE)
transitions corresponding to its atomic energy levels. The PE transitions
are a function of atomic number so that the energy levels of adjacent
elements in the Periodic Table are all shifted to higher binding energy.
As suggested by this unique set of binding energies, XPS is a good
elemental surface analysis technique. Figure 12 shows a spectrum from a

,Ag3d s12

1500

Ag3d 312

.--..
(.) 1000
Q)
~
(I)

C
::J N
0 500
(J
+
t
0
380 375 370 365 360

BE, eV

Figure 11: XPS spectrum of the Ag3d transition showing the spin-orbit splitting
into the 3d s/ 2 and 3d 3 / 2 components.
 Characterization of Semiconductor Materials 621

Si2p
800 Si02.104.3eV Si,99.8eV

>-
t-
(i) 400
z
....
UJ
Z
t-4

Figure 12: XPS spectrum of a Si surface with the native oxide showing the
chemical shift in the Si2p transition.

clean Si wafer to illustrate this point. Two Si2p transitions are observed,
one for elemental Si and one for the native oxide formed on the wafer as a
result of air exposure. One can get a feel for the surface sensitivity of XPS
since the native oxide thickness is typically less than 30A. The surface
sensitivity, as in AES, is controlled by the inelastic mean free path of the
electron as illustrated in Figure 3, rather than the path length of the x-rays
used for excitation.
The ability to distingu ish different oxidation states, as in the case of Si
and Si02, has been one of the recognized strengths of XPS. These chemical
shifts in the core level binding energies are due to changes in the valence
electron density due to compou nd formation. Althoug h, the chemical shifts
may beas large as 10-12 eV, there is frequent overlapfor manycompounds
as illustrated in Table 1. 15 However, there are many sources of chemical
information in the spectra. The sources include first the identification of
the elements present and their relative concentrations, then the chemical
shift of the cation to determine its approximate oxidation state and finally
the chemical shift of the anion to determine its oxidation state. Table 2
illustrates the magnitude of the chemical shifts observed for anionic
species X-2, X0 3 -2 and X04 -2 when X is S, Se and Te. 16 Combination of this
information gives a detailed picture of the chemistry of the surface under
investigation in many cases. There are other spectral features which
provide additional chemical information but which are too detailed for the
scope of th is text.
Figure 13 illustrates the use of XPS in the investigation of the anodiza-
tion of GaAs.7 Both the As3d and Ga3d transitions may be observed. By
combining XPS analysis with ion sputtering the composition of the ano-
622 Semiconductor Materials

Table 1 : Chemical Shifts in the Cr2P3/2 Transition of Chromium Compounds

Chromium, Cr

COMPOUND 2Pt BINDING ENERGY. eV

573 578 583

Cr

CrB 2
I
Cr2S3
I
CrN
I
Cr(CO)6
I
K 3Cr(CN)6
I
cr0 2
Cr203
I
Crl3
II
CrBr3
I
CrCI 3
I
cr0 3 I
K2Cr0 4
I
K 2Cr207 I
CrF 3
I
Table 2: XPS Chemical Shifts
Oxidation ~E Relative to
Compound State Elemental State

S 5e Te
X- 2 -2 -1.4 -0.8 -0.6
)CO 0 0 0 0
XOa- 2 +4 3.6 3.7 2.9
XOc - 2 +6 5.5 4.2 3.6
w. E. Swartz, K. J. Wynne and D. M. Hercules, ANAL CHEM., 43 1884 (1971)

dized layer is obtained at various depths. The outer surface appears to be

predominately Ga2 0 3 as determined by the chemical shift in the Ga3d
peak and the absence of As. In the bulk of the oxide, the composition is a
mixture of AS 2 0 3 and Ga2 0 3 as determined from the chemical shifts in both
the As3d and Ga3d transitions. At the oxide-GaAs substrate interface
there is a transition region where both the As3d and Ga3d exhibit two
 Characterization of Semiconductor Materials 623

As 3d Go 3d

(GO(GOAsl

40 20 0
BINDING ENERGY (eV)

Figure 13: XPS spectrum of anodized and annealed GaAs showing the chemi-
cally shifted Ga3d and As3d transitions at various depths in the oxide and at the
GaAs substrate.

peaks, one for the oxide and one for GaAs. The oxidation of many compound
semiconductors has been studied by XPS. The composition of the oxide,
especially as a fu nction of depth, has been fou nd to be strongly dependent
on the method and conditions of formation.
Investigation of metallization schemes used to contact semiconductor
devices is another key area where XPS has been applied. As an example
Figure 14 shows the Pt4f and Si2p spectra obtained from the silicides
which are formed when Pt is used to contact Si,17 Two different silicides
may be formed depending on the annealing conditions used in the process.
The PT 4f7/ 2 and 4fs/ 2 doublet exhibits a chemical shift of less than 1 eV
between the Pt 2 Si and PtSi phases which may be formed. This chemical
shift is easily detectable. The corresponding Si2 p transitions have essen-
tially the same binding energy. The chemical information obtained from
XPS compliments that obtained from a variety of otherthin film and surface
analysis techniques in the investigation of a variety of contact materials.
Since the photoelectron spectra of many elements exhibit only small
chemical shifts for a series of compounds in which the electronegativity
varies over a wide range, it is frequently necessary to examine the other
features of the spectrum. One of these features which frequently exhibits
useful chemical information even when the photoelectron spectra do not,
624 Semiconductor Materials

80 78 76 74 72 70

BINDING ENEAGY,eV

Figure 14: XPS spectrum of the Pt4f 7 / 2 and Pt4f s/ 2 doublet and Si2p transition
of the two silicide phases, Pt 2 Si and PtSi, of platinum.

is the corresponding Auger transitions. Since Auger emission is a multi-

step process in which two electrons are emitted, the Auger and photo-
electron, the electron shells surrounding the atom have more time to
undergo relaxation. This almost always results in larger chemical shifts for
the Auger transitions.
Table 3 compares the binding energies of photoelectron and Auger
transitions for a series of metals and their oxides. 15 In all cases, the Auger
transition exhibits a factor of two larger chemical shift over that of the
photoelectron transition. However, it is important to remember that the
Auger spectra are more complex and exhibit broader line widths. In
addition, Auger transitions are not always available due to the limited
energy range of excitation of the x-ray source.
The detection limit for XPS is approximately 0.5% atomic or 5 X 10 18
atoms/cm 3 in Si with a sensitivity variation of 102 • Data sets are available
which provide relative sensitivity factors based on peak area. 18 The sensi-
tivity factors are specific to the instrument design, yet, once established
the results are more easily quantified than AES data.
The x-rays used for excitation do less damage to the surface than
charged particle excitation sources. There is evidence for x-ray induced
desorption even though only to a minor extent. Sample charging is minor
since only the secondary electron and sample return currents must be
balanced.
XPS has traditionally been more of a research tool in the semiconductor
industry but is becoming more of a routine analytical technique as more
people realize the extensive chemical information that may be obtained
from the spectra.

Secondary Ion Mass Spectroscopy

Secondary Ion Mass Spectroscopy (81 MS) is the mass analysis of
secondary ions generated by ion sputtering. As illustrated in Figure 15,
 Characterization of Semiconductor Materials 625

Table 3: Chemical Shifts in X-Ray Excited Auger Spectra

Binding Energy, eV (AI Radiation)

Compound 2p 3d KLL LMM MNN
-
Mg 49.8 300.8

MgO 51.2 307.2

AI 72.8 93.5

AI 20 3 75.4 100.2

Zn 9.9 494.0

ZnO 10.7 498.6

Ge 29.4 341.5

Ge02 33.2 349.3

Ag 374.0 1128.2

A9 2S04 374.2 1132.2

Sn 492.9 1048.3

Sn02 494.6 1053.4

Figure 15: Schematic diagram of secondary particles and radiation generated by

an incident ion beam.
626 Semiconductor Materials

bombarding the surface of a solid with an energetic ion beam generates a

variety of secondary transitions, including electrons, photons and ions.
Detection of anyofthese secondary events could serve as the basisforany
analytical probe. However, SIMS equipment is optimized forthe detection
of positive and secondary ions.
There are several major design features which must be taken into
consideration in selection and application of SIMS as an analytical tool.
One of these is the use of SIMS as an ion imaging tool, ion microscope, or
as an ion microprobe. The ion microscope utilizes an ion lens to image the
ions removed from an area of the sample surface. It often has many of the
other features of an ion microprobe and, as a result, is positioned at the top
end of the line in performance and price. Figure 16 is a schematic of an ion
microprobe which contains the essential features of a SI MS system. These
include the ion source and secondary ion mass analyzer. The ion source
shown here is a duoplasmatron source which has the capability of gener-
ating ion beams from a gas source of 1-2 micrometers spot size at up to 20
KV potential. Other ion sources include the hot filament activated gas
sources which achieve 100 micrometerspot sizes at potentials of typically
5 KV maximum and liquid metal ion sources which achieve spot sizes of
2000A using field emission of low melting point metals.
More expensive instrument designs have a primary ion mass analyzer
to separate the positive and negative ions and the neutrals which are
produced in the source. Since the ions are charged a condenser lens may
be used to focus the ions while charged deflection plates are used to
position the beam or raster it over the sample surface.

Primary
Ion Mass
Analyzer

Secondary
Ion Mass
Analyzer

Sample

Figure 16: Schematic diagram of a secondary ion probe mass spectrometer.

 Characterization of Semiconductor Materials 627

Applying a potential to the sample increases the secondary ion collec-

tion efficiency due to their radial distribution. Simple electrostatic analysis
is often used prior to the mass analyzer in order to select a narrow energy
distribution of the secondary ions. This allows improved performance of
the mass spectrometer. The mass spectrometer can be a quadruple
analyzer for low to intermediate charge to mass ratio resolution or a
magnetic sector for high resolution.
Since SI MS is basically a depth profiling technique in that generation
of secondary ions requires removal of material, it is necessary to generate
the ions from a uniform depth. Since ion beams have Gaussian shapes, it is
necessary to raster the beam over an area slightly larger than the area of
analysis in order to mai ntai n a flat sam pi ing area. 19 Otherwise, ions com ing
from the sidewalls of the crater would result in a signal coming from a
region of shallow depth, often referred to as the memory effect. This is
avoided by gating the detection system such that the signal is only
accepted when the primary ion beam is away from the crater wall.
The key design consideration for SI MS instrumentation is the efficient
generation of secondary ions. One aspect of this is the selection of the
primary beam energy. As can be seen in Figure 17, the sputtering yield,
atoms removed per incident ion, is dependent on the incident ion energy.
SI MS ion sources are usually designed to operate in the 5 to 20 KVenergy
region. There is no benefit in going to higher accelerating voltages since
the sputtering yield is flat or decreases above 20 KV.
Only a few per cent of the atoms removed by sputtering are ionized.
The remainder come off as neutral atoms or atom clusters. Proper selection of
the primary ion can enhance the ion yield. Electropositive primary ions
enhance the yield of negative secondary ions while electronegative pri-
mary ions enhance the yield of positive secondary ions. On this basis, the
favored primary ions are 0- and Cs+, although there are other factors
which may dictate the use of other primary ions.
The secondary ion yield is a function of the electronegativity of the
elements. When a negative primary ion beam is utilized the relative
positive ion yield will be greatest for those elements with the lowest

C II
~ 10
E 9 •
~ 8
'; 7
~ 6
Ot 5
SPUTTERING YIELDS
.~ 4
=
5. 2
3
(atoms/ion')
ON COPPER
FOR ARGON

en I

o 5 10 15 20 25 30 35 40
Ion Energy(keV)

Figure 17: Plot of the sputtering yield versus ion energy for argon on copper.
628 Semiconductor Materials

electronegativity. Figure 18 illustrates the variation in secondary ion

intensity as a function of atomic number, which correlates with electronega-
tivity.2o Conversely, when a positive primary ion beam is utilized the
relative negative ion yield will be greatest for those elements with the
highest electronegativity.
The SI MS spectrum is a plot of the secondary ion intensity versus the
mass to charge ratio. As can be seen from Figure 19, the spectrum from
even high purity elements like Si can be very complex. The spectrum
consists of ionized atoms and isotopes, ionic complexes, and multiply
ionized species. The ion intensity is usually plotted on a log scale due to the
dynamic range, 106 , of the data.
Figure 20 illustrates the range of sensitivities 21 available for P im-
planted in Si, from 10 17 to 1021 atoms per cm 3 . This is a factor of 10-100
more sensitive than AES or XPS. However, SI MS data is difficult to quantify
because the ion yield is matrix dependent. As a result, other techniques
such as neutron activation analysis are used to normalize the SI MS data.
The depth resolution of SIMS is approximately 20A, the depth from which
secondary ions are generated. As illustrated here the surface sensitivity in
combination with the inherent sputtering can be utilized to generate in-
depth profiles of 0.5 micrometers or more with high sensitivity. The depth
scale, however, is not known accurately since the sputter rate depends on
a wide range of variables. The sputter depth is frequently determined
through the use of mechanical stylus techniques, ellipsometry or inter-
ferometric techniques.

13.5 KeV 0-
• Pure Element
10' .. Compound

10'
Relative ·Th
Intensity
M+ 10 4

10' BD~O S

2
10 0 10 20 30 40 50 60 90 100

Atomic Number (Z)

Figure 18: Plot of the relative positive secondary ion yield versus atomic num-
ber for 13.5 keV oxygen ions.
 Characterization of Semiconductor Materials 629

100 ~---r----.--...,.---r--........--,.----,r------r"---r--
__- _ - _ -_ _- __
High Purity Silicon
Oxygfn Bombardment
10

~
28 S ·+
.; '2

·
c
~ 0.1

·
>
~ 0.01
·
~

0.001

0.0001
o 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
MOIII Ch<lrg.

Figure 19: Plot of the relative secondary ion intensity versus the mass-to-charge
ratio resulting from oxygen bombardment of high purity silicon.

BOkeV 31p Implants

10 22 n-T'"T"TT"TT"TT"'I"T''I''T''I''T''r''''I- ..

Normalized to Doses Determined

By Neutron Activation

Dose - 1.09 x 10 16at!cm 2

1.13 x 10 15 at/cm 2
1.70x10 14 atlcm'2
"0 5.90 x 10 13at/cm 2
o
~ 10 20 •
o
~
c
.2
~ . .
• •.

~ 10
19
=I~ '\ \
g : \ : ~
8 ; .•~.;\\
10

10 17
18
.:j
.
,
.
"\.
'\.\~.
""- .\ ,
\
, ~

~C,..;r~\ . .
• ""'4.'~ .. .,
'~,~
~.. •

o 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Depth (micrometers)

Figure 20: Depth profiles of phosphorus implanted into silicon at 80 keV show-
ing the concentration versus depth.
630 Semiconductor Materials

Even with these limitations SIMS is a powerful tool forthe analysis of

dopants in semiconductor materials. Figure 21 illustrates an example
where SIMS has been used successfully. Boron profiles in Si are shown
before and after laser annealing. 22 The dopant is redistributed as a resu It of
laser annealing. The maximum B concentration decreases while the tail of
the profile diffuses to a greater depth. It is interesting to note that the
redistribution of B is concentration dependent. The tail of the implant
profile is redistributed to a much greater depth after laser annealing forthe
high dose implant than the low dose implant.
SIMS is one of a few analytical tools capable of distinguishing isotopes.
This has resulted in some well designed experiments that take advantage
of this feature. For example, Coleman et al. 23 utilized SIMS to investigate

o _10 16/cm 2 )
As ~ 15 2 (
Implanted -10 /cm J
o _10 14/cm 2
• _10 16/cm 2 )
Laser • _10 15/cm 2 ~
Annealed 14 2 (
• -10 /cm ,
---.
C')
I
E
~
u
r:
o
;:
ca
ECI,)
10
19

CJ
r:
o
U

1017 ~_ _...-._ _a...-_ _ a..-_----r.-_.. .

o 0.1 0.2 0.3 0.4 0.5
Depth (micrometers)
Figure 21: Depth profiles of boron implanted into sil icon at different doses
showing the concentration versus depth before and after laser anneal ing.
 Characterization of Semiconductor Materials 631

the anodic oxidation of GaAs. By using isotopically labeled H2 0, theywere

able to distinguish the mechanism by which anodic oxidation proceeds.
Figure 22 illustrates the depth profiles that were obtained from a GaAs
(001) wafer anodized in H2 018 then H2 016 and another sample anodized in
the opposite sequence. From this study the authors were able to show that
oxygen is incorporated into the growing oxide at the oxide-electrolyte
interface as opposed to the oxide-semiconductor interface. Mass tansport
occurs through the interstices of the growing oxide.
The most frequent application of SIMS in the semiconductor industry
is in the analysis of dopants in single crystalline substrates. However,
SI MS is widely used in the analysis of a broad range of materials but with
some limitations. Easily ionized elements such as Na, Li orCI may migrate
during ion bombardment. The charge that builds up on insulators during
ion bombardment may reach sufficient field strength to cause charge
induced ion migration. This effect may be minimized by lowering the
sample temperature of by neutralizing the surface charge. This may be
accomplished by a number of techniques including positioning a hot fila-
ment in proximity to the sample or exposing the surface with a scanning
electron beam. The degree of success in neutralizing the surface charge,
however, greatly influences the secondary yield. The ratio of neutral
species versus secondary ions increases as a result of ion neutralization
during sputtering.
The many factors that influence ion yield make quantification of the
data difficult and limit the range of applications of the technique. Byadding

2
COUNTS
PER
SECOND 0
8

20 AO 60 80 100 120 140

RELATIVE DEPTH
Figure 22: Depth profile of the isotopic distribution of oxygen in an anodic
oxide grown on GaAs(001): curve (A) is for GaAs(001) anodized in H 2 0 18 then
H 2 0 16 while curve (8) is for anodization first in H 2 0 16 then H 2 0 18 .
632 Semiconductor Materials

a photon source with sufficient energy to ionize the material removed in

the sputtering process to the SIMS system, the ion yield can be increased
to approximately 1000/0. Through the use of the additional photon source,
the matrix dependence of the ion yield can be minimized. The data
obtained in this manner is much easier to quantify. There is the added
benefit of improved sensitivity since only ions are detected.
An example of th is approach, which is frequently referred to as Sputter
Assisted Laser Ionization (SALI) is shown in Figure 23. Curve (a) shows the
SIMS spectrum of a GaAswaferusing staticAr- bombardment, while curve
(b) shows a comparable SALI spectrum with the introduction of a 248 nm
laser. 24 The SI MS spectrum exhibits a significant difference in the Ga+ and
As+ intensity. With the addition of the ionizing laser, the ion yields of Ga and
As are more nearly equal and the ion yields of trace elements in the GaAs
are enhanced.

Resonance Ionization Spectroscopy

Resonance Ionization Spectroscopy (RIS) is a technique which is
similar to SALI. The material to be analyzed is removed from the surface of

BODO
-'"
'c::J
23 Na +
(a) SIMS

E 6000
:e
~
(/)
z 4000 xB
Q
>-
a: Ga2"
«

~~_~L
0 2000
z
0
u
w
(/)
0

(b) SALI

OL...-.....L----I-~---L-~---'-_...Io..-..--L-_"'---

500 820 1140 1460 1780 2100

CHANNEL (20 NS/CH)
Figure 23: The positive secondary ion SIMS spectrum in trace (a) is from a
GaAs wafer under static Ar + bombardment. A SALI spectrum is shown in trace
(b) for the same surface under static Ar+ bombardment, plus an accompanying
248 nm laser for ionization.
 Characterization of Semiconductor Materials 633

the sample by ion sputtering. A laser beam is positioned above the sample
so that it intersects with the vapor cloud of atoms as shown in Figure 24.
The laser is tuned tothe frequency necessary to ionize the atom of interest.
The ions are extracted from the sample region, then energy analyzed
before passing into a mass spectrometer. The spectrum like SIMS is a plot
of the intensity versus the mass-to-charge ratio. 25
RIS reportedly is capable of achieving sensitivities reaching 1 part in
10 12 and a selectivity that eliminates ambiguity in the interpretation of the
results. 26 Several factors contribute to the enhanced sensitivity of RIS
over similar techniques like SIMS. RIS has a lower background. The ions
that are generated during the sputtering process are extracted before the
laser pulse ionizes the remaining neutral species. As a result, only ions
generated in the laser pulse pass into the mass spectrometer. Additionally,
only selected ions are generated in the laser pulse. Figure 25 shows the
five basic schemes used in the resonance ionization process. 26 Typically, a
tunable dye laser is adjusted so that it emits precisely the correct wave-
length to excite an electron in an atom from its original state to a higher
state. Occasionally, a second photon from a second laser is used to excite
the atom further to an even higher state. After excitation, a second or third
photon is used to interact with the excited atom, causing the electron to be
released from the atom. Thereby, producing a positive ion and a free
electron. The key to RIS is choosing resonately excited states that can be
easily excited and that have large photoionization cross-sections, so that
they can be ionized with high efficiency. It is possible to saturate all of
these processes with commercially available lasers, so that an atom in the
initial state will be excited through the resonant intermediate states and
into the ionization continuum with unit probability during a single laser
pulse.
RIS is extremely selective, in that, only atoms of a given element are
ionized. The intermediate excited states through which the ionization
proceeds may be chosen such that they are uniquely characteristic of that

DEFLECTION
PLATES

~ t;;:; CHOPPING
SLITS DOUBLE-FOCUSING

c:::; 0 MASS SPECTROMETER

~
UADRUPOLE
FOCUSING MAGNETS
ENERGY MASS
~
ION SOURCE
ANALYZER ANALYZER
"-BENDING
~ MAGNET

DETECTOR

TUNABLE DYE LASER

Figure 24: Schematic diagram of sputter initiated resonance ionization spec-

trometer.
634 Semiconductor Materials

W = W1 (OR w2l

W1

2 3 4 5

Figure 25: Schematic diagram of the five basic schemes for R IS.

element. As a result, RIS provides sensitive analysis of solid samples for all
the elements except He and Ne. Sensitivities of down to 1010 atoms/cm 3
have been reported for Na in Si,27
Figure 26 shows a plot of the concentration of 8 in Si as measured by
RIS versus the 8 concentration determined by electrical resistivity.25
There is generally good agreement between the values down to the part-
per-billion level. The RIS values for the samples lowest in 8 lie above the
least squares line fitting the values for the samples with the higher 8
concentration. This is attributed to contamination resulting from sputtering of
the stainless steel slits, a common problem for RIS in the detection of
extremely low concentration levels.
Several approaches have been taken to remove material from the
sample surface to be introduced into the laser beam where resonance
ionization occurs. When an ion beam is utilized, many of the analytical
capabilities are similar to SI MS. The sampling depth of approximately 20A
is determ ined by the sputtering process. The depth that is probed depends
on how long one wants to continue the analysis. Due to the generation of a
crater during the sputtering process, the ion beam must be rastered and
the signal gated such that only material from the flat portion of the crater,
uniform depth, is analyzed.
Since RIS isthe newestofthesurfaceanalysistechniques, there isyet
much to be learned about its sensitivity and sensitivity variation. It shows
 Characterization of Semiconductor Materials 635
103~ --------.,

102 .BORON in SILICON

.BORON in NOS STEEL
~
e:.a. 10 1
en
w
:3 100
~
en
~ 10- 1
en

10- 2

10 -3 10 -2 10 -1 100 10 1 10 2 10 3
TEKTRONIX VALUES (PPM)

Figure 26: Correlation plot showing the boron concentration in silicon measured
by R IS versus the value determined by electrical measurements.

promise of being one of the most sensitive analytical techniques available

for solids analysis. Commercially produced instruments are now available
which should accelerate the learning process.

Rutherford Backscattering Spectroscopy

Rutherford Backscattering Spectroscopy(RBS) is the energy analysis
of ions that are backscattered from a surface. Typically ions with low mass,
such as H+ or He+, are accelerated toward a target at a potential of 0.5 - 2.0
MeV. Asshown in Figure27, the target, M 2 , recoilswhilethe primary ion, M 1 ,
scatters at an energy E1 at an angle e. The scattering energy, E1 , is easily
calculated from the relationship,

where

(3)

The scattering cross-section is a smoothly varying function of the

target atomic mass as shown in Figure 28. From this curve it is obvious that
the scattering efficiency is very low for those elements with low atomic
mass. In addition, it is difficult to distinguish elements which have similar
masses when the elements have high atomic masses. 28
Figure 29 shows the equipment necessary to perform RBS. The
accelerator must be capable of generating MeV ions from the light elements.
636 Semiconductor Materials

Modern instruments make use of compact tandetron accelerators which

allow the construction of RSS systems which are not significantly larger
than other surface analysis equipment. The analysis of the backscattered
ions may be achieved through the use of an electrostaticanalyzeror asolid
state detector. The solid state detector, the preferred detection system, is
positioned in front of the target at an angle of approximately 30° from the
BEFORE COLLIS ION

AT REST

AnIR COLLIS ION

M >M
2 1

Figure 27: Schematic diagram illustrating a Rutherford backscattering coli ision.

0.8

0.6

0.4

M, =4.0
0.2 9 = 160 0

TARGET ATOM MASS (AMU)

Figure 28: Plot of the Rutherford backscattering cross-section versus target

atomic mass.
 Characterization of Semiconductor Materials 637

Ion Detector

Electrostatic
Analyzer

==F=ro=m=Ac=c~~el=er=ato=r= 1~J-
, Target

Beam
,-Jg:1
~ /,\:;~:~

Figure 29: Schematic diagram of a Rutherford backscattering spectrometer.

incoming primary beam. A thin mylar sheet is placed in front of the detector
to attentuate low energy secondary ions and secondary electrons.
The spectra are plots of scattered ion intensity versus energy. An RSS
spectrum is the sum of a family of curves from each atomic mass in the
target. As shown in Figure 30, KE o represents inelastic scattering from the
front surface of the target. 28 At a depth X, the primary ion loses additional
energy through electron scattering both going into and escaping from the
solid. Since Rutherford scattering occurs at all depths, a curve is generated
which is the sum of all these events. Each atomic mass in the target
generates a separate curve based on its scattering cross-section. 29
Figure 31 illustrates the application of RSS in the analysis of the
silicides formed during the interaction of Ni and Si. 30 The dashed line
represents the as-deposited Ni on Si case, where the Ni and Si exhibit
distinct scattering energies. Upon heating at 300°C for 90 minutes, Ni 2 Si
forms which is represented by the open circles. The curve for Ni has
decreased in intensity and broadened while the silicide portion of the Si
curve has moved toward the Ni. Additional heating results in a further
decrease in intensity and broadening of the Ni curve and an increase in the
Si curve for the silicide. Since the scattering cross-sections for Si and Ni
are known, the stoichiometry for the different phases of silicide can be
calcu lated without the use of standards. There are many examples Ii ke th is
in the literature where a heavy metal in a matrix of a low atomic mass
element lends itself to RSS analysis.
Since RSS is essentially a non-destructive quantitative analysis tech-
nique, it is frequently used to calibrate other surface analysis techniques.
It, however, has a limited range of sensitivity of about 10 18 atoms/cm3 in a
Si matrix. 31 This sensitivity is adequate for calibrating XPS and Auger
samples but not for many SIMS samples.
638 Semiconductor Materials

SCATIERING - T H I N FILM-
YIELD

REAR SURFACE FRONT SURFACE

ox l •

----~~-_+_-:d----+--r-__4~--Eo

kEo
kEo - Nx 11 SII = E l
kEo-Nx~S~ =E 2

EO' E1 kEo
ENERGY OF BACKSCATIERED ION

Figure 30: A plot of the Rutherford backscattering yield versus the energy of
the backscattered ion with an accompanying illustration showing the scattering
location in the sampled depth.

n + Si NI As Deposited r"", - NI
<100>
6 ,
,,
,
"'''''''
~
I
300°C 90' Annealing I I
~ • I

300·C90mln ~
1I. 00

4
0
300 C90mlnJ
0
351 C 30 min
~
10' <1
- NISI
.0 , ,

Additional ~ •0 : :
Sequential -- .0 , I

Annealing \~
~ ,
~ •
•
0 ,
I
"
d
2 ~ ~ .0 : ~
et

~ :0 :
.o:
~ .0 I "
L -\ ~
• • 0 I d
~ •8 I ~
, J
O~--_-.l_---"'~..&:at."":;"_.l-~-""_.L-I
0.6 1.0 1.4 1.8
ENERGY (Me.V)

Figure 31: RSS spectra of the phases of nickel silicide formed following the
deposition and annealing of nickel on silicon.
 Characterization of Semiconductor Materials 639

Of the surface analysis techniques, RSS is unique in its ability to

distingu ish whether a dopant occupies a substitutional or interstitial site in
a crystalline lattice. When the primary ion beam is oriented along the
crystalline planes, the ions penetrate long distances into the crystal along
the open channels. Scattering occurs at crystal imperfections and intersti-
tial impurity sites. Figure 32 compares the RSS spectra from Si implanted
Si (100) samples which are positioned such that random scattering and
channeling occur. 32 The virgin sample exhibits minimal scattering except
in the random orientation, indicating the quality of the crystal. After implanta-
tion, the crystal has undergone extensive damage which is evident in the
increased scattering along the channeling direction. Subsequent heating
at 550°C and 850°C anneals out much of the damage, however, the crystal
quality of the virgin sample is not recovered.
The same equipment used to do RSS can be used for nuclear reaction
analysis (NRA).28 Instead of Rutherford scattering the primary ion must
penetrate the nucleus of the target atom and induce a nuclear reaction as
depicted in Figure 33. The nuclear reaction cross-section as a function of
incident ion energy must be known in order to select an energy which will
result in adequate yield. The energies required for NRA are frequently
higher than those used for RSS.
Table 4 lists some useful nuclear reactions. NRA compliments RSS in
that, many of the useful nuclear reactions are for low atomic number
elements for which RSS has low sensitivity. Since the nuclear reaction

1500

o
-J
W
>=

0.48 0.40 0.32 0.24 0.16 0.08 o 0.08

DEPTH (fLml
Figure 32: RSS spectra for Si(100) in the random and <110> aligned directions
before and after 80 keV 30 Si+ implant and subsequent anneal at 550° and 850°C.
640 Semiconductor Materials

830 KeV

Figure 33: Schematic diagram illustrating an ion induced nuclear reaction.

Table 4: Useful Nuclear Reactions

Nucleus Reaction
2H 2H(3He,p)4He
3He 3He(d,p)4He
eLi eLi(d ,o)4He
7Li 7Li(p,o)4He
aBe aBe(d ,o)7Li
"B 1'B(p,o)8Be
12C '2C(d,p)13C
'3C '3C(d.p)14C
UN 14N (d ,O)'2C
1SN 15N(p.O)12C
1eo 1eO(d.p)170
18 0 180(p,O)'5N
1(~F U~F(p,a)1eo
27AI 27AI(p,y)28Si

cross-sections are well known, NRA like RSS is quantitative without the
use of standards. This is especially beneficial for elements like H wh ich are
difficult to detect and quantify by other analytical techniques.

Summary
More attention has been given to the surface analysis techniques in
th is chapter than will be given to the imag ing and bu Ik analysis tech niq ues.
This is the area of expertise of the author and one which has received
increasing attention as device dimensions have decreased. Table 5 is
provided as a summary of the characteristic features of these techniques
that were discussed in this section.

IMAGING ANALYSIS TECHNIQUES

Scanning Electron Microscopy

Scanning electron microscopy is surface imaging of solids using
 Characterization of Semiconductor Materials 641

Table 5: Summary of Surface Analytical Techniques:

Capabilities and Limitations
CHARACTER I ST I C AES XPS SIMS RIS RBS NRA

EXITATION SOURCE e X-RAY ION ION ION ION

DETECTED EMISSION e- e- ION ION ION ION
ELEMENTAL DETECT I ON Z ~ 3 Z ~ 1 Z ~ 1 Z ~ 3 Z ~ 2 Z ~ 1
ELEMENTAL IDENTIFICATION EXCELLENT EXCELLENT GOOD EXCELLENT GOOD GOOD
SENSITIVITY VARIATION 102 102 10 4 103 103
DETECTION LIMITS 0.1% 0.5% 10- 4% 10- 7% 10-3% 10-3%
CHEMICAL INFORMATION YES YES NO NO NO NO
LATERAL RESOLUTION 50 NM 150 ~M 1 ~M 1 ~M 1 ~'M IMM
DEPTH RESOLUT I ON 5A 5A 20A 2GA 100A 100A
DEPTH PROBED ~SPUTTER DEPTH :> 104A 10 4A
DEPTH ANALYS I S ~DESTRUCTIVE > NON- NON-
DESTRUCTIVE DESTRUCTIVE
BEAM INDUCED HIGH LOW LOW LOW LOW LOW
DECOMPOS IT ION
SAMPLE CHARGING YES MINOR YES YES NO NO
STANDARDS REQU I RED YES YES YES YES NO NO
MATRIX EFFECTS MINOR MINOR MAJOR MINOR NO NO
SPEC I AL FEATURE SPATI AL CHEMICAL HIGH HIGH NON- LIGHT ELEMENT
RESOLUTION INFORMATION SENSI- SENSI - DESTRUC- ANALYSIS
TIVITY TIVITY TIVE DEPTH
ANALYS I S

electron beam generated secondary electrons. The equipment utilized

frequently has additional analytical tools that take advantage of the other
types of radiation generated by electron beam excitation. Figure 34
illustrates the electron beam interaction with a solid. The primary beam
may befocused to aspot50A in diameter. 33 Upon interactingwith the solid,
secondary electrons are generated which are utilized to image the surface.
As the high energy electrons penetrate the solid they undergo scattering
which increases the interaction volume. Some of the primary electronswill
be backscattered toward the surface from an area much larger than the
region exposed to the primary beam. The energetic primary electrons will
ionize the atoms in the solid producing x-rays which are characteristic of
the elements that are present. With a suitable set of detectors, all of these
events may be monitored.
Secondary electrons are low energy even though the primary electron
beam is several keV or higher. Figure 35 shows the average energy
distribution of secondary electrons from metals. 34 The peak in the distribu-
tion is below 5 eV. In order to efficiently collect the secondary electrons, a
high poential bias is applied to a scintillator tube which is positioned in
proximitytothe sample. The signal is converted to light and fed outthrough
a light pipe to a photomultiplier tube as shown in Figure 36. Images are
generated by synchronizing the raster of the electron beam with the
output of the photomultiplier tube.
Backscattered electrons have the same energy as the primary elec-
trons. The backscattering coefficient, like that of ions in RBS, is a well
known, smoothlyvarying function of atomic number as shown in Figure37.
642 Semiconductor Materials

d
SECONDARY ELECTRON (E < 50eV) EMISSION

'/h~~:tr-- l= -v'n f
Z = leas 8 Z = l(eos 28)

TRANSMITIED ELECTRONS SPECIMEN

KOSSEl TRANSMISSION CURRENT

~----+4-- X-RAY RESOLUTION --6-I-----~

RX

Figure 34: Diagram illustrating the interaction of the primary electron beam
with a sol id surface in the production of secondary and backscattered electrons,
x-rays and other secondary radiation.

Since the backscattering yield varies more than the secondary electron
yield across the Periodic Table, backscattered electrons will yield better
image contrast in many situations. 35 The information depth for backscat-
tered electrons as a result of the energy dependence of the escape depth
is 102 greater than secondary electrons. 34
One of the most common analytical attachments to the SEM ~s the
energy dispersive x-ray spectrometer (EDX). The high energy primary
electron beam excites x-rays which are characteristic of the elements
which are present in the solid to a depth of 0.5 micrometers or greater
 Characterization of Semiconductor Materials 643

1.0

0.8

0.6
GJ
~
0.4

0.2

0 5 10 15 20 25 30
Energy E eV

Figure 35: Plot of the average intensity of secondary electrons from metals as a
fu ncti on of energy.

incident
electron
beam

scintillator

Figure 36: Schematic diagram of a scintillator tube used for the detection of
secondary electrons.

depending on the accelerating potential. 36 The emitted x-rays are detected

by a solid state detector which is positioned in the vicinity of the sample,
Figure 38. The detector is a Li doped Si crystal which is biased at high
voltage. X-rays interacting with the detector create electron-hole pairs
which are swept through the detector due to the high voltage bias. The
charge pulse is converted to a voltage pulse by a charge-sensitive
preamplifier. The voltage distribution can be displayed on a cathode ray
tube or an x-y recorder. The useful energy range for EDS systems is from
1.0 to 20 keV which limits the analysis to light element with Z > 9. It is
possible to operate without the Be window in front of the detector in an
644 Semiconductor Materials

ultra-high vacuum system. This permits the analysis of the lighter elements
down to C.
The major disadvantage of EDX is its ability to operate in the pulse
counting mode and detect simultaneously the characteristic x-rays for all
elements above F in the Periodic Table. A full spectrum may be obtained in

0.5
en
c ....
•.: c: 0.4
.....-
Q,)Q,)

(U .5:!-

~o
....
0 ....
0Q,) -
W\,
0.3

~CJ 0.2
m
0.1

Atomic Number (Z)

Figure 37: Plot of the electron backscattering coefficient versus atomic number.

-.scan
Electron
beam
1
l H.'J. bias

1 \
l
Si(Li)
detect ~_ _- - J
I
CRT I
vdeo dispay

\ \
\' I
'
\\ I
\\1
t
I
- - --
t
Linear
amplifier
Figure 38: Diagram illustrating the detection of electron beam excited x-rays
with a solid state lithium doped silicon detector.
 Characterization of Semiconductor Materials 645

a much shorter time with the EDX analyzer than with the wavelength
dispersive x-ray (WDX) analyzer but at the expense of energy resolution.
The EDX analyzer has a resolution of approximately 150 eV, whereas, the
WDX analyzer has a resolution of 5 eV. The Li doped Si detector also
requires liquid nitrogen cooling to keep the Li from diffusing and rapidly
degrading the performance. 33
A schematic diagram of the wavelength dispersive detector is shown
in Figure 39. The electron beam excited x-rays interact with a diffraction
crystal which disperses the x-rays. As the crystal is rotated, the different
wavelength x-rays are allowed to enter the detector. A variety of crystals
are used in order to optimize the energy resolution and collection
efficiency of the broad range of x-ray energies for elements Z > 6. The
detection system may be used to generate a spectrum of x-ray intensity
versus wavelength from which the characteristic x-ray lines may be
identified. It may also be operated at a fixed wavelength, so that the
detector output represents an intensity map of the sample surface for one
characteristic x-ray. The most commonly used detector for the WDX
spectrometer is a gas flow proportional counter. When an x-ray enters the
tube through a thin window on the side and is absorbed by an atom of the
gas it causes a photoelectron to be ejected which then loses its energy by
ionizing other gas atoms. The electrons are then attracted to a central wire
which gives rise to a charge pulse.
For bulk samples more than a few micrometers thick, spatial resolution
for elemental analysis does not improve for probes much less than 1

Wavelength, A
Electron
Beam

~ High
Voltage

~
~

speCI~~
Diffraction
Crystal

Figure 39: Diagram illustrating the detection of electron beam excited x-rays
with a wavelength dispersive detector.
646 Semiconductor Materials

micrometer in diameter since the volume of x-ray production is determined

by electron beam scattering. Spatial resolution equal to or smaller than
the probe diameter can be obtained for thin foils.
One of the most rapidly growing applications of the SEM is voltage
contrast. As IC geometries continue to shrink, it becomes increasingly
difficult to test device perforrnance with physical probes. Since the
electron beam in the SEM may be focused to 50A, it can easily be
localized on any feature of modern IC structures. By introducing an
electron spectrometer in the sample chamber to energy analyze the
secondary electrons, the SEM becomes a voltage probe of the surface.
The voltage applied to conductive leads alters the secondary electron
energy in the local area. The electron spectrometer detects these
differences. Many different types of spectrometer have been applied to
voltage contrast, however, one of the most common is the retarding field
spectrometer. As shown in Figure 40, the spectrometer is mounted in the
path of the electron beam. A small aperture allows the electron beam to
pass through to the sample which is by necessity an operating device.
Voltage contrast is used to test for conductive lead continuity, propagation
delays and etc., where circuit designs or process parameters are being
verified. 37

Scanning Transmission Electron Microscopy

The scanning transmission electron microscope (STEM) utilizes an
electron beam much like the SEM but at higher accelerating potential. A

Beam
Blanking
Plates

Electron
Lens

Scanning
Coils

Electron
Lens

Vacuum ....ttl.-
System .....--
Spectrometer ....
Specimen
(IC) - ...
- _-
_...---_ _

Figure 40: Schematic diagram of electron beam optical collum equipped with a
retarding field electron spectrometer for voltage contrast measurements.
 Characterization of Semiconductor Materials 647

higher accelerating potential is utilized since only electrons that are

transmitted through thinned samples are imaged. The accelerating
potential depends on the sample thickness and atomic mass but is
typically 100-200 kV. When the directly transmitted beam is imaged this is
usually referred to as the bright field image. By utilizing the diffracted
beam for crystalline materials, a change in contrast is observed in what is
referred to as a darkfield image.
As shown in Figure 41, the STEM can accommodate a variety of
analytical attachments. Like the SEM, the STEM can be utilized for
secondary electron and backscattered electron imaging and x-ray analysis
from the front side of the sample and lattice imaging, microdiffraction and
electron energy loss from the transmitted beam. 38
The STEM is capable of imaging features as small as 2A since the
sample is thinned. Electron scattering which occurs in the bulk of the
sample is minimized since the primary beam has a short path length
through the sample. Samples are thinned to approximately 2000A
through a combination of chemical and/or mechanical polishing and ion
milling. Ion milling is continued until a photodetector mounted behind the
specimen shuts the system down due to the light emitted from the ion gu n
filament. The specimen is mounted on a wire grid for ease of handling
since the sample is prepared in a separate vacuum chamber.
Samples may be thinned vertically or horizontally. Figure 42 shows a
micrograph of the cross-section of an epitaxial Si layer grown on an Si
substrate. Stacking faults occur in the epitaxial Si layer as a result of
impurities, possibly native oxide, that remain on the single crystalline
substrate after cleaning. 39 Cross-sections like this may be utilized to
evaluate various epitaxial growth techniques, implantation damage,
deposited films and contact formation.

SEM module
EDX signal ~------.... ..~ c::::::r::::t-_--_-_-_--_'..;-.--0 Backscattered
: electron signal
, - .....
: ---0 Secondary
I electron signal
....1_-0 Specimen (absorbed)
current signal

1 -_ _00 Dark-field
signal

Mlcrodlffractlon
Bright-field o--~""""
signal
lattice 1---00 Electron energy loss
Imaging spectrometer signal

Figure 41: Diagram of the analytical attachments and modes of operation of a

STEM for evaluating thinned specimens.
648 Semiconductor Materials

Figure 42: Cross-sectional TEM micrograph of an epitaxial silicon layer grown

on a silicon substrate showing the presence of stacking faults caused by remnants
of the native ox ide.

Since the metallization systems used in device structures are poly-

crystalline, they may be evaluated by a combination of microdiffraction
patterns and transmission electron micrographs. Figure 43 illustrates the
nature of the electron diffraction pattern that may be observed. 38 Single
crystalline samples produce ordered electron diffraction patterns which
depend on the crystal structure of the system being studied. From the
pattern it is possible to deduce the indices of the crystal plane giving rise
to the diffraction spots. It is possible to experimentally determine the
crystallographic direction of a dislocation or the plane of a stacking fault.
As the sample becomes more disordered, the ordered diffraction pattern
is accompanied by diffuse rings until only the diffuse rings appear for
randomly oriented samples. Figure 44 illustrates how the electron
diffraction patterns correlate with the TEM micrographs of thin films with
an initial composition of Si/Ti = 4.5. The sample heated to 650°C shows
very fine grain size and a diffuse diffraction pattern. Comparable samples
heated to 850°C and 1050°C show grain growth and an increase in order
in the diffraction pattern. 40
High temperature heating cycles employed in device processing
frequency lead to precipitation in the lattice of single crystalline substrates.
Depending on the nature of the precipitate and its location, it may have a
beneficial or harmful role in device processing. Figure 45 shows the
consequences of a precipitate. 41 The precipitate grows, usually during
thermal cycling, causing strain on the lattice. If the strain is sufficiently
large, a stacking fault will propagate through the crystal lattice. The
presence of precipitates may be minimized by lowering the device
processing temperatures or by eliminating the elements which lead to
precipitation. These frequently are transition metals which form complexes
with the 0 present in Czochrolski grown Si.
The composition of these precipitates may be evaluated by x-ray
 Characterization of Semiconductor Materials 649

\ Ewald
\ sphere

~9--
2! t • 6
~
Ko+20 I
K I
O~
Single /
crystal /

Textured
grains

Random
orientation

Figure 43: Diagram of the electron scattering that occurs from single crystalline,
polycrystalline and randomly oriented films.

analysis or electron energy loss spectroscopy (EELS). A schematic illustra-

tion of an EELS apparatus is shown in Figu re 46. After passing through the
specimen, the electron energy is analyzed utilizing a magnetic sector
electron spectrometer. A magnetic instrument is utilized since it is the
only type of electron spectrometer with the resolving power to handle the
high electron energies necessary for STEM analysis. The high energy
primary electrons loss energy passing through the sample due to
ionization of the energy levels of atoms present. This results in the loss
peaks at discrete energy levels. EELS is best suited to the analysis of light
elements, however, the analysis may be localized to the precipitate
region.
Because of the perfection of silicon crystals STEM is of limited use
until the crystal slices are heat treated as in diffusion or oxidation. However,
650 Semiconductor Materials

Figure 44: TEM micrograph and diffraction patterns of samples with initial com-
position SilTi = 4.5 reacted at (a) 650°; (b) 850° and (c) 1050°C.
 Characterization of Semiconductor Materials 651

n
p+

Figure 45: TEM micrographs of a decorated stacking fault with a precipitate

found at a pn-junction with a leakage problem.
652 Semiconductor Materials

Incident
electron beam
@.,

\'
puuUWk? a Thin specimen

Detector <focal)
plane

, - - '---i-
~ . . - - - - • - - - -1 <Eo)-
B I

t Be(K) edge
~ ~
§
.&

Figure 46: Schematic diagram of a magnetic sector electron energy loss spec-
trometer.
 Characterization of Semiconductor Materials 653

once defects, such as precipitates or stacking faults, are introduced then

STEM is the best technique to understand the materials science involved.
Defect analysis is accomplished through a combination of imaging, crystal-
lographic and chemical analysis. The major weaknesses of STEM are the
limited area of analysis, a few hundred micrometers, and the extremely
time consuming sample preparation, 0.5-2 days. As a result, STEM is
restricted in the range of applications where it may be applied on a routine
basis.

X-ray Topography
X-ray topography (XRT) is a technique which provides a photographic
image of the distribution of defects within a crystal. Topographs are
recorded from either transmitted or reflected x-rays.42 Contrast on the
photographic recording medium occurs from either orientation contrast,
where a portion of the crystal is misaligned, or extinction contrast, where
the lattice around a defect is distorted.
X-ray topography can image an entire wafer but at a resolution of not
greater than approximately 1 micrometer under carefully controlled con-
ditions. More typical values are in the 10-20 micrometer range. As illustrated
in Figure 47, the x-ray source is positioned at a distance sufficiently far
from the sample so that the x-rays appearto be collimated. The objective is
to image x-rays that are diffracted by the single crystalline sample at a fixed
Bragg angle. The sample is moved between a set of defining slits at the
appropriate angle in parallel with x-ray sensitive film. When the proper
Bragg angles are chosen the diffracted x-rays expose the film. If precipi-
tates, stacking faults, or other crystal imperfections are present dark
images will appear on the film due to the local change in the diffraction
angle.
XRT is a non-destructive technique which may be utilized for process
evaluation following a series of steps. Figure 48 shows a topograph which

SAMPLE

POINT X-RAY SOURCE

MOTION OF SAMPLE
AND FILM FOR
TRAVERSE TOPOGRAPH

Figure 47: Schematic diagram of the equipment necessary to accomplish x-ray

topography.
654 Semiconductor Materials

Figure 48: X-ray topograph of Czochralski grown silicon wafer showing radial
distribution of oxygen precipitates.

was taken from a Czochralski (CZ) grown Si wafer. The CZ growth technique
utilizes a quartz linerwhich gradually dissolves in the Si melt. The dissolved 0
precipitates following high temperature processing steps producing the
swirl pattern observed in the XRT topograph. XRT may be utilized to
monitor the crystal growth process, not realtime but after the wafers are
processed.
XRT is used to identify or study process steps which introduce damage
to the substrate. The x-ray topograph in Figure 49 shows stacking faults
which extend from the identifying label generated on an Si wafer using
laser writing. By analogy, one can imagine using XRT to study processes
which generate damage to getter impurities or high temperature processes
which invariably nucleate precipitates. Because the images of the defects
are 100-1000 times larger than those obtained with electron microscopy,
interpretation is difficult. XRT images only the strain not the defect causing
the strain.

BULK ANALYSIS TECHNIQUES

Fourier Transform Infrared Spectroscopy

Infrared absorption spectroscopy has been utilized for many years in
the evaluation of semiconductor materials. With the advent of Fourier
transform infrared (FTI R) spectroscopy, which has better sensitivity than
older grating instruments, infrared spectroscopy has seen a resurgence in
 Characterization of Semiconductor Materials 655

Figure 49: X-ray topograph of silicon wafer following laser scribing showing the
presence of stacking faults.

interest. One version of FTIR spectroscopy is shown schematically in

Figure 50. Radiation from the IR source passes through a beam splitter
onto a fixed and movable mirror. The IR radiation is recombined in an
interference pattern which is determined by the position of the movable
mirror. Some of the IR radiation passing through the sample is absorbed
before striking the detector. The resolution and accuracy of FTIR is strongly
dependent on the repeatability and accuracy of positioning the mirror.
FTIR is not only asensitive bulkanalysis technique but also capable of
determining the net and total impurity concentration. The energy level
diagrams provided in Figure 51 , provide some insight into the IR absorption
process. 43 At room temperature, shallow donor and acceptor impurity
levels will be ionized. By lowering the sample temperature to liquid He
temperature, the ionized states will be depopulated. Electrons are excited
to bou nd states when IR radiation is absorbed with no energy greater than
or equal to the bandgap. The IR radiation absorbed is proportional to the
net impurity concentration. If the sample is simultaneously irradiated with
a second photon source with energy greater than the bandgap, the IR
radiation absorbed is proportional to the total impurity concentration.
Table 6 lists the strongest IR absorption lines and sensitivity for
656 Semiconductor Materials

. . . . . . ._ _- - - - 1 Mirror

Beam Splitter Movable Mirror

_s_o~_~_ce_I~-·--------"----I-~---~

Sample

Figure 50: Schematic diagram of a Fourier Transform infrared spectrometer.

CB l/III,e, ~,~:' 1/ CB /IUU/lft/lft ) Bound states

+ +
D--~!.- D- - __..-0-0- -
A-----O-O-- A -- - - ..0-0--

\\~\\\\ )
Bound States
VB \\\\'\\\\p+p+\\ VB \\\

(I) n-Type Compensated (b) Low Temperature

T- 29SOK tee] T- lS·K)

uPPffiJUJI
hV~
--- --6-0-- -----~hV

\\\\\\\\\\\\\\ p+p+ \\\\ \\\\\\\\\\

(e) IR Transmission (t) Steady State
No Energy ~ Bandgap C.) Illumination with Illumination
Photons and IR Transmission
tNet I mpurillest hV~8andgap notal I mpuriliest

Figure 51: Energy level diagram illustrating the population of donor and acceptor
levels in the band gap of silicon at room temperature and 15°K.

impurities commonly found in Si. 43 The stated sensitivities for all the
impurities except C and 0 are for a sample temperature of 12°K. Since C
and 0 are not electrically active in Si, there is no significant gain in
sensitivity obtained by lowering the sample temperature. The FTI R sensi-
tivity is enhanced by using a thick specimen, 5 mm, since it is proportional
 Characterization of Semiconductor Materials 657

to optical path length. Thinner specimens may be used with a proportionate

drop in sensitivity. Quantitative analysis is based upon the measured per-
cent transmission at the characteristic wavelength compared to standards.
Even though there is not a significant gain in sensitivity for C and 0 at
lowersampletemperatures, the IR absorption bandsaresharperasshown
for 0 in Figure 52. The sharper bands make it easier to disti ngu ish 0 atoms

Table 6: FTIR Absorption Line Frequencies and Sensitivities

Strongest Absorption Sensitivity

Impurity
Line (cm- 1) (A tomsl cm 3 )

Phosphorus 315.9 1.5 x 1011

Arsenic 382.2 2.7 x 1011
Antimony 293.6 3.1 x 1011
Boron 319.7 3.1 x 1011
Aluminum 471.7 2.1 x 1012
Gallium 548.0 2.7 x 1012
Indium 1175.9 1.6 x 10 13
Carbon 605.0 2.5 x 1016
Oxygen 1136.0 2.5 x 1015

Sample Thickness - 5 mm

Sample Temperature - 1'i' K except Carbon and Oxygen which were at room
temperature

100 _------+--------i-----"t-1

80

w
o
z 60
~
(fj
z
«
a:
~

40

20 ~----_+_----_i-----t--'
1200 1150 1100 1050
WAVE NUMBERS
0
Figure 52: Infrared absorption spectrum of oxygen in silicon at 300 and 55°K.
658 Semiconductor Materials

that occupy different lattice sites. The use of FTI R to study the interstitial
and substitutional 0 concentrations as a function of the Si substrate
thermal history has been a major tool in the development of process
parameters. 44
FTI R is a powerful tool forthe investigation of compound semiconduc-
tor materials, in addition to Si. The spectra, however, tend to be more
complicated since the impurity atom can occupy multiple sites. Figure 53
illustrates this point with the example of GaAs doped with 28Si and 30Si.
Both the 28Si and 30Si can occupy Ga and As sites resulting in four possible
IR peaks. 45
FTIR has also been used in the determination of Si epitaxial layer
thicknesses in the range from 1 micrometer to 200 micrometers. The
epitaxial layer thickness is proportional to the number of interference
fringe spacings which occur when IR radiation is reflected off of the

15 30Si Ga - 3 0SiAs

lJ...
U. 10
W
o
U
Z
o
.-
0-
cr:
a
~ 5
<t

445 450 455 460 465

ENERGY (em-I)
Figure 53: Infrared absorption spectra at liquid nitrogen temperature for GaAs
sample doped with both 30 Si and 28 Si showing the isotopic combinations for
the pair absorption.
 Characterization of Semiconductor Materials 659

interface between an epitaxial layer and a Si substrate with an approximate

102 higher dopant density. The relationship is defined as follows:

M
T=----- (4)
2N(v2 - v 1 )

where T is the epitaxial layer thickness, M the number of interference

fringe spacings, N the refractive index and v is the wavelength in cm- 1 •
Since FTI R analysis is non-destructive, it has become a routine analysis
tool for epitaxial layer thicknesses.

Deep Level Transient Spectroscopy

The study of the electrical properties of matter by capacitance measure-
ments is a well established technique. Many semiconductors do not
readily lend themselves to such methods since they are too highly conduc-
tive except in the form of reverse biased p-n junctions. The reverse bias
creates a depletion layer which is analogous to a parallel plate capacitor.
The basis of the technique is the measurement ofthejunction capacitance
C and slope I::::.cf I::::. vas the reverse bias is increased. In the most usual form
of measurement I::::.c and I::::. v come from point measurements of C versus V.
The capacitance may also be measured at some fixed voltage by super-
imposing a small oscillating voltage on the applied bias. The depletion
width remains approximately constant and the junction capacitance, C =
I::::. Qf I::::. V, is determined by measuring the current induced by the oscillating
voltage. When deep levels are present the oscillating voltage will uncover
charge associated with deep levels. 46
Deep states are those which are positioned deep in the band gap as
contrasted to shallow states wh ich are located near the band edges. Deep
defect states are referred to as traps, recombination centers, generation
centers, deep levels and deep impurities. These terms often have precise
meanings but a particular defect state may be both a trap and a recombi-
nation center depending on such variables as doping and temperature.
Because the rates of defect state capture and emission processes are
temperature dependent, variation of the junction temperature, while moni-
toring the junction capacitance at constant frequency, can often give the
same information as frequency response. However, temperature variation
also effects the equilibrium Fermi level, EF• As the temperature is increased
E F may cross a defect state resulting in a capacitance step. The emission
rate and Fermi level effects are mutually exclusive. The temperature
dependent measurement is, therefore, inherently ambiguous which com-
plementary frequency response measurements may resolve. 47
Electronic transmissions within the space charge region consist entirely
of emission processes. Because states within the space charge region
have no possibility of being filled by capture processes, emission processes
can only be observed following the forced introduction of carriers which
are captured by defect states. Initially the junction is reverse biased to
establish space charge conditions. States in the space charge region are
empty because no mobile carriers are available for capture. A bias pulse
660 Semiconductor Materials

toward zero bias will momentarily collapse the space charge region,
making majority carriers available for capture. When the pulse is turned off
and VR re-established, the ju nction capacitance is reduced because com-
pensating majority carrier charge has been trapped in the space charge
region. This charge can subsequently be excited and sweptfrom the space
charge region by the applied junction potential.
Alternatively, a pulse into forward bias can be used to inject a minority
carrier population. However, any injection pulse using either optical or
voltage excitation introduces both majority and minority carriers. The
relative ratio of minority to majority carriers may be varied by varying the
magnitude of the injected current.
Defect states which are filled during the excitation pulse will return to
their initial state if sufficient excitation energy, thermal or optical, is
present. Such processes can be followed as junction capacitance transients.
The strength of the method is that each defect may be studied independently
through its unique activation energy for carrier emission, cross-section for
carrier capture and cross-section for optical excitation.
The capture of carriers normally proceeds exponentially during an
injection or zero bias pulse. By measuring the capacitance as a function of
pulse duration, it is easy to obtain the capture rate from the slope of log [Coo
- C(T)l vs Twhere T is the duration of the pulse. For majority carrier capture,
the cross-section is obtained from the expression

(5)

where, for example, n is the concentration of electrons and <VN> is the

average thermal velocity of electrons.
The main advantage of Deep Level Transient Spectroscopy (DLTS)
is its high sensitivity to electrically active traps.48 The expression

N = 6C . N
T 2C 0 (6)

where No is the background doping concentration, provides an approxi-

mation to the trap concentration. For 4 ohm/cm material, No is approxi-
mately 10 15. Achange in capacitance of 0.1 fF may be determined for a C of
1OpF with modern instrumentation. From the above expression a sensitivity
of the order of 1010/cm 3 may be obtained by DLTS for electrically active
traps. DLTS has the disadvantages that all traps are not electrically active
or necessarily unambiguous. In addition, it requires device fabrication, is
sensitive to doping concentration and has poor spatial resolution. Yet,
DLTS is one of the most sensitive tools available for the evaluation of
semiconductor materials.

Photoluminescence Spectroscopy
Photoluminescence (PL) Spectroscopy is a measure of the intensityof
radiation versus wavelength emitted as a result of radiative recombination
of electron-hole pairs or excitons excited from their thermal equilibrium
states by optical excitation. 49 An electron-hole pair excited from the
 Characterization of Semiconductor Materials 661

ground state can recombine radiatively through various kinds of recombi-

nation processes, as shown schematically in Figure 54. The most simple
recombination process is band-ta-band recombination where a free electron
excited in the conduction band recombines radiatively with a free hole
excited in the valence band. Impurities which introduce traps, donor or
acceptor levels, in the band gap provide alternate paths for de-excitation.
When an electron or hole is captured by a trap center and then the trapped
carrier recombines radiatively with the remaining carrier, this is called band-
to-impurity recombination. When both the excited electron and hole are
captured by different trap centers and then the trapped electron and hole
recombine radiatively, this is known as donor-acceptor pair recombination.
At low temperatures, a generated electron-hole pair becomes an
exciton. An exciton is a complex with an electron and a hole bound
together by Couloub attraction which can move freely as a quasiparticle in
a semiconductor crystal. These free excitons decay to the ground state
through free-exciton (FE) recombination accompanied by luminescence.
Impurity-exciton complexes are formed when free excitons are bound to
impurity centers. Bound excitons (BE) radiatively decay at just below the
free-exciton energy.
Analysis of PL spectra provides a large amount of information about
semiconductors and the impurities and defects that are present in them.
The most effective application of PL is the identification of shallow impuri-
ties. This is accomplished by measuring the characteristic positions of the
BE luminescence lines at low temperature. The spectral positions will
differ depending on the impurity, while the intensity is related to the
concentration. PL has been used in the analysis of elements such as B, P,
AI, As, and N in Si in the concentration range of 10 11 -10 15 atoms/cm 3 .lt has
also been used to study C, Si, Mn, Mg, Te, etc., in GaAs down to 10 13
atoms/cm 3 •50

CONDUCTION BAND - - •
- -
• • -
hv

- -..0 ,..---- VALENCE BAND--

Figure 54: Diagram of the possible photoluminescence transitions.

662 Semiconductor Materials

The PL intensity is not directly related to shallow-impurity concentra-

tion because of competing non-radiative decay processes forthe BE. The
intensity also depends on the excitation level. It has been found empirically
that good correlation can be obtained between impurity levels determined
by electrical measurements and the intensity ratio of the BE to FE when
recorded at moderate excitation levels. Measurement of the intensity
ratios minimizes the influence of variables dependent on the crystal
growth and process conditions. Tajima has obtained the calibration curves
shown in Figure 55 for Band P in float-zone refined Si. 51 The concentration
range between 10 11 to 10 15 atoms/cm 3 represents the practical range
over which PL may be applied to Si.
Room temperature PL due to band-to-band recombination can be
utilized to characterize thermally induced defects in Si. Some thermally
induced defects in Si act as non-radiative recombination centers which
trap excess carriers. The presence of such non-radiative recombination

10 2 c--------------------.

10'

0
+=
e
~
:t:
Ul
c 10- 1
~
c:

-I
CL
10- 2

10-3 a.-...L-.............~___I..............."""_'UoI..6__"'__'_"".............._"_l~...........

lOll 10 '2 10 13 10'4 10'5

Impurity content, em- 3

Figure 55: Cal ibration curves for the P donor and B acceptor concentrations in
Si from analysis of the BE and FE photoluminescence intensity ratios.
 Characterization of Semiconductor Materials 663

centers leads to a reduction in the PL intensity. Figure 56 shows the

dependence of the PL intensity on annealing temperatures for samples
held at liquid helium and room temperature. 52 The structure and intensity
of the excitonic peak at low temperature changes little as a result of
annealing. The intensity of the broad band-to-band recombination peak
decreases rapidly with increasing annealing temperature. This rapid de-
crease in intensity is attributed to the increase in the thermally induced
non-radiative recombination centers in the crystal. It is believed that the
thermally induced defects are induced by oxygen precipitates since a
strong correlation was found between the etch-pit density and the PL
intensity, Figure 57. 52
PL is a non-destructive technique which requires minimal sample
preparation. It is restricted to analysis of single crystalline wafers or
epitaxial layers. The sampling depth is approximately 3 micrometers, the
optical attentuation length. Through the use of laser excitation spatial

4.2 K ROOM TEMP.

9

-... ....>-
>-
t il
Z
-
Vl
Z
W W
.... .... 600·C .. ~
Z Z -----
50~
w w
u u
z z
w w
U U
1Il til
L&J W
Z
~
:J
-
Z
~
:J
..I ..J

1.08 1.10 1.12 1.14 0.9 1.0 1.1 1.2 1.3

PHOTON ENERGY (eV) PHOTON ENERGY (eV)

Figure 56: PL spectra measured at liquid helium temperature (a), and at room
temperature (b) as a function of annealing temperature.
664 Semiconductor Materials

1 CZ-Si: B

.
::»
a
.
t-
>-
....t-
V)
Z
ILl
C
....

CZ-Ie - - IOil I: 9.1.,d' cm

'7
3

CZ-1 10.3110 cm- 3

(16h annealing)

16' ~......,~_~_..a.-_..&.-_..-..-_.-.-_-..
o 400 500 600 700 800 900
TEMPERATURE ( ·C )
Figure 57: Relation between room temperature PL intensity and etch-pit density
estimated by the Wright-etch method.

resolution of 1 micrometer can be achieved which may be used to map the

PL intensity distribution of the surface.
PL is limited to the analysis of shallow acceptors in GaAs since the
binding energies of donors are too small to experimentally resolve. It is
particularly difficult to analyze the dopant impurity concentration in GaAs
by PL because there are many competing recombination channels due to
the presence of a high background of impurities and defects.

Neutron Activation Analysis

Neutron activation analysis (NAA) is accomplished by placing the
sample in the thermal neutron flux available in the core of a nuclear reactor.
Radioactive isotopes are produced through nuclear reactions. The most
common reaction (n, "I) produces an isotope one neutron heavier than the
 Characterization of Semiconductor Materials 665

target isotope. The intensity of the beta or gamma radiation from the
radioactive product is measured as a function of energy. Isotope identifi-
cation is based on the characteristic energy of the beta or gamma radiation.
The calculations upon which NAA are based yield the number of impurity
atoms in the sample. A knowledge of sample volume yields concentration.

Table 7: Neutron Activation Analysis of Silicon

HALF-LIFE OF 31 Si = 2.6 hr
Sensitivity Factor Affecting
Element Sensitivity
(Atoms/em 3)
8 Short Half Life 12 8 - 20 ms

Na

AI Short Half Life 28 AI = 2.3 s

Fe Low Isotopic Abundance

Zn Long Half-Life 65 Zn : 235 days

As Medium Half-Life

Ag Predominately Gamma-Ray
Emitters
Au Large Cross-Section

Table 8: Neutron Activation Analysis of GaAs

Half-Life Of 78As = 24 hr : 72 Ga =: 14 hrs

Sensitivity Factor Affecting

Element (Atoms/cm 3 ) Sensitivity

Na Half-Life 24 Na - 15 hrs

Fe 5 X 10 15 Low Isotopic Abundance

Zn

SI Half-Life 31 Si - 2.6 hrs

S 3 13 has No Gamma-Rays

Se

Cr Low Isotopic Abundance

666 Semiconductor Materials

Table 9: Carbon and Oxygen Content of Commercially Available Silicon

(Using Charged Particle Accelerators)

MATERIAL CONCENTRATION (Xl0 17 ot/cm3)

CAR BON o x YGE N

FLOAT ZONE 0.08 - 0.35 0.05 - 0.2

(prepored under Argon)

FLOAT ZONE 0.03 - 0.4 0.01 - 0.2

(prepared In vacuum)

CZOCHRALSKI 0.3 - 3.0 2 - 10

(grown under Argon)

POLYCRYSTALLINE 0.2 - 0.8 0.8 - 3

The measure of the analyzed volume or area is often the major limitation to
accuracy and precision. 53
The detection limit for NAA is 5 X 10 10 atoms/cm 3 for Au in Si. This is the
ideal case where Au has a large cross-section for activation and is predomi-
nantly a gamma-ray emitter while in a host matrix with a short half-life.
Table 7 lists elements that were detected by NAA in Czochralski grown Si
along with the sensitivity. Factors which affect sensitivity adversely include
long half-life which lowers the count rate, short half-life where the isotope
decays before sufficient time is available for getting the sample into the
counting chamber and low isotopic abundance. Table 8 provides a similar
listing of elements that were detected in semi-insulating GaAs. The appli-
cation of NAA to GaAs is less favorable than to Si, since As and Ga have
significantly longer half-lives.
NAA is one of the most sensitive and accurate bulk analysis techniques.
Although it is not always readily accessible, it is frequently used to calibrate
other analytical techniques. One major weakness is the insensitivity of
NAA for many for light elements.
Activation analysis can be extended to light elements through the use
of accelerators as was described for NRA. Carbon and oxygen in Si were
studied using charged particle activation analysis. 54 The resu Its, verifythat
the C and 0 content offloat zone grown Si is lowerthan that of Czolchralski
grown material. Charged particle activation analysis like NAA may not be
easily accessible but it is frequently used as a technique to calibrate other
analytical tools.

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Ack now ledgements

Figures 2 and 9 are reprinted by permission of The Physical Electronics Divi-

sion of Perkin-Elmer Inc. Figure 3 is reprinted by permission of the publisher,
John Wiley and Sons Ltd. Figures 5, 7, 14, 21, 23,53 and 55 are reprinted
by permission of the publisher, The American I nstitute of Physics. Figures 6,
13, 22 and 32 are reprinted by permission of the publisher, The Electro-
chemical Society. Figure 10 is reprinted by permission of Surface Science
Laboratories. Figure 18 is reprinted by permission of the publisher, The
American Chemical Society. Figures 24, 26 and 45 are reprinted by permis-
sion of the publisher, Elsevier Science Publishers. Figure 25 is reprinted by
permission of the publisher, The American Physical Society. Figures 28 and 30
are reprinted by permission of the publisher Academic Press. Figures 38,41,
43 and 46 are reprinted by permission of the publisher Marcel-Dekker Inc.
Figure 53 is reprinted by permission of Digilab Division of Bio-Rad Labora-
tories. Figures 56 and 57 are reprinted by permission of the publisher, The
Japanese Journal of Applied Physics.
Index

Acceptors - 27 Channel - 1, 4
Adsorption current - 4
adatom - 412,421 Charge - 58, 59
binding energy - 411 fixed oxide - 58
Amphoteric - 362 mobile ionic - 58
Atomic mobility - 96, 102 oxide trapped - 59
Auger electron spectroscopy Chemical vapor deposition (CVD) -
(AES) - 6, 611-617 6,80
analysis - 67,70,178,294 boron nitride - 115, 122
chemical shift - 614 polycrystalline silicon - 106
cylindrical mirror analyzer - Si -82,94
613 Silicon carbide - 106, 115, 122
detection limit - 616 Si0 2 -75, 106, 115
energy level diagram - 611 Si 3 N4 - 75, 105, 106, 115
profiling - 66, 614 Chemisorption - 333, 421
Child-Langmuir Law - 209, 397
Bipolar devices - 65, 87, 576, CMOS - 89
581,587,590,603,605 Collector - 111
Boltzmann constant - 464 Condensation - 410
Conductivity - 308
Capacitance, parasitic - 106, Crucible-12, 19,20
149,592 Crystal Growth
Capacitance-voltage technique - Czochralski - 9
59,71 float-zone - 9, 20, 475
Carrier seed crystal - 12, 82
concentration - 27 Crystallographic orientation - 84,
velocity - 27 133

669
670 Semiconductor Materials

Crystal puller - 11 oxygen - 40,50,67,74

predeposition - 459-462
Deep level transient spectros- surface - 415
copy (DLTS) -7,71,659- vacancy - 465, 491, 496,501
660 Diode - 96
Defect - 6, 94 Dislocation - 6, 13, 23, 24, 32,
density - 55, 67,86, 172 475
monovacancy - 473 misfit - 94, 178
point - 421, 455, 470, 472- Donor - 27
476,490,498,500 oxygen - 40
saucer pits - 33 Dopant- 15, 18, 19,20,21,63
Denuded zone - 42, 91,92, 173 MBE films - 361-362
Deposition N-type - 15, 22, 61
orientation dependent - 149, P-type - 15, 22, 61
172 segregation - 61
Desorption substitutional - 477, 488
association reaction - 421 Drain current - 4
ion-induced - 367 Dynamic random access memory
mean residence time - 411 (DRAM) - 4
Diamond lattice - 26
Die - 22 Eddy current sensor - 22
Dielectric Effusion cell - 426
breakdown - 67 Electric field - 73
constant - 4, 60 Electromigration - 6, 604-606
films - 47,48,58 Electronic printer printhead - 112,
interlevel - 440,592 114
isolation - 106, 109, 112, 136, Electron paramagnetic resonance
155 (EPR) -473
Diffusion - 6, 455-539, 595-598 Electron spin resonance - 70
activation energy - 464, 469, Ellipsometry - 55,70
486,488,491 Enthalpy - 468, 488
Arrhenius expression - 469, 616 Entropy - 468
barrier - 55, 439, 602-603, 606 Epitaxial
bulk-415,616 homoepitaxy - 84
coefficient - 69, 463, 495 heteroepitaxy - 84
continuum theory - 456-464 silicon - 22, 82, 84, 85, 86, 89,
diffusivity - 469-471,476- 90,91,178,183
477,482,487,495,501, Etching - 126
596 anisotropic - 6,109,112,126,
dopant - 67, 69 136,138,145,149,157,
Fick's Laws - 456, 495 158,162,172
flux - 466 chemical - 23, 24, 64
grain boundary - 596-599, choline - 187, 189
606,616 cleanup - 186, 187
Henry's Law - 460 concentration dependent - 127
interstitialcy - 466, 476-486, Dash - 173
500 defect etch - 91, 92, 128, 172
oxidation enhanced - 70,479- planar - 126
485 RCA clean - 187
 Index 671

reactive ion - 6 N-type - 84

Schimmel - 173 P-type - 84
Secco - 172, 173 substitutional - 477
Sirtl - 172, 173 Inelastic mean free path - 613
vapor-86,89,90,91 Infra red - 36, 38, 654-659
Wright-Jenkins - 173, 178 epitaxial layer thickness meas-
Yang-173 urement - 658
Evaporation - 329,336-355 Fourier transform (FTI R) - 7
flash eva poration - 348 sensitivity - 657
hot-wall evaporation - 349 Ingot -11,12,15,18,20,22
rate - 337 -339 Integrated circuits - 9
rate monitors - 354 Interface
reactive evaporation - 352-354 Si0 2 /Si - 58, 59,61,62,65,
so urces - 340-345 66,67,68,70,71
sublimation - 350 traps - 59
three-temperature - 419-420 Interferometry - 249
uniformity - 345-346 Interst itia I - 20
of alloys - 347 oxygen - 37,38,41
of compounds - 347-348 self - 455, 472-490, 499
silicon - 69, 70
Fermi level - 471 Ion bombardment
Field effect transistor (FET) - 587- cleaning - 422-425
588 influence on microstructure -
Flatband voltage - 60 425-428
influence on stress - 430-438
Gate ion beam mixing - 428
delay - 1 Ion implantation - 512-540
insulator - 4 critical energy - 520
length - 1 electronic sto pping - 519
oxide - 1, 60, 592 implantation masking - 522-
voltage - 4 526
Gettering - 34, 41 ion channeling - 527-538
backside - 91,94, 173 Lindhard, Scharff & Schiott
ox ygen preci pitates - 173 (LSS) range theory - 528
vacuum - 335 nuclear stopping - 519
Gibbs free energy - 468 projected range - 521-522
Grain boundary, polycrystalline range theory - 515-522
silicon - 73, 91 Ion plating - 424

Hall mobility - 424 Junction - 82

High electron mobility transistor breakdown voltage - 61
(HEMT) - 363 depth - 1,67,506
Hydrophilic - 25
Hydrophobic - 25 Knock-on sputtering - 367
Knudsen cell - 343-344
Implantation - 6 effusion cell - 343-344, 351
Impurity - 6,15,18,43,90
getter ing - 65 Lifetime, minority-carrier - 34
672 Semiconductor Materials

Lithography - 541-574 hydrogen - 295, 300

Abbe principle - 557 Nucleation - 41, 96, 102, 412-415
contact printing - 551 preferential - 416
electron beam lithography - 6, sites - 94, 415, 424
543-551 , 570
ion beam - 6 Ohmic contacts - 438
numerical aperture - 555, 558 Optical emission - 249
optical - 6,559 Outgassing rate - 333
projection printing - 555-556 Oxidation
wafer stepper - 556-557 ambient - 48, 65, 67, 68
x-ray - 6, 571-573 Anodization - 46,73, 75
dopant concentration depend-
Melting point - 82 ence - 63,478
Metallization - 575-607 mechanism - 68, 70
multilevel - 440 orientation dependence - 49,62
ohmic contact - 438, 598 plasma assisted - 72
polysilicon - 592 reaction kinetics - 47, 50, 51,
Rent's rule - 581 52,53,54,67
silicides - 439,601-604 sil icides - 73
step coverage - 440 surface preparation depend-
wiring structure - 581 ence - 64
Microstructure - 6, 415 temperature - 49, 52
Mobility - 27 thermal -46,48,50,51,52,54,
atomic - 90 55,59,70,75
Molecular beam epitaxy - 330, Oxide - 70
355-364 capacitance - 60
apparatus - 356 charge - 62, 65, 69, 71
application - 362-364 interlevel insulation - 592
epitaxy growth - 360-362 Oxygen - 15, 19,20,31,32,35,
three-temperature evaporation - 37,91
420-422 diffusion - 39, 40
MOS device - 58, 65,73,87,89, dissolved - 9,38
91,109,133
gate - 601 , 603-605 Packaging, thermal conduction
Multiquantum well laser (MOW) - module - 584
363 Packing density - 109
Pascal - 330
Neutron activation analysis Periodic table - 9
(NAA) - 7,664-666 Group III - 15,27
charged particle activation - Group V - 27
666 Group VI - 15
sensitivity - 665 Phase transitions - 6
Nitridation Phosphorus- 15,18,27,33
plasma - 67 Photoluminescence (PL) - 7, 660-
polycrystalline silicon - 73 664
thermal - 66 bound-exciton - 661
Nuclear reaction analysis (N RA) - detection limit - 661
639-640,666 free exciton - 661
 Index 673

Photomask - 541-544,551 film properties - 284-289

alignment - 22 Ge - 310
Photoresist, multiple level resist - interface properties - 315-318
568 metals - 311-312
negative - 542-551, 560-567 reacto rs - 268-280
photoactive compound - 560 silicides - 312-313
positive - 542-551, 560-567 silicon - 305-310
sensitivity - 549 silicon dioxide - 301-305
Physisorption - 332 silicon nitride - 289-301
Plasma - 191 source gases - 280-281
anisotropy - 191, 193, 227- uniformity - 281-284
229,252 Polishing - 25
chemical effects - 213-217 Polycrystalline - 9, 11
DC plasma - 193,195,196 Polycrystalline silicon - 6, 24, 74,
feedstock composition - 210- 96,104,109,112,308
213 gettering - 91
fundamental aspects - 192- interconnect - 439
210 oxidation - 73
mechanism - 230-241 polysilicon charge -11,21,82
modeling - 241-242 Positron annihilation - 474
non-equilibrium - 191 Precipitates - 6, 42
plasma body - 193 carbon - 34
plasma sheath - 193, 195, 208, oxygen - 20, 32, 35,40,41,43,
209,393,395 91,173
reactor load ing - 223 Preferential deposition, epitaxial
RF plasma - 193, 194, 195, Si -96
196,394
surface chemistry - 217 -241 Quartz crucible - 9, 11, 12, 48
Plasma etching - 242 reactor - 82
AI-263
compound semiconductors - Radiation damage - 443-444
264 Radiation hardened - 106, 109,
defects - 257 129,136
endpoint detection - 249 Radio frequency (RF), induction
equipment - 244-248 coil - 9
oxide - 260 Refractive index - 285, 292, 294,
pattern ing - 242-244 302
radiation damage - 257 Resistivity - 15, 20, 25, 31
selectivity - 254 Resonance ionization spectroscopy
Si -259 (RIS) -7,633-635
silicides - 259 detection limits - 633
silicon nitride - 264 resonance ionization schemes -
throughput - 256 633
uniformity - 253 Rutherford backscattering spectro-
Plasma enhanced chemical vapor scopy (RSS) - 6, 70,294,
deposition - 265 316,635-640
compound semiconductors - energy analyzer - 636
310-311 scattering cross-section - 635
674 Semiconductor Materials

Scanning electron microscopy - Silicon nitride - 55, 105, 111, 122

96,158,162,640-646 Solubility, oxygen - 39
backscattered electrons - 641 Spread ing resistance - 18
energy dispersive x-ray spec- Sp Jtter assisted laser ionization
trometer - 642 (SALI) - 632
secondary electrons - 641 Sputtering 329,364-410
wavelength dispersive 'an- alloys - 376-378
alyzer - 645 bias - 424, 442
Scanning transmission electron cleaning - 422
microscopy (STEM) -7,475, compounds - 376-378
646-653 glow discharge - 378-391
bright field image - 647 ion beam - 392-394
darkfield image - 647 magnetron - 382-391
electron diffraction - 648 mechanisms - 365-369
electron energy loss spectros- planar diodes - 378-380
copy - 649 reactive - 400-409
Schottky barrier - 362, 598, 601 R F sputtering - 394-399
Secondary ion mass spectroscopy sputtered species - 369-371
(SIMS) - 6, 70, 624-632 triode - 381-382
detection limit - 628 yield - 371-370
mass analyzer - 628 Stacking faults - 6, 32, 33, 69, 70,
secondary ion yield - 627 91,104,155,157,173,178,
Segregat io n - 63 183,500,647
coefficient - 15, 18, 20, 21, 31, oxidation-induced - 499-500
34,35,38 Stereographic projection - 133
surface - 362 Sticki ng coefficient - 421
Sheet resistance - 509-512, 514 Stress, compressive - 430
Silicide - 6, 73 deposited films - 429
molybdenum - 439 intrinsic - 429-438
paladium - 439 oxide - 69, 303
platinum - 439 SiN x films - 295-299
tantalum - 74 tensile - 430
titanium - 439 thermal - 429
tungsten - 439 Structure zone model - 415-419,
Silicon carbide - 34, 111, 122 426
Silicon dioxide - 4,12,48,50, Movchan and Demchishin - 416
54,74, 105, 109, 122 Sublimation - 343, 350
monoxide - 25 Substrate - 13
silica - 25 p+ - 89
Silicon halide Substitutional - 34, 37,38,41
SiBr4 - 85 Suscepto r - 11
SiCI 4 - 82,85,90,102,122
SiHCI 3 - 82, 95,90, 102 Target poisoning
SiH 2 CI 2 - 85,90, 102 reactive sputtering - 402-408
SiH 4 - 85, ~O Thermal decomposition - 86
SiHBR - 85 Threshold voltage - 4, 61
Sil 4 - 85 Torr - 330
Silicon monoxide - 12, 19 Transistor - 82
 Index 675

Trap, defect - 91 X-ray diffraction - 70

X-ray lithography - 115
Vacancy, d iffusivity - 487 -490 X-ray photoelectron spectroscopy
silicon - 70, 455, 472-485 (XPS) -6,70,303,618-624
Very large scale integration (V LSI) - Auger transition - 624
1, 5, 6, 7, 70, 73,91, 181 chemical shift - 621
detection limit - 624
Ultra large scale integration (ULSI) - energy analyzers - 618
1, 5, 6, 7, 91, 183 monochrometer - 618
profil ing - 620
Wafer - 22, 23, 25, 34 X-ray orientation - 22
flatness - 25 X-ray topography (XRT) - 7,
Work damage - 22, 23 653-654
Work function - 60