Logical Effort

Sizing Transistors for Speed

Estimating Delays
w  Would be nice to have a
“back of the envelope”
method for sizing gates for
speed
w  Logical Effort
n  Book by Sutherland, Sproull,
Harris
n  Chapter 1 is on our web page
n  Also Chapter 4 in our textbook

1
 Gate Delay Model
w  First, normalize a model of delay to
dimensionless units to isolate fabrication effects

w  dabs = d τ

n  τ is the delay of a minimum inverter driving another

minimum inverter with no parasitics
n  In a 0.6u process, this is approx 40ps
n  Now we can think about delay in terms of d and
scale it to whatever process we’re using

Gate Delay
w  Delay of a gate d has two components
n  A fixed part called parasitic delay p

n  A part proportional to the load on the output called

the effort delay or stage effort f

n  Total delay is measured in units of τ, and is sum of

these delays

w  d = f + p

2
 Effort Delay
w  The effort delay (due to load) can be further broken
down into two terms: f = g * h

n  g = logical effort which captures properties of the gate’s

structure

n  h = electrical effort which captures properties of load and

transistor sizes
l  h = Cout/Cin
l  Cout is capacitance that loads the output

l  Cin is capacitance presented at the input

n  So, d = gh + p

Logical Effort
w  Logical effort normalizes the output drive
capability of a gate to match a unit inverter
n  How much more input capacitance does a gate need
to present to offer the same drive as an inverter?

a 2 4
2
b 2 g = 5/3
x x 4
x
a 1 2
a 1
2 b 1
g=1 g = 4/3

(a )( b) (c )

3
 Computing Logical Effort
w  DEF: Logical effort is the ratio of the input
capacitance of a gate to the input capacitance
of an inverter delivering the same output
current.
w  Measure from delay vs. fanout plots
w  Or estimate by counting transistor widths
2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1

Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3

Logical Effort of Other Gates

w  Logical effort of common gates assuming that
P/N size ratio is 2
Number of inputs
Gate Type 1 2 3 4 5 n
Inverter 1
NAND 4/3 5/3 6/3 7/3 (n+2)/3
NOR 5/3 7/3 9/3 11/3 (2n+1)/3
MUX 2 2 2 2 2
XOR 4 12 32

4
 Electrical Effort
w  Value of logical effort g is independent of
transistor size
n  It’s related to the ratios and the topology

w  Electrical effort h captures the drive capability

of the transistors via sizing
n  Electrical effort h = Cout/Cin
n  Note that as transistor sizes for a gate increase, h
decreases because Cin goes up

Parasitic Delay
w  Parasitic delay p is caused by the internal
capacitance of the gate
n  It’s constant and independent of transistor size
n  As you increase the transistor size, you also
increase the cap of the gate/source/drain areas
which keeps it constant
n  For our purposes, normalize pinv to 1
l  N-input NAND = n*pinv
l  N-input NOR = n*pinv

l  N-way mux = 2n*pinv

l  XOR = 4* pinv

5
 Plots of Gate Delay
6

2
 =  
3  , p
5

  4
 =  
:g
D
AN
4

tN u

 1
inp

 =
,p
o-­‐

 1
Tw

=
g  
3
r:
rte
ve

Effort  delay
In

Parasitic  d elay
0
0 1 2 3 4 5
Electrical  e ffort: h

Delay Estimation
Remember, τ in
Our process ~ 40ps

~200ps

~240ps

6
 Delay Estimation
Remember, τ in
Our process ~ 40ps
~200ps

τ in 180nm = ~ 12ps
FO4 Inverter delay = 60ps
FO4 NAND delay = 72ps

~240ps

Example: Ring Oscillator

w  Estimate the frequency of an N-stage ring
oscillator

Logical Effort: g =
Electrical Effort: h =
Parasitic Delay: p =
Stage Delay: d =
Period of osc =

7
 Example: Ring Oscillator
w  Estimate the frequency of an N-stage ring
oscillator

Logical Effort: g = 1
Electrical Effort: h = 1
Parasitic Delay: p = 1
Stage Delay: d = 2 so dabs = 80ps
Period: 2*N*dabs = 4.96ns, Freq = ~200MHz
For N = 31

Example: FO4 Inverter

w  Estimate the delay of a fanout-of-4 (FO4)
inverter
d

Logical Effort: g=
Electrical Effort: h=
Parasitic Delay: p=
Stage Delay: d=

8
 Example: FO4 Inverter
w  Estimate the delay of a fanout-of-4 (FO4)
inverter
d

The FO4 delay is about

200 ps in 0.6 µm process
60 ps in a 180 nm process
Logical Effort: g=1 f/3 ns in an f µm process
Electrical Effort: h=4
Parasitic Delay: p=1
Stage Delay: d = gh + p = 5

Delay Estimation

w  If Cin = x, Cout = 10x, thus h = 10

w  g = 9/3 = 3
w  d = gh + p = 3*10 + 4*1 = 34 (1360 ps)

9
Multi Stage Delay

Off-Path Load

Ctotal
Cuseful

10
Summary – multistage networks
w  Logical effort generalizes to multistage
networks
w  Path Logical Effort G= gi ∏
Cout − path
w  Path Electrical Effort H=
Cin − path

w  Path Effort F = ∏ fi = ∏ gi hi

w  Can we write F = GH?

Branching Effort
w  Remember branching effort
n  Accounts for branching between stages in path

Con path + Coff path

b=
Con path Note:
B = ∏ bi
∏ h = BH i

w  Now we compute the path effort

n  F = GBH

11
 Multistage Delays

w  Path Effort Delay DF = ∑ f i

w  Path Parasitic Delay P = ∑ pi

w  Path Delay D = ∑ di = DF + P

Designing Fast D = ∑ di = DF + P
Circuits
w  Delay is smallest when each stage bears
same effort
fˆ = gi hi = F N
1

w  Thus the minimum delay of N stage path is

1
D = NF N + P
w  This is a key result of logical effort
n  Find fastest possible delay
n  Doesn’t require calculating gate sizes

12
 Minimizing Path Delay

Choosing Transistor Sizes

13
 Example
0 1 2

minD=N*F 1/N + P = 3*(1.3333) + 6 = 10

Example, continued

f(min) = gi * bi * hi

14
 Transistor Sizes for Example

Another Example, Larger Load

15
8C Load Example Cont.

Example 1.6 from Chap 1

2
1
0

16
 Example 1.6 Continued

f(min) = gi * bi * hi

Example: 3-stage path

w  Select gate sizes x and y for least delay from
A to B
x

y
x
45
A 8
x
y B
45

17
 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

Logical Effort G=
Electrical Effort H=
Branching Effort B=
Path Effort F=
Best Stage Effort fˆ =
Parasitic Delay P=
Delay D=

Example: 3-stage path

x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ = 3 F = 5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4

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 Example: 3-stage path
w  Work backward for sizes
y=
x=
x

y
x
45
A 8
x
y B
45

Example: 3-stage path

w  Work backward for sizes f(min) = gi * bi * hi

y = 45 * (5/3) / 5 = 15 (gi*bi*Cout)/fmin= Cin

x = (15*2) * (5/3) / 5 = 10

45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3
8 10 15
1:1 ratio 2:3 ratio 4:1 ratio

19
 Example 1.7 from Chap 1

(gi*bi*Cout)/fmin=Cin

Note: Don’t care about parasitics for gate sizing, only if you
want to know absolute delay…

Misc. Comments
w  Note that you never size the first gate
n  This gate is assumed to be fixed
n  If you were allowed to size it, the algorithm would try
to make it as large as possible
w  This is an estimation algorithm
n  Authors claim that sizing a gate by 1.5x too big or
small still results in a path delay within 15% of
minimum

20
 Sensitivity Analysis
w  How sensitive is delay to using exactly the
best number of stages? 1.6
1.51

D(N) /D(N)
1.4
1.26
1.2 1.15

1.0

(ρ=6) (ρ =2.4)

0.0
0.5 0.7 1.0 1.4 2.0

N/ N

w  2.4 < ρ < 6 gives delay within 15% of optimal

n  We can be sloppy!
n  I like ρ = 4

Evaluating Different Options

21
 Option #1

Option #2

What if we consider gate area and power?

What about a 4-input NOR?

22
 How many stages?

w  Consider three alternatives for driving a load

25 times the input capacitance
n  One inverter
n  Three inverters in series
n  Five inverters in series
w  They all do the job, but which one is fastest?

How many stages?

w  In all cases: G = 1, B = 1, and H = 25
w  Path delay is N(25)1/N + N Pinv
n  N = 1, D = 26 units
n  N = 3, D = 11.8 units
n  N = 5, D = 14.5 units
w  Since N=3 is best, each stage will bear an
effort of (25)1/3 = 2.9
n  So, each stage is ~3x larger than the last
n  In general, the best stage effort is between 3 and 4
(not e as often stated)
l  The e value doesn’t use parasitics…

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 Choosing the Best # of Stages
w  You can solve the delay equations to determine
the number of stages N that will achieve the
minimum delay
n  Approximate by Log4F
Path Effort Best Min Delay Stage effort
F N D f
0-5.83 1 1.0-6.8 0-5.8
5.83-22.3 2 6.8-11.4 2.4-4.7
22.3-82.2 3 11.4-16.0 2.8-4.4
82.2-300 4 16.0-20.7 3.0-4.2
300-1090 5 20.7-25.3 3.1-4.1
1090-3920 6 25.3-29.8 3.2-4.0

Example

w  String of inverters driving an off-chip load

n  Pad cap and load = 40pf
n  Equivalent to 20,000 microns of gate cap
n  Assume first inverter in chain has 7.2u of input cap
n  How many stages in inv chain?
w  H = 20,000/7.2 = 2777
w  From the table, 6 stages is best
w  Stage effort = f = (2777)1/6 = 3.75
w  Path delay D = 6*3.75 +6*Pinv = 28.5
n  D = 1.14ns if τ = 40ps

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 Other N’s?
w  N=2: f=(2777)1/2 = 52.7
n  delay = 2(52.7) +2 = 158.1 = 6.324ns
w  N=3: f=(2777)1/3 = 14
n  delay = 3(14) +3 = 45 = 1.8ns
w  N=4: f=(2777)1/4 = 7.26
n  delay = 4(7.26) + 4 = 33.04 = 1.32ns
w  N=5: f=(2777)1/5 = 4.88
n  delay = 5(4.88) +5 = 29.4 = 1.18ns
w  N=6: delay = 1.14ns
w  N=7: f=(2777)1/7 = 3.105
n  delay = 7(3.105) +7 = 28.7 = 1.15ns

Summary
w  Compute path effort F = GBH
w  Use table, or estimate N = log4F to decide on
number of stages
w  Estimate minimum possible delay
D = NF1/N + Σpi
w  Add or remove stages in your logic to get close
to N
w  Compute effort at each stage fmin = F1/N
w  Starting at output, work backwards to compute
transistor sizes Cin = (gi * bi * Cout)/fmin

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 Limits of Logical Effort
w  Chicken and egg problem
n  Need path to compute G
n  But don’t know number of stages without G
w  Simplistic delay model
n  Neglects input rise time effects
w  Interconnect
n  Iteration required in designs with wire
w  Maximum speed only
n  Not minimum area/power for constrained delay

Summary
w  Logical effort is useful for thinking of delay in
circuits
n  Numeric logical effort characterizes gates
n  NANDs are faster than NORs in CMOS
n  Paths are fastest when effort delays are ~4
n  Path delay is weakly sensitive to stages, sizes
n  But using fewer stages doesn’t mean faster paths
n  Delay of path is about log4F FO4 inverter delays
n  Inverters and NAND2 best for driving large caps
w  Provides language for discussing fast circuits
n  But requires practice to master

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