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OPA277, OPA2277, OPA4277

SBOS079B – MARCH 1999 – REVISED JUNE 2015

OPAx277 High Precision Operational Amplifiers

1 Features OPAx277 series operational amplifiers operate from
±2-V to ±18-V supplies with excellent performance.
•
1 Ultralow Offset Voltage: 10 μV Unlike most operational amplifiers which are specified
• Ultralow Drift: ±0.1 μV/°C at only one supply voltage, the OPAx277 series is
• High Open-Loop Gain: 134 dB specified for real-world applications; a single limit
• High Common-Mode Rejection: 140 dB applies over the ±5-V to ±15-V supply range. High
performance is maintained as the amplifiers swing to
• High Power Supply Rejection: 130 dB their specified limits. Because the initial offset voltage
• Low Bias Current: 1-nA maximum (±20 μV maximum) is so low, user adjustment is
• Wide Supply Range: ±2 V to ±18 V usually not required. However, the single version
(OPA277) provides external trim pins for special
• Low Quiescent Current: 800 μA/amplifier applications.
• Single, Dual, and Quad Versions
OPA277 operational amplifiers are easy to use and
• Replaces OP-07, OP-77, and OP-177 free from phase inversion and the overload problems
found in some other operational amplifiers. They are
2 Applications stable in unity gain and provide excellent dynamic
• Transducer Amplifiers behavior over a wide range of load conditions. Dual
and quad versions feature completely independent
• Bridge Amplifiers circuitry for lowest crosstalk and freedom from
• Temperature Measurements interaction, even when overdriven or overloaded.
• Strain Gage Amplifiers
Device Information(1)
• Precision Integrators
PART NUMBER PACKAGE BODY SIZE (NOM)
• Battery-Powered Instruments
VSON (8) 4.00 mm × 4.00 mm
• Test Equipment OPA277
SOIC (8) 3.91 mm × 4.90 mm
OPA2277
PDIP (8) 6.35 mm × 9.81 mm
3 Description
SOIC (14) 3.91 mm × 8.65 mm
The OPAx277 series precision operational amplifiers OPA4277
replace the industry standard OP-177. They offer PDIP (14) 6.35 mm × 19.30 mm
improved noise, wider output voltage swing, and are (1) For all available packages, see the orderable addendum at
twice as fast with half the quiescent current. Features the end of the data sheet.
include ultralow offset voltage and drift, low bias
current, high common-mode rejection, and high 0.1 Hz to 10 Hz Noise
power supply rejection. Single, dual, and quad
versions have identical specifications, for maximum
design flexibility. Noise signal is bandwidth limited to
lie between 0.1Hz and 10Hz.
50nV/div

1s/div

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 16
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 19
3 Description ............................................................. 1 8 Application and Implementation ........................ 20
4 Revision History..................................................... 2 8.1 Application Information............................................ 20
8.2 Typical Applications ............................................... 20
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 6 9 Power Supply Recommendations...................... 22
6.1 Absolute Maximum Ratings ...................................... 6 10 Layout................................................................... 22
6.2 ESD Ratings ............................................................ 6 10.1 Layout Guidelines ................................................. 22
6.3 Recommended Operating Conditions....................... 6 10.2 Layout Example .................................................... 23
6.4 Thermal Information for OPA277 .............................. 6 10.3 DFN Package........................................................ 24
6.5 Thermal Information for OPA2277 ............................ 6 11 Device and Documentation Support ................. 25
6.6 Thermal Information for OPA4277 ............................ 7 11.1 Device Support .................................................... 25
6.7 Electrical Characteristics for OPAx277P, OPAx277U, 11.2 Documentation Support ....................................... 25
and OPAx277xA ........................................................ 7 11.3 Community Resources.......................................... 26
6.8 Electrical Characteristics for OPAx277AIDRM ......... 9 11.4 Trademarks ........................................................... 26
6.9 Typical Characteristics ............................................ 12 11.5 Electrostatic Discharge Caution ............................ 26
7 Detailed Description ............................................ 16 11.6 Glossary ................................................................ 26
7.1 Overview ................................................................. 16 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 16 Information ........................................................... 26

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (April 2005) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1

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5 Pin Configuration and Functions

OPA277 P and D Packages

8-Pin PDIP and SOIC OPA277 DRM Package
Top View 8-Pin VSON
Top View

Offset Trim 1 8 Offset Trim

–In 2 7 V+ Offset Trim 1 8 Offset Trim

Pin 1
+In 3 6 Output −In 2 Indicator 7 V+

V– 4 5 NC(1)
+In 3 6 Output

V− 4 5 NC

Thermal Pad
on Bottom
(Connect to V−)

Pin Functions: OPA277

PIN
I/O DESCRIPTION
NO. NAME
1 Offset Trim I Input offset voltage trim (leave floating if not used)
2 –In I Inverting input
3 +In I Noninverting input
4 V– — Negative (lowest) power supply
5 NC — No internal connection (can be left floating)
6 Output O Output
7 V+ — Positive (highest) power supply
8 Offset Trim — Input offset voltage trim (leave floating if not used)

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OPA2277 P and D Packages

8-Pin PDIP and SOIC OPA2277 DRM Package
Top View 8-Pin VSON
Top View
Out A 1 8 V+

–In A 2 A 7 Out B Out A 1 8 Out B

+In A 3 B 6 –In B Pin 1

−In A 2 Indicator 7 V+
V– 4 5 +In B

+In A 3 6 −In B

V− 4 5 +In B

Thermal Pad
on Bottom
(Connect to V−)

Pin Functions: OPA2277

PIN
PDIP, I/O DESCRIPTION
NAME DFN NO.
SOIC NO.
Out A 1 1 O Output channel A
–In A 2 2 I Inverting input channel A
+In A 3 3 I Noninverting input channel A
V– 4 4 — Negative (lowest) power supply
+In B 5 5 I Noninverting input channel B
–In B 6 6 I Inverting input channel B
Out B 7 8 O Output channel B
V+ 8 7 — Positive (highest) power supply

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OPA4277 P and D Packages

14 Pins PDIP and SOIC
Top View

Out A 1 14 Out D

–In A 2 13 –In D
A D
+In A 3 12 +In D

V+ 4 11 V–

+In B 5 10 +In C
B C
–In B 6 9 –In C

Out B 7 8 Out C

Pin Functions: OPA4277

PIN
I/O DESCRIPTION
NO. NAME
1 Out A O Output channel A
2 –In A I Inverting input channel A
3 +In A I Noninverting input channel A
4 V+ — Positive (highest) power supply
5 +In B I Noninverting input channel B
6 –In B I Inverting input channel B
7 Out B O Output channel B
8 Out C O Output channel C
9 –In C I Inverting input channel C
10 +In C I Noninverting input channel C
11 V– — Negative (lowest) power supply
12 +In D I Noninverting input channel D
13 –In D I Inverting input channel D
14 Out D O Output channel D

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, Vs = (V+) – (V–) 36 V
Input voltage (V–) –0.7 (V+) +0.7 V
Output short-circuit (2) Continuous
Operating temperature –55 125 °C
Junction temperature 150 °C
Lead temperature 300 °C
Storage temperature, Tstg –55 125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage, Vs = (V+) – (V–) 4 (±2) 30 (±15) 36 (±18) V
Specified temperature –40 +85 °C

6.4 Thermal Information for OPA277

OPA277
THERMAL METRIC (1) P (PDIP) D (SOIC) DRM (VSON) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 49.2 110.1 40.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.4 52.2 41.3 °C/W
RθJB Junction-to-board thermal resistance 26.4 52.3 16.7 °C/W
ψJT Junction-to-top characterization parameter 15.4 10.4 0.6 °C/W
ψJB Junction-to-board characterization parameter 26.3 51.5 16.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — 3.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Thermal Information for OPA2277

OPA2277
(1)
THERMAL METRIC P (PDIP) D (SOIC) DRM (VSON) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 47.2 107.4 39.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 36.0 45.8 36.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Thermal Information for OPA2277 (continued)

OPA2277
THERMAL METRIC (1) P (PDIP) D (SOIC) DRM (VSON) UNIT
8 PINS
RθJB Junction-to-board thermal resistance 24.4 47.9 15.4 °C/W
ψJT Junction-to-top characterization parameter 13.4 5.7 0.4 °C/W
ψJB Junction-to-board characterization parameter 24.3 47.3 15.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — 2.2 °C/W

6.6 Thermal Information for OPA4277

OPA4277
(1)
THERMAL METRIC D (SOIC) P (PDIP) UNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 67.0 66.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.1 20.5 °C/W
RθJB Junction-to-board thermal resistance 22.5 26.8 °C/W
ψJT Junction-to-top characterization parameter 2.2 2.1 °C/W
ψJB Junction-to-board characterization parameter 22.1 26.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.7 Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA

At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
OPA277PA, UA
OPA277P, U
TEST OPA2277PA, UA
PARAMETER OPA2277P, U UNIT
CONDITIONS OPA4277PA, UA
(1) (1)
MIN TYP MAX MIN TYP MAX
OFFSET VOLTAGE
V0S Input Offset Voltage ±10 ±20 ±20 ±50 µV
OPA277P, U
(high-grade, ±30
single)
Input Offset OPA2277P, U TA = –40°C to ±50
Voltage Over (high-grade, dual) µV
85°C
Temperature
All PA, UA,
±100
Versions
AIDRM Versions
OPA277P, U
(high-grade, ±0.1 ±0.15
single)
Input Offset TA = –40°C to
dV0S/dT OPA2277P, U µV/°C
Voltage Drift 85°C ±0.1 ±0.25
(high-grade, dual)
All PA, UA,
±0.15 ±1
AIDRM Versions
(2)
vs Time 0.2 See µV/mo
Input Offset VS = ±2 V to ±18 (2)
±0.3 ±0.5 See ±1
Voltage: (all vs Power Supply V
models) µV/V
(PSRR) TA = –40°C to
±0.5 ±1
85°C
(2)
Channel Separation (dual, quad) DC 0.1 See µV/V

(1) VS = ±15 V
(2) Specifications are the same as OPA277P, U.

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Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA (continued)

At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
OPA277PA, UA
OPA277P, U
TEST OPA2277PA, UA
PARAMETER OPA2277P, U UNIT
CONDITIONS OPA4277PA, UA
MIN TYP (1) MAX MIN TYP (1)
MAX
INPUT BIAS CURRENT
(2)
TA = –40°C to ±0.5 ±1 See ±2.8
IB Input Bias Current nA
85°C ±2 ±4
(2)
TA = –40°C to ±0.5 ±1 See ±2.8
IOS Input Offset Current nA
85°C ±2 ±4
NOISE
(2)
Input Voltage Noise, f = 0.1 to 10 Hz 0.22 See µVPP
(2)
f = 10 Hz 12 See
(2)
Input Voltage f = 100 Hz 8 See
en nV/√Hz
Noise Density f = 1 kHz 8 See (2)

(2)
f = 10 kHz 8 See
(2)
in Current Noise Density, f = 1 kHz 0.2 See pA/√Hz
INPUT VOLTAGE RANGE
(2) (2)
VCM Common-Mode Voltage Range (V–)+2 (V+)–2 See See V
VCM = (V–) +2 V (2)
130 140 115 See
to (V+) –2 V
CMRR Common-Mode Rejection dB
TA = –40°C to
128 115
85°C
INPUT IMPEDANCE
(2)
Differential 100 || 3 See MΩ || pF
VCM = (V–) +2 V (2)
Common-Mode 250 || 3 See GΩ || pF
to (V+) –2 V
OPEN-LOOP GAIN
VO = (V–)+0.5 V
to (2)
140 See
(V+)–1.2 V,
RL = 10 kΩ
AOL Open-Loop Voltage Gain dB
VO = (V–)+1.5 V
to (2) (2)
126 134 See See
(V+)–1.5 V,
RL = 2 kΩ
VO = (V–)+1.5 V
to
(V+)–1.5 V, (2)
RL = 2 kΩ 126 See dB

TA = –40°C to
85°C
FREQUENCY RESPONSE
(2)
GBW Gain-Bandwidth Product 1 See MHz
(2)
SR Slew Rate 0.8 See V/µs
(2)
0.1% VS = ±15 V, 14 See
Settling Time G = 1, (2)
µs
0.01% 10-V Step 16 See
(2)
Overload Recovery Time VIN × G = VS 3 See µs
1 kHz, G = 1, (2)
THD+N Total Harmonic Distortion + Noise 0.002% See
VO = 3.5 Vrms

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Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA (continued)

At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
OPA277PA, UA
OPA277P, U
TEST OPA2277PA, UA
PARAMETER OPA2277P, U UNIT
CONDITIONS OPA4277PA, UA
MIN TYP (1) MAX MIN TYP (1)
MAX
OUTPUT
(2) (2)
RL = 10 kΩ (V–)+0.5 (V+)–1.2 See See
TA = –40°C to (2) (2)
(V–)+0.5 (V+)–1.2 See See
+85°C
VO Voltage Output (2) (2)
V
RL = 2 kΩ (V–)+1.5 (V+)–1.5 See See
TA = –40°C to (2) (2)
(V–)+1.5 (V+)–1.5 See See
+85°C
(2)
ISC Short-Circuit Current ±35 See mA
(3)
CLOAD Capacitive Load Drive See
(2)
ZO Open-loop output impedance f = 1 MHz 40 See Ω
POWER SUPPLY
(2) (2)
VS Specified Voltage Range ±5 ±15 See See V
(2) (2)
Operating Voltage Range ±2 ±18 See See V
(2) (2)
IO = 0 ±790 ±825 See See
IQ Quiescent Current (per amplifier) TA = –40°C to (2)
µA
±900 See
85°C
TEMPERATURE RANGE
(2) (2)
Specified Range –40 85 See See °C
(2) (2)
Operating Range –55 125 See See °C

(3) See Typical Characteristics

6.8 Electrical Characteristics for OPAx277AIDRM

At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
OPA277AIDRM
PARAMETER TEST CONDITIONS OPA2277AIDRM UNIT
MIN TYP (1) MAX
OFFSET VOLTAGE
V0S Input Offset Voltage ±35 ±100 µV
OPA277P, U (high-grade,
single)

Input Offset Voltage OPA2277P, U (high-grade,

dual) TA = –40°C to 85°C µV
Over Temperature
All PA, UA, Versions
AIDRM Versions ±165
OPA277P, U (high-grade,
single)
Input Offset Voltage OPA2277P, U (high-grade,
dV0S/dT TA = –40°C to 85°C µV/°C
Drift dual)
All PA, UA, AIDRM
±0.15 ±1
Versions
(2)
vs Time See µV/mo
Input Offset Voltage: (2)
VS = ±2 V to ±18 V See ±1
(all models) vs Power Supply (PSRR) µV/V
TA = –40°C to 85°C ±1
(2)
Channel Separation (dual, quad) DC See µV/V

(1) VS = ±15 V
(2) Specifications are the same as OPA277P, U.

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Electrical Characteristics for OPAx277AIDRM (continued)

At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
OPA277AIDRM
PARAMETER TEST CONDITIONS OPA2277AIDRM UNIT
MIN TYP (1) MAX
INPUT BIAS CURRENT
±2.8
IB Input Bias Current TA = –40°C to 85°C nA
±4
±2.8
IOS Input Offset Current TA = –40°C to 85°C nA
±4
NOISE
(2)
Input Voltage Noise, f = 0.1 to 10 Hz See µVPP
(2)
f = 10 Hz See
(2)
Input Voltage Noise f = 100 Hz See
en nV/√Hz
Density f = 1 kHz See (2)

(2)
f = 10 kHz See
(2)
in Current Noise Density, f = 1 kHz See pA/√Hz
INPUT VOLTAGE RANGE
(2) (2)
VCM Common-Mode Voltage Range See See V
VCM = (V–) +2 V to (2)
115 See
CMRR Common-Mode Rejection (V+) –2 V dB
TA = –40°C to 85°C 115
INPUT IMPEDANCE
(2)
Differential See MΩ || pF
VCM = (V–) +2 V to (2)
Common-Mode See GΩ || pF
(V+) –2 V
OPEN-LOOP GAIN
VO = (V–)+0.5 V to
(2)
(V+)–1.2 V, See
RL = 10 kΩ
AOL Open-Loop Voltage Gain dB
VO = (V–)+1.5 V to
(2) (2)
(V+)–1.5 V, See See
RL = 2 kΩ
VO = (V–)+1.5 V to
(V+)–1.5 V, (2)
RL = 2 kΩ See dB

TA = –40°C to 85°C
FREQUENCY RESPONSE
(2)
GBW Gain-Bandwidth Product See MHz
(2)
SR Slew Rate See V/µs
(2)
0.1% VS = ±15 V, See
Settling Time G = 1, (2)
µs
0.01% 10-V Step See
(2)
Overload Recovery Time VIN × G = VS See µs
1 kHz, G = 1, (2)
THD+N Total Harmonic Distortion + Noise See
VO = 3.5 Vrms
OUTPUT
(2) (2)
RL = 10 kΩ See See
(2) (2)
TA = –40°C to +85°C See See
VO Voltage Output (2) (2)
V
RL = 2 kΩ See See
(2) (2)
TA = –40°C to +85°C See See
(2)
ISC Short-Circuit Current See mA
CLOAD Capacitive Load Drive
(2)
ZO Open-loop output impedance f = 1 MHz See Ω

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Electrical Characteristics for OPAx277AIDRM (continued)

At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
OPA277AIDRM
PARAMETER TEST CONDITIONS OPA2277AIDRM UNIT
MIN TYP (1) MAX
POWER SUPPLY
(2) (2)
VS Specified Voltage Range See See V
(2) (2)
Operating Voltage Range See See V
(2) (2)
IO = 0 See See
IQ Quiescent Current (per amplifier) (2)
µA
TA = –40°C to 85°C See
TEMPERATURE RANGE
(2) (2)
Specified Range See See °C
(2) (2)
Operating Range See See °C

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6.9 Typical Characteristics

At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

140 140
G CL = 0
120 0 120
CL = 1500pF +PSR
100 –30 –PSR
100

PSR, CMR (dB)

80 –60

Phase (°)
AOL (dB)

φ 80
60 –90 CMR
60
40 –120
40
20 –150

0 –180 20

–20 0
0.1 1 10 100 1k 10k 100k 1M 10M 0.1 1 10 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. Power Supply and Common-Mode Rejection vs
Frequency
INPUT NOISE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
1000
Noise signal is bandwidth limited to
lie between 0.1Hz and 10Hz.
Current Noise
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)

50nV/div

100

10 Voltage Noise

1
0.1 1 10 100 1k 1s/div
Frequency (Hz)

Figure 3. Input Noise and Current Noise Spectral Density Figure 4. Input Noise Voltage vs Time
vs Frequency
140 1
VOUT = 3.5Vrms

120
Channel Separation (dB)

THD+Noise (%)

0.1
100
Dual and quad devices. G = 1, G = 10, RL = 2kΩ, 10kΩ
all channels. Quad measured
80 channel A to D or B to C —other
0.01
combinations yield similar or
improved rejection.
60 G = 1, RL = 2kΩ, 10kΩ

40 0.001
10 100 1k 10k 100k 1M 10 100 1k 10k 100k

Frequency (Hz) Frequency (Hz)

Figure 5. Channel Separation vs Frequency Figure 6. Total Harmonic Distortion + Noise vs Frequency

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Typical Characteristics (continued)

At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
16 35
Typical distribution Typical distribution
14 of packaged units. 30 of packaged units.
Single, dual, and Single, dual, and

Percent of Amplifiers (%)

Percent of Amplifiers (%)

12 quad included. quad included.

25
10
20
8
15
6
10
4

2 5

0 0
– 50– 45– 40– 35– 30– 25– 20– 15– 10– 5 0 5 10 15 20 25 30 35 40 45 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Offset Voltage (µV) Offset Voltage (µV/°C)

Figure 7. Offset Voltage Production Distribution Figure 8. Offset Voltage Drift Production Distribution
3 160

2 150
Offset Voltage Change (µV)

CMR
AOL, CMR, PSR (dB)

1 140 AOL

0 130
PSR
–1 120

–2 110

–3 100
0 15 30 45 60 75 90 105 120 –75 –50 –25 0 25 50 75 100 125
Time from Power Supply Turn-On (s) Temperature ( °C)

Figure 9. Warm-Up Offset Voltage Drift Figure 10. AOL, CMR, PSR vs Temperature
5 1000 100
4 950 90
900 80

Short-Circuit Current (mA)

3
Quiescent Current (µA)
Input Bias Current (nA)

2 850 70
±I Q
1 800 60

0 750 50
–ISC
–1 700 40
650 +ISC 30
–2
Curves represent typical 600 20
–3
production units.
550 10
–4
500 0
–5
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C)
Temperature ( °C)

Figure 11. Input Bias Current vs Temperature Figure 12. Quiescent Current and Short-Circuit Current vs
Temperature

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Typical Characteristics (continued)

At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
2.0 2.0
Curve shows normalized change in Curve shows normalized change in bias current
1.5 bias current with respect to VS = ±10V 1.5 with respect to VCM = 0V. Typical I B may range
(+20V). Typical I B may range from from –05.nA to +0.5nA at V CM = 0V.
1.0 1.0
–0.5nA to +0.5nA at V S = ±10V. VS = ±5V
0.5 0.5
∆IB (nA)

∆IB (nA)
0.0 0.0
VCM = 0V
–0.5 –0.5
VS = ±15V
–1.0 –1.0

–1.5 –1.5

–2.0 –2.0
0 5 10 15 20 25 30 35 40 –15 –10 –5 0 5 10 15
Supply Voltage (V) Common-Mode Voltage (V)

Figure 13. Change in Input Bias Current vs Figure 14. Change in Input Bias Current vs
Power Supply Voltage Common-Mode Voltage
1000 100
10V step
per amplifier
CL = 1500pF
900
Quiescent Current (µA)

50
Settling Time (µs)

0.01%
800
0.1%

700
20
600

500 10
0 ±5 ±10 ±15 ±20 ±1 ±10 ±100
Supply Voltage (V) Gain (V/V)

Figure 15. Quiescent Current vs Supply Voltage Figure 16. Settling Time vs Closed-Loop Gain
30 (V+)
VS = ±15V (V+) – 1
25 –55°C
(V+) – 2
Output Voltage Swing (V)
Output Voltage (V PP)

(V+) – 3
20 125°C
(V+) – 4
(V+) – 5 25°C
15
(V–) + 5
125°C 25°C
10 (V–) + 4
VS = ±5V (V–) + 3
5 (V–) + 2
–55°C
(V–) + 1
0 (V–)
1k 10k 100k 1M 0 ±5 ±10 ±15 ±20 ±25 ±30
Frequency (Hz) Output Current (mA)

Figure 17. Maximum Output Voltage vs Frequency Figure 18. Output Voltage Swing vs Output Current

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Typical Characteristics (continued)

At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
60
Gain = –1
50

40
Overshoot (%)

Gain = +1

2V/div
30

20
Gain = ±10
10

0
10 100 1k 10k 100k
Load Capacitance (pF) 10µs/div

Figure 19. Small-Signal Overshoot vs Load Capacitance Figure 20. Large-Signal Step Response
G = 1, CL = 1500 pF, VS = ±15 V
20mV/div

20mV/div

1µs/div 1µs/div

Figure 21. Small-Signal Step Response Figure 22. Small-Signal Step Response
G= +1, CL = 0, VS = ±15 V G= 1, CL = 1500 pF, VS = ±15 V
100
70
50

30
Impedance (:)

20

10
7
5

3
2

1
1k 10k 100k 1M
Frequency (Hz)

Figure 23. Open-Loop Output Impedance

VS = ±15 V

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7 Detailed Description

7.1 Overview
The OPAx277 series precision operational amplifiers replace the industry standard OP-177. They offer improved
noise, wider output voltage swing, and are twice as fast with half the quiescent current. Features include ultralow
offset voltage and drift, low bias current, high common-mode rejection, and high power supply rejection. Single,
dual, and quad versions have identical specifications, for maximum design flexibility.

7.2 Functional Block Diagram

Input Offset
Adjust
(OPA277 only)

+IN +
Output
-IN ±

Input Offset
Adjust Compensation
(OPA277 only)

7.3 Feature Description

The OPAx277 series is unity-gain stable and free from unexpected output phase reversal, making it easy to use
in a wide range of applications. Applications with noisy or high-impedance power supplies may require
decoupling capacitors close to the device pins. In most cases 0.1-μF capacitors are adequate.
The OPAx277 series has low offset voltage and drift. To achieve highest performance, the circuit layout and
mechanical conditions should be optimized. Offset voltage and drift can be degraded by small thermoelectric
potentials at the operational amplifier inputs. Connections of dissimilar metals generate thermal potential, which
can degrade the ultimate performance of the OPAx277 series. These thermal potentials can be made to cancel
by assuring that they are equal in both input terminals.
• Keep the thermal mass of the connections to the two input terminals similar
• Locate heat sources as far as possible from the critical input circuitry
• Shield operational amplifier and input circuitry from air currents, such as cooling fans

7.3.1 Operating Voltage

OPAx277 series operational amplifiers operate from ±2-V to ±18-V supplies with excellent performance. Unlike
most operational amplifiers, which are specified at only one supply voltage, the OPA277 series is specified for
real-world applications; a single limit applies over the ±5-V to ±15-V supply range. This allows a customer
operating at VS = ±10 V to have the same assured performance as a customer using ±15-V supplies. In addition,
key parameters are assured over the specified temperature range, –40°C to 85°C. Most behavior remains
unchanged through the full operating voltage range (±2 V to ±18 V). Parameters which vary significantly with
operating voltage or temperature are shown in Typical Characteristics.

7.3.2 Offset Voltage Adjustment

The OPAx277 series is laser-trimmed for low offset voltage and drift, so most circuits do not require external
adjustment. However, offset voltage trim connections are provided on pins 1 and 8. Offset voltage can be
adjusted by connecting a potentiometer, as shown in Figure 24. Only use this adjustment to null the offset of the
operational amplifier. This adjustment should not be used to compensate for offsets created elsewhere in a
system, because this can introduce additional temperature drift.

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Feature Description (continued)

V+
Trim Range: Exceeds
Offset Voltage Specification
0.1µF
20kΩ
7
2 1
8
OPA277 6
3

4 OPA277 single op amp only.

0.1µF Use offset adjust pins only to null
offset voltage of op amp—see text.

V–

Figure 24. OPA277 Offset Voltage Trim Circuit

7.3.3 Input Protection

The inputs of the OPAx277 series are protected with 1-kΩ series input resistors and diode clamps. The inputs
can withstand ±30-V differential inputs without damage. The protection diodes conduct current when the inputs
are over-driven. This may disturb the slewing behavior of unity-gain follower applications, but will not damage the
operational amplifier.
1 k

1 k ±

Figure 25. OPAx277 Input Protection

7.3.4 Input Bias Current Cancellation

The input stage base current of the OPAx277 series is internally compensated with an equal and opposite
cancellation circuit. The resulting input bias current is the difference between the input stage base current and
the cancellation current. This residual input bias current can be positive or negative.
When the bias current is canceled in this manner, the input bias current and input offset current are
approximately the same magnitude. As a result, it is not necessary to use a bias current cancellation resistor, as
is often done with other operational amplifiers (see Figure 26). A resistor added to cancel input bias current
errors may actually increase offset voltage and noise.
R2 R2

R1 R1

Op Amp OPA277

RB = R2 || R1
No bias current
cancellation resistor
(see text)

(a) (b)
Conventional op amp with external bias OPA277 with no external bias current
current cancellation resistor. cancellation resistor.

Figure 26. Input Bias Current Cancellation

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Feature Description (continued)

7.3.5 EMI Rejection Ratio (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this report provides the EMIRR IN+, which specifically describes the EMIRR performance when
the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the noninverting
input is tested for EMIRR for the following three reasons:
1. Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
2. The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
3. EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a printed circuit board (PCB). This isolation allows the RF signal to be applied directly to
the noninverting input terminal with no complex interactions from other components or connecting PCB
traces.
A more formal discussion of the EMIRR IN+ definition and test method is provided in application report
SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download at www.ti.com. The EMIRR IN+
of the OPA277 is plotted versus frequency as shown in Figure 27.
120
PRF = -10 dbm
VS = r2.5 V
100 VCM = 0 V

80
EMIRR IN+ (db)

60

40

20

0
10 100 1k 10k
Frequency (MHz)

Figure 27. OPA277 EMIRR IN+ vs Frequency

If available, any dual and quad operational amplifier device versions have nearly similar EMIRR IN+
performance. The OPA277 unity-gain bandwidth is 1 MHz. EMIRR performance below this frequency denotes
interfering signals that fall within the operational amplifier bandwidth.

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Feature Description (continued)

Table 1 shows the EMIRR IN+ values for the OPA277 at particular frequencies commonly encountered in real-
world applications. Applications listed in Table 1 may be centered on or operated near the particular frequency
shown. This information may be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.

Table 1. OPA277 EMIRR IN+ for Frequencies of Interest

FREQUENCY APPLICATION/ALLOCATION EMIRR IN+
400 MHz Mobile radio, mobile satellite/space operation, weather, radar, UHF 59.1 dB
GSM, radio com/nav./GPS (to 1.6 GHz), ISM, aeronautical mobile,
900 MHz 77.9 dB
UHF
1.8 GHz GSM, mobile personal comm. broadband, satellite, L-band 91.3 dB
802.11b/g/n, Bluetooth™, mobile personal comm., ISM, amateur
2.4 GHz 93.3 dB
radio/satellite, S-band
3.6 GHz Radiolocation, aero comm./nav., satellite, mobile, S-band 105.9 dB
802.11a/n, aero comm./nav., mobile comm., space/satellite
5.0 GHz 107.5 dB
operation, C-band

7.3.5.1 EMIRR IN+ Test Configuration

Figure 28 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
operational amplifier noninverting input terminal using a transmission line. The operational amplifier is configured
in a unity gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter
(DMM). Note that a large impedance mismatch at the operational amplifier input causes a voltage reflection;
however, this effect is characterized and accounted for when determining the EMIRR IN+. The resulting dc offset
voltage is sampled and measured by the multimeter. The LPF isolates the multimeter from residual RF signals
that may interfere with multimeter accuracy. Refer to SBOA128 for more details.
Ambient temperature: 25Û&

+VS

±
50  Low-Pass Filter
+

RF source
-VS
DC Bias: 0 V Sample /
Modulation: None (CW) Averaging Digital Multimeter
Frequency Sweep: 201 pt. Log Not shown: 0.1 µF and 10 µF
supply decoupling

Figure 28. EMIRR IN+ Test Configuration Schematic

7.4 Device Functional Modes

The OPAx277 has a single functional mode and is operational when the power-supply voltage is greater than 4 V
(±2 V). The maximum power supply voltage for the OPAx277 is 36 V (±18 V).

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The OPAx277 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer ultralow offset voltage and offset voltage drift, as well as 1-MHz bandwidth and high
capacitive load drive. These features make the OPAx277 a robust, high-performance operational amplifier for
high-voltage industrial applications.

8.2 Typical Applications

8.2.1 Second-Order Lowpass Filter

2.25 k

1 nF
2.25 k 1.13 k
Input ±
Output
4 nF +

Figure 29. Second-Order Lowpass Filter

8.2.1.1 Design Requirements

• Gain = 1 V/V
• Lowpass cutoff frequency = 50 kHz
• –40 db/dec filter response
• Maintain less than 3-dB gain peaking in the gain versus frequency response

8.2.1.2 Detailed Design Procedure

WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.

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Typical Applications (continued)

8.2.1.3 Application Curve

20

Gain (db)
-20

-40

-60
100 1k 10k 100k 1M
Frequency (Hz)

Figure 30. OPA277 Second-Order 50-kHz, Lowpass Filter

8.2.2 Load Cell Amplifier

V+

1/2 R2
VOUT = (V1 – V2)(1 + )
OPA2277 R1

R2

V–

R–∆R R+∆R V+
V2 R1
V1 Load
Cell
1/2
R+∆R R–∆R
OPA2277

V–
R2 R1

For integrated solution see: INA126, INA2126 (dual)

INA125 (on-board reference)
INA122 (single-supply)

Figure 31. Load Cell Amplifier

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Typical Applications (continued)

8.2.3 Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction Compensation

IREG ∼ 1mA
5V

12
V+ VLIN 1
1/2 13 IR1 14
+
IR2 11
OPA2277 VIN 10
Type J VREG
V+
RF 4
10kΩ RG

RG 9
R XTR105 B
RF 1250Ω
412Ω
10kΩ
3 E
RG
8
IO
–
1/2 2 VIN 7
1kΩ
OPA2277 IRET
IO = 4mA + (V IN – VIN) 40
+ –

50Ω V– 6 RG

25Ω
RCM = 1250Ω

2RF
(G = 1 + = 50)
R
0.01µF

Figure 32. Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction
Compensation

9 Power Supply Recommendations

The OPAx277 is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply from –40°C
to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in the Typical Characteristics.

CAUTION
Supply voltages larger than 36 V can permanently damage the device; see the
Absolute Maximum Ratings.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.

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Layout Guidelines (continued)

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques, SLOA089.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
• (DFN package only) The leadframe die pad should be soldered to a thermal pad on the PCB. The mechanical
drawings located at the end of this data sheet list the physical dimensions for the package and pad.
• (DFN package only) Soldering the exposed pad significantly improves board-level reliability during
temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have
low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long
term reliability.

10.2 Layout Example

VIN +
RG VOUT

RF

(Schematic Representation)

Place components
Run the input traces close to device and to
as far away from each other to reduce
the supply lines parasitic errors VS+
as possible RF

Offset trim Offset trim

RG
GND ±IN V+ GND

VIN +IN OUTPUT

Use low-ESR, ceramic

V± NC
bypass capacitor

Use low-ESR, GND VOUT

VS±
ceramic bypass Ground (GND) plane on another layer
capacitor

Figure 33. OPA277 Layout Example for the Noninverting Configuration

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10.3 DFN Package

The OPAx277 series uses the 8-lead DFN (also known as SON), a QFN package with contacts on only two sides
of the package bottom. This leadless, near-chip-scale package maximizes board space and enhances thermal
and electrical characteristics through an exposed pad.
DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved
electrical parasitics, with a pinout scheme that is consistent with other commonly-used packages, such as SO
and MSOP. Additionally, the absence of external leads eliminates bent-lead issues.
The DFN package can be easily mounted using standard printed-circuit-board (PCB) assembly techniques. See
QFN/SON PCB Attachment (SLUA271) and Quad Flatpack No-Lead Logic Packages (SCBA017), both available
for download at www.ti.com.
The exposed leadframe die pad on the bottom of the package should be connected to V–.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 WEBENCH Filter Designer Tool

WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.

11.1.1.2 TINA-TI™ (Free Software Download)

TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.

11.1.1.3 TI Precision Designs

The OPA277 is featured in several TI Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.

11.2 Documentation Support

11.2.1 Related Documentation
For related documentation, see the following:
• QFN/SON PCB Attachment, SLUA271
• Quad Flatpack No-Lead Logic Packages, SCBA017
• EMI Rejection Ratio of Operational Amplifiers, SBOA128
• Circuit Board Layout Techniques, SLOA089

11.2.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
OPA277 Click here Click here Click here Click here Click here
OPA2277 Click here Click here Click here Click here Click here
OPA4277 Click here Click here Click here Click here Click here

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11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA2277AIDRMT ACTIVE VSON DRM 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM BHZ

OPA2277AIDRMTG4 ACTIVE VSON DRM 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM BHZ

OPA2277P ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA2277P

OPA2277PA ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA2277P
A
OPA2277PAG4 ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA2277P
A
OPA2277U ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR OPA
2277U
OPA2277U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
OPA2277U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
OPA2277UA ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UA/2K5E4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UAE4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UAG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
OPA277AIDRMR ACTIVE VSON DRM 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM NSS

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2021

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA277AIDRMT ACTIVE VSON DRM 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM NSS

OPA277P ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA277P

OPA277PA ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA277P
A
OPA277PAG4 ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA277P
A
OPA277U ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR OPA
277U
OPA277U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR OPA
277U
OPA277U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR OPA
277U
OPA277UA ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UA/2K5E4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UAE4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UAG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR OPA
277U
OPA4277PA ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type OPA4277PA

OPA4277UA ACTIVE SOIC D 14 50 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA

OPA4277UA/2K5 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2021

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA4277UA/2K5E4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA

OPA4277UAE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA2277, OPA4277 :

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2021

• Enhanced Product : OPA2277-EP, OPA4277-EP

• Space : OPA4277-SP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2277AIDRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
OPA2277U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2277UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA277AIDRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
OPA277AIDRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
OPA277U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA277UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4277UA/2K5 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2277AIDRMT VSON DRM 8 250 210.0 185.0 35.0
OPA2277U/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA2277UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA277AIDRMR VSON DRM 8 3000 356.0 356.0 35.0
OPA277AIDRMT VSON DRM 8 250 210.0 185.0 35.0
OPA277U/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA277UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA4277UA/2K5 SOIC D 14 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA2277P P PDIP 8 50 506 13.97 11230 4.32
OPA2277PA P PDIP 8 50 506 13.97 11230 4.32
OPA2277PAG4 P PDIP 8 50 506 13.97 11230 4.32
OPA2277U D SOIC 8 75 506.6 8 3940 4.32
OPA2277UA D SOIC 8 75 506.6 8 3940 4.32
OPA2277UAE4 D SOIC 8 75 506.6 8 3940 4.32
OPA2277UAG4 D SOIC 8 75 506.6 8 3940 4.32
OPA2277UG4 D SOIC 8 75 506.6 8 3940 4.32
OPA277P P PDIP 8 50 506 13.97 11230 4.32
OPA277PA P PDIP 8 50 506 13.97 11230 4.32
OPA277PAG4 P PDIP 8 50 506 13.97 11230 4.32
OPA277U D SOIC 8 75 506.6 8 3940 4.32
OPA277UA D SOIC 8 75 506.6 8 3940 4.32
OPA277UAE4 D SOIC 8 75 506.6 8 3940 4.32
OPA277UAG4 D SOIC 8 75 506.6 8 3940 4.32
OPA277UG4 D SOIC 8 75 506.6 8 3940 4.32
OPA4277PA N PDIP 14 25 506 13.97 11230 4.32
OPA4277UA D SOIC 14 50 506.6 8 3940 4.32
OPA4277UAE4 D SOIC 14 50 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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