ESD Circuit Synthesis and Analysis Using TCAD and SPICE

John Rodriguez, Michael C. Smayling, and William L. Wilson"

Texas Instruments
Houston, Texas. USA

*Electrical and Computer Engineering Department, Rice University

Houston, Texas, USA

Abstract diffusion combination. The N+ resistor allows the internal

voltage to be clamped to the drain junction breakdown level
This paper describes the development of a SPICE sub-circuit of 15V, which is sufficient to protect the gate oxide, even
model for an avalanche triggered SCR used for ESD though the pad voltage may exceed this value. The Human
protection. The approach for developing the model is Body Model (HBM) ESD failure threshold for this device is
presented, including the extensive use of TCAD tools, which above 6KV.

1-'
provides physical insight. This is the first SPICE model
presented for an avalanche triggered SCR demonstrating
accurate terminal behavior under both steady state and WELL
transient triggering conditions. It is intended for use in a
design environment for examining ESD circuit behavior at
the clip level. I
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Introduction !
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Design of ESD protection circuits is an important part of y- ! 4- -
product development. From a process development view, the !
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challenges posed by the trends in advanced technologies
include the thinning of the gate oxides, the shallow
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source/drain junctions, and the importance placed on reduced Ai !

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U 0 capacitance (1). In addition, ESD circuits are complex I !
and often consist of multiple stages that integrate various ! ! 00
components to form a complete structure (2-4). In order to ! ! 00
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address these challenges economically, a systematic ESD ! I I 00
circuit development approach is necessary. L ! 00

In this paper, we present the results of a novel approach that N+ N+ P+ ' N+

emphasizes SCR physics and operation using detailed TCAD f \ f \
simulations and component measurements. The process and Trigger Device Primary Protection Device
device simulationsyield valuable insight into the dynamics of Figure 1. Layout View ofthe Avalanche Triggered SCR.
the ESD components and circuits. Silicon test structures
were fabricated to verify the TCAD results. The systematic Grounded Gate
NMOS ~ f Primary
i Protection
~ ~ Device:
~ ~
methods outlined here emphasize the use of CAD tools for PNPN SCR structure
ESD protection circuit analysis and synthesis. Methods of
validating the models are proposed. To Internal ++
Device

Avalanche Triggered SCR Description

Circuits 0
Diffusion Resistor I "
Fig. 1 shows the layout of the avalanche triggered SCR used
in this study. The input pad is connected to P+ and N+
diffusions inside an N-well, as well as to one end of an N+
dfiised resistor. The drain of a grounded gate NMOS is
connected to the other end of the resistor. This connection
also leads to the internal chip circuitry in the actual product. Lw-1 P- Epi / P+ Substrate
The cross section of this circuit is shown in Fig. 2. The SCR Figure 2. Avalanche Triggered SCR cross-section, showing the components
consists of the P+ difFusion/N-well/P-well/N+ source of interest and some of the important elements required to model in SPICE.

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 Design: Circuit & ComponentsLayout, Process

Circuit Physical
Test Structure Structure

Components
-- Component Bias
Charactenzation Conditions
(LabVIEW) & SPICE
Parameter Extraction
Steady State & (IC-CAP). Component 4 Device Simulation
Transient Bias Models Validated with
Conditions Measured Data Circuit I-V Data
- & “Intemal Views”
1
Sub-Circuit Schematic
v v & Model for SPICE
Circuits
Steady State & v 1
Transient SPICE ESD Circuit
Measurements Simulations ESD Biases Chip Level Circuit
Response

Based on S F k E
ESD Circuit SPICE Parameters
Model Complete
1 I I I

Figure 3 Flow chart showing the systematic approach for developing accurate SPICE models for ESD components and circuits The simulated I-V data for
components can be used for SPICE parameter extraction if component structures are not available The “intemal views” are physical parameters obtained from
the device simulator at strategic points on the simulated I-V charactenstics, which explicitly demonstrate the circuit dynamics The intemal views, together
with the component SPICE models are used to develop a physically based sub-circuit model of the ESD protection circuit Steady state and transient response
of the circuit are used for model validation Physically based models allow analysis of chip level behavior dunng ESD stress and SPICE parameter sensitivity

Component and Circuit Analysis Methodology

The AT-SCR is an example of a complex protection circuit

consisting of multiple stages and components. A systematic N-well
approach is necessary in order to develop an accurate SPICE
model. Fig. 3 shows a flow chart of the process used in
developing the SPICE model for the AT-SCR. From the
layout and the simulations, four specific components were
identified:

N+ diffusion Resistor,
NMOS transistor in breakdown mode,
Lateral NPN transistor,
PNP transistor.
Figure 4.Mid-injection current flowlines for the lateral NPN transistor.
All of these components were simulated individually using
the TMNAvant! TCAD tools. As an example, Fig. 4 shows
the lateral NPN transistor mid-injection current flowlines to verify the simulations. The modeling data were collected
during the forward gummel simulation. Simulations were also using IC-CAP software. LabVIEW software on a PC was
run for the complete ESD circuit. used for measuring the characteristics of the components on
different wafers for statistics. In this case, generic routines
Specially designed test structures including the ESD circuit using parameterized bias conditions were helpful in gathering
and its components were fabricated and characterized in order the data for all of the components in an efficient manner.

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 I

Circuit measurements were made on the integrated SCR demonstrates the accuracy of the SCR model in steady state
structure using a TEKTRONIX curve tracer for steady state operation.
triggering and on-state characteristics. A pulse generator was
used to apply -15 nsec rise time voltage pulses to the circuit Fig. 8 shows electron current density plots. on a log scale,
through a load resistor. Source and pad voltages were obtained from the circuit device simulations. The letters in
measured using a lGHz bandwidth digital oscilloscope. The the figure refer to the measured I-V “turn-points’’ labeled in
fast rise time measurements required hgh frequency probes Fig. 5 . These plots explicitly indicate that as the NMOS
and a test fixture designed to minimize lead inductance and transistor enters a high current mode of operation, the lateral
capacitance. Packaged parts were used for these transient NPN transistor begins to conduct. The simulation results also
measurements, on circuits that had been previously indicate (not shown here) that the PNP transistor is the last
characterized using component measurements and w e component to participate in the conduction, as it turns on at
tracer data. The steady state and transient circuit level data point D. Figure 9 shows the measured and simulated response
were useful for validating the ESD sub-circuit SPICE model. of the SCR voltages under the transient excitation. Figure 10
shows the simulated pad current for the same transient
SPICE Model Discussion and Validation condition.
0-
Figure 5 shows curve tracer data for the SCR. This data show Input
six regions of interest, which require explanation. In A, the Pad
device is off and behaves as an open circuit. In B, the drain is
at avalanche breakdown and at C the MOS is in a “snapback’ 1
S
holding mode (4,5). D is the SCR trigger point and E is
latchup. F is the holding point, just before the SCR turns
back off. The MOS avalanche current (at point B) through
the P-well resistance serves to raise tlie potential near the
surface. allowing the P-well/N+ source diffusion to become
forward biased and to become an electron emitter. Some of
these electrons diffuse through the P-well and drift to the N+
contact in the N-well, which now behaves as a NPN collector
(point C). This current forward biases the N-well@+ junction
via the N-well resistance; this effect is clearly observed from Figure 6. SPICE sub-circuit model of the avalanche triggered SCR.
the NPN current density result shown in Fig. 4. When the
PNP turns on, the SCR latches.

5 0.06

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5 0.05 -

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2
i
0.03 -
0.02 -
0.01 -
0.00 4 ? , . , F , ,
0 2 4 6 8 10 12 14 16 18 20
Pad Voltage (V)
L .. .. . ... . . -
Figure 7. ISPICE simulation of the curve Uace measurement in Fig. 5 shows
Figure 5 . Curve tracer data for the avalanche triggered SCR. the model accuracy in stead; state triggering and turn-offcondition.

ESD Simulations
The SPICE representation of this circuit is shown in Fig. 6.
The possibility of avalanche breakdown of the resistor N+/P- Figures 11 and 12 show the voltage and current response of
well junction, observed under some conditions, is accounted the SCR circuit to a 2KV HBM ESD stress. Again, as the pad
for with diode D 1. D2 is the N- welvP-substrate diode. Fig. voltage rises past the NMOS avalanche point, the internal
7 shows the SPICE simulation result of the curve trace data circuits’ voltage becomes clamped, protecting the internal
shown in Fig. 5, including the turn off slope. This simulation circuitry. In all cases, the SPICE runs demonstrate the same

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 sequence of component triggering: NMOS - NPN - PNP -
latchup, as observed in the TCAD results.
0 16

0 14 .y
.....
Conclusions \
A systematic approach for ESD circuit synthesis and analysis
using CAD tools has been demonstrated. Methods of
validating the models are presented, and excellent results are 0.02 -
obtained in the specific example of an avalanche triggered
SCR. This approach makes extensive use of simulation tools
for gaining insight into the circuit dynamics. Test structures
consisting of the ESD circuit as well as its components are
suggested as a way to verify the modeling results.

35 -
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Vertical
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Distance Horizontal

P+

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Figure 8. Plots of the electron current density on a log scale, showing the
evolution of the current flow at key points on the I-V. The NMOS is
conducting first, followed by the lateral NPN. The PNP starts to conduct at
point D, initiating the latchup condition in E.

.-----
-----_____ References

-Simulated Fad (1) Kaoru Narita, Yoko Horiguchi, Takeo Fujii, Kunio Nakamura, “A novel
............ on-chip electrostatic discharge (ESD) protection with common discharge
...
lines for high speed CMOS LSI’s,” IEEE Transactions on Electron Devices,
Vol. 7, NO. 44, pp. 1124 - 1130, July 1997.
I
! (2) Charvaka Duwury, Ajith Amerasekera, “ESD: A pervasive reliability
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(3) Amerasekera and Duvvury, ESD in Silicon Integrated Circuits, New
York Wiley & Sons, 1995.
” (4) T. Li, et al., “Study of a CMOS U0 protection circuit using circuit level
0 25 50 75 100 125 150 simulation,” IRPS Proceedings, pp. 333-338, 1997.
Time (nsec) ( 5 ) Ajith Ameresekera, Sridhar Ramaswamy, Mi-Chang Chang, Charvaka
Duvvury, “Modeling MOS snapback and parasitic bipolar action for circuit
Figure 9. Measured and simulated voltages of the SCF. mder a low voltage level ESD and high current simulations,” IRPS Proceedings, pp. 3 18-326,
transient trigger condition. 1996.

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