Chapter 6

MOSFET V t

6.1 15 -cm =1015 cm-3, E f = E v + 0.26eV oxide trap density = 8x1010 cm-2, Z = 50
m, L = 2 m, T ox = 5nm

(a) V’ fb = V fb + V. V fb = 3.1 - (3.1 + 0.86) = -0.86eV, V = Q f /C ox = 18.5 mV.

Therefore V’ fb  V fb = -0.86 eV
When oxide thickness is thin, the trap charge effect can be ignored.

(b) V t = V’ fb + V ox + V s  V fb + 2 B + (2 s qN a 2 B )1/2/C ox

= -0.86 +0.6 + 0.02V = -0.24V

(c) To make V t = 0.5V, one should implant boron into silicon substrate such that
 V t = Q imp /C ox . Therefore ion implant dose should be
(0.5V+0.24V)  C ox q = 3.21012 cm-2.

6.2 (a) Using Equation 4.16.4 and referring to Table 1-4, we find
 N (GaAs)   4.7  1017 
bi   Bn  kT ln c   1V  kT ln 17 
  0.96V .
 Nd   110 
Then,
2 sbi 1 213 0 bi 1
Wdep    0.12 m .
q Nd q Nd

213 0  bi  V  1
2
qN d Wdep
(b) Wdep  0.2 m  V    bi  1.82V .
q Nd 213 0 
A negative V g is need to increase W dep and turn-off the channel. (A metal/N-
type semiconductor Schottky diode exhibits the same forward/reverse bias
properties as an P+/N diode.)

(c) Yes. If the positive V g is kept small (say 0.5V), the forward current of the
Schottky gate maybe comparable to the subthreshold drain leakage current. A
positive V g would reduce W dep and therefore raise I ds .

(d) The channel thickness or doping concentration must be reduced so that

W dep  channel thickness at V g = 0.

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 F kT N sub
6.3 Cox  6.9  10 7 2
, B  ln  0.47eV
cm q ni
1
(a)` Vt  V fb  2 B  2q s N sub 2 B
C ox
Eg 1
Vt    B  2 B  2q s N sub 2 B  0.09  0.61  0.52V
2 C ox
1
(b) Vt  V fb  2 B  2q s N sub 2 B
C ox
Eg 1
Vt    B  2 B  2q s N sub 2 B  0.56  0.47  0.61  1.64V
2 C ox
1
(c) Vt  V fb  2 B  2q s N sub 2 B
Cox
E 1
Vt  g   B  2 B  2q s N sub 2 B  0.52V
2 Cox

(d) Vb  0V
Vs  0V
Vd  2.5V
Vg  2.5V

(e) Vb  2.5V
Vs  2.5V
Vd  0V
Vg  0V

 nWC ox
(f) I dsat  (V gs  Vt ) 2
2L
I dsatc (2.5  (0.52)) 2
  5.3
I dsatb (2.5  (1.64)) 2

The transistor with the lower absolute value of threshold voltage has a higher
saturation current. That is why P+ poly-gate PMOSFETs are typically used in
IC.

(g) The ratio of the current is the ratio of the mobilities.

To find  n ,
Vgs  Vt  0.2/ 6Toxe  2.5  0.52  0.2V / 6  5  10 7 cm  1.07 MV / cm
and  n = 250cm2V-1s-1.

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 To find  p ,
 V gs  1.5Vt  0.25 / 6Toxe   2.5  1.5  (0.52)  0.25V / 6  5  10 7 cm  1.01MV / cm
and  p = 63cm2V-1s-1.

I dsat ( c ) p 1
 
I dsat ( a ) n 4

Basic MOSFET IV Characteristics

6.4 (a) Due to the highly doped regions nearby, transistor C-V always approaches C ox
in inversion. Hence, it is impossible to determine the frequency. Either high or
low frequency could have been used.

(b) Since V t >V fb , this is a NMOS.

(c) From the I d -V g curve, V t is 0.55V. More precisely,

W  V  V
I d  C ox Vds V g  Vt  ds   0.55  Vt  ds  0
L  2  2
V t  0 .5 V
W
(d) Slope of curve I d - V g line  C ox Vds  5  10 3  1 .
L
Vds  0.1V
From the CV curve,
W F
C ox WL  1pF  C ox  10 -4
L cm 2
5  10 3 cm 2
Thus,    500
0.1  10  4 Vs

(e) Vdsat  V g  Vt
C oxW A 2
I dsat  (Vdsat ) 2  0.025 2
.Vdsat
2L V

Vg 1V 2.5V
V dsat 0.5V 2V
I dsat 6.25mA 100mA

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 I d (mA)
V g =2.5V
100

V g =1V
6.25
V d (V)
0.5 2

6.5 (a) For V gs =4V, V dsat ~ 3V=(V gs -V t ) and V t =1V

(b) I dsat   n C oxW / 2 L  (V g  Vt ) 2

C ox  3.45  10 7 F / cm 2
2 I dsat
n   361cm 2 / Vs
W 
Cox  (Vg  Vt ) 2
L

(c) At V gs =3V, V dsat =(3-1)V=2V

I dsat  361  3.45  10 7  (10 / 2)  (3  1) 2 / 2  1.25  10 3 A

6.6 (a) At saturation, V d = V dsat = V g -V t . V dd =2V. Therefore the transistor is in

saturation mode when V g <2.5V. I dsat = 125(V g -0.5)2A. When V g >2.5V, the
transistor is in linear region with I d = 500(V g -1.5) A.

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 40
35
30
SQRT(Idsat, A) 25
20
15
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Gate Voltage, Vi (V)

(b) & (c) Transconductance: solid line, Output Conductance: dotted line
gd , gm
gm
500 A/v

250 A/v
gd

Vi
0.5 1.5 2.5 3.0

6.7 (a) V gs  Vt  2V
V gs  2.5V
(b) Qn  C ox (V gs  Vt  Vc )  0 (Pinch-Off)

(c) I ds @ Vds  4V
Vdsat  V gs  Vt  3V
(in saturation)
I ds  (V gs  Vt ) 2
32
I ds  10 3  2
 2.25  10 3 A
2

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 (d)
C

Cox
(Same for high and
low frequencies)

Vfb Vt Vg

kT N a
6.8 (a)  B  ln  0.297V
q ni
 ox
C ox   7.08  10 8 F
t ox cm 2
Eg
V fb   Si  (  Si    B )  0.857 V
2
2 s qN a 2 B
V g  V fb  Vs  Vox  Vt  V fb  2 B   0.064V
C ox
 nCoxW
(b) I dsat  V g  Vt   1.21mA
2

2L

(c) Since V d is less than (V g -V t ), it is in the linear region.

C oxW  Vd2 
Id  V g  V V t d  
L  2 
I d C oxW
gd 
V D

L

Vg  Vt   Vd  1.17mS 

(d) Since V d is less than (V g -V t ), it is in the linear region.

C oxW  Vd 
2

Id  V g  Vt Vd  
L  2 
I d C oxW
gd   Vd  1.13mS
V g L

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 Potential and Carrier Velocity in MOSFET Channel

dVc dV
6.9 I d  Q n  n W  (V g  Vt  Vc )C ox  n c W
dx dx
x Vc
Id
 dx   (V g  Vt  Vc )dVc
0
 n C oxW 0

 I d  x /(  n C oxW )  (V g  Vt )Vc  1 / 2Vc2

Solving this quadratic equation of V c , we get

2I d x
Vc ( x)  (V g  Vt )  (V g  Vt ) 2 
 n C oxW

Choosing “-” so that V c (0)=0,

 2I d x 
Vc ( x)  (V g  Vt ) 1  1  
  n C oxW (V g  Vt ) 2 
 W 
 2 x n C ox (V g  Vt ) 2 
 (V g  Vt ) 1  1  2L 
  n C oxW (V g  Vt ) 2 
 

 (V g  Vt ) 1  1  x / L . 

6.10 (a) I ds  WCoxe (Vgs  mVcs  Vt )  es d Vcs dx

x
Vcs
I
0
ds dx  WC oxe  s  (V gs  mVcs  Vt )dVcs
0

mVcs
I ds x  WC oxe  s (V gs  Vt  )Vcs
2

Equating the expression above with

W m
I ds  C oxe  s (V gs  Vt  Vds )Vds ,
L 2

we get

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 x mVds  mVcs
V gs  Vt  Vds  (V gs  Vt  )Vcs
L 2  2
2 x
mVcs  2(V g  Vt )Vcs  (2(V g  Vt )  mVds )Vds  0
L

Solving the quadratic equation, we get

x
V gs  Vt (V g  Vt ) 2  m (2(V g  Vt )  mVds )Vds
Vcs   L
m m
V gs  Vt x
Vcs  (1  1  )
m L

 x
(b) Qinv ( x)  C oxe (V gs  mVcs  Vt )  C oxe V gs  Vt  (V gs  Vt )(1  1  
 L
  x   x
 C oxe V gs  Vt 1  1  1    C oxe (V gs  Vt ) 1  
  L   L

dVcs Vg  Vt   1  1  1  Vg  Vt   1 

(c)  ε( x)        
dx m  2  1  x  L  2mL  1  x 
 L  L

 
dVcs  n V g  Vt   1 
 ( x)   n   n ε( x)   
dx 2mL  1 x 
 L
 
 x   n V g  Vt   1 
(d) WQinv  n ε  W .C oxe (V gs  Vt ) 1  .  
 L 2mL  1 x 
 L
WC oxe  n
 Vgs  Vt 2  I dsat
2mL

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 (e)
V cs

IV Characteristics of Novel MOSFET

dVc dV
6.11 (a) I d  Qn  n W  (V g  Vt  Vc )C ox ( x)  n c W
dx dx
 dV
 (V g  Vt  Vc ) 2ox  n c W
Ax  B dx
L/2 Vds

 
L / 2
I d  ( Ax 2  B)dx  
0
(V g  Vt  Vc ) ox  nWdVc

A
 I d  [ x 3  Bx] LL/ 2/ 2   ox  nW [(V g  Vt )Vc  1 / 2Vc2 ]V0ds
3
W  ox  n
 Id   2
 [(V g  Vt )Vds  1 / 2Vds2 ]
L AL
B
12
I
(b) Vdsat  Vds @ d |Vgs  0 Vdsat  V g  Vt
Vds
(c) It suggests a large W dmax . Vox  Qn / C ox

dVc dV
6.12 (a) I d  Qn  n W ( x)  (V g  Vt  Vc )C ox  n c W ( x)
dx dx
L Vds

  I d / W ( x)dx   (V g  Vt  Vc )  n C ox dVc
0 0

 I d  ln[(W0  L) / W0 ]   n C ox [(V g  Vt )Vds  1 / 2Vds2 ]

 n C ox
 Id  [(V g  Vt )Vds  1 / 2Vds2 ]
ln(1  L / W0 )

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 I d
(b) Vdsat  Vds @ |V  0 Vdsat  V g  Vt
Vds gs
 n C ox (V g  Vt ) 2
 I dast  
ln(1  L / W0 ) 2

CMOS
6.13 (a) V fb,NMOS = -(E g /2) – (kT/q * ln(5e15/1e10)) = - 0.55 -0 .4 = -0.95V
V fb,PMOS = -0.55 + 0.4 = -0.15V
Not symmetrical

(b) V fb,NMOS = 0.55 - 0.4 = 0.15V

V fb,PMOS = 0.55 + 0.4 = 0.95V
Not symmetrical

(c) Since V ox and V s will be symmetrical, I would use a mid-gap gate material such
as tungsten.
So the workfuction will be 4.05 eV + E g,Si /2 = 4.6eV. However, processing
issues makes tungsten (or any metal gates for that matter) a challenge to
implement.

(d) In the same process, the NMOS and PMOS will have same oxide thickness. If
the substrate doping levels for n and p flavors are the same, then I would use P+
gates for PMOS devices and N+ gates for NMOS devices. In this way, the
flatband voltages will be symmetrical and the resulting |V t | small.

6.14 (a) PMOS, N-type substrate:

N
 n  kT ln d  0.38V
ni
Eg
Vfb   m   si    n  4.1  4.05  0.55  0.38  0.12V .
2

NMOS, N-type substrate:

N
 p  kT ln a  0.42V
ni
Eg
Vfb   m   si    p  4.1  4.05  0.55  0.42  0.92V
2

 ox F
(b) C ox   6.9  10 7
t ox cm 2

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 PMOS:
1
Vt  V fb  2 n  2 s qN d 2 n  0.12  0.76  0.10  0.98V
C ox
NMOS:
1
V fb  2 p  2 s qN d 2 p  0.92  0.84  0.24  0.16V
C ox

(c) The threshold voltage must be changed by

Qimpl
Vt    0.82V .
C ox
Hence,
C
Qimpl  5.7  10 7 .
cm 2

 s dVcs dx
6.15 I ds  WC oxe (V gs  mVcs  Vt )
dVcs
1 ε sat
dx
0
L
I ds dx  
0
Vds
WC oxe  s V gs  mVcs  Vt   I ds ε sat dVcs
Vds m
I ds L  I ds  WC oxe  s (V gs  Vt  Vds )Vds
 sat 2

m V 
I ds  WC oxe  s (V gs  Vt   L  ds 
Vds )Vds
2 ε sat 
W m  V  I ds (Long channel)
I ds  C oxe  s (V gs  Vt  V ds )V ds 1  ds   .
L 2  Lε sat  1  V ds ε sat L

6.16
NFET Operation Mode PFET Operation Mode
A Cut-off Linear
B Saturation Linear
C Linear Saturation
D Linear Cut-off

A: Vgs<Vth for NFET, therefore it is cut off. For PFET |Vgs| > |Vth| and
|Vds|<|Vdsat| (|Vds|~0V, |Vdsat| ~ 1.05V), so it operates in linear mode.

B: For NFET Vgs > Vth and Vds>Vdsat (Vds~1.75V, Vdsat ~ 0.3V), so it operates
in saturation mode. For PFET |Vgs| > |Vth| and |Vds|<|Vdsat| (|Vds|~0.25V, |Vdsat|
~ 0.6V), so it operates in linear mode.

The answers to C and D can be worked out through the same procedure.

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 6.17 (a)

Vo
{ NMOS cut-off
PMOS linear

A { NMOS saturated
PMOS linear

B
{ NMOS saturated
PMOS saturated

{ NMOS linear
PMOS saturated
C { NMOS linear
PMOS cut-off
D
0 VTn Vx (VDD+VTp) V
DD
Vi

(b) At the point B where V i =V x , the NMOS is just becoming saturated from the
linear region. Since NMOS is in the linear region
 V x  Vtn 2 
I dn  K N V x  Vtn V x  Vtn   
 2 

Since PMOS is saturated

I dp  P Vdd  V x  Vtp 
K 2

But I DN = I DP
 Vx  1  35
2

40V x  1   5  Vx  1
2 2
 
 2  2
 
40(V x - 1)2 = 40(4 - V x )2  V x = 2.45 V

Thus,
Point V i (V) V o (V)
A 1 5
B 2.45 3.45
C 2.45 1.45
D 4 0

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 Body Effect
6.18 For a P-channel MOSFET, we have
2 s qN d (2 B  Vbs )
Vt  V fb  2 B 
C ox
2 s qN d
V t  ( 2 B  Vbs  2 B )
C ox
(a) For 100 nm oxide, C ox = 3.4510-8 F/cm2.
If V bs = 5V, V t = -0.8V.
By iteration, using initial guess of  B = 0.3V, we obtain
N d = 8.91014 /cm3 and  B = 0.284V.

(b) If V sb is -2.5 V, V t = -0.497V.

V t = -1.5 - 0.497 = 2.0 V

Velocity-Saturation Effect
6.19 In all 3 cases, use the general equation I=WQ inv v drift .

Case A:
The NMOS is in the triode region.
On source side, Q inv =C ox (V g -V t ) = 138e-9(5-.7) = 593 nC/cm2.
So  drift = I/(WQ inv ) = 1.5e-3/(15e-4  593e-9) = 1.7 x 106 cm/sec.
On drain side, Q inv = C ox (V g -V t -V d ) = 138e-9(5-.7-.5) = 524 nC/cm2.
Thus,  dr = 1.5e-3/(15e-4  524e-9) = 1.9 x 106 cm/sec.

Case B:
The NMOS enters saturation region.
On source side,  dr = 3.75e-3/(15e-4593e-9) = 4.2 x 106 cm/sec.
On drain side, the electron velocity is saturated.
Thus,  dr =  sat = 8 x 106 cm/sec.

Case C:
Similar to case B.
On source side,  dr = 4e-3/(15e-4593e-9) = 4.5 x 106 cm/sec.
On drain side,  dr =  sat = 8 x 106 cm/sec.

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 6.20
T ox W L Vt Vg
V dsat  No change   
I dsat     

Reducing T ox means smaller V t => larger V dsat (1/(V g -V t ) + 1/(E sat L))-1 & larger
I dsat (Q inv  C ox ).
Reducing W has no effect on V dsat and decreases I dsat since I dsat = WQ inv v sat .
Reducing L reduces V dsat (as discussed in lecture) and increases I dsat . If you want to
consider very short-channel length devices (L => 0), then essentially I dsat is
independent of L.
Reducing V t => larger V dsat & larger I dsat .
Reducing V g => smaller V dsat & smaller I dsat .

 V   V 
6.21 I d   s C oxW V gs  Vt  m ds Vds  L  ds 
 2   ε sat 
 WC ox V gs  Vt  mVds Vsat

 WC ox V gs  Vt  mVds  s
ε sat
2

 V   
V gs  Vt  m ds Vds  V gs  Vt  mVds ε sat / 2 L  ds
V

 2   ε sat 
ε L
 V gs  Vt  mVds  sat  V gs  Vt  mVds 
Vds
2 2

V gsVds  VtVds  V gs  Vt  mVds ε sat L

Vds V gs  Vt  mε sat L   (V gs  Vt )ε sat L

1
(V g  Vt )ε sat L
 m 1 
Vds   
Vgs  Vt  mε sat L   (Vgs  Vt ) ε sat L 

  1  m
 m  C oxe  ns  V gs  Vt 
W
W
C oxe  ns V gs  Vt  Vds Vds   

L  2  L   Vds  2
6.22 I ds  
V
1  ds 1  1  1
 
ε sat L Vds2  ε sat L  Vds
1 m 1
 
Vdsat V gs  Vt ε sat L

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 6.23 (a) We know that
 
 
1
   2
   1
V V
Vdsat  ε c L 1  2 
g t

E c L  
 
 1

 4 
 c L = 0.1 V  Vdsat  0.1  1  2 
2
   1 = 0.54 V
 0.1  
 

 1

 4 
(b)  c L = 10 V  Vdsat
2
 10  1  2    1 = 1.83 V

 10  
 
(c) We know that
 C Z 2 10fF
I dsat  n0 ox Vdsat and Cox Z  .
2L L
 n0 10fF
7mA  0.54 2
2 L2
   n0 = 480 cm2 V-1 s-1

6.24 V dsat =  sat L(V g -V t ) / (V g - V t +  sat L)

What is  sat ? 2v sat / s =  sat .  s is given by the universal mobility curve.

At T ox =60A, (V g +V t +0.2)/6T ox =  eff = .9MV/cm.

From the curve,  s ~ 250 cm2V-1s-1.

This yields  sat ~ 2(8x106)/250 V/cm = 6.4x104V/cm. Plug this back into the
expression for V dsat to get L ~ 0.19um.

I dsat /W = Q inv v sat = C ox (V g -V t -V dsat )v sat

= (3.9 o /60e-8)  (2.5-.5-.75)  8106 = 575uA/um width.

Note: You will often find in literature that the saturation current is stated in units
of uA/um instead of amperes. Also, notice that the Q inv at V c =V dsat is not zero.
That is, I dsat is limited by velocity saturation instead of pinch-off.

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 6.25 (a)
V gs  Vt
1 2
mE sat L
2mv sat L 2  1.2  8  10 6 cm / s  1  10 5 cm
V gs  Vt  mE sat L    0.64V
 ns 300cm 2 / V  s
(b)
V gs  Vt  mE sat L

Vgs  Vt  ns Vgs  Vt  300cm 2 / Vs  0.2V

L    3.13  10 6 cm  31.3nm
mE sat 2mv sat 2  1.2  8  10 6 cm / s

Effective Channel Length

6.26 (a) For very small V ds ,
V L
Rchannel  ds 
I ds  s C oxW (V g  Vt )
In a short-channel device, S/D resistance can seriously degrade saturation
current. Note that series resistance is worse for higher currents because R channel
is the lowest under these bias conditions.

(b) Rtotal  Rs  Rd  Rchannel  Rsd  Rchannel

 Leff  Lgate  L
 Rsd     Rsd  ( )
  s C oxW (V g  Vt )   s C oxW (V g  Vt )

Think of R total as the y-value, L gate as the x-value, and ( s C ox W(V g -V t ))-1 as the
slope. This fits nicely into the standard equation of the line: y = mx + b. You
can choose devices with several gate lengths and measure the current from these
devices at discrete gate voltages. Remember, that you are assuming V ds is small
(<100mV) in these measurements.

From the current, you can plot R total versus L gate . One sample data line is taken
with the same V g at different gate lengths. For example, if you measure your
current at 5 different V g ’s, you will get 5 separate curves. Ideally, all the lines
will intersect at the same point on your plot. This intersection point occurs at
L gate = L and R total = R sd .
In practice, it is not always straightforward to make such a plot. For instance,
V t can be difficult to determine accurately. Also, there is a strong dependence
of mobility on gate voltage for thin-oxide MOSFETs. It’s a good idea to check
your data by taking measurements at several different V g instead of at 2 or 3
gate voltages.

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 (c) I dsat  k(Vgs -I dsat Rs -Vt ) , where k is a constant of proportionality
I dsat ( 1  kRs )  k(Vgs -Vt )  I dsat 0 , notice here that k  I dsat0 /(V gs - Vt )
I dsat  I dsat 0 / ( 1  kRs )  I dsat 0 / ( 1  I dsat 0 Rs /(V gs -Vt ))

(d)  sat = (V gs +V t +0.2)/6T ox = 1.1 MV/cm.

 s ~225cm2V-1s-1 is picked out from the universal mobility plot.
 sat = 2v sat /( s ) = 7x104V/cm.
I dsat0 = (long channel I dsat ) / (1+ (V gs -V t )/( sat L))
= 1.6mA / (1 + (1.1/.7)) = 0.622mA.

Plug in 0.622mA into the expression derived in part c and get the following:
@ R s = 0ohms, I dsat = .62mA
@ R s = 100ohms, I dsat = .59mA
@ R s = 1000ohms, I dsat = .40mA

6.27 (a) Choose three transistors with same channel width, Z, and different channel
length, L 1 , L 2 ,and L 3 . Measure I dsat at saturation condition for the 3 transistors
to
get I d1 , I d2 , and I d3 . Solve the 3 equations to get C ox , and L eff .

(b)L = L- L eff when gate oxide thickness is 4.5nm. Z =10 m,  = 300 cm2/Vs.
Using approach of (a), L  0.1 m.

3.0
-1
2.5 Idsat = const(Ldrawn - L)
-1

2.0
Idsat

1.5

1.0
0.1 m : L
0.5

0.0
0 1 2 3 4 5
Channel Length(m)

(c) 2.59mA(L 1 - L eff ) = ZC ox (V gs -V t ), V t = 0.5V.

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© 2010 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This publication is protected by Copyright and written permission should be obtained from
the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying,
recording, or likewise. For information regarding permission(s), write to: Rights and Permissions Department, Pearson Education, Inc., Upper Saddle River, NJ 07458.