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Intel Interview Questions

This document contains a list of interview questions related to Intel projects. Some of the questions covered include: the difference between setup and hold time violations and which is more dangerous; synchronous vs asynchronous circuits and which is better in terms of area, speed and power; combinational vs sequential circuits; 0-99 and 0-1-2-3-4-0 sequence detectors; VLSI and ASIC design flows; types of routing; drawing logic gates from NAND gates; full adder gate-level circuit; toggling circuit; metastability and how to prevent it; race conditions and how to remove them; MOSFET I-V characteristics; CMOS inverter circuit and voltage transfer characteristics; setup and hold time with

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181 views

Intel Interview Questions

This document contains a list of interview questions related to Intel projects. Some of the questions covered include: the difference between setup and hold time violations and which is more dangerous; synchronous vs asynchronous circuits and which is better in terms of area, speed and power; combinational vs sequential circuits; 0-99 and 0-1-2-3-4-0 sequence detectors; VLSI and ASIC design flows; types of routing; drawing logic gates from NAND gates; full adder gate-level circuit; toggling circuit; metastability and how to prevent it; race conditions and how to remove them; MOSFET I-V characteristics; CMOS inverter circuit and voltage transfer characteristics; setup and hold time with

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gfhd
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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INTEL INTERVIEW QUESTIONS –

Q. Projects
Q. Which one is more prone – setup or hold time?
A. Setup time is more likely to happen as it depends on clock frequency. If we don’t meet the
minimum frequency requirement for the system to work properly, we’ll end up with setup
time violation. But hold violation is frequency independent, so it doesn’t vary with clock.
NOTE: HOLD VIOLATION IS MORE DANGEROUS THAN SETUP VIOLATION AS IT CANT BE
MODIFIED AFTER MANUFACTURING !!!
Q. Difference between synchronous and asynchronous ckt.? Which one is better on the
basis of Area, Speed and Power?
Q. Difference between combinational and sequential ckt.? (2)
Q. 0-99 sequence detector
A. Using UP counter / 2 decade counter?
Q. 0-1-2-3-4-0-…………. Sequence detector
Q. VLSI or ASIC design flow? (2)
1. Specifications -> what logic the IC must perform, the operating frequency of the clock,
required area
2. Architectural design/ Behavioral description -> what blocks the ckt. Will contain
3. RTL (Register Transfer Level) description -> describe the data flow that will implement the
desired digital circuit [RTL describes the interconnection of logic elements, combination or
sequential]
Q. Types of Routing?
Q. Draw 4x1 MUX from 2-ip NAND gate
A. First draw 4x1 MUX from 2x1 MUXes (3 required). Now, each 2x1 mux requires 3 – 2 ip
NAND gates. Thus total number of 2-ip NAND gates required are 9.
Q. Draw OR gate from 2x1 MUX
Q. Draw buffer and inverter from 2 input XOR gate
A. Buffer – give 1 ip 0, other as x ; Inverter – give ip as 1, other as x
Q. Gate level ckt. Of Full Adder
Q. Toggling circuit
Q. What is setup and hold violation? Its cause? How to fix it?
Q. If combinational delay is more b/w 2 FFs (standard arrangement), how to remove hold
violation?
Q. If buffer is inserted between clock path of capture FF, then what will happen?
Q. What is metastability? How it occurs? Ways to prevent it?
Q. What is race condition? Why it occurs? How to remove race conditions?
Q. I-V Characteristics of MOSFET. Explain each region with the current equation
Q. Draw CMOS inverter ckt. And explain its VTC (2)
Q. When NMOS will be ON. Give an input just greater than the threshold voltage and draw
current, voltage waveforms
Q. Draw 2-ip NOR gate and its truth table
Q. Setup and hold time, explain with waveforms
Q. Draw CMOS design of (A + BC + D)’
Q. Difference between latch and FF.
Q. Draw FF using latch
Q. OP-amp related: Draw Op-amp, gain of op-amp, common-mode gain, CMRR with
formula, unity gain frequency
Q. What is effect of setup and hold violations?
A. Output goes into metastable state and settles somewhere between 0 and VDD. After
some time it either goes to logic low or high depending on the noise present. What is mean
time b/w failure?
Q. Explain synchronizer. Explain ckt. diagram and explain how it matches asynchronous and
synchronous signals?
A. Asynchronous inputs are the inputs that can change the output of the FF irrespective of
the clock e,g. set, preset. Synchronous inputs are those that can have effect on output of
the FF depending on the clock e,g. D, JK, SR etc . The condition for these synchronous inputs
to remain synchronous is that they shouldn’t change in the setup-hold window, if this is not
the case then they will also act as asynchronous inputs only.
Two Flop synchronizer: Two FFs connected in series with common clock pulse.
Asynchronous input feeds into the first FF. (Read from Notebook)
Can synchronizer fail??
NOTE: THERE DOESN’T EXIST ANY CIRCUIT WHICH CAN COMPLETELY REMOVE THE
PROBLEM OF METASTABILITY OR IT BRINGS DOWN THE PROBABILITY OF FF GOING INTO
METASTABLE STATE TO 0. WE CAN ONLY TO REDUCE THIS PROBABILITY !!!
Q. Any idea about DSP?
Q. What is Hot encoding?
Q. Write rising edge detector Verilog code
Q. Write D-FF Verilog code
Q. FIFO Block diagram
Q. What is clock gated circuit?
Q. How to reduce leakage power and dynamic power?
Q. What is logic restructuring?
A. A gate-level dynamic power optimization technique?
Q. Skew and its different types?
Q. Delays in Verilog?
Q. Blocking vs. Non-blocking?
Q. Glitch/ Hazards?
Q. Clock gating, CDC uses?
Q. Control system concept of damping (underdamped, overdamped, critically damped)?
Q. What are various forms of RAM?
A. Its not SRAM, DRAM. Single-port RAM, Dual-port RAM.

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