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LM5163
SNVSBB3 – OCTOBER 2019

LM5163 100-V Input, 0.5-A Synchronous Buck DC/DC Converter with Ultra-low IQ
1 Features 3 Description
1• Designed for reliable and rugged applications The LM5163 synchronous buck converter is designed
to regulate over a wide input voltage range,
– Wide input voltage range of 6 V to 100 V minimizing the need for external surge suppression
– Junction temperature range: –40°C to +150°C components. A minimum controllable on-time of 50 ns
– Fixed 3-ms internal soft-start timer facilitates large step-down conversion ratios, enabling
the direct step-down from a 48-V nominal input to
– Peak and valley current-limit protection
low-voltage rails for reduced system complexity and
– Input UVLO and thermal shutdown protection solution cost. The LM5163 operates during input
• Suited for scalable Industrial power supplies and voltage dips as low as 6 V, at nearly 100% duty cycle
battery packs if needed, making it an excellent choice for wide input
supply range industrial and high cell count battery
– Low minimum on- and off-times of 50 ns
pack applications.
– Adjustable switching frequency up to 1 MHz
With integrated high-side and low-side power
– Diode emulation for high light-load efficiency MOSFETs, the LM5163 delivers up to 0.5-A of output
– 10.5-µA no-load input quiescent current current. A constant on-time (COT) control architecture
– 3-µA shutdown quiescent current provides nearly constant switching frequency with
excellent load and line transient response. Additional
• Ultra–low EMI emission
features of the LM5163 include ultra-low IQ and diode
– Optimized for CISPR 25 class 5 standard emulation mode operation for high light-load
• Integration reduces solution size and cost efficiency, innovative peak and valley overcurrent
– COT mode control architecture protection, integrated VCC bias supply and bootstrap
diode, precision enable and input UVLO, and thermal
– Integrated 0.725-Ω NFET buck switch shutdown protection with automatic recovery. An
– Integrated 0.34-Ω NFET synchronous rectifier open-drain PGOOD indicator provides sequencing,
eliminates external Schottky diode fault reporting, and output voltage monitoring.
– 1.2-V internal voltage reference The LM5163 is available in a thermally-enhanced, 8-
– No loop compensation components pin SO PowerPAD™ package. Its 1.27-mm pin pitch
provides adequate spacing for high-voltage
– Internal VCC bias regulator and boot diode
applications.
– Open-drain power good indicator
– 8-Pin SOIC package with PowerPAD™ Device Information(1)
• Create a custom regulator design using PART NUMBER PACKAGE BODY SIZE (NOM)
WEBENCH® power designer LM5163 SO PowerPAD (8) 4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.

• Industrial battery pack (≥10S)

• Battery pack – e-bike/e-scooter/LEV
• Motor drives, drones, communications equipment
Typical Application Typical Application Efficiency, VOUT = 12 V
LO VOUT = 12 V 100
U1
VIN = 6 V...100 V 120 µH I OUT = 0.5 A
95
VIN SW
CBST 90
CIN
LM5163
2.2 nF RFB1
Efficiency (%)

85
2.2 µF EN/UVLO BST 448 k:
COUT
80
22 µF
RON FB 75
RRON
RFB2
100 k: 70 VIN = 15V
49.9 k:
GND PGOOD VIN = 24V
65 VIN = 48V
VIN = 60V
60
*VOUT tracks V IN if VIN < 12 V 0.001 0.01 0.1 0.5
Load (A) D001
1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 16
2 Applications ........................................................... 1 8.1 Application Information............................................ 16
3 Description ............................................................. 1 8.2 Typical Application .................................................. 16
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 23
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 24
6 Specifications......................................................... 4 10.1 Layout Guidelines ................................................. 24
6.1 Absolute Maximum Ratings ...................................... 4 10.2 Layout Example .................................................... 26
6.2 ESD Ratings.............................................................. 4 11 Device and Documentation Support ................. 27
6.3 Recommended Operating Conditions....................... 4 11.1 Device Support...................................................... 27
6.4 Thermal Information .................................................. 5 11.2 Related Documentation ....................................... 27
6.5 Electrical Characteristics........................................... 5 11.3 Receiving Notification of Documentation Updates 28
6.6 Typical Characteristics ............................................. 7 11.4 Support Resources ............................................... 28
7 Detailed Description .............................................. 9 11.5 Trademarks ........................................................... 28
7.1 Overview .................................................................. 9 11.6 Electrostatic Discharge Caution ............................ 28
7.2 Functional Block Diagram ....................................... 10 11.7 Glossary ................................................................ 28
7.3 Feature Description................................................. 10 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 15 Information ........................................................... 28

4 Revision History
DATE REVISION NOTES
October 2019 * Initial release

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5 Pin Configuration and Functions

DDA Package
8-Pin SO PowerPAD
Top View

GND SW

VIN BST
EP

EN/UVLO PGOOD

RON FB

Pin Functions
PIN
I/O (1) DESCRIPTION
NO. NAME
1 GND G Ground connection for internal circuits
Regulator supply input pin to high-side power MOSFET and internal bias regulator. Connect
2 VIN P/I
directly to the input supply of the buck converter with short, low impedance paths.
Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is
below 1.1 V, the converter is in shutdown mode with all functions disabled. If the UVLO voltage is
3 EN/UVLO I greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal VCC
regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up
sequence begins.
4 RON I On-time programming pin. A resistor between this pin and GND sets the buck switch on-time.
5 FB I Feedback input of voltage regulation comparator
Power good indicator. This pin is an open-drain output pin. Connect to a source voltage through an
6 PGOOD O
external pullup resistor between 10 kΩ to 100 kΩ.
Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF 50-V X7R ceramic capacitor
7 BST P/I
between BST and SW to bias the internal high-side gate driver.
Switching node that is internally connected to the source of the high-side NMOS buck switch and
8 SW P the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power
inductor.
Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and
— EP —
connect to a large copper plane to reduce thermal resistance.

(1) G = Ground, I = Input, O = Output, P = Power

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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted) (1)
MIN MAX UNIT
VIN to GND –0.3 100
EN to GND –0.3 100
Input voltage V
FB to GND –0.3 5.5
RON to GND –0.3 5.5
Bootstrap
External BST to SW capacitance 1.5 2.5 nF
capacitor
BST to GND –0.3 105.5
BST to SW –0.3 5.5
Output voltage SW to GND –1.5 100 V
SW to GND (20-ns transient) –3
PGOOD to GND –0.3 14
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted)(1)
MIN NOM MAX UNIT
VIN Input voltage 6 100 V
VSW Switch node voltage 100 V
VEN/UVLO Enable voltage 100 V
ILOAD Load current 0.5 0.6 A
FSW Switching frequency 1000 kHz
CBST External BST to SW capacitance 2.2 nF
tON Programmable on-time 50 10000 ns

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6.4 Thermal Information

LM5163
THERMAL METRIC DDA (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 43.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 59.5 °C/W
RθJB Junction-to-board thermal resistance 16.1 °C/W
ΨJT Junction-to-top characterization parameter 4.0 °C/W
ΨJB Junction-to-board characterization parameter 16.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.9 °C/W

6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the full –40°C to 150°C junction
temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQ-SHUTDOWN VIN shutdown current VEN = 0 V 3 15 µA
IQ-SLEEP1 VIN sleep current VEN = 2.5 V, VFB = 1.5 V 10.5 25 µA
IQ-ACTIVE VIN active current VEN = 2.5 V 600 880 µA
EN/UVLO
VSD-RISING Shutdown threshold VEN/UVLO rising 1.1 V
VSD-FALLING Shutdown threshold VEN/UVLO falling 0.45 V
VEN-RISING Enable threshold VEN/UVLO rising 1.45 1.5 1.55 V
VEN-FALLING Enable threshold VEN/UVLO falling 1.35 1.4 1.44 V
FEEDBACK
VREF FB regulation voltage VFB falling 1.181 1.2 1.218 V
TIMING
tON1 On-time1 VVIN = 6 V, RRON = 75 kΩ 5000 ns
tON2 On-time2 VVIN = 6 V, RRON = 25 kΩ 650 ns
tON3 On-time3 VVIN = 12 V, RRON = 75 kΩ 2550 ns
tON4 On-time4 VVIN = 12 V, RRON = 25 kΩ 830 ns
PGOOD
FB upper threshold for PGOOD high
VPG-UTH VFB rising 1.105 1.14 1.175 V
to low
FB lower threshold for PGOOD high to
VPG-LTH VFB falling 1.055 1.08 1.1 V
low
PGOOD upper and lower threshold
VPG-HYS VFB falling 60 mV
hysteresis
RPG PGOOD pulldown resistance VFB = 1 V 30 Ω
BOOTSTRAP
VBST-UV Gate drive UVLO VBST rising 2.7 3.4 V
POWER SWITCHES
RDSON-HS High-side MOSFET RDSON ISW = –100 mA 0.725 Ω
RDSON-LS Low-side MOSFET RDSON ISW = 100 mA 0.33 Ω

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Electrical Characteristics (continued)

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the full –40°C to 150°C junction
temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SOFT START
tSS Internal soft-start time 1.75 3 4.75 ms
CURRENT LIMIT
IPEAK1 Peak current limit threshold (HS) 0.63 0.75 0.87 A
IPEAK2 Peak current limit threshold (LS) 0.63 0.75 0.87 A
IDELTA-ILIM Min of (IPEAK1 or IPEAK2) minus IVALLEY 100 mA
IVALLEY Valley current limit threshold 0.5 0.6 0.72 A
THERMAL SHUTDOWN
TSD Thermal shutdown threshold TJ rising 175 °C
TSD-HYS Thermal shutdown hysteresis 10 °C

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6.6 Typical Characteristics

At TA = 25°C, VOUT = 12 V, LO = 120 µH, RRON = 105 kΩ, unless otherwise specified.

100 100

95

90 90
Efficiency (%)

Efficiency (%)
85

80 80

75

70 VIN = 15V 70 VIN = 15V

VIN = 24V VIN = 24V
65 VIN = 48V VIN = 48V
VIN = 60V VIN = 60V
60 60
0.001 0.01 0.1 0.5 0 0.1 0.2 0.3 0.4 0.5
Load (A) D001
Load (A) D002
Figure 1. Conversion Efficiency (Log Scale) Figure 2. Conversion Efficiency (Linear Scale)
25 25
Sleep Sleep
Shutdown Shutdown
20 20
Quiescent Current (PA)

Quiescent Current (PA)

15 15

10 10

5 5

0 0
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100
Junction Temperature (qC) D005
Input Voltage (V) D006
Figure 3. VIN Shutdown and Sleep Supply Current versus Figure 4. VIN Shutdown and Sleep Supply Current versus
Temperature Input Voltage
725 600

700
580
675
Active Current (PA)

Active Current (PA)

650 560

625
540

600
520
575

550 500
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100
Junction Temperature (qC) D007 Input Voltage (V) D008
Figure 5. VIN Active Current versus Temperature Figure 6. VIN Active Current versus Input Voltage

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Typical Characteristics (continued)

At TA = 25°C, VOUT = 12 V, LO = 120 µH, RRON = 105 kΩ, unless otherwise specified.
1.21 1.4

1.2
FB Regulation Threshold (V)

1.205
1

RDSON (:)
0.8
1.2
0.6

0.4
1.195

0.2 High-Side FET

Low-Side FET
1.19 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (qC) D009
Junction Temperature (qC) D010
Figure 7. Feedback Comparator Threshold versus Figure 8. MOSFETs On-State Resistance versus
Temperature Temperature
0.8 6
RRT = 105 k:
RRT = 43.2 k:
5
0.7
Current Limit (A)

4
ON-Time (Ps)

0.6 3

2
0.5
1
Peak Current
Valley Current
0.4 0
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100
Junction Temperature (qC) D011 Input Voltage (V) D012
Figure 9. Peak and Valley Current Limit versus Temperature Figure 10. COT On-Time versus VIN

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7 Detailed Description

7.1 Overview
The LM5163 is an easy-to-use, ultra-low IQ constant on-time (COT) synchronous step-down buck regulator. With
integrated high-side and low-side power MOSFETs, the LM5163 is a low-cost, highly efficient buck converter that
operates from a wide input voltage of 6 V to 100 V, delivering up to 0.5-A DC load current. The LM5163 is
available in an 8-pin SO Power PAD package with 1.27-mm pin pitch for adequate spacing in high-voltage
applications. This constant on-time (COT) converter is ideal for low-noise, high-current, and fast load transient
requirements, operating with a predictive on-time switching pulse. Over the input voltage range, input voltage
feedforward is employed to achieve a quasi-fixed switching frequency. A controllable on-time as low as 50 ns
permits high step-down ratios and a minimum forced off-time of 50 ns provides extremely high duty cycles,
allowing VIN to drop close to VOUT before frequency foldback occurs. At light loads, the device transitions into an
ultra-low IQ mode to maintain high efficiency and prevent draining battery cells connected to the input when the
system is in standby. The LM5163 implements a smart peak and valley current limit detection circuit to ensure
robust protection during output short circuit conditions. Control loop compensation is not required for this
regulator, reducing design time and external component count.
The LM5163 incorporates additional features for comprehensive system requirements, including an open-drain
power good circuit for the following:
• Power-rail sequencing and fault reporting
• Internally-fixed soft start
• Monotonic start-up into prebiased loads
• Precision enable for programmable line undervoltage lockout (UVLO)
• Smart cycle-by-cycle current limit for optimal inductor sizing
• Thermal shutdown with automatic recovery
These features enable a flexible and easy-to-use platform for a wide range of applications. The LM5163 supports
a wide range of end-equipment systems requiring a regulated output from a high input supply where the transient
voltage deviates from the DC level. The following are examples of such end equipment systems:
• 48-V automotive systems
• High cell-count battery-pack systems
• 24-V industrial systems
• 48-V telecom and PoE voltage ranges
The pin arrangement is designed for a simple layout requiring only a few external components.

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7.2 Functional Block Diagram

VIN VIN VDD

BIAS
REGULATOR
CIN VDD UVLO
RUV1
EN/UVLO
± STANDBY
+
THERMAL
RUV2 SHUTDOWN
1.5 V

± SHUTDOWN BST
+
LOGIC
0.4 V
VIN
CBST
RON ON/OFF DISABLE
TIMERS

VOUT CONSTANT
LO VOUT
ON-TIME SW
CONTROL
RFB1 VCC
LOGIC
FEEDBACK
COMPARATOR SLEEP COUT
FB
± DETECT
RRON ZC
VREF +
ZX DETECT + PGOOD
±

RFB2 PEAK/VALLEY
CURRENT LIMIT
FB ±
GND +
PGOOD
0.9*VREF COMPARATOR

7.3 Feature Description

7.3.1 Control Architecture
The LM5163 step-down switching converter employs a constant on-time (COT) control scheme. The COT control
scheme sets a fixed on-time tON of the high-side FET using a timing resistor (RON). The tON is adjusted as Vin
changes and is inversely proportional to the input voltage to maintain a fixed frequency when in continuous
conduction mode (CCM). After expiration of tON, the high-side FET remains off until the feedback pin is equal or
below the reference voltage of 1.2 V. To maintain stability, the feedback comparator requires a minimal ripple
voltage that is in phase with the inductor current during the off-time. Furthermore, this change in feedback
voltage during the off-time must be large enough to dominate any noise present at the feedback node. The
minimum recommended ripple voltage is 20 mV. See Table 1 for different types of ripple injection schemes that
ensure stability over the full input voltage range.
During a rapid start-up or a positive load step, the regulator operates with minimum off-times until regulation is
achieved. This feature enables extremely fast load transient response with minimum output voltage undershoot.
When regulating the output in steady-state operation, the off-time automatically adjusts itself to produce the SW-
pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. In CCM, the
switching frequency FSW is programmed by the RRON resistor. Use Equation 1 to calculate the switching
frequency.

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Feature Description (continued)

VOUT (V) ˜ 2500
FSW (kHz)
RRON (k:)
(1)

Table 1. Ripple Generation Methods

TYPE 1 TYPE 2 TYPE 3
Lowest Cost Reduced Ripple Minimum Ripple

LO VIN LO VOUT LO VOUT

VIN VOUT VIN
VIN SW VIN SW VIN SW
LM5163 CBST LM5163 CBST LM5163 RA CA
CIN CFF CIN CBST
RFB1 RESR EN/UVLO BST RFB1 RESR
EN/UVLO BST EN/UVLO BST RFB1 COUT
CB

RON FB RON FB RON FB

RFB2 COUT RFB2 COUT
RRON RRON RRON RFB2
GND PGOOD GND PGOOD GND PGOOD

10
20mV CA t
RESR t FSW ˜ (RFB1 || RFB2 ) (7)
20mV ˜ VOUT 'IL(nom) (4) R C d
RESR t A A
VFB1 ˜ 'IL(nom) (2) VOUT
RESR t VIN-nom VOUT ˜ t ON @VIN-nom
VOUT 2 ˜ VIN ˜ FSW ˜ COUT (5)
RESR t 20mV (8)
2 ˜ VIN ˜ FSW ˜ COUT (3) 1
CFF t t TR-settling
2S ˜ FSW ˜ (RFB1 || RFB2 ) (6) CB t 3 ˜ R
FB1 (9)

Table 1 presents three different methods for generating appropriate voltage ripple at the feedback node. Type-1
ripple generation method uses a single resistor, RESR, in series with the output capacitor. The generated voltage
ripple has two components: capacitive ripple caused by the inductor ripple current charging and discharging the
output capacitor and resistive ripple caused by the inductor ripple current flowing into the output capacitor and
through series resistance RESR. The capacitive ripple component is out of phase with the inductor current and
does not decrease monotonically during the off-time. The resistive ripple component is in phase with the inductor
current and decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at
VOUT for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off time. Equation 2 and
Equation 3 define the value of the series resistance RESR to ensure sufficient in-phase ripple at the feedback
node.
Type-2 ripple generation uses a CFF capacitor in addition to the series resistor. As the output voltage ripple is
directly AC-coupled by CFF to the feedback node, the RESR and ultimately the output voltage ripple are reduced
by a factor of VOUT / VFB1.
Type-3 ripple generation uses an RC network consisting of RA and CA, and the switch node voltage to generate a
triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled into the
feedback node with capacitor CB. Because this circuit does not use output voltage ripple, it is suited for
applications where low output voltage ripple is critical. The AN-1481 Controlling Output Ripple and Achieving
ESR Independence in Constant On-time (COT) Regulator Designs Application Note provides additional details
on this topic.
Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains the highest
efficiency at light load currents by decreasing the effective switching frequency. DEM operation occurs when the
synchronous power MOSFET switches off as inductor valley current reaches zero. Here, the load current is less
than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current
reduces switching loss, and preventing negative current conduction reduces conduction loss. Power conversion
efficiency is higher in a DEM converter than an equivalent forced-PWM CCM converter. With DEM operation, the
duration that both power MOSFETs remain off progressively increases as load current decreases. When this idle
duration exceeds 15 μs, the converter transitions into an ultra-low IQ mode, consuming only 10-μA quiescent
current from the input.

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Feature Description (continued)

7.3.2 Internal VCC Regulator and Bootstrap Capacitor
The LM5163 contains an internal linear regulator that is powered from VIN with a nominal output of 5 V,
eliminating the need for an external capacitor to stabilize the linear regulator. The internal VCC regulator supplies
current to internal circuit blocks including the synchronous FET driver and logic circuits. The input pin (VIN) can
be connected directly to line voltages up to 100 V. As the power MOSFET has a low total gate charge, use a low
bootstrap capacitor value to reduce the stress on the internal regulator. It is required to select a high-quality 2.2-
nF 50-V X7R ceramic bootstrap capacitor as specified in the Absolute Maximum Ratings section. Selecting a
higher value capacitance stresses the internal VCC regulator and damages the device. A lower capacitance than
required is not sufficient to drive the internal gate of the power MOSFET. An internal diode connects from the
VCC regulator to the BST pin to replenish the charge in the high-side gate drive bootstrap capacitor when the
SW voltage is low.

7.3.3 Regulation Comparator

The feedback voltage at FB is compared to an internal 1.2-V reference. The LM5163 voltage regulation loop
regulates the output voltage by maintaining the FB voltage equal to the internal reference voltage, VREF. A
resistor divider programs the ratio from output voltage VOUT to FB.
For a target VOUT setpoint, use Equation 10 to calculate RFB2 based on the selected RFB1.
1.2 V
RFB2 ˜ RFB1
VOUT 1.2 V
(10)
TI recommends selecting RFB1 in the range of 100 kΩ to 1 MΩ for most applications. A larger RFB1 consumes
less DC current, which is mandatory if light-load efficiency is critical. RFB1 larger than 1 MΩ is not recommended
as the feedback path becomes more susceptible to noise. It is important to route the feedback trace away from
the noisy area of the PCB and keep the feedback resistors close to the FB pin.

7.3.4 Internal Soft Start

The LM5163 employs an internal soft-start control ramp that allows the output voltage to gradually reach a
steady-state operating point, thereby reducing start-up stresses and current surges. The soft-start feature
produces a controlled, monotonic output voltage start-up. The soft-start time is internally set to 3 ms.

7.3.5 On-Time Generator

The on-time of the LM5163 high-side FET is determined by the RRON resistor and is inversely proportional to the
input voltage, VIN. The inverse relationship with VIN results in a nearly constant frequency as VIN is varied. Use
Equation 11 to calculate the on-time.
RRON k:
t ON V
VIN V ˜ 2.5
(11)
Use Equation 12 to determine the RRON resistor to set a specific switching frequency in CCM.
VOUT (V) ˜ 2500
RRON (k:)
FSW (kHz)
(12)
Select RRON for a minimum on-time (at maximum VIN) greater than 50 ns for proper operation. In addition to this
minimum on-time, the maximum frequency for this device is limited to 1 MHz.

7.3.6 Current Limit

The LM5163 manages overcurrent conditions with cycle-by-cycle current limiting of the peak inductor current.
The current sensed in the high-side MOSFET is compared every switching cycle to the current limit threshold
(0.75 A). To protect the converter from potential current runaway conditions, the LM5163 includes a foldback
valley current limit feature, set at 0.6 A, that is enabled if a peak current limit is detected. As shown in Figure 11,
if the peak current in the high-side MOSFET exceeds 0.75 A (typical), the present cycle is immediately

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Feature Description (continued)

terminated regardless of the programmed on-time (tON), the high-side MOSFET is turned off and the foldback
valley current limit is activated. The low-side MOSFET remains on until the inductor current drops below this
foldback valley current limit, after which the next on-pulse is initiated. This method folds back the switching
frequency to prevent overheating and limits the average output current to less than 0.75 A to ensure proper
short-circuit and heavy-load protection of the LM5163.
vFB

VREF

iL
Peak ILIM
IAVG(ILIM)
Valley ILIM

IAVG1
t
tON < tON
tSW > tSW

Figure 11. Current Limit Timing Diagram

Current is sensed after a leading-edge blanking time following the high-side MOSFET turnon transition. The
propagation delay of the current limit comparator is 100 ns. During high step-down conditions when the on-time
is less than 100 ns, a back-up peak current limit comparator in the low-side FET also set at 0.75 A enables the
foldback valley current limit set at 0.6 A. This innovative current limit scheme enables ultra-low duty-cycle
operation, permitting large step-down voltage conversions while ensuring robust protection of the converter.

7.3.7 N-Channel Buck Switch and Driver

The LM5163 integrates an N-channel buck switch and associated floating high-side gate driver. The gate-driver
circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage bootstrap diode. A
high-quality 2.2-nF, 50-V X7R ceramic capacitor connected between the BST and SW pins provides the voltage
to the high-side driver during the buck switch on-time. See the Internal VCC Regulator and Bootstrap Capacitor
section for limitations. During the off-time, the SW pin is pulled down to approximately 0 V, and the bootstrap
capacitor charges from the internal VCC through the internal bootstrap diode. The minimum off-timer, set to 50
ns (typical), ensures a minimum time each cycle to recharge the bootstrap capacitor. When the on-time is less
than 300 ns, the minimum off-timer is forced to 250 ns to ensure that the BST capacitor is charged in a single
cycle. This is vital during wake up from sleep mode when the BST capacitor is most likely discharged.

7.3.8 Synchronous Rectifier

The LM5163 provides an internal low-side synchronous rectifier N-channel MOSFET. This MOSFET provides a
low-resistance path for the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier operates in a diode emulation mode. Diode emulation enables the regulator to operate
in a pulse-skipping mode during light load conditions. This mode leads to a reduction in the average switching
frequency at light loads. Switching losses and FET gate driver losses, both of which are proportional to switching
frequency, are significantly reduced at very light loads and efficiency is improved. This pulse-skipping mode also
reduces the circulating inductor current and losses associated with conventional CCM at light loads.

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Feature Description (continued)

7.3.9 Enable/Undervoltage Lockout (EN/UVLO)
The LM5163 contains a dual-level EN/UVLO circuit. When the EN/UVLO voltage is below 1.1 V (typical), the
converter is in a low-current shutdown mode and the input quiescent current (IQ) is dropped down to 3 µA. When
the voltage is greater than 1.1 V but less than 1.5 V (typical), the converter is in standby mode. In standby mode
the internal bias regulator is active while the control circuit is disabled. When the voltage exceeds the rising
threshold of 1.5 V (typical), normal operation begins. Install a resistor divider from VIN to GND to set the
minimum operating voltage of the regulator. Use Equation 13 and Equation 14 to calculate the input UVLO
turnon and turnoff voltages, respectively.
§ RUV1 ·
VIN(on) 1.5 V ˜ ¨ 1 ¸
© RUV2 ¹ (13)
§ RUV1 ·
VIN(off) 1.4 V ˜ ¨ 1 ¸
© RUV2 ¹ (14)
TI recommends selecting RUV1 in the range of 1 MΩ for most applications. A larger RUV1 consumes less DC
current, which is mandatory if light-load efficiency is critical. If input UVLO is not required, the power-supply
designer can either drive EN/UVLO as an enable input driven by a logic signal or connect it directly to VIN. If
EN/UVLO is directly connected to VIN, the regulator begins switching as soon as the internal bias rails are
active.

7.3.10 Power Good (PGOOD)

The LM5163 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level. Use
the PGOOD signal for start-up sequencing of downstream converters or for fault protection and output
monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 14 V.
The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the
voltage from a higher voltage pullup rail. When the FB voltage exceeds 95% of the internal reference VREF, the
internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls
below 90% of VREF, an internal 25-Ω PGOOD switch turns on and PGOOD is pulled low to indicate that the
output voltage is out of regulation. The rising edge of PGOOD has a built-in deglitch delay of 5 µs.

7.3.11 Thermal Protection

The LM5163 includes an internal junction temperature monitor to protect the device in the event of a higher than
normal junction temperature. If the junction temperature exceeds 175°C (typical), thermal shutdown occurs to
prevent further power dissipation and temperature rise. The LM5163 initiates a restart sequence when the
junction temperature falls to 165°C, based on a typical thermal shutdown hysteresis of 10°C. This is a non-
latching protection, so the device cycles into and out of thermal shutdown if the fault persists.

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7.4 Device Functional Modes

7.4.1 Shutdown Mode
EN/UVLO provides ON and OFF control for the LM5163. When VEN/UVLO is below approximately 1.1 V, the
device is in shutdown mode. Both the internal linear regulator and the switching regulator are off. The quiescent
current in shutdown mode drops to 3 µA at VIN = 24 V. The LM5163 also employs internal bias rail undervoltage
protection. If the internal bias supply voltage is below the UV threshold, the regulator remains off.

7.4.2 Active Mode

The LM5163 is in active mode when VEN/UVLO is above the precision enable threshold and the internal bias rail is
above its UV threshold. In COT active mode, the LM5163 is in one of three modes depending on the load
current:
1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current
ripple
2. Pulse skipping and diode emulation mode (DEM) when the load current is less than half of the peak-to-peak
inductor current ripple in CCM operation
3. Current limit CCM with peak and valley current limit protection when an overcurrent condition is applied at
the output

7.4.3 Sleep Mode

The Control Architecture section gives a brief introduction to the LM5163 diode emulation (DEM) feature. The
converter enters DEM during light-load conditions when the inductor current decays to zero and the synchronous
MOSFET is turned off to prevent negative current in the system. In the DEM state, the load current is lower than
half of the peak-to-peak inductor current ripple and the switching frequency decreases when the load is further
decreased as the device operates in a pulse skipping mode. A switching pulse is set when VFB drops below 1.2
V.
As the frequency of operation decreases and VFB remains above 1.2 V (VREF) with the output capacitor sourcing
the load current for greater than 15 µs, the converter enters an ultra-low IQ sleep mode to prevent draining the
input power supply. The input quiescent current (IQ) required by the LM5163 decreases to 10 µA in sleep mode,
improving the light-load efficiency of the regulator. In this mode, all internal controller circuits are turned off to
ensure very low current consumption by the device. Such low IQ renders the LM5163 as the best option to
extend operating lifetime for off-battery applications. The FB comparator and internal bias rail are active to detect
when the FB voltage drops below the internal reference VREF and the converter transitions out of sleep mode into
active mode. There is a 9-µs wake-up delay from sleep to active states.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5163 requires only a few external components to step down from a wide range of supply voltages to a
fixed output voltage. Several features are integrated to meet system design requirements, including the following:
• Precision enable
• Input voltage UVLO
• Internal soft start
• Programmable switching frequency
• A PGOOD indicator
To expedite and streamline the process of designing of a LM5163-based converter, a comprehensive LM5163
quickstart calculator is available for download to assist the designer with component selection for a given
application. This tool is complemented by the availability of an evaluation module (EVM), numerous PSPICE
models, as well as TI's WEBENCH® Power Designer. In order to modify the LM5164-Q1EVM-041 for the
LM5163-Q1, change the inductor LO to 120 µH, the resistor RA to 226 kΩ, and the capacitance COUT to 22 µF.
See Figure 12 for the LM5163-Q1 applications circuit.

8.2 Typical Application

Figure 12 shows the schematic for a 12-V 0.5-A COT converter.
LO VOUT = 12 V
VIN = 15 V...100 V U1 IOUT = 0.5 A
120 PH
VIN SW
RA CA
CIN LM5163 CBST
2.2 nF 226 k: 3.3 nF
2.2 PF EN/UVLO BST RFB1
CB
453 k: COUT
56 pF 22 PF
RON FB
RRON
100 k: RFB2
GND PGOOD 49.9 k:

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Figure 12. Typical Application VIN(nom) = 48 V, VOUT = 12 V, IOUT(max) = 0.5 A, FSW(nom) = 300 kHz

NOTE
This and subsequent design examples are provided herein to showcase the LM5163
converter in several different applications. Depending on the source impedance of the
input supply bus, an electrolytic capacitor may be required at the input to ensure stability,
particularly at low input voltage and high output current operating conditions. See the
Power Supply Recommendations section for more details.

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Typical Application (continued)

8.2.1 Design Requirements
The target full-load efficiency is 92% based on a nominal input voltage of 48 V and an output voltage of 12 V.
The required input voltage range is 15 V to 100 V. The LM5163 delivers a fixed 12-V output voltage. The
switching frequency is set by resistor RRON at 300 kHz. The output voltage soft-start time is 3 ms. Table 2 lists
the required components. Refer to the LM5164-Q1EVM-041 User's Guide for more detail.

Table 2. List of Components

COUNT REF DES VALUE DESCRIPTION PART NUMBER MANUFACTURER
2 CIN 2.2 µF Capacitor, Ceramic, 2.2 µF, 100 V, X7R, 10% CGA6N3X7R2A225K230AB TDK
1 COUT 22 µF Capacitor, Ceramic, 22 µF, 25 V, X7R, 10% TMK325B7226KMHT Taiyo Yuden
1 CA 3300 pF Capacitor, Ceramic, 3300 pF, 16 V, X7R, 10% CGA3E2X7R2A332K080AA TDK
1 CB 56 pF Capacitor, Ceramic, 56 pF, 50 V, X7R, 10% C0603C560J5GACTU Kemet
1 CBST 2.2 nF Capacitor, Ceramic, 2200 pF, 50 V, X7R, 10% GCM155R71H222KA37D MuRata
1 LO 120 µH Inductor, 120 µH, 210 mΩ, 1.65 A MSS1260-124KL Coilcraft
1 RRON 100 kΩ Resistor, Chip, 100 k, 1%, 0.1 W, 0603 RG1608P-1053-B-T5 Susumu Co Ltd
1 RFB1 453 kΩ Resistor, Chip, 453 k, 1%, 0.1 W, 0603 RT0603BRD07448KL Yageo
1 RFB2 49.9 kΩ Resistor, Chip, 49.9 k, 1%, 0.1 W, 0603 RG1608P-4992-B-T5 Susumu Co Ltd
1 RA 226 kΩ Resistor, Chip, 226 k, 1%, 0.1W, 0603 RT0603BRD07226KL Yageo
1 U1 Wide VIN synchronous buck converter LM5163DDAR TI

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5163 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Switching Frequency (RRON)

The switching frequency of the LM5163 is set by the on-time programming resistor placed at RON. As shown by
Equation 15, a standard 100 kΩ, 1% resistor sets the switching frequency at 300 kHz.
VOUT (V) ˜ 2500
RRON (k:)
FSW (kHz)
(15)
Note that at very low duty cycles, the 50 ns minimum controllable on-time of the high-side MOSFET, tON(min),
limits the maximum switching frequency. In CCM, tON(min) limits the voltage conversion step-down ratio for a given
switching frequency. Use Equation 16 to calculate the minimum controllable duty cycle.
DMIN t ON(min) ˜ FSW
(16)

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Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range,
solution size, and efficiency. Use Equation 17 to calculate the maximum supply voltage for a given tON(min) before
switching frequency reduction occurs.
VOUT
VIN(max)
t ON(min) ˜ FSW
(17)

8.2.2.3 Buck Inductor (LO)

Use Equation 18 and Equation 19 to calculate the inductor ripple current (assuming CCM operation) and peak
inductor current, respectively.
VOUT § VOUT ·
'IL ˜ ¨1 ¸
FSW ˜ LO © VIN ¹
(18)
'IL
IL(peak) IOUT(max)
2 (19)
For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 50%
of the rated load current at nominal input voltage. Use Equation 20 to calculate the inductance.
VOUT § VOUT ·
LO ˜ ¨1 ¸
FSW ˜ 'IL ¨ V ¸
© IN(nom) ¹ (20)
Choosing a 120-μH inductor in this design results in 250-mA peak-to-peak ripple current at a nominal input
voltage of 48 V, equivalent to 50% of the 500-mA rated load current.
Check the inductor data sheet to make sure the saturation current of the inductor is well above the current limit
setting of the LM5163. Ferrite-core inductors have relatively lower core losses and are preferred at high switching
frequencies, but exhibit a hard saturation characteristic – the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, and
reduced efficiency, in turn compromising reliability. Note that inductor saturation current levels generally
decrease as the core temperature increases.

8.2.2.4 Output Capacitor (COUT)

Select a ceramic output capacitor to limit the capacitive voltage ripple at the converter output. This is the
sinusoidal ripple voltage that is generated from the triangular inductor current ripple flowing into and out of the
capacitor. Select an output capacitance using Equation 21 to limit the voltage ripple component to 0.5% of the
output voltage.
'IL
COUT t
8 ˜ FSW ˜ VOUT(ripple)
(21)
Substituting ΔIL(nom) of 250-mA gives COUT greater than 3.1 μF. With voltage coefficients of ceramic capacitors
taken in consideration, a 22-µF, 25-V rated capacitor with X7R dielectric is selected.

8.2.2.5 Input Capacitor (CIN)

An input capacitor is necessary to limit the input ripple voltage while providing AC current to the buck power
stage at every switching cycle. To minimize the parasitic inductance in the switching loop, position the input
capacitors as close as possible to the VIN and GND pins of the LM5163. The input capacitors conduct a square-
wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive
component of AC ripple voltage is a triangular waveform.
Along with the ESR-related ripple component, use Equation 22 to calculate the peak-to-peak ripple voltage
amplitude.
IOUT ˜ D ˜ 1 D
VIN(ripple) IOUT ˜ RESR
FSW ˜ CIN
(22)

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Use Equation 23 to calculate the input capacitance required for a load current, based on an input voltage ripple
specification (ΔVIN).
IOUT ˜ D ˜ 1 D
CIN t
FSW ˜ VIN(ripple) IOUT ˜ RESR
(23)
The recommended high-frequency input capacitance is 2.2 µF or higher. Ensure the input capacitor is a high-
quality X7S or X7R ceramic capacitor with sufficient voltage rating for CIN. Based on the voltage coefficient of
ceramic capacitors, choose a voltage rating of twice the maximum input voltage. Additionally, some bulk
capacitance is required if the LM5163 is not located within approximately 5 cm from the input voltage source.
This capacitor provides parallel damping to the resonance associated with parasitic inductance of the supply
lines and high-Q ceramics. See the Power Supply Recommendations section for more detail.

8.2.2.6 Type 3 Ripple Network

A Type 3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT to generate a
triangular ramp that is in phase with the inductor current. This triangular ramp is then AC-coupled into the
feedback node using capacitor CB as shown in Figure 12. Type 3 ripple injection is suited for applications where
low output voltage ripple is crucial.
Use Equation 24 and Equation 25 to calculate RA and CA to provide the required ripple amplitude at the FB pin.
10
CA t
FSW ˜ RFB1 RFB2
(24)
For the feedback resistor values given in Figure 12, Equation 24 dictates a minimum CA of 742 pF. In this design,
a 3300 pF capacitance is chosen. This is done to keep RA within practical limits between 100 kΩ and 1 MΩ when
using Equation 25.
VIN(nom) VOUT ˜ t ON(nom)
R A CA t
20mV
(25)
Based on CA set at 3.3 nF, RA is calculated to be 226 kΩ to provide a 20-mV ripple voltage at FB. The general
recommendation for a Type 3 network is to calculate RA and CA to get 20 mV of ripple at typical operating
conditions, while ensuring a 12-mV minimum ripple voltage on FB at minimum VIN.
While the amplitude of the generated ripple does not affect the output voltage ripple, it impacts the output
regulation as it reflects as a DC error of approximately half the amplitude of the generated ripple. For example, a
converter circuit with Type 3 network that generates a 40-mV ripple voltage at the feedback node has
approximately 10-mV worse load regulation scaled up through the FB divider to VOUT than the same circuit that
generates a 20-mV ripple at FB. Use Equation 26 to calculate the coupling capacitance CB.
t TR-settling
CB t
3 ˜ RFB1
where
• tTR-settling is the desired load transient response settling time (26)
CB calculates to 56 pF based on a 75-µs settling time. This value avoids excessive coupling capacitor discharge
by the feedback resistors during sleep intervals when operating at light loads. To avoid capacitance fall-off with
DC bias, use a C0G or NP0 dielectric capacitor for CB.

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8.2.3 Application Curves

100 100

95

90 90
Efficiency (%)

Efficiency (%)
85

80 80

75

70 VIN = 15V 70 VIN = 15V

VIN = 24V VIN = 24V
65 VIN = 48V VIN = 48V
VIN = 60V VIN = 60V
60 60
0.001 0.01 0.1 0.5 0 0.1 0.2 0.3 0.4 0.5
Load (A) D001
Load (A) D002
Figure 13. Conversion Efficiency (Log Scale) Figure 14. Conversion Efficiency (Linear Scale)

12.6

12.5

12.4
Output Voltage (V)

VOUT 100mV/DIV
12.3

12.2

12.1

12 VIN = 15V
IOUT 250mA/DIV
VIN = 24V
11.9 VIN = 48V
VIN = 60V 100 µs/DIV
11.8
0 0.1 0.2 0.3 0.4 0.5
Output Current (A) Load
VIN = 24 V IOUT = 0.125 A to 0.5 A at 0.1
A/μs
Figure 15. Load and Line Regulation Performance
Figure 16. Load Step Response

VIN 10V/DIV VIN 10V/DIV

VOUT 2V/DIV VOUT 2V/DIV

IOUT 100mA/DIV 1 ms/DIV IOUT 100mA/DIV

1 ms/DIV

VIN = 24 V IOUT = 0 A VIN = 24 V IOUT = 0.5 A (Resistive)

Figure 17. No-Load Start-up with VIN Figure 18. Full-Load Start-up with VIN

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EN 5V/DIV EN 5V/DIV

VOUT 5V/DIV VOUT 5V/DIV

IOUT 500mA/DIV

2 ms/DIV IOUT 500mA/DIV

2 ms/DIV

VIN = 24 V IOUT = 0 A VIN = 24 V IOUT = 0.5 A (Resistive)

Figure 19. No-Load Start-up and Shutdown with EN/UVLO Figure 20. Full-Load Start-up and Shutdown with EN/UVLO

VOUT 5V/DIV
EN 5V/DIV

VOUT 5V/DIV

VSW 10V/DIV

IOUT 500mA/DIV

IOUT 500mA/DIV
2 ms/DIV 500 µs/DIV

VIN = 24 V IOUT = 0 A VIN = 24 V Load = 0 A to Short

Figure 21. Pre-bias Start-up with EN/UVLO Figure 22. Short Circuit Applied

VOUT 5V/DIV

VOUT 5V/DIV

VSW 10V/DIV

VSW 10V/DIV

100 µs/DIV
10 ms/DIV
IOUT 500mA/DIV
IOUT 500mA/DIV

VIN = 24 V Load = Short to 0 A VIN = 24 V Load = 0 A to Short to 0 A

Figure 23. Short Circuit Recovery Figure 24. No Load to Short Circuit/Short Circuit Recovery

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VSW 10V/DIV
VSW 10V/DIV

VOUT 20mV/DIV

VOUT 50mV/DIV
10 ms/DIV 5 µs/DIV

VIN = 24 V IOUT = 0 A VIN = 24 V IOUT = 0.5 A

Figure 25. No-Load Switching Figure 26. Full-Load Switching

Peak Peak
S t a r t 150 k H z Stop 30 MHz Start 30 MHz Stop 108 MHz
Average Average

VIN = 48 V Load = 0.5 A VIN = 48 V Load = 0.5 A

Figure 27. CISPR 25 Class 5 Conducted Emissions Plot, Figure 28. CISPR 25 Class 5 Conducted Emissions Plot, 30
150 kHz to 30 MHz MHz to 108 MHz

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9 Power Supply Recommendations

The LM5163 buck converter is designed to operate from a wide input voltage range between 6 V and 100 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions tables. In addition, the input supply must be capable of delivering the required input current
to the fully-loaded regulator. Use Equation 27 to estimate the average input current.
VOUT ˜ IOUT
IIN
VIN ˜ K
where
• η is the efficiency (27)
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have
an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR ceramic
input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at VIN each
time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a
load transient. If the converter is operating close to the minimum input voltage, this dip can cause false UVLO
fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the input
supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics. The
moderate ESR of the electrolytic capacitor helps to damp the input resonant circuit and reduce any voltage
overshoots. A 10-μF electrolytic capacitor with a typical ESR of 0.5 Ω provides enough damping for most input
circuit configurations.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters
Application Report provides helpful suggestions when designing an input filter for any switching regulator.

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10 Layout

10.1 Layout Guidelines

PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or
degrade the power supply performance.
1. To help eliminate these problems, bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with
a high-quality dielectric. Place CIN as close as possible to the LM5163 VIN and GND pins. Grounding for
both the input and output capacitors must consist of localized top-side planes that connect to the GND pin
and GND PAD.
2. Minimize the loop area formed by the input capacitor connections to the VIN and GND pins.
3. Locate the inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive
capacitive coupling.
4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
5. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, soft-
start, and enable components to the ground plane. This prevents any switched or load currents from flowing
in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic
output voltage ripple behavior.
7. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
8. Minimize trace length to the FB pin. Place both feedback resistors, RFB1 and RFB2, close to the FB pin. Place
CFF (if needed) directly in parallel with RFB1. If output setpoint accuracy at the load is important, connect the
VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on
the other side of a grounded shielding layer.
9. The RON pin is sensitive to noise. Thus, locate the RRON resistor as close as possible to the device and
route with minimal lengths of trace. The parasitic capacitance from RON to GND must not exceed 20 pF.
10. Provide adequate heat sinking for the LM5163 to keep the junction temperature below 150°C. For operation
at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-
sinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper layers,
these thermal vias must also be connected to inner layer heat-spreading ground planes.

10.1.1 Compact PCB Layout for EMI Reduction

Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimizing radiated EMI is to identify the pulsing current path and minimize the area of that path.
Figure 29 denotes the critical switching loop of the buck converter power stage in terms of EMI. The topological
architecture of a buck converter means that a particularly high di/dt current path exists in the loop comprising the
input capacitor and the integrated MOSFETs of the LM5163, and it becomes mandatory to reduce the parasitic
inductance of this loop by minimizing the effective loop area.

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Layout Guidelines (continued)

VIN
VIN
2 CIN
LM5163
High
BST di/dt
High-side loop
Q1
NMOS LO
gate driver
SW
8 VOUT

CO
Low-side Q2
NMOS
gate driver
GND
1 GND

Figure 29. DC/DC Buck Converter With Power Stage Circuit Switching Loop

The input capacitor provides the primary path for the high di/dt components of the current of the high-side
MOSFET. Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction.
Keep the trace connecting SW to the inductor as short as possible and just wide enough to carry the load current
without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to
minimize parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the
return terminal of the capacitor to the GND pin and exposed PAD of the LM5163.

10.1.2 Feedback Resistors

Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin,
rather than close to the load. This reduces the trace length of FB signal and noise coupling. The FB pin is the
input to the feedback comparator, and as such, is a high impedance node sensitive to noise. The output node is
a low impedance node, so the trace from VOUT to the resistor divider can be long if a short path is not available.
Route the voltage sense trace from the load to the feedback resistor divider, keeping away from the SW node,
the inductor, and VIN to avoid contaminating the feedback signal with switch noise, while also minimizing the
trace length. This is most important when high feedback resistances greater than 100 kΩ are used to set the
output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node, and VIN so
there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon. This
provides further shielding for the voltage feedback path from switching noise sources.

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: LM5163
LM5163
SNVSBB3 – OCTOBER 2019 www.ti.com

10.2 Layout Example

Figure 30 shows an example layout for the PCB top layer of a 2-layer board with essential components placed
on the top side.
Type 3 ripple
injection
Connect BST cap
close to BST and SW

Place FB resistors very

close to FB & GND pins

PGOOD
connection

Thermal vias under

LM5163 PAD

Place resistor R8
close to the RON pin

VOUT GND Optional RC Connect ceramic EN/UVLO

connection connection snubber to input cap close to connection
reduce SW VIN and GND
node ringing

Figure 30. LM5163 Single-Sided PCB Layout Example

26 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: LM5163

 LM5163
www.ti.com SNVSBB3 – OCTOBER 2019

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

• LM5163 Quickstart Calculator
• LM5163 Simulation Models
• TI Reference Design Library
• Technical Articles:
– Use a Low-quiescent-current Switcher for High-voltage Conversion
– Powering Smart Sensor Transmitters in Industrial Applications
– Industrial Strength Design – Part 1
– Trends in Building Automation: Predictive Maintenance
– Trends in Building Automation: Connected Sensors for User Comfort

11.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5163 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Related Documentation

For related documentation see the following:
• Texas Instruments, LM5164-Q1EVM-041 EVM User's Guide
• Texas Instruments, Selecting an Ideal Ripple Generation Network for Your COT Buck Converter Application
Report
• Texas Instruments, Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding
Applications White Paper
• Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies White Paper
• Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies White Paper
• Texas Instruments, 24-V AC Power Stage with Wide VIN Converter and Battery Gauge for Smart Thermostat
Design Guide
• Texas Instruments, Accurate Gauging and 50-μA Standby Current, 13S, 48-V Li-ion Battery Pack Reference
Design Guide
• Texas Instruments, AN-2162: Simple Success with Conducted EMI from DC/DC Converters Application
Report

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: LM5163
LM5163
SNVSBB3 – OCTOBER 2019 www.ti.com

Related Documentation (continued)

• Texas Instruments, Powering Drones with a Wide VIN DC/DC Converter Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: LM5163

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM5163DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 150 LM5163

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM5163 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

• Automotive: LM5163-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-May-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5163DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-May-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5163DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0

Pack Materials-Page 2
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