Logic Circuits

Q. Draw the block diagram of dual 4-to-1 line Multiplexer? Explain its operation by
function table.

The logic symbol and logic diagram is shown in the following figures -

The function table is shown in the next table -

Q. What are the different logic gates used for the design of Digital Circuits? Give their logic
symbols and truth tables.
Q. What is a counter? Discuss its working principle.

In digital logic and computing, a counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in relationship to a clock signal. In
practice, there are two types of counters:

• Up counters, which increase (increment) in value

• Down counters, which decrease (decrement) in value

counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide
variety of designs exist, e.g:
 • Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-
flops
• Synchronous counter – all state bits change under control of a single clock
• Decade counter – counts through ten states per stage
• Up–down counter – counts both up and down, under command of a control input
• Ring counter – formed by a shift register with feedback connection in a ring
• Johnson counter – a twisted ring counter
• Cascaded counter

Each is useful for different applications. Usually, counter circuits are digital in nature, and count in
natural binary. Many types of counter circuit are available as digital building blocks, for example a
number of chips in the 4000 series implement different counters.

Occasionally there are advantages to using a counting sequence other than the natural binary sequence
such as the binary coded decimal counter, a linear feedback shift register counter, or a Gray-code
counter.

The following figure shows the basic structure of a computer –

Q. Write short note on T flip-flop.

If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If
the T input is low, the flip-flop holds the previous value. This behavior is described by the
characteristic equation:

(or, without benefit of the XOR operator, the equivalent:

)

and can be described in a truth table:

 T Flip-Flop operation
Characteristic table Excitation table
T Q Qnext Comment Q Qnext T Comment
0 0 0 hold state (no clk) 0 0 0 No change
0 1 1 hold state (no clk) 1 1 0 No change
1 0 1 toggle 0 1 1 Complement
1 1 0 toggle 1 0 1 Complement

When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency
is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has
application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J &
K pins are connected together and act as T) or D flip-flop (T input and Qprevious is connected to the D
input through an XOR gate). The T flip-flop is a single input version of the JK flip-flop. As shown in
the following figure, T flip-flop is obtained from the JK type if both inputs are tied together. The
output of the T flip-flop "toggles" with each clock pulse.

(a) Logic diagram

(b) Graphical symbol

(c) Transition table

Figure: Clocked T flip-flop

Q. Write short note on J-K flip-flop.

A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is
defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note
that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied
to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches
to Q=0 and vice versa.

A clocked JK flip-flop is shown in the following figure, Output Q is ANDed with K and CP inputs so
that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, output Q' is
ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.
Because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1)
after the outputs have been complemented once will cause repeated and continuous transitions of the
outputs. To avoid this, the clock pulses must have a time duration less than the propagation delay
through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-
triggered construction.

(a) Logic diagram

(b) Graphical symbol

(c) Transition table

Figure: Clocked JK flip-flop

Q. Discuss Encoder and Decoder.

An encoder is a combinational logic circuit that essentially performs the opposite function of the
decoder circuit. An encoder accepts an active level (i.e. ‘1’) on one of its inputs representing a digit
(e.g. decimal or octal digit) and converts it to a coded output (e.g. binary of BCD). The process of
converting from familiar symbols or numbers to a coded format is called encoding. We expect the
Decimal-to-BCD encoder to have 10 inputs and 4 outputs. The logic symbol for this 10-line-to-4-line
decoder is presented in Figure 2-11 and the associated conversion table listed in Table 2-13 with A3
representing the most significant bit.

Figure: Logic symbol for Decimal-to-BCD Encoder

Decimal BCD Code

Digit
A3 A2 A1 A0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

Table 2-13 Decimal-to-BCD code table

Now, note that the MSB is defined by the function

A3 = 8 + 9

Similarly, A2, A1 and A0 are defined by the functions

A2 = 4 + 5 + 6 + 7

A1 = 2 + 3 + 6 + 7

A0 = 1 + 3 + 5 + 7 + 9

Now we can implement the logic circuit for the decimal-to-BCD-decoder as illustrated in the
following figure-.

Figure: Logic circuit for Decimal-to-BCD encoder

Note that a connection for the decimal digit zero is not required as in this case the BCD outputs are all
LOW when there are no HIGH inputs.
A decoder is a device which does the reverse of an encoder, undoing the encoding so that the original
information can be retrieved. In digital electronics, a decoder can take the form of a multiple-input,
multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output
codes are different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be on for the
decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is
necessary in applications such as data multiplexing, 7 segment display and memory address decoding.

The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1)
only when all its inputs are "High." Such output is called as "active High output". If instead of AND
gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are "High".
Such output is called as "active low output".

Example: A 2-to-4 Line Single Bit Decoder

A slightly more complex decoder would be the n-to-2n type binary decoders. These type of decoders
are combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n
unique outputs. A maximum of 2n outputs because in case the 'n' bit coded information has unused bit
combinations, the decoder may have less than 2n outputs. We can have 2-to-4 decoder, 3-to-8 decoder
or 4-to-16 decoder. We can form a 3-to-8 decoder from two 2-to-4 decoders (with enable signals).

Similarly, we can also form a 4-to-16 decoder by combining two 3-to-8 decoders. In this type of
circuit design, the enable inputs of both 3-to-8 decoders originate from a 4th input, which acts as a
selector between the two 3-to-8 decoders. This allows the 4th input to enable either the top or bottom
decoder, which produces outputs of D(0) through D(7) for the first decoder, and D(8) through D(15)
for the second decoder.

.
 Computer Organization and Design
Q. Explain the three basic computer instruction formats.

Instruction formats vary between microprocessors and minicomputers and mainframe computers. As
the machine instructions are generally longer in larger computers with their larger memory words,
the instruction format or how the instruction is translated differs. Each instruction is composed of
fields. The lengths of instructions and the lengths and positions of the fields differ depending on the
instruction and the computer. An operation (function) code is part of all instructions. How the
remainder of the instruction is translated and the names assigned to the parts vary.
A typical machine instruction begins with the specification of an operation to be performed, the
operation (op) code. The op code, a part of every instruction, is usually located at the beginning of
each instruction format. Following the op code is information, if needed, to define the location of
the data or the operand on which the operation is to be performed. This location in memory,
called the operand address, normally defines the location that contains the operand at the start of
the operation (the source), or that will contain the modified operand upon completion of the operation
(the destination). The remainder of the instruction and how it is structured differs from one computer
or computer type to another. The designators in each field and the positions of the fields within the
instruction determine how the instruction will affect the operand, registers, memory, and general flow
of data in and out of the computer.

Microcomputer Instruction Formats

A basic 16-bit microinstruction is divided into a number of separate fields. Refer to figure 8-3 as a
reference. You’ll notice the lengths of the fields vary. The op code is located in the most significant
bits (215 through 213). B (bit 212) tells the computer to use all 16 bits as a word or divide the 16 bits
into 8-bit bytes

Figure—Example of microinstruction format

D (bits 29 through 26) is a code identifying the destination portion of the instruction. S (bits 23 through
2°) identifies the source portion. TD (bits 211 and 210) and TS (bits 25 and 24) are bits in the
instruction word that identify the type of addressing mode being used to locate the destination and
source addresses. As shown in the figure, two or three memory words are required for some
instructions depending on the addressing mode indicated by TD and Ts. Addressing modes are
discussed in the next section. Microcomputers may have more than one instruction format for the
one-word instructions. The format depends on the type of instruction being used.

Mainframe Computer Instruction Formats

The instruction formats for large mainframe computers vary greatly between types, generations, and
manufacturers of computers. For our example, we selected the instruction format for CPU instructions
of a mainframe computer with 32-bit computer instructions. These instructions can have up to
seven basic formats designated I, II, III, IV-A, IV-B, IV-C and V. The majority of these instructions
are full memory word (32-bit) instructions. Only formats IV-A, IV-B and IV-C are upper or lower
half-word (16-bit) instructions.

Figure—Microcomputer instruction formats with two and three memory words

Q. Explain instruction cycle in detail.

An instruction cycle (also called fetch-and-execute cycle, fetch-decode-execute cycle, and FDX) is the
time period during which a computer processes a machine language instruction from its memory or the
sequence of actions that the central processing unit (CPU) performs to execute each machine code
instruction in a program.

Each computer's CPU can have different cycles based on different instruction sets.

1. Fetch the instruction from main memory

The CPU uses the value of the program counter (PC) on the address bus. The CPU then fetches the
instruction from main memory via the data bus into the memory data register (MDR). The value from
the MDR is then placed into the current instruction register (CIR), a circuit that holds the instruction
temporarily so that it can be decoded and executed.
2. Decode the instruction

The instruction decoder interprets and implements the instruction. The instruction register (IR) holds
the current instruction, while the program counter (PC) holds the address in memory of the next
instruction to be executed.

3. Fetch data from main memory

Read the effective address from main memory if the instruction has an indirect address. Fetch required
data from main memory to be processed and place it into data registers.

4. Execute the instruction

From the instruction register, the data forming the instruction is decoded by the control unit. It then
passes the decoded information as a sequence of control signals to the relevant function units of the
CPU to perform the actions required by the instruction such as reading values from registers, passing
them to the Arithmetic logic unit (ALU) to add them together and writing the result back to a register.
A condition signal is sent back to the control unit by the ALU if it is involved.

5. Store results

Also called write back to memory. The result generated by the operation is stored in the main memory,
or sent to an output device. Based on the condition feedback from the ALU, the PC is either
incremented to address the next instruction or updated to a different address where the next instruction
will be fetched. The cycle is then repeated.

The following flow chart shows the Instruction Cycle -

 Figure: Instruction Cycle

Q. Explain memory reference instructions in detail.

Most of the computer's instructions tell it to perform a particular basic arithmetic calculation. The form
of these instructions, in the mode of operation of the computer chosen as the most straightforward for
introducing its instruction set, is shown below:
The dR and sR fields, giving the destination register and the source register for an operation, can
contain any value from 0 to 7. The sB field, indicating the base/address register whose contents
indicate the general area in memory from which a memory operand comes, can only contain a value
from 1 to 7; this distinguishes the latter two formats in the diagram from the first one. Similarly, the
sX field, which indicates the arithmetic/index register whose contents are used to select the element of
an array used as a memory operand, can only contain a value from 1 to 7; this distinguishes the third
format in the diagram from the second one. The convention used in this diagram, that a zero field in an
instruction indicates that the same field must be nonzero in instruction formats below it not otherwise
distinguished by opcode bits, but has no effect on fields above it, is followed in diagrams elsewhere in
these pages as well.

The first two bits of the seven-bit opcode shown in the instruction may be 00, 01, or 10. Instructions
starting with 11 are used for other instructions needed by the computer, such as instructions used to
transfer control from one part of a program to another.

The opcode is divided into two parts: the first part indicates the type of number the instruction works
with:

000 Byte 8-bit integer

001 Halfword 16-bit integer
010 Integer 32-bit integer
011 Long 64-bit integer
1000 Medium 48-bit floating-point
1001 Floating 32-bit floating-point
1010 Double 64-bit floating-point
1011 Quad 128-bit floating-point

and the second part indicates the operation performed by the instruction:

0000 000 Swap

0001 001 Compare
0010 010 Load
0011 011 Store
0100 100 Add
0101 101 Subtract
0110 110 Multiply
0111 111 Divide
1000 Insert
1001 Unsigned Compare
1010 Unsigned Load
1011 XOR
1100 AND
1101 OR
1110 Multiply Extensibly
1111 Divide Extensibly

The first eight operations apply both to floating-point numbers and integers; the second eight
operations apply only to integers.

Q. Show and explain the register transfer for the Fetch phase.

The instruction must be fetched from main memory, and then executed by the CPU. This is
fundamentally how a computer operates, with its CPU reading and executing a series of instructions
written in its machine language. From this arise all functions of a computer familiar from the user's
end.

The Fetch-Execute cycle in Transfer Notation

Expressed in register transfer notation:

MAR<-[PC]

MDR<-[[MemoryLocation]]

PC+1<-PC (The increment here indicates one instruction.)

IR<-MDR
Q. Discuss various registers required in computer.

A processor register (or general purpose register) is a small amount of storage available on the CPU
whose contents can be accessed more quickly than storage available elsewhere. Typically, this
specialized storage is not considered part of the normal memory range for the machine. Most, but not
all, modern computers adopt the so-called load-store architecture. Under this paradigm data is
'shuffled' from subordinated memory- be it L# cache or RAM- into registers, 'crunched' therein by
running instructions from the instruction set, then transferred out. A common property of computer
programs is locality of reference: the same values are often accessed repeatedly; and holding these
frequently used values in registers improves program execution performance.
Processor registers are at the top of the memory hierarchy, and provide the fastest way for a CPU to
access data. The term is often used to refer only to the group of registers that are directly encoded as
part of an instruction, as defined by the instruction set. More properly, these are called the
"architectural registers".
Allocating frequently used variables to registers can be critical to a program's performance. This
action, namely register allocation is performed by a compiler in the code generation phase.
Registers are normally measured by the number of bits they can hold, for example, an "8-bit register"
or a "32-bit register". Registers are now usually implemented as a register file, but they have also been
implemented using individual flip-flops, high speed core memory, thin film memory, and other ways
in various machines.

A processor often contains several kinds of registers, that can be classified according to their content
or instructions that operate on them:

• User-accessible Registers - The most common division of user-accessible registers is into data
registers and address registers.
• Data registers are used to hold numeric values such as integer and floating-point values. In
some older and low end CPUs, a special data register, known as the accumulator, is used
implicitly for many operations.
• Address registers hold addresses and are used by instructions that indirectly access memory.
o Some processors contain registers that may only be used to hold an address or only to
hold numeric values (in some cases used as an index register whose value is added as
an offset from some address); others allow registers to hold either kind of quantity. A
wide variety of possible addressing modes, used to specify the effective address of an
operand, exist.
o A stack pointer, sometimes called a stack register, is the name given to a register that
can be used by some instructions to maintain a stack (data structure).
• Conditional registers hold truth-values often used to determine whether some instruction
should or should not be executed.
• General purpose registers (GPRs) can store both data and addresses, i.e., they are combined
Data/Address registers.
• Floating point registers (FPRs) store floating point numbers in many architectures.
• Constant registers hold read-only values such as zero, one, or pi.
• Vector registers hold data for vector processing done by SIMD instructions (Single
Instruction, Multiple Data).
• Special purpose registers hold program state; they usually include the program counter (aka
instruction pointer), stack pointer, and status register (aka processor status word). In embedded
microprocessors, they can also correspond to specialised hardware elements.
o Instruction registers store the instruction currently being executed.
• In some architectures, model-specific registers (also called machine-specific registers) store
data and settings related to the processor itself. Because their meanings are attached to the
design of a specific processor, they cannot be expected to remain standard between processor
generations.
 • Control and status registers - It has three types. Program counter, instruction registers,
Program status word (PSW).
• Registers related to fetching information from RAM, a collection of storage registers located
on separate chips from the CPU (unlike most of the above, these are generally not architectural
registers):
o Memory buffer register
o Memory data register
o Memory address register
o Memory Type Range Registers (MTRR)

CPU
Q. What are the Addressing Modes? Explain all types of addressing modes.

Addressing modes are an aspect of the instruction set architecture in most central processing unit
(CPU) designs. The various addressing modes that are defined in a given instruction set architecture
define how machine language instructions in that architecture identify the operand (or operands) of
each instruction. An addressing mode specifies how to calculate the effective memory address of an
operand by using information held in registers and/or constants contained within a machine instruction
or elsewhere.

Simple addressing modes for code

Absolute

+----+------------------------------+
|jump| address |
+----+------------------------------+

(Effective PC address = address)

The effective address for an absolute instruction address is the address parameter itself with no
modifications.

PC-relative

+----+------------------------------+
|jump| offset | jump relative
+----+------------------------------+

(Effective PC address = next instruction address + offset, offset may be

negative)

The effective address for a PC-relative instruction address is the offset parameter added to the address
of the next instruction. This offset is usually signed to allow reference to code both before and after the
instruction.
Register indirect

+-------+-----+
|jumpVia| reg |
+-------+-----+

(Effective PC address = contents of register 'reg')

The effective address for a Register indirect instruction is the address in the specified register. For
example, (A7) to access the content of address register A7.

Sequential addressing modes

Sequential execution

+------+
| nop | execute the following instruction
+------+

(Effective PC address = next instruction address)

The CPU, after executing a sequential instruction, immediately executes the following instruction.

Sequential execution is not considered to be an addressing mode on some computers.

Conditional execution

Some computer architectures (e.g. ARM) have conditional instructions which can in some cases
obviate the need for conditional branches and avoid flushing the instruction pipeline. An instruction
such as a 'compare' is used to set a condition code, and subsequent instructions include a test on that
condition code to see whether they are obeyed or ignored.

skip

+------+-----+-----+
|skipEQ| reg1| reg2| skip the following instruction if reg1=reg2
+------+-----+-----+

(Effective PC address = next instruction address + 1)

Skip addressing may be considered a special kind of PC-relative addressing mode with a fixed "+1"
offset. Like PC-relative addressing, some CPUs have versions of this addressing mode that only refer
to one register ("skip if reg1==0") or no registers, implicitly referring to some previously-set bit in the
status register. Other CPUs have a version that selects a specific bit in a specific byte to test ("skip if
bit 7 of reg12 is 0").

Unlike all other conditional branches, a "skip" instruction never needs to flush the instruction pipeline.
Simple addressing modes for data

Register

+------+-----+-----+-----+
| mul | reg1| reg2| reg3| reg1 := reg2 * reg3;
+------+-----+-----+-----+

This "addressing mode" does not have an effective address and is not considered to be an addressing
mode on some computers.

Base plus offset, and variations

This is sometimes referred to as 'base plus displacement'

+------+-----+-----+----------------+
| load | reg | base| offset | reg := RAM[base + offset]
+------+-----+-----+----------------+

(Effective address = offset + contents of specified base register)

The offset is usually a signed 16-bit value (though the 80386 expanded it to 32 bits).

If the offset is zero, this becomes an example of register indirect addressing; the effective address is
just the value in the base register.

This addressing mode is closely related to the indexed absolute addressing mode.

Immediate/literal

+------+-----+-----+----------------+
| add | reg1| reg2| constant | reg1 := reg2 + constant;
+------+-----+-----+----------------+

This "addressing mode" does not have an effective address, and is not considered to be an addressing
mode on some computers.

Implicit

+-----------------+
| clear carry bit |
+-----------------+

The implied addressing mode, also called the implicit addressing mode, does not explicitly specify an
effective address for either the source or the destination (or sometimes both).

Either the source (if any) or destination effective address (or sometimes both) is implied by the
opcode.
Other addressing modes for code or data

Absolute/Direct
+------+-----+--------------------------------------+
| load | reg | address |
+------+-----+--------------------------------------+

(Effective address = address as given in instruction)

This requires space in an instruction for quite a large address. It is often available on CISC machines
which have variable-length instructions, such as x86.

Indexed absolute

+------+-----+-----+--------------------------------+
| load | reg |index| address |
+------+-----+-----+--------------------------------+

(Effective address = address + contents of specified index register)

This also requires space in an instruction for quite a large address. The address could be the start of an
array or vector, and the index could select the particular array element required. The processor may
scale the index register to allow for the size of each array element.

Base plus index

+------+-----+-----+-----+
| load | reg | base|index|
+------+-----+-----+-----+

(Effective address = contents of specified base register + contents of

specified index register)

The base register could contain the start address of an array or vector, and the index could select the
particular array element required. The processor may scale the index register to allow for the size of
each array element. This could be used for accessing elements of an array passed as a parameter.

Base plus index plus offset

+------+-----+-----+-----+----------------+
| load | reg | base|index| offset |
+------+-----+-----+-----+----------------+

(Effective address = offset + contents of specified base register + contents of

specified index register)

The base register could contain the start address of an array or vector of records, the index could select
the particular record required, and the offset could select a field within that record. The processor may
scale the index register to allow for the size of each array element.
Scaled

+------+-----+-----+-----+
| load | reg | base|index|
+------+-----+-----+-----+

(Effective address = contents of specified base register + scaled contents of

specified index register)

The base register could contain the start address of an array or vector, and the index could contain the
number of the particular array element required.

Register indirect

+------+-----+-----+
| load | reg | base|
+------+-----+-----+

(Effective address = contents of base register)

A few computers have this as a distinct addressing mode. Many computers just use base plus offset
with an offset value of 0. For example, (A7)

Register auto increment indirect

+------+-----+-------+
| load | reg | base |
+------+-----+-------+

(Effective address = contents of base register)

After determining the effective address, the value in the base register is incremented by the size of the
data item that is to be accessed.

Autodecrement register indirect

+------+-----+-----+
| load | reg | base|
+------+-----+-----+

(Effective address = new contents of base register)

Before determining the effective address, the value in the base register is decremented by the size of
the data item, which is to be accessed.

Within a loop, this addressing mode can be used to step backwards through all the elements of an array
or vector. A stack can be implemented by using this mode in conjunction with the previous addressing
mode (auto increment).
Memory indirect

Indirect addressing may be used for code or data. It can make implementation of pointers or references
or handles much easier, and can also make it easier to call subroutines which are not otherwise
addressable. Indirect addressing does carry a performance penalty due to the extra memory access
involved.

PC-relative

+------+------+---------+----------------+
| load | reg1 | base=PC | offset | reg1 := RAM[PC + offset]
+------+------+---------+----------------+

(Effective address = PC + offset)

The PC-relative addressing mode is used to load a register from a "constant" stored in program
memory a short distance away from the current instruction. It can be seen as a special case of the "base
plus offset" addressing mode, one that selects the program counter (PC) as the "base register".

Obsolete addressing modes

The addressing modes listed here were used in the 1950–1980 time frame, but are no longer available
on most current computers.

Multi-level memory indirect

If the word size is larger than the address then the word referenced for memory-indirect addressing
could itself have an indirect flag set to indicate another memory indirect cycle. Care is needed to
ensure that a chain of indirect addresses does not refer to itself; if it did, you could get an infinite loop
while trying to resolve an address. The IBM 1620, the Data General Nova, and the NAR 2 each have
such a multi-level memory indirect, and could enter such a infinite address calculation loop. The
memory indirect addressing mode on the Nova influenced the invention of indirect threaded code.

Q. What is the purpose of Addressing Modes?

An addressing mode which, in one given architecture, is treated as a single addressing mode may
represent functionality that, in another architecture, is covered by two or more addressing modes. For
example, some complex instruction set computer (CISC) computer architectures, such as the Digital
Equipment Corporation (DEC) VAX, treat registers and literal/immediate constants as just another
addressing mode. Others, such as the IBM System/390 and most reduced instruction set computer
(RISC) designs, encode this information within the instruction. Thus, the latter machines have three
distinct instruction codes for copying one register to another, copying a literal constant into a register,
and copying the contents of a memory location into a register, while the VAX has only a single
"MOV" instruction.

The term "addressing mode" is itself subject to different interpretations: either "memory address
calculation mode" or "operand accessing mode". Under the first interpretation instructions that do not
read from memory or write to memory (such as "add literal to register") are considered not to have an
"addressing mode". The second interpretation allows for machines such as VAX which use operand
mode bits to allow for a literal operand. Only the first interpretation applies to instructions such as
"load effective address".

Q. What is Instruction Format? Explain various Instruction Formats.

Six basic instruction formats shall support 16 and 32-bit instructions. The operation code (opcode)
shall normally consist of the 8 most significant bits of the instruction.

1. Register-to-Register Format

The register-to-register format is a 16-bit instruction consisting of an 8-bit opcode and two 4-bit
general register (GR) fields that typically specify any of 16 general registers. In addition, these fields
may contain a shift count, condition code, opcode extension, bit number, or the operand for immediate
short instructions.

MSB LSB
------------------------------------
| Opcode | GR1 | GR2 |
------------------------------------
0 7 8 11 12 15

2. Instruction Counter Relative Format

The Instruction Counter (IC) Relative Format is a 16-bit instruction consisting of an 8-bit opcode and
an 8-bit displacement field.

MSB LSB
-----------------------------------
| Opcode | Displacement |
-----------------------------------
0 7 8 15

3. Base Relative Format

The base relative instruction format is a 16-bit instruction consisting of a 6-bit opcode, a 2-bit base
register field and an 8-bit displacement field. The base register (BR) field allows the designation of
one of four different registers.

MSB LSB
------------------------------------
| Opcode | BR | Displacement |
------------------------------------
0 5 6 7 8 15

BR = 0 implies general register 12

BR = 1 implies general register 13
BR = 2 implies general register 14
BR = 3 implies general register 15

4. Base Relative Indexed Format

The base relative indexed instruction format is a 16-bit instruction consisting of a 6-bit opcode, a 2-bit
base register field, a 4-bit opcode extension and a 4-bit index register field. The base register (BR)
field allows the designation of one of four different base registers and the index register (RX) field
allows the designation of one of fifteen different index registers.

MSB LSB
-------------------------------------
| Opcode | BR | Op.Ex. | RX |
-------------------------------------
0 5 6 7 8 11 12 15

BR = 0 implies general register 12

BR = 1 implies general register 13
BR = 2 implies general register 14
BR = 3 implies general register 15
RX = 0 implies no indexing

5. Long Instruction Format

The Long Instruction Format is a 32-bit instruction consisting of an 8-bit opcode, a 4-bit general
register field, a 4-bit index register field and a 16-bit address field.

MSB LSB
------------------------------------------------------------------
| Opcode | GR1 | RX | 16-Bit Address Field |
------------------------------------------------------------------
0 7 8 11 12 15 16 31

Typically, GR1 is one of the 16 general registers on which the instruction is performing the operation.
RX is one of the 15 general registers being used as an index register. The 16-bit address field is either
a full 16-bit memory address or a 16-bit operand if the instruction specifies immediate addressing.

6. Immediate Opcode Extension Format

The immediate opcode extension format is a 32-bit instruction consisting of an 8-bit opcode, a 4-bit
general register field, a 4-bit opcode extension and a 16-bit data field. Typically, GR1 is one of the 16
general registers on which the instruction is performing the operation. Op.Ex. is an opcode extension.

MSB LSB
------------------------------------------------------------------
| Opcode | GR1 | Op.Ex. | 16-Bit Immediate Data |
------------------------------------------------------------------
0 7 8 11 12 15 16 31
7. Special Format

The special instruction format is a 16-bit instruction consisting of an 8-bit opcode followed by an 8-bit
opcode extension (Op.Ex.).

MSB LSB
-----------------------------------
| Opcode | Op.Ex. |
-----------------------------------
0 7 8 15

Q. Explain the different types of Data Manipulation Instructions.

Data manipulation instructions use the ALU in the CPU to carry out these instructions. One of the
operand must be kept in the accumulator or reg. A for 8-bit operations. For 16-bit operations the
operand is kept in a register pair HL.

Arithmetic :- ADD, ADC, SUB, SBC, CP, INC, DEC, DAA

Logic :- AND, OR, XOR, NEG, CPL

Bit :- BIT, SET, RES

Shift & Rotate :- SLA, SRA, SRL, RLC, RRC, RR, RL

Examples :-
1. adding two numbers in stored registers
2. subtracting two numbers stored in registers
3. adding two numbers stored in memory
4. incrementing the value in a register
5. decrementing the value in a register
6. comparing two numbers stored in registers and finding which one is larger
7. anding two numbers in stored registers
8. oring two numbers in stored registers
9. xoring two numbers in stored registers
10. complementing (1’s and 2’s) number in a register
11. testing a bit, resetting and setting it
12. shifting and rotating data in a register

Q. Explain Displacement Addressing Mode.

The most common addressing mode and the one that's easiest to understand is the displacement-only
(or direct) addressing mode. The displacement-only addressing mode consists of a 16 bit constant that
specifies the address of the target location. The instruction mov al ds:[8088h] loads the al register with
a copy of the byte at memory location 8088h. Likewise the instruction mov ds:[1234h] dl stores the
value in the dl register to memory location 1234h:

The displacement-only addressing mode is perfect for accessing simple variables.

Intel named this the displacement-only addressing mode because a 16 bit constant (displacement)
follows the mov opcode in memory. In that respect it is quite similar to the direct addressing mode on
the x86 processors. There are some minor differences however. First of all a displacement is exactly
that- some distance from some other point. On the x86 a direct address can be thought of as a
displacement from address zero. On the 80x86 processors this displacement is an offset from the
beginning of a segment (the data segment in this example). The example will typically access bytes in
memory.

By default all displacement-only values provide offsets into the data segment. If we want to provide an
offset into a different segment we must use a segment override prefix before your address. For
example to access location 1234h in the extra segment (es) we would use an instruction of the form
mov ax es:[1234h]. Likewise to access this location in the code segment we would use the instruction
mov ax cs:[1234h]. The ds: prefix in the previous examples is not a segment override. The CPU uses
the data segment register by default.

Control Unit
Q. Write short note on RISC.

RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a
small, highly-optimized set of instructions, rather than a more specialized set of instructions often
found in other types of architectures.
For any given level of general performance, a RISC chip will typically have far fewer transistors
dedicated to the core logic which originally allowed designers to increase the size of the register set
and increase internal parallelism.
Other features, which are typically found in RISC architectures are:
 • Uniform instruction format, using a single word with the opcode in the same bit positions in
every instruction, demanding less decoding;
• Identical general purpose registers, allowing any register to be used in any context, simplifying
compiler design (although normally there are separate floating point registers);
• Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or
load-store operations;
• Few data types in hardware

RISC designs are also more likely to feature a Harvard memory model, where the instruction stream
and the data stream are conceptually separated; this means that modifying the memory where code is
held might not have any effect on the instructions executed by the processor (because the CPU has a
separate instruction and data cache), at least until a special synchronization instruction is issued. On
the upside, this allows both caches to be accessed simultaneously, which can often improve
performance.

Many early RISC designs also shared the characteristic of having a branch delay slot. A branch delay
slot is an instruction space immediately following a jump or branch. The instruction in this space is
executed, whether or not the branch is taken (in other words the effect of the branch is delayed). This
instruction keeps the ALU of the CPU busy for the extra time normally needed to perform a branch.
Nowadays the branch delay slot is considered an unfortunate side effect of a particular strategy for
implementing some RISC designs, and modern RISC designs generally do away with it (such as
PowerPC, more recent versions of SPARC, and MIPS).

Q. Explain the difference between Hardwired Control and Micro programmed Control.

Hardwired Control Micro programmed Control

1. A hardwired control unit has a processor that A micro programmed control unit makes use of
generates signals or instructions to be a micro sequencer from which instruction bits
implemented in correct sequence. are decoded to be implemented.
2. It works through the use of distinct It acts as the device supervisor that controls the
components, drums, a sequential circuit rest of the subsystems including arithmetic and
design, or flip chips. logic units, registers, instruction registers, off-
chip input/output, and buses.
3. Once the control unit of a hard-wired computer In the case of a micro-programmed computer,
is designed and built, it is virtually impossible simply altering the microprogram stored in its
to alter its architecture and instruction set. control memory can change the computer’s
instruction set.
4. The task of designing the computer in the first The task of designing the computer in the first
place is complex. place is simple.
5. It is faster. It is comparatively slower.
6. Hardwired control is a control mechanism to Microprogrammed control is a control
generate control signals by using appropriate mechanism to generate control signals by using
finite state machine (FSM). a memory called control storage (CS), which
contains the control signals.
7.

Q. Explain instruction cycle in detail.

An instruction cycle (also called fetch-and-execute cycle, fetch-decode-execute cycle, and FDX) is
the time period during which a computer processes a machine language instruction from its memory or
the sequence of actions that the central processing unit (CPU) performs to execute each machine code
instruction in a program.

Instruction cycle

Each computer's CPU can have different cycles based on different instruction sets.

1. Fetch the instruction from main memory

The CPU uses the value of the program counter (PC) on the address bus. The CPU then fetches the
instruction from main memory via the data bus into the memory data register (MDR). The value from
the MDR is then placed into the current instruction register (CIR), a circuit that holds the instruction
temporarily so that it can be decoded and executed.

2. Decode the instruction

The instruction decoder interprets and implements the instruction. The instruction register (IR) holds
the current instruction, while the program counter (PC) holds the address in memory of the next
instruction to be executed.
Fetch data from main memory

Read the effective address from main memory if the instruction has an indirect address. Fetch required
data from main memory to be processed and place it into data registers.

3. Execute the instruction

From the instruction register, the data forming the instruction is decoded by the control unit. It then
passes the decoded information as a sequence of control signals to the relevant function units of the
CPU to perform the actions required by the instruction such as reading values from registers, passing
them to the Arithmetic logic unit (ALU) to add them together and writing the result back to a register.
A condition signal is sent back to the control unit by the ALU if it is involved.

4. Store results

Also called write back to memory. The result generated by the operation is stored in the main memory,
or sent to an output device. Based on the condition feedback from the ALU, the PC is either
incremented to address the next instruction or updated to a different address where the next instruction
will be fetched. The cycle is then repeated.

Fetch cycle

Steps 1 and 2 of the Instruction Cycle are called the Fetch Cycle. These steps are the same for each
instruction. The fetch cycle processes the instruction from the instruction word which contains an
opcode and an operand.

Execute cycle

Steps 3 and 4 of the Instruction Cycle are part of the Execute Cycle. These steps will change with each
instruction.

The first step of the execute cycle is the Process-Memory. Data is transferred between the CPU and
the I/O module. Next is the Data-Processing uses mathematical operations as well as logical operations
in reference to data. Central alterations is the next step, is a sequence of operations, for example a
jump operation. The last step is a combined operation from all the other steps.

Q. Discuss CISC characteristics.

A complex instruction set computer (CISC, pronounced like "sisk") is a computer instruction set
architecture (ISA) in which each instruction can execute several low-level operations, such as a load
from memory, an arithmetic operation, and a memory store, all in a single instruction.
Typically CISC chips have a large amount of different and complex instructions. The philosophy
behind it is that hardware is always faster than software, therefore one should make a powerful
instruction set, which provides programmers with assembly instructions to do a lot with short
programs.
A CISC (Complex Instruction Set Computer) is a instruction set architecture (ISA) for a
microprocessor in which a set of the low-level operations to the CPU like loading from memory, the
arithmetic and logical operations, storing the results in the memory etc. can be handled using a single
instruction.
The CISC uses the complex addressing modes to allow the computing operations involving the data
structures, memory allocation, memory manipulation, array accesses etc to be combined into a single
instruction using a high language programming mode thereby resulting in a compact code and fewer
calls to main memory.
The plus point of the CISC architecture is that it provides a higher level of throughput at lower
memory using easily programmable high-level language constructs. On the down side, at times, a
sequence of instructions instead of the complex procedure calls, may be error prone and may not be
suitable for implementation of some complex hardware control functions.
The CISC, or Complex Instruction Set Computer, is an Instruction Set that ultimately yielded many of
the most commercially successful processor designs in recent history, including the Intel Pentium/Core
and AMD Athlon line of processors. The CISC instruction set is designed to allow an instruction to
carry out multiple operations in a single execution. CISC requires a more complicated CPU design
than that of RISC (as it is handling multiple operations per instruction), but typically meant other
resources, such as memory, were less taxed.

Q. Describe the design procedure for Hardwired Control.

To execute instructions, a computer's processor must generate the control signals used to perform the
processor's actions in the proper sequence. This sequence of actions can either be executed by another
processor's software (for example in software emulation or simulation of a processor) or in hardware.
In hardwired control, the instruction bits directly generate the signals.
Before microprocessors, hardwired control usually was implemented using discrete components, flip-
chips, or even rotating discs or drums. This can be generally done by two methods.

Method1:

The classical method of sequential circuit design. It attempts to minimize the amount of hardwire, in
particular, by using only log2p flip flops to realize a p state circuit.

Method2:

An approach that uses one flip flop per state and is known as one hot method. While expensive in
terms of flip flops, this method simplifies controller unit design and debugging.

In practice, processor control units are often so complex that no one design method by itself can yield
a satisfactory circuit at an acceptable cost. The most acceptable design may consist of several linked,
but independently designed, sequential circuits.
 Fig: Moore state machine ith set of outputs for given set of inputs in the ith state

Fig: Hardwired control unit organization using a sequence counter from 0 to n 1

Q. Explain the working of a Microprogrammed Control Unit.

The control signals needed in each step of instruction execution can be generated by the finite state
machine method, also called hardwired control, or, alternatively, by the microprogrammed control
method discussed below.

o Control word (CW):

A word with each bit for one of the control signals. Each step of the instruction
execution is represented by a control word with all of the bits corresponding to the
control signals needed for the step set to one.
o Microinstruction:

Each step in a sequence of steps in the execution of a certain machine instruction is

considered as a microinstruction, and it is represented by a control word. All of the bits
corresponding to the control signals that need to be asserted in this step are set to 1, and
all others are set to 0 (horizontal organization).

o Microprogram:

Composed of a sequence of microinstructions corresponding to the sequence of steps in

the execution of a given machine instruction.

o Microprogramming:

The method of generating the control signals by properly setting the individual bits in a
control word of a step.
Q. Explain the Control unit with a block diagram.

A control unit in general is a central (or sometimes distributed but clearly distinguishable) part of
whatsoever machinery that controls its operation, provided that a piece of machinery is complex and
organized enough to contain any such unit. One domain in which the term is specifically used is the
area of computer design.
The functions performed by the control unit vary greatly by the internal architecture of the CPU, since
the control unit really implements this architecture. On a regular processor that executes x86
instructions natively the control unit performs the tasks of fetching, decoding, managing execution and
then storing results. On a x86 processor with a RISC core, the control unit has significantly more work
to do. It manages the translation of x86 instructions to RISC micro-instructions, manages scheduling
the micro-instructions between the various execution units, and juggles the output from these units to
make sure they end up where they are supposed to go. On one of these processors the control unit may
be broken into other units (such as a scheduling unit to handle scheduling and a retirement unit to deal
with results coming from the pipeline) due to the complexity of the job it must perform.
The following figure shows the structure of a control unit -

Fig: Relation of Control unit with others

Fig: Control unit processing

Q. Explain Microprogramming.

The Micro programming language is a very basic programming language used in teaching computer
science students principles of compiler construction. The language itself is built on top of an even
more basic language called Tiny, which is also used in compiler construction courses. Among the
features present in Micro, but not in Tiny, include IF statements, WHILE statements, variable
declarations, floating point numbers, and the multiplication and division operators.

The level of abstraction of a microprogram can vary according to the amount of control signal
encoding and the amount of explicit parallelism found in the microinstruction format. On one end of a
spectrum, a vertical microinstruction is highly encoded and looks like a simple macroinstruction; it
might contain a single opcode field and one or two operand specifiers.

Each vertical microinstruction specifies a single datapath operation and, when decoded, activates
multiple control signals. Branches within vertical microprograms are typically handled as separate
microinstructions using a "branch" or "jump" opcode. This style of microprogramming is the most
natural to someone experienced in regular assembly language programming, and is similar to
programming in a RISC instruction set.

A horizontal microinstruction might be completely unencoded, with each control signal assigned to a
separate bit position in the microinstruction format (as in Wilkes' original proposal and the simple
example given in the definitions section above). This extreme, however, is usually impractical since
groups of control signals are often mutually exclusive and the resulting representation efficiency is too
low. Instead, horizontal microinstructions typically use several operation fields, each encoding one of
several mutually exclusive choices.

• Advantages
o Systematic control unit design
o Ease of implementing a code-compatible family of computers
o Ability to emulate other computer systems
o Ability to debug system using microdiagnostics
o Field modification without rewiring or board replacement
o Low marginal cost for additional function, given that additional microinstructions fit
within the control store or do not otherwise impact the packaging constraints
o Reconfigurable computing using a writable control store
• Disadvantages
o Uneconomical for small systems due to relatively high fixed cost of control store and
microinstruction sequencing logic
o Another level of interpretation with associated overhead
o Instruction cycle time limited by control store access time
o Limited support tools

Q. Explain Handshaking.

In information technology, telecommunications, and related fields, handshaking is an automated

process of negotiation that dynamically sets parameters of a communications channel established
between two entities before normal communication over the channel begins. It follows the physical
establishment of the channel and precedes normal information transfer.

It is usually a process that takes place when a computer is about to communicate with a foreign device
to establish rules for communication. When a computer communicates with another device like a
modem, printer, or network server, it needs to handshake with it to establish a connection.
Handshaking may be used to negotiate parameters that are acceptable to equipment and systems at
both ends of the communication channel, including, but not limited to, information transfer rate,
coding alphabet, parity, interrupt procedure, and other protocol or hardware features.

Handshaking makes it possible to connect relatively heterogeneous systems or equipment over a

communication channel without the need for human intervention to set parameters. One classic
example of handshaking is that of modems, which typically negotiate communication parameters for a
brief period when a connection is first established, and thereafter use those parameters to provide
optimal information transfer over the channel as a function of its quality and capacity. The "squealing"
(which is actually a sound that changes in pitch 100 times every second) noises made by some
modems with speaker output immediately after a connection is established are in fact the sounds of
modems at both ends engaging in a handshaking procedure; once the procedure is completed, the
speaker might be silenced, depending on the settings of operating system or the application controlling
the modem.

Q. Compare CISC and RISC.

CISC RISC
1. Stands for Complex Instruction Set Computer. Stands for Reduced Instruction Set Computer.
2. The philosophy behind it: hardware is always The philosophy behind it: very few uses
faster than software; therefore one should make complex assembly language instructions as used
a powerful instruction set. by CISC, and programmers mostly use
Compilers, which tend to use smaller set of
instructions and can produce more efficient
codes.
3. A powerful, large, variable-length and slower Smaller, simpler, fixed-length and faster (on
(on execution) instruction-set. Needs fewer execution) instruction-set. Needs more
instructions to accomplish a task. instructions to accomplish a task.
4. CISC chip takes more time to develop for its RISC chips takes less time to develop, incurs
complexity, incurs more manufacturing cost. less manufacturing cost.
5. CISC processors require multiple clock cycles RISC processors execute instruction in a single
for executing an instruction. clock cycle.
6. CISC processor offers legacy support, i.e. if Newer RISC chips also provide some legacy
someone switches to a new version of CISC, support by keeping the instruction set simple.
he/she need not modify the code written earlier.
This effectively increases processor
complexity.
7. CISC processors require large micro code RISC processors includes instruction decode
ROMs that stores hundreds of lines of logic inside them.
translated micro code.

8. Experienced programmers with assembly Programmers can find it easier to learn and
instructions can do a lot with short programs. develop code with the smaller instruction set.
Intel and AMD CPUs use CISC chips. Apple for instance uses RISC chips.

Input/Output Unit
Q. Explain the difference between programmed I/O and interrupt initiated I/O.

INTERRUPT DRIVEN I/O —

The interrupt technique requires more complex hardware and software, but makes far more
efficient use of the computer’s time and capacities. In an interrupt driven I/O the I/O section itself is
capable of accessing memory via the computer communication buses. The I/O processor can, while
conducting I/O operations

Q. Explain the bus architecture in I/O interface.

I/O buses connect the CPU to all other components, except RAM. Data are moved on the buses from
one component to another, and data from other components to the CPU and RAM. The I/O buses
differ from the system bus in speed. Their speed will always be lower than the system bus speed. Over
the years, different I/O buses have been developed. On modern PCs, you will usually find four buses:

• The ISA bus, which is an old low speed bus, soon to be excluded from the PC design.
• The PCI bus, which is a new high speed bus.
• The USB bus (Universal Serial Bus), which is a new low speed bus.
• The AGP bus which solely is used for the graphics card.

I/O buses are really extensions to the system bus. On the motherboard, the system bus ends in a
controller chip, which forms a bridge to the I/O buses. The buses have had a very central placement in
the PC's data exchange. Actually, all components except the CPU communicate with each other and
with RAM via the different I/O buses. The logic is shown in the following figure-
Q. Explain Instruction Cycle in detail.

An instruction cycle (also called fetch-and-execute cycle, fetch-decode-execute cycle, and FDX) is
the time period during which a computer processes a machine language instruction from its memory or
the sequence of actions that the central processing unit (CPU) performs to execute each machine code
instruction in a program.

Instruction cycle

1. Fetch the instruction from main memory

The CPU uses the value of the program counter (PC) on the address bus. The CPU then fetches the
instruction from main memory via the data bus into the memory data register (MDR). The value from
the MDR is then placed into the current instruction register (CIR), a circuit that holds the instruction
temporarily so that it can be decoded and executed.

2. Decode the instruction

The instruction decoder interprets and implements the instruction. The instruction register (IR) holds
the current instruction, while the program counter (PC) holds the address in memory of the next
instruction to be executed.

3. Execute the instruction

From the instruction register, the data forming the instruction is decoded by the control unit. It then
passes the decoded information as a sequence of control signals to the relevant function units of the
CPU to perform the actions required by the instruction such as reading values from registers, passing
them to the Arithmetic logic unit (ALU) to add them together and writing the result back to a register.
A condition signal is sent back to the control unit by the ALU if it is involved.
4. Store results

Also called write back to memory. The result generated by the operation is stored in the main memory,
or sent to an output device. Based on the condition feedback from the ALU, the PC is either
incremented to address the next instruction or updated to a different address where the next instruction
will be fetched. The cycle is then repeated.

Fetch cycle

Steps 1 and 2 of the Instruction Cycle are called the Fetch Cycle. These steps are the same for each
instruction. The fetch cycle processes the instruction from the instruction word which contains an
opcode and an operand.

Execute cycle

Steps 3 and 4 of the Instruction Cycle are part of the Execute Cycle. These steps will change with each
instruction.

The first step of the execute cycle is the Process-Memory. Data is transferred between the CPU and
the I/O module. Next are the Data-Processing uses mathematical operations as well as logical
operations in reference to data. Central alterations is the next step, is a sequence of operations, for
example a jump operation. The last step is a combined operation from all the other steps.

Q. Explain Interrupt Cycle with a flow-chart.

The process of communication between the CPU and an external device can be handled in many ways.
Due to the relative speeds of the CPU and most other devices, we prefer to utilize a technique that
minimizes the CPU idle time. One technique to accomplish this is with an interrupt facility. Here the
external device informs the CPU when it is ready. Consider the case of a simple input/output interrupt
request. While the computer is running a program, it does not check the interrupt flags. In the event
that a flag is set, the computer is temporarily interrupted to handle the input/output transfer. It then
returns to the current program to continue on where it left off.

In a Von Neumann machine, only one program can be executed at any given time even though several
may be stored in memory. The interrupt facility handles the data transfer for other programs used to
service a device. We use the ION and IOF instructions to program our machine to set interrupt facility
(the IEN flag).

Interrupt Facility:

Ø The instructions ION and IOF set IEN flag enabling the programmer to make the decision on
whether or not to use the interrupt facility.

Ø When the device is ready, it informs the computer by setting its flag

§ Input device sets FGI to 1

 § Output device sets FGO to 1

Ø If either FGI or FGO is set to 1 and IEN is 1, then control signal R is set to 1. (This can occur
on any clock cycle after T2.)

The semantics for the transfer of control to the interrupt handler are:

RT0: AR¬ 0, TR¬ PC

RT1: M[AR]¬ TR, PC¬ 0
RT2: PC¬ PC+1, IEN¬ 0, R¬ 0.

The service routine must have instructions to perform these six tasks:

1. Save contents of processor registers (AC, E on our machine)

2. Check which flag is set (FGI/FGO)
3. Service the device whose flag is set.
4. Restore contents of processor registers.
5. Turn the interrupt facility on.
6. Return to the running program.
 Fig: Interrupt Cycle

Q. What is the difference between Serial and Parallel Transfer? Using a shift Register with
parallel load explain how to convert serial input data to parallel output and parallel input
data to serial output.

Serial Transfer Parallel Transfer

1. Parallel data transfer refers to the type of data Serial data transfer refers to the type of data
transfer in which a group of bits are transfer in which a group of data bits are
 transferred simultaneously transferred one bit at a time
2. Parallel data transfer requires more cables Serial data transfer requires less cables
3. The parallel ports are faster, and easier The serial ports are faster, and easier as they
because they don’t require multiplexing require multiplexing

A register capable of shifting both right and left is called a bi-directional shift register. Now if this
same register has both bi-directional shift and parallel-load capabilities, it is called a bi-directional
shift register with parallel load.

A brief description of the operation of the above circuit is as follows:

1. A “clear” control is used to clear the register to 0.

2. A “clock” input for clock pulses to synchronize all operations.
3. Two mode control signals “ S0 & S1” are used to control the mode of operations, as per the table.

4. A serial input associated with shift-right operation mode.

5. A serial input associated with shift-left operation mode.
6. A parallel-load with 4 input lines I4, I3, I2, and I1 with I1 and I4 being LSB & MSB respectively.
7. 4 parallel output lines A4, A3, A2, and A1 with A1 and A4 being the LSB & MSB respectively.

The circuit in the next page performs this above-mentioned operation.

Q. Describe the concepts of Interrupt and Vectored Interrupt in handling I/O devices.

Interrupt

I/O operations are started as a result of the execution of a program instruction. Once started, the I/O
device continues its operation at the same time that the job program is being executed. Eventually the
I/O operation reaches a point at which a program routine that is related to the I/O operation must be
executed. At that point the I/O device involved requests an interrupt. The interrupt action results in a
forced branch to the required subroutine.

In addition to the routine needed to start an I/O operation, subroutines are required to:

1. Transfer a data word between an I/O device and main storage (for write or read operations)
2. Handle unusual (or check) conditions related to the I/O device
3. Handle the ending of the I/O device operation

Some I/O devices do not require program-instruction handling of data transfers to or from core
storage. These devices are described in subsequent sections of this book. Their method of transferring
data is called cycle steal and is not related to the interrupt program-subroutine method of handling data
described in this section.

Vectored Interrupt

The Interrupt provides the CPU with the address of the Interrupt handler without having to check it
itself.

• It can be embedded in hardware.

• It can be an external device.
• Priority resolution is used where multiple devices are involved. (Only one ISA maybe executed
at one time).
• It may point to a ISR address or a Vector table

The following figure shows the Vectored interrupt controller -

Q. Explain the timing diagram of an Input transfer on a Synchronous bus.

Consider the example processor-memory synchronous bus of Figure (a). Figure (b) uses a timing
diagram to describe the protocol for reading the memory over the bus. In the diagram, time proceeds to
the right along the x-axis. The diagram shows that the processor must set the rd/wr line low for a read
to occur. The diagram also shows, using two vertical lines, that the processor must place the address
on addr for at least tsetup time before setting the enable line high. The diagram shows that the high
enable line triggers the memory to put data on the data wires after a time tread. Note that a timing
diagram represents control lines, like rd/wr and enable, as either being high or low, while it represents
data lines, like addr and data, as being either invalid (a single horizontal line) or valid (two horizontal
lines); the value of data lines is not normally relevant when describing a protocol.

The following figure shows the timing diagram of Input transfers in case of Read and Write operation
-

Figure: Timing diagram of Input transfers in case of Read and Write operation

Q. How computer buses can be used to communicate with memory and I/O?

A bus, in computing, is a set of physical connections (cables, printed circuits, etc.) which can be
shared by multiple hardware components in order to communicate with one another. The purpose of
buses is to reduce the number of "pathways" needed for communication between the components, by
carrying out all communications over a single data channel. This is why the metaphor of a "data
highway" is sometimes used.

A chipset is the component which routes data between the computer's buses, so that all the
components which make up the computer can communicate with each other. The chipset originally
was made up of a large number of electronic chips, hence the name. It generally has two components:
 • The NorthBridge (also called the memory controller) is in charge of controlling transfers
between the processor and the RAM, which is way it is located physically near the processor. It
is sometimes called the GMCH, for Graphic and Memory Controller Hub.
• The SouthBridge (also called the input/output controller or expansion controller) handles
communications between peripheral devices. It is also called the ICH (I/O Controller Hub).
The tem bridge is generally used to designate a component which connects two buses.

The following figure shows the bus is interacting with memory and I/O -

Memory Unit
Q. Explain Memory Hierarchy in Computer System.

The term memory hierarchy is used in the theory of computation when discussing performance issues
in computer architectural design, algorithm predictions, and the lower level programming constructs
such as involving locality of reference. A 'memory hierarchy' in computer storage distinguishes each
level in the 'hierarchy' by response time. Since response time, complexity, and capacity are related, the
levels may also be distinguished by the controlling technology.
The many trade-offs in designing for high performance will include the structure of the memory
hierarchy, i.e. the size and technology of each component. So the various components can be viewed
as forming a hierarchy of memories (m1,m2,...,mn) in which each member mi is in a sense subordinate
to the next highest member mi-1 of the hierarchy. To limit waiting by higher levels, a lower level will
respond by filling a buffer and then signaling to activate the transfer.

There are four major storage levels.

1. Internal – Processor registers and cache.

2. Main – the system RAM and controller cards.
3. On-line mass storage – Secondary storage.
4. Off-line bulk storage – Tertiary and Off-line storage.

This is a most general memory hierarchy structuring. Many other structures are useful. For example, a
paging algorithm may be considered as a level for virtual memory when designing a computer
architecture.

The following figure shows the memory hierarchy -

Figure: Memory Hierarchy

Q. What is virtual Memory? Discuss its role in Computer System.

Virtual memory is a computer system technique which gives an application program the impression
that it has contiguous working memory (an address space), while in fact it may be physically
fragmented and may even overflow on to disk storage.

Developed for multitasking kernels, virtual memory provides two primary functions:

1. Each process has its own address space, thereby not required to be relocated nor required to use
relative addressing mode.
2. Each process sees one contiguous block of free memory upon launch. Fragmentation is hidden.

All implementations (excluding emulators) require hardware support. This is typically in the form of a
Memory Management Unit built into the CPU.

Systems that use this technique make programming of large applications easier and use real physical
memory (e.g. RAM) more efficiently than those without virtual memory. Virtual memory differs
significantly from memory virtualization in that virtual memory allows resources to be virtualized as
memory for a specific system, as opposed to a large pool of memory being virtualized as smaller pools
for many different systems.

Note that "virtual memory" is more than just "using disk space to extend physical memory size" - that
is merely the extension of the memory hierarchy to include hard disk drives. Extending memory to
disk is a normal consequence of using virtual memory techniques, but could be done by other means
such as overlays or swapping programs and their data completely out to disk while they are inactive.
The definition of "virtual memory" is based on redefining the address space with a contiguous virtual
memory addresses to "trick" programs into thinking they are using large blocks of contiguous
addresses.

The following figure shows the working of a virtual memory –

 Figure: Working of Virtual Memory

Q. Discuss any Memory Management technique in detail.

In computer operating systems there are various ways in which the operating system can store and
retrieve data from secondary storage for use in main memory. One such memory management scheme
is referred to as paging. In the paging memory-management scheme, the operating system retrieves
data from secondary storage in same-size blocks called pages. The main advantage of paging is that it
allows the physical address space of a process to be noncontiguous. Prior to paging, systems had to fit
whole programs into storage contiguously which caused various storage and fragmentation problems.

Paging is an important part of virtual memory implementation in most contemporary general-purpose

operating systems, allowing them to use disk storage for data that does not fit into physical Random-
access memory (RAM). Paging is usually implemented as architecture-specific code built into the
kernel of the operating system.

The main functions of paging are performed when a program tries to access pages that are not
currently mapped to physical memory (RAM). This situation is known as a page fault. The operating
system must then take control and handle the page fault, in a manner invisible to the program.
Therefore, the operating system must:

1. Determine the location of the data in auxiliary storage.

2. Obtain an empty page frame in RAM to use as a container for the data.
3. Load the requested data into the available page frame.
 4. Update the page table to show the new data.
5. Return control to the program, transparently retrying the instruction that caused the page fault.

The need to reference memory at a particular address arises from two main sources:

• Processor trying to load and execute a program's instructions itself.

• Data being accessed by a program's instruction.

In step 2, when a page has to be loaded and all existing pages in RAM are currently in use, one of the
existing pages must be swapped with the requested new page. The paging system must determine the
page to swap by choosing one that is least likely to be needed within a short time. There are various
page replacement algorithms that try to answer such issue.

Most operating systems use some approximation of the least recently used (LRU) page replacement
algorithm (the LRU itself cannot be implemented on the current hardware) or working set based
algorithm.

If a page chosen to be swapped has been modified since loading (if the page is dirty), it has to be
written to auxiliary storage, otherwise it is simply discarded.

In addition to swapping in pages because they are necessary, in reaction to a page fault, there are
several strategies for guessing what pages might be needed, and speculatively pre-loading them.

Q. What are the criteria on which Memory Hierarchy is formed? What information it
Conveys? Differentiate between Main Memory and Cache Memory.

The term memory hierarchy is used in the theory of computation when discussing performance issues
in computer architectural design, algorithm predictions, and the lower level programming constructs
such as involving locality of reference. A 'memory hierarchy' in computer storage distinguishes each
level in the 'hierarchy' by response time. Since response time, complexity, and capacity are related, the
levels may also be distinguished by the controlling technology.

The many trade-offs in designing for high performance will include the structure of the memory
hierarchy, i.e. the size and technology of each component. So the various components can be viewed
as forming a hierarchy of memories (m1,m2,...,mn) in which each member mi is in a sense subordinate
to the next highest member mi-1 of the hierarchy. To limit waiting by higher levels, a lower level will
respond by filling a buffer and then signaling to activate the transfer.
There are four major storage levels.

1. Internal – Processor registers and cache.

2. Main – the system RAM and controller cards.
3. On-line mass storage – Secondary storage.
4. Off-line bulk storage – Tertiary and Off-line storage.
 Main Memory Cache Memory
1. Main Memory is directly accessible to the 1. Cache Memory is used by the CPU of a
CPU. computer.
2. The computer needs this memory for 2. The computer does not need this memory
constant processing of data and for constant processing of data and
instructions. instructions.
3. It is small in size. 3. It is smaller in size.
4. It is comparatively slower. 4. It is faster.
5. Main Memory is less costly. 5. Cache is very costly.
6. Main memory can hold several process 6. It contains only very small piece of
together in multiprocessing environment. information (instructions).

Q. Explain various Page replacement techniques.

In a computer operating system that uses paging for virtual memory management, page replacement
algorithms decide which memory pages to page out (swap out, write to disk) when a page of memory
needs to be allocated. Paging happens when a page fault occurs and a free page cannot be used to
satisfy the allocation, either because there are none, or because the number of free pages is lower than
some threshold.

Local and Global Replacement

Replacement algorithms can be local or global.

When a process incurs a page fault, a local page replacement algorithm selects for replacement some
page that belongs to that same process (or a group of processes sharing a memory partition). A global
replacement algorithm is free to select any page in memory.

Local page replacement assumes some form of memory partitioning that determines how many pages
are to be assigned to a given process or a group of processes. Most popular forms of partitioning are
fixed partitioning and balanced set algorithms based on the working set model. The advantage of local
page replacement is its scalability: each process can handle its page faults independently without
contending for some shared global data structure.

Precleaning

Most replacement algorithms simply return the target page as their result. This means that if target
page is dirty (that is, contains data that have to be written to the stable storage before page can be
reclaimed), I/O has to be initiated to send that page to the stable storage (to clean the page). In the
early days of virtual memory, time spent on cleaning was not of much concern, because virtual
memory was first implemented on systems with full duplex channels to the stable storage, and
cleaning was customarily overlapped with paging. Contemporary commodity hardware, on the other
hand, does not support full duplex transfers, and cleaning of target pages becomes an issue.
To deal with this situation, various precleaning policies are implemented. Precleaning is the
mechanism that starts I/O on dirty pages that are (likely) to be replaced soon. The idea is that by the
time the precleaned page is actually selected for the replacement, the I/O will complete and the page
will be clean. Precleaning assumes that it is possible to identify pages that will be replaced next.
Precleaning that is too eager can waste I/O bandwidth by writing pages that manage to get re-dirtied
before being selected for replacement.

Anticipatory paging

Some systems use demand paging -- waiting until a page is actually requested before loading it into
RAM.

Other systems attempt to reduce latency by guessing which pages not in RAM are likely to be needed
soon, and pre-loading such pages into RAM, before that page is requested. (This is often in
combination with pre-cleaning, which guesses which pages currently in RAM are not likely to be
needed soon, and pre-writing them out to storage).

When a page fault occurs, "anticipatory paging" systems will not only bring in the referenced page, but
also the next few consecutive pages (analogous to a prefetch input queue in a CPU).

The swap prefetch mechanism goes even further in loading pages (even if they are not consecutive)
that are likely to be needed soon.

Q. What is the need of Memory Protection? Explain how the protection is provided to the
Memory?

Memory protection is a way to control memory access rights on a computer, and is a part of most
modern operating systems. The main purpose of memory protection is to prevent a process from
accessing memory that has not been allocated to it. This prevents a bug within a process from affecting
other processes, or the operating system itself. Memory protection is a behavior that is distinct from
ASLR and the NX bit.

Methods

1. Segmentation

Segmentation refers to dividing a computer's memory into segments. The Global Descriptor Table and
Local Descriptor Tables can be used to reference segments in the computer's memory. Pointers to
memory segments on x86 processors can also be stored in the processor's segment registers. Initially
x86 processors had 4 segment registers, CS (code segment), SS (stack segment), DS (data segment)
and ES (extra segment); later another two segment registers were added – FS and GS.

2. Paging

In paging, the memory address space is divided into equal, small pieces, called pages. Using a virtual
memory mechanism, each page can be made to reside in any location of the physical memory, or be
flagged as being protected. Virtual memory makes it possible to have a linear virtual memory address
space and to use it to access blocks fragmented over physical memory address space. Most computer
architectures based on pages, most notably x86 architecture; also use pages for memory protection.

3. Protection Keys

A protection key mechanism divides physical memory up into blocks of a particular size (e.g. 2KB),
each of which has an associated numerical value called a protection key. Each process also has a
protection key value associated with it. On a memory access the hardware checks that the current
process's protection key matches the value associated with the memory block being accessed; if not, an
exception occurs. This mechanism was used in the System/360 architecture.

The System/360 protection keys described above are associated with physical addresses. This is
different from the protection key mechanism used by processors such as the Intel Itanium and the
Hewlett-Packard Precision Architecture (HP/PA, also known as PA-RISC), which are associated with
virtual addresses, and which allow multiple keys per process.

4. Simulated Segmentation

Simulation is use of a monitoring program to interpret the machine code instructions of some
computer. Such an Instruction Set Simulator can provide memory protection by using a segmentation-
like scheme and validating the target address and length of each instruction in real time before actually
executing them. The simulator must calculate the target address and length and compare this against a
list of valid address ranges that it holds concerning the thread's environment, such as any dynamic
memory blocks acquired since the thread's inception plus any valid shared static memory slots. The
meaning of "valid" may change throughout the thread's life depending upon context: it may sometimes
be allowed to alter a static block of storage, and sometimes not, depending upon the current mode of
execution which may or may not depend on a storage key or supervisor state.

5. Capability-based addressing

Capability-based addressing is a method of memory protection, that is unused in modern commercial

computers. In this, pointers are replaced by protected objects (called capabilities) that can only be
created via using privileged instructions which may only be executed by the kernel, or some other
process authorized to do so. This effectively lets the kernel control which processes may access which
objects in memory, with no need to use separate address spaces or context switches. Capabilities have
never gained mainstream adoption in commercial hardware, but they are widely used in research
systems such as KeyKOS and its successors, and are used conceptually as the basis for some virtual
machines, most notably Smalltalk and Java.

Q. Explain the Associative Memory with a block diagram.

Content-addressable memory (CAM) is a special type of computer memory used in certain very high
speed searching applications. It is also known as associative memory, associative storage, or
associative array, although the last term is more often used for a programming data structure.
The block diagram is shown in the following figure -

Fig: Block diagram

Fig: Single-Cycle CAM Architecture

Fig: Multi-Cycle CAM Parallelism

Q. Explain the working of Dynamic Memory. Why Dynamic Memory is more suitable for
computer RAM?

Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of
data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the
information eventually fades unless the capacitor charge is refreshed periodically.

To read a bit from a column, the following operations take place:

1. The sense amplifier is switched off and the bit lines are precharged to exactly matching
voltages that are intermediate between high and low logic levels. The bit lines are constructed
symmetrically to keep them balanced as precisely as possible.
2. The precharge circuit is switched off. Because the bit lines are very long, their capacitance will
hold the precharge voltage for a brief time. This is an example of dynamic logic.
3. The selected row's word line is driven high. This connects one storage capacitor to one of the
two bit lines. Charge is shared between the selected storage cell and the appropriate bit line,
slightly altering the voltage on the line. Although every effort is made to keep the capacitance
of the storage cells high and the capacitance of the bit lines low, capacitance is proportional to
physical size, and the length of the bit lines means that the net effect is a very small
perturbation of one bit line's voltage.
4. The sense amplifier is switched on. The positive feedback takes over and amplifies the small
voltage difference until one bit line is fully low and the other is fully high. At this point, the
row is "open" and a column can be selected.
5. Read data from the DRAM is taken from the sense amplifiers, selected by the column address.
Many reads can be performed while the row is open in this way.
6. While reads proceed, current is flowing back up the bit lines from the sense amplifiers to the
storage cells. This restores (refreshes) the charge in the storage cell. Due to the length of the bit
lines, this takes significant time beyond the end of sense amplification, and overlaps with one
or more column reads.
7. When done with the current row, the word line is switched off to disconnect the storage
capacitors (the row is "closed"), the sense amplifier is switched off, and the bit lines are
precharged again.

The following figure shows the memory read operation -

 Fig: Principle of operation of DRAM read, for simple 4 by 4 array

To write to memory, the row is opened and a given column's sense amplifier is temporarily forced to
the desired state, so it drives the bit line which charges the capacitor to the desired value. Due to the
positive feedback, the amplifier will then hold it stable even after the forcing is removed. During a
write to a particular cell, the entire row is read out, one value changed, and then the entire row is
written back in, as illustrated in the following figure –
 Fig: Principle of operation of DRAM write, for simple 4 by 4 array

The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required
per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. The
transistors and capacitors used are extremely small -- millions can fit on a single memory chip.

Q. Discuss about implementation of Virtual Memory and Cache Memory. What is their
importance?

Virtual Memory implementation

The implementation of Virtual Memory is done in the following steps -

The following figure shows the implementation scheme –

Cache Memory implementation

1. Addressing Constraints
In order to minimize effective memory access time, the access should be triggered as soon as the
effective address of the memory reference becomes available.

2. Access Time and Miss Ratio Targets

The performance of a cache is determined both by the fraction of memory requests it can satisfy
(hit/miss ratio) and the speed at which it can satisfy them (access time). There have been numerous
studies on cache hit/miss ratios with respect to the cache and line sizes, and the set associativity.
3. Cache Consistency
Since cache is a photo or copy of a small piece main memory, it is important that the cache always
reflects what is in main memory. Some common terms used to describe the process of maintaining
cache consistency are:

3.1 Snoop
When a cache is watching the address lines for transaction, this is called a snoop. This function allows
the cache to see if any transactions are accessing memory it contains within itself.

3.2 Snarf
When a cache takes the information from the data lines, the cache is said to have snarfed the data. This
function allows the cache to be updated and maintain consistency. Snoop and snarf are the
mechanisms the cache uses to maintain consistency.

Two other terms are commonly used to describe the inconsistencies in the cache data, these terms are:

3.3 Dirty Data

When data is modified within cache but not modified in main memory, the data in the cache is called
“dirty data.”

3.4 Stale Data

When data is modified within main memory but not modified in cache, the data in the cache is called
stale data.

Modern general-purpose computer operating systems generally use virtual memory techniques for
ordinary applications, such as word processors, spreadsheets, multimedia players, accounting, etc.,
except where the required hardware support (a memory management unit) is unavailable.

Cache is an extremely fast memory used to store instructions that are repeatedly used by the CPU. It
accelerates the CPU instruction retrieval process and result in a more efficient system. Without a
cache, the CPU has to retrieve instruction directly from the RAM. Since the RAM operates at a much
lower speed than the CPU (18ns to 0.3 ns), the full efficiency of the CPU is not utilized. Its
productivity effectively reduced by (18/0.3=60) times.

Q. Compare Shared Memory Multiprocessor Architecture and Distributed Memory

Architecture.

Shared Memory Multiprocessor Architecture

The shared IPs include the UART controller, the Debug Module for the processors, the SysACE
controller for the compact flash reader, a small shared Block RAM memory for booting purposes and a
timer to record execution times. The external memory controller is a slightly modified version of the
standard Xilinx MultiChannel OPB DDR RAM controller, augmented to support up to eight Xilinx
CacheLink ports instead of the standard four ports, in order to implement up to eight MicroBlaze cores
with instruction caches active. Each MicroBlaze in the system is connected to a local memory through
the Local Memory Busses (LMB) for private data. The shared instruction and data segments of the
applications resides on the external DDR memory, while private data are saved in the local memories.
The processor core can be further configured with a local data cache for the shared data segment.
The following figure shows the architecture –

Fig: The CerberO Architecture

Distributed Memory Architecture

The following figure shows distributed memory architecture -

Fig: Distributed Memory Architecture

1. Each processor has its own memory system, which it can access directly
2. To obtain data that is stored in some other processor’s memory, a processor must communicate with
that to request the data
3. Each processor has its own local memory system
4. More total bandwidth in the memory system than in a centralized memory system
5. The latency to complete a memory request is lower each processor’s memory is located
physically
close to it

Q. What are the various types of ROM? Discuss the methods of programming ROMs.

Mask-Programmed ROM

Mask-Programmed ROM chips are integrated circuits that physically encode the data to be stored, and
thus it is impossible to change their contents after fabrication. Other types of non-volatile solid-state
memory permit some degree of modification:

Programmable read-only memory

Programmable read-only memory (PROM), or one-time programmable ROM (OTP), can be written to
or programmed via a special device called a PROM programmer. Typically, this device uses high
voltages to permanently destroy or create internal links (fuses or antifuses) within the chip.
Consequently, a PROM can only be programmed once.

Erasable programmable read-only memory

Erasable programmable read-only memory (EPROM) can be erased by exposure to strong ultraviolet
light (typically for 10 minutes or longer), then rewritten with a process that again requires application
of higher than usual voltage. Repeated exposure to UV light will eventually wear out an EPROM, but
the endurance of most EPROM chips exceeds 1000 cycles of erasing and reprogramming. EPROM
chip packages can often be identified by the prominent quartz "window" which allows UV light to
enter. After programming, the window is typically covered with a label to prevent accidental erasure.
Some EPROM chips are factory-erased before they are packaged, and include no window; these are
effectively PROM.

Electrically erasable programmable read-only memory

Electrically erasable programmable read-only memory (EEPROM) is based on a similar

semiconductor structure to EPROM, but allows its entire contents (or selected banks) to be electrically
erased, then rewritten electrically, so that they need not be removed from the computer (or camera,
MP3 player, etc.). Writing or flashing an EEPROM is much slower (milliseconds per bit) than reading
from a ROM or writing to a RAM (nanoseconds in both cases).
Electrically alterable read-only memory

Electrically alterable read-only memory (EAROM) is a type of EEPROM that can be modified one bit
at a time. Writing is a very slow process and again requires higher voltage (usually around 12 V) than
is used for read access. EAROMs are intended for applications that require infrequent and only partial
rewriting. EAROM may be used as non-volatile storage for critical system setup information; in many
applications, EAROM has been supplanted by CMOS RAM supplied by mains power and backed-up
with a lithium battery.

Flash memory

Flash memory (or simply flash) is a modern type of EEPROM invented in 1984. Flash memory can be
erased and rewritten faster than ordinary EEPROM, and newer designs feature very high endurance
(exceeding 1,000,000 cycles). Modern NAND flash makes efficient use of silicon chip area, resulting
in individual ICs with a capacity as high as 32 GB as of 2007; this feature, along with its endurance
and physical durability, has allowed NAND flash to replace magnetic in some applications (such as
USB flash drives). Flash memory is sometimes called flash ROM or flash EEPROM when used as a
replacement for older ROM types, but not in applications that take advantage of its ability to be
modified quickly and frequently.

PROGRAMMING METHOD DETAILS

Essentially, this technique includes the following steps:

1. Perform blank check at VDD = VDDmin. Report failure. The device may not be properly erased.
2. Program location with pulses and verify after each pulse at VDD = VDDP:
where VDDP = VDD range required during programming(4.5V - 5.5V).
a) Programming condition:
VPP = 13.0V to 13.25V
VDD = VDDP = 4.5V to 5.5V
VPP must be VDD + 7.25V to keep “programming mode” active.
b) Verify condition:
VDD = VDDP
VPP VDD + 7.5V but not to exceed 13.25V
If location fails to program after “N” pulses, (suggested maximum program pulses of 8) then report
error as a programming failure.
3. Once location passes “Step 2", apply 3X over programming, i.e., apply three times the number of
pulses that were required to program the location. This will guarantee a solid programming margin.
The over programming should be made “software programmable” for easy updates.
4. Program all locations.
5. Verify all locations (using speed verify mode) at
VDD = VDDmin
6. Verify all locations at VDD = VDDmax
VDDmin is the minimum operating voltage spec. for the part. VDDmax is the maximum operating
Voltage spec. for the part.
Q. Discuss the working of DMA in details.

Direct memory access (DMA) is a feature of modern computers and microprocessors that allows
certain hardware subsystems within the computer to access system memory for reading and/or writing
independently of the central processing unit. Many hardware systems use DMA including disk drive
controllers, graphics cards, network cards and sound cards. DMA is also used for intra-chip data
transfer in multi-core processors, especially in multiprocessor system-on-chips, where its processing
element is equipped with a local memory (often called scratchpad memory) and DMA is used for
transferring data between the local memory and the main memory. Computers that have DMA
channels can transfer data to and from devices with much less CPU overhead than computers without
a DMA channel. Similarly a processing element inside a multi-core processor can transfer data to and
from its local memory without occupying its processor time and allowing computation and data
transfer concurrency.

The DMA controller can issue commands to the memory that behave exactly like the commands
issued by the CPU. The DMA controller in a sense is a second processor in the system but is dedicated
to an I/O function. The DMA controller as shown below connects one or more I/O ports directly to
memory, where the I/O data stream passes through the DMA controller faster and more efficiently
than through the processor as the DMA channel is specialised to the data transfer task.

The following figure shows the structure of DMA Controller –

Fig: DMA Controller

Q. What are the difference between Magnetic Tape and Magnetic Disk.

Magnetic Tape Magnetic Disk

1. Magnetic tape is a medium for magnetic Magnetic disk refers to the storage of data on a
recording generally consisting of a thin magnetized medium.
magnetizable coating on a long and narrow strip
of plastic.
2. Magnetic tape allowed massive amounts of data Common uses of magnetic disk are for
to be stored in computers for long periods of computer data mass storage on hard disks and
time and to be rapidly accessed when needed. the recording of analog audio and video works
on analog tape. Since much of audio and video
production is moving to digital systems, the
usage of hard disks is expected to increase at
the expense of analog tape.
3. Audio recording and Video recording is Analog recording, Digital recording and
possible Magneto-optical recording is possible

4. It can be accessed only sequentially. It can be accessed both sequentially and

randomly.

Q. Explain Main Memory and its components.

Primary storage (or main memory or internal memory), often referred to simply as memory, is the only
one directly accessible to the CPU. The CPU continuously reads instructions stored there and executes
them as required. Any data actively operated on is also stored there in uniform manner.
As shown in the diagram, traditionally there are two more sub-layers of the primary storage, besides
main large-capacity RAM:

• Processor registers are located inside the processor. Each register typically holds a word of data
(often 32 or 64 bits). CPU instructions instruct the arithmetic and logic unit to perform various
calculations or other operations on this data (or with the help of it). Registers are technically
among the fastest of all forms of computer data storage.
• Processor cache is an intermediate stage between ultra-fast registers and much slower main
memory. It's introduced solely to increase performance of the computer. Most actively used
information in the main memory is just duplicated in the cache memory, which is faster, but of
much lesser capacity. On the other hand it is much slower, but much larger than processor
registers. Multi-level hierarchical cache setup is also commonly used—primary cache being
smallest, fastest and located inside the processor; secondary cache being somewhat larger and
slower.