SYSTEM INTEGRATION

Droop Compensation Versus Ideal Regulation

By Conor Quinn, Product Marketing Manager, and
Paul Nikkel, Principal Design Engineer, Artesyn Technologies,
Eden Prairie, Minn.

dvances in silicon technology have led to voltage during large step changes in load current.

A
significantly faster processors, memory Artesyn’s new VRM10 series of processor power VRMs,
and switching logic. These high-perfor- for example, include two models with different power rat-
mance semiconductor devices can de- ings and different levels of droop compensation. Both
mand very fast changes in load current, models comply with Intel’s VRM10.x specifications. The
posing considerable challenges for the voltage regulator top-of-the-range VRM10-85-12-U model, which is in-
supplying their core voltage. When switching out of “sleep” tended for powering high-end server-type processors, such
mode, for example, processors often activate a large num- as Intel’s Xeon, has an output load line impedance, or droop
ber of hitherto dormant circuits, resulting in a large step- compensation value of 1.25 mV. Fig. 1 shows that with this
change in load current within a few hundred nanoseconds. level of droop compensation, if the VRM is programmed
Minimizing peak-to-peak voltage deviation in the face of to generate a 1.4-V output, this will decrease to 1.275 V at
such large dynamic changes in load current involves inno- 100 A of load current.
vative power conversion techniques, especially if large As highlighted in Fig. 1, if the processor is demanding
amounts of output capacitance are to be avoided. very little current, it makes sense to stay at the top of the
Several techniques have been proposed to address these regulation window, because any step change in current
challenging regulation requirements. One method that has demand can only result in a lowering of the VRM’s output
gained wide industry acceptance is called “droop” compen- voltage. Conversely, if the processor is operating at full load
sation. Designers interested in applying this technique must the next step-change in current can only be to a lower value,
understand how it works, when it should be used, and more causing a rise in VRM output voltage. Thus, it is best to
importantly, when it should not be used. stay at the bottom of the regulation window. It follows that
at half load, when the next (worst-case) step change can by
Reduced Transient Response definition only be a half-load step, it is best to be posi-
Droop compensation intentionally increases the dc out- tioned in the middle of the regulation window.
put impedance of a converter, lowering its output voltage, Droop compensation has the potential for improving
as load current increases. The technique was first employed the load step response by a factor of two, as shown by the
with dc-dc converters designed for parallel operation to waveforms in Fig. 2a. In this figure, the black waveform
help balance current sharing. It is now used by a number represents the output voltage of the converter without
of the leading multi-phase pulse width modulated (PWM) droop compensation during a transition from no load to
controller ICs and voltage regulator modules (VRMs) de- full load and back to no load. The red waveform shows the
signed to power latest-generation processors. The effect of output voltage with droop compensation. In both scenarios,
droop compensation is to reduce overshoot of the core the magnitudes of the voltage excursions are identical dur-
ing the load transients. However, the total excursion under
droop compensation is reduced by a factor of two by modi-
1.40 fying the regulation point with load current. In effect, the
output impedance of the converter is programmed to
1.38 match the ESR (equivalent series resistance) of the output
Output Voltage (V)

capacitors.
1.32
Vout Max. However, this fact is only true for a full-load step. The
Vout @ 12.0 Vin magnitude of the voltage excursion can be estimated by
1.28
Vout Min. multiplying the step current by the ESR of the output ca-
1.24 pacitors. No PWM controller can change that fact of life
for power system designers, whose job is to decide how
1.20 much, if any, output resistance to design into a VRM. Figs.
0 20 40 60 80 100
2a (full-load step), 2b (half-load step) and 2c (quarter-load
Output Current (A)
step) may help them choose the most appropriate load line
Fig. 1. Droop compensation characteristic of Artesyn’s VRM10-85-12-U. Continued on page 67.

Power Electronics Technology November 2004 64 www.powerelectronics.com

 SYSTEM INTEGRATION

Continued from page 64.

impedance. These diagrams illustrate
how the magnitude of the required 2 /2
step response is a key factor in mak-
ing this decision.
The amount of droop shown
(a) Full-Load Step (b) Half-Load Step (c) Quarter-Load Step
matches the output voltage change for
a full-load step, which corresponds to
Fig. 2. Graphs comparing transient response characteristics with (red traces) and without
a dc output impedance that matches (black traces) droop compensation for different load steps.
the effective ESR of the distribution
impedance, including all the output this; it will show two minimums of livery. Eliminating voltage overshoot
capacitance. 15 mV at different frequencies, rather significantly improves transient re-
Choosing the amount of droop than a single minimum of 7.5 mV. sponse performance in the face of
compensation to apply remains a By monitoring the voltage on a large step-changes in load current. As
slightly empirical process, because the processor running with a VRM that a result, Artesyn implements droop
designer needs to know the worst-case has a known droop characteristic, the compensation on all its latest-genera-
transient load change that the system output resistance or droop can be tion VRM10 series converters. Droop
is likely to experience. This may prove used as a current shunt. The dc volt- compensation also can reduce the
hard to predict, in which case it is age variation can be correlated to cur- number of capacitors needed to main-
probably best to err on the side of cau- rent variation. This may provide a way tain the required peak-to-peak dy-
tion and be prepared for full-load to measure processor current without namic response; this improves over-
transients; if this results in an unac- the need for a current probe and a all system reliability, lowers imple-
ceptable degree of droop, more ca- large inductive loop between the VRM mentation costs and saves valuable
pacitors can be used to lower the ESR, output capacitors and the processor. board space. PETech
so that less droop is needed. Droop compensation certainly has For more information on this article,
If the load-step magnitude is be- a role to play in processor power de- CIRCLE 360 on Reader Service Card
tween 100% and 50% of full load,
droop impedances less than the ESR
magnitude also can result in some im-
provements. However, for load steps
of less than 50% of full load, droop
compensation is unlikely to offer any
performance advantages, as high-
lighted by Fig. 2b, which shows both
a 0% to 50% step response and a 50%
to 100% step response. Fig. 2c, for
example, shows how droop can actu- Yokogawa's SignalExplorer
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CIRCLE 247 on Reader Service Card or freeproductinfo.net/pet
www.powerelectronics.com 67 Power Electronics Technology November 2004