Product Order Technical Tools & Support & Reference

Folder Now Documents Software Community Design

LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

LM5122 Wide-Input Synchronous Boost Controller With Multiple Phase Capability

1 Features 2 Applications
•
1 Maximum Input Voltage: 65 V • 12-V, 24-V, and 48-V Power Systems
• Minimum Input Voltage: 3 V (4.5 V for Start-Up) • Automotive Start-Stop
• Output Voltage up to 100 V • Audio Power Supply
• Bypass (VOUT = VIN) Operation • High-Current Boost Power Supply
• 1.2-V Reference with ±1% Accuracy
• Free-Run and Synchronizable Switching to 1 MHz 3 Description
The LM5122 is a multi-phase capable synchronous
• Peak-Current-Mode Control
boost controller intended for high-efficiency
• Robust 3-A Integrated Gate Drivers synchronous boost regulator applications. The control
• Adaptive Dead-Time Control method is based upon peak-current-mode control.
• Optional Diode-Emulation Mode Current-mode control provides inherent line feed
forward, cycle-by-cycle current limiting, and ease of
• Programmable Cycle-by-Cycle Current Limit loop compensation.
• Hiccup-Mode Overload Protection
The switching frequency is programmable up to
• Programmable Line UVLO 1 MHz. Higher efficiency is achieved by two robust N-
• Programmable Soft Start channel MOSFET gate drivers with adaptive dead-
• Thermal Shutdown Protection time control. A user-selectable diode-emulation mode
also enables discontinuous-mode operation for
• Low Shutdown Quiescent Current: 9 μA improved efficiency at light load conditions.
• Programmable Slope Compensation
An internal charge pump allows 100% duty cycle for
• Programmable Skip-Cycle Mode Reduces high-side synchronous switch (bypass operation). A
Standby Power 180° phase shifted clock output enables easy multi-
• Allows External VCC Supply phase interleaved configuration. Additional features
• Inductor DCR Current Sensing Capability include thermal shutdown, frequency synchronization,
hiccup-mode current limit, and adjustable line
• Multi-phase Capability undervoltage lockout.
• Thermally Enhanced 20 or 24-Pin HTSSOP
• Create a Custom Design Using the LM5122 With Device Information(1)
the WEBENCH® Power Designer PART NUMBER PACKAGE BODY SIZE (NOM)
LM5122 HTSSOP (20) 6.50 mm × 4.40 mm
LM5122Z HTSSOP (24) 7.80 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

space
space
Simplified Application Diagram
VIN VOUT

VCC BST SW
LO
CSN HO
CSP COMP
VIN FB
UVLO RES
SLOPE SS
SYNCIN/RT MODE
SYNCOUT PGND
AGND
LM5122 OPT

Copyright © 2017, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 22
2 Applications ........................................................... 1 8 Application and Implementation ........................ 25
3 Description ............................................................. 1 8.1 Application Information............................................ 25
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 35
5 Pin Configuration and Functions ......................... 4 9 Power Supply Recommendations...................... 44
6 Specifications......................................................... 6 10 Layout................................................................... 44
6.1 Absolute Maximum Ratings ...................................... 6 10.1 Layout Guidelines ................................................. 44
6.2 ESD Ratings: LM5122, LM5122Z ............................. 6 10.2 Layout Example .................................................... 44
6.3 Recommended Operating Conditions....................... 7 11 Device and Documentation Support ................. 45
6.4 Thermal Information ................................................. 7 11.1 Device Support...................................................... 45
6.5 Electrical Characteristics........................................... 7 11.2 Receiving Notification of Documentation Updates 45
6.6 Typical Characteristics ............................................ 11 11.3 Community Resources.......................................... 45
7 Detailed Description ............................................ 14 11.4 Trademarks ........................................................... 45
7.1 Overview ................................................................. 14 11.5 Electrostatic Discharge Caution ............................ 45
7.2 Functional Block Diagram ....................................... 14 11.6 Glossary ................................................................ 45
7.3 Feature Description................................................. 15 12 Mechanical, Packaging, and Orderable
Information ........................................................... 46

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from May 1, 2017 to June 9, 2017 Page

• Changed by splitting out the automotive datasheet from this commercial datasheet ........................................................... 1
• Added 24-pin HTTSOP package option ................................................................................................................................. 1
• Added links for WEBENCH ................................................................................................................................................... 1
• Added 24-HTSSOP pin configuration..................................................................................................................................... 4
• Added 24-HTSSOP Functions ............................................................................................................................................... 5
• Changed UVLO value............................................................................................................................................................. 6
• Changed VCC value .............................................................................................................................................................. 6
• Changed one NC value ......................................................................................................................................................... 6
• Changed from outlet to contact ............................................................................................................................................. 6
• Added LM5122Z part number ................................................................................................................................................ 6
• Changed 20-HTSSOP Thermal Information and added 24-HTSSOP thermal values ........................................................... 7
• Added ICSP –ICSN (LM5122Z only) specs ................................................................................................................................ 9
• Added No load, 50% to 50% (LM5122Z only) specs ........................................................................................................... 10
• Added 24-pin HTSSOP ........................................................................................................................................................ 14
• Added Negative to Positive conversion example ................................................................................................................. 34

Changes from Revision F (May 2015) to Revision G Page

• Added Automotive ESD feature.............................................................................................................................................. 1

• Added paragraph and second equation .............................................................................................................................. 22
• Changed equation ............................................................................................................................................................... 22

2 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Changes from Revision E (December 2014) to Revision F Page

• Changed Handling Ratings to ESD Ratings and moved Storage temperature to Absolute Max Ratings ............................ 6
• Added Ohm symbol in Current Sense Resistor RS equation 28 .......................................................................................... 37
• Changed typo to reflect an Ohm symbol in Current Sense Resistor RS equation 29 .......................................................... 37

Changes from Revision D (September 2013) to Revision E Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1

Changes from Revision C (August, 2013) to Revision D Page

• Changed 5 kΩ to 20 kΩ.......................................................................................................................................................... 8
• Changed CCOMP to CHF ........................................................................................................................................................ 42

Changes from Revision B (May, 2013) to Revision C Page

• Deleted Package Addendum................................................................................................................................................ 44

Changes from Revision A (May, 2013) to Revision B Page

• Deleted Device Info table ....................................................................................................................................................... 5

Changes from Original (March, 2013) to Revision A Page

• Released full datasheet. ......................................................................................................................................................... 5

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

5 Pin Configuration and Functions

PWP Package
20-Pin HTSSOP With Exposed Pad
Top View

SYNCOUT 1 20 BST

OPT 2 19 HO

CSN 3 18 SW

CSP 4 17 VCC

VIN 5 16 LO
EP
UVLO 6 15 PGND

SS 7 14 RES

SYNCIN/RT 8 13 MODE

AGND 9 12 SLOPE

FB 10 11 COMP

PWP Package
24-Pin HTSSOP With Exposed Pad
Top View

SYNCOUT 1 24 BST

OPT 2 23 HO

NC 3 22 SW

CSN 4 21 NC

CSP 5 20 NC

VIN 6 19 VCC
EP
NC 7 18 LO

UVLO 8 17 PGND

SS 9 16 RES

SYNCIN/RT 10 15 MODE

AGND 11 14 SLOPE

FB 12 13 COMP

4 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Pin Functions
PIN
TYPE (1) DESCRIPTION
NAME 24-Pin 20-Pin
Analog ground connection. Return for the internal voltage reference and analog
AGND 11 9 G
circuits.
High-side driver supply for bootstrap gate drive. Connect to the cathode of the
external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor
BST 24 20 P supplies current to charge the high-side N-channel MOSFET gate and should be
placed as close to controller as possible. An internal BST charge pump supplies 200-
µA current into bootstrap capacitor for bypass operation.
Output of the internal error amplifier. Connect the loop compensation network
COMP 13 11 O
between this pin and the FB pin.
Inverting input of current sense amplifier. Connect to the negative-side of the current
CSN 4 3 I
sense resistor.
Non-inverting input of current sense amplifier. Connect to the positive-side of the
CSP 5 4 I
current sense resistor.
Feedback. Inverting input of the internal error amplifier. A resistor divider from the
output to this pin sets the output voltage level. The regulation threshold at the FB pin
FB 12 10 I
is 1.2 V. The controller is configured as slave mode if the FB pin voltage is above 2.7
V at initial power-on.
High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side
HO 23 19 O
synchronous N-channel MOSFET switch through a short, low inductance path.
Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side
LO 18 16 O
N-channel MOSFET switch through a short, low inductance path.
Switching mode selection pin. 700-kΩ pullup and 100-kΩ pulldown resistor internal
hold MODE pin to 0.15 V as a default. By adding external pullup or pulldown resistor,
MODE pin voltage can be programmed. When MODE pin voltage is greater than 1.2-
V diode emulation mode threshold, forced PWM mode is enabled, allowing current to
flow in either direction through the high-side N-channel MOSFET switch. When
MODE 15 13 I
MODE pin voltage is less than 1.2 V, the controller works in diode emulation mode.
Skip cycle comparator is activated as a default. If MODE pin is grounded, the
controller still operates in diode emulation mode, but the skip cycle comparator will
not be triggered in normal operation, this enables pulse skipping operation at light
load.
Clock synchronization selection pin. This pin also enables/disables SYNCOUT
OPT 2 2 I
related with master/slave configuration. The OPT pin should not be left floating.
Power ground connection pin for low-side N-channel MOSFET gate driver. Connect
PGND 17 15 G
directly to the source terminal of the low-side N-channel MOSFET switch.
The restart timer pin for an external capacitor that configures hiccup mode off-time
RES 16 14 O and restart delay during over load conditions. Connect directly to the AGND when
hiccup mode operation is not required.
Slope compensation is programmed by a single resistor between SLOPE and the
SLOPE 14 12 I
AGND.
Soft-start programming pin. An external capacitor and an internal 10-μA current
SS 9 7 I
source set the ramp rate of the internal error amplifier reference during soft-start.
Switching node of the boost regulator. Connect to the bootstrap capacitor, the source
SW 22 18 I/O terminal of the high-side N-channel MOSFET switch and the drain terminal of the
low-side N-channel MOSFET switch through short, low inductance paths.
The internal oscillator frequency is programmed by a single resistor between RT and
the AGND. The internal oscillator can be synchronized to an external clock by
SYNCIN/RT 10 8 I applying a positive pulse signal into this SYNCIN pin. The recommended maximum
internal oscillator frequency in master configuration is 2 MHz which leads to 1 MHz
maximum switching frequency.
Clock output pin. SYNCOUT provides 180° shifted clock output for an interleaved
SYNCOUT 1 1 O operation. SYNCOUT pin can be left floating when it is not used. See Slave Mode
and SYNCOUT section.

(1) G = Ground, I = Input, O = Output, P = Power

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Pin Functions (continued)

PIN
TYPE (1) DESCRIPTION
NAME 24-Pin 20-Pin
Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator
is in the shutdown mode with all functions disabled. If the UVLO pin voltage is
greater than 0.4 V and below 1.2 V, the regulator is in standby mode with the VCC
UVLO 8 6 I regulator operational and no switching at the HO and LO outputs. If the UVLO pin
voltage is above 1.2 V, the start-up sequence begins. A 10-μA current source at
UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external
UVLO resistors to provide hysteresis. The UVLO pin should not be left floating.
VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor
VCC 19 17 P/O/I
located as close as possible to controller.
Supply voltage input source for the VCC regulator. Connect to input capacitor and
VIN 6 5 P/I
source power supply connection with short, low impedance paths.
Exposed pad of the package. No internal electrical connections. Must be soldered to
EP EP N/A
the large ground plane to reduce thermal resistance.
NC 3, 7, 20, 21 — No electrical contact

6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN, CSP, CSN –0.3 75 V
BST to SW, FB, MODE, UVLO, OPT, VCC (2) –0.3 15 V
SW –5 105 V
Input
BST –0.3 115 V
SS, SLOPE, SYNCIN/RT –0.3 7 V
CSP to CSN, PGND –0.3 0.3 V
HO to SW –0.3 BST to SW + 0.3 V
Output (3) LO –0.3 VCC + 0.3 V
COMP, RES, SYNCOUT –0.3 7 V
Thermal Junction temperature –40 150 °C
Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless
otherwise specified, all voltages are referenced to AGND pin.
(2) See Application and Implementation when input supply voltage is less than the VCC voltage.
(3) All output pins are not specified to have an external voltage applied.

6.2 ESD Ratings: LM5122, LM5122Z

VALUE UNIT
(1)
Electrostatic Human body model (HBM), per JESD22-A114 ±2000
V(ESD) V
discharge Charged device model (CDM), per JESD22-C101 (2)
±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
(2)
Input supply voltage VIN 4.5 65 V
Low-side driver bias voltage VCC 14 V
High-side driver bias voltage BST to SW 3.8 14 V
Current sense common mode range (2) CSP, CSN 3 65 V
Switch node voltage SW 100 V
Junction temperature, TJ –40 125 °C

(1) Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but do not ensure
specific performance limits.
(2) Minimum VIN operating voltage is always 4.5 V. The minimum input power supply voltage can be 3 V after start-up, assuming VIN
voltage is supplied from an available external source.

6.4 Thermal Information

LM5122, LM5122Z
THERMAL METRIC PWP UNIT
20 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 36 32.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 20.1 15.6 °C/W
RθJB Junction-to-board thermal resistance 16.8 7.5 °C/W
ψJT Junction-to-top characterization parameter 0.4 0.2 °C/W
ψJB Junction-to-board characterization parameter 16.7 7.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 1.1 °C/W

6.5 Electrical Characteristics

Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference
purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN SUPPLY
ISHUTDOWN VIN shutdown current VUVLO = 0 V 9 17 µA
IBIAS VIN operating current (exclude the
VUVLO = 2 V, non-switching 4 5 mA
current into RT resistor)
VCC REGULATOR
VCC(REG) VCC regulation No load 6.9 7.6 8.3 V
VVIN = 4.5 V, no external load 0.25 V
VCC dropout (VIN to VCC)
VVIN = 4.5 V, IVCC = 25 mA 0.28 0.5 V
VCC sourcing current limit VVCC = 0 V 50 62 mA
VCC operating current (exclude VVCC = 8.3 V 3.5 5 mA
IVCC
the current into RT resistor) VVCC = 12 V 4.5 8 mA
VCC rising, VVIN = 4.5 V 3.9 4 4.1 V
VCC undervoltage threshold
VCC falling, VVIN = 4.5 V 3.7 V
VCC undervoltage hysteresis 0.385 V
UNDERVOLTAGE LOCKOUT
UVLO threshold UVLO rising 1.17 1.2 1.23 V
UVLO hysteresis current VUVLO = 1.4 V 7 10 13 µA
UVLO standby enable threshold UVLO rising 0.3 0.4 0.5 V
UVLO standby enable hysteresis 0.1 0.125 V

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Electrical Characteristics (continued)

Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference
purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MODE
Diode emulation mode threshold MODE rising 1.2 1.24 1.28 V
Diode emulation mode hysteresis 0.1 V
Default MODE voltage 145 155 170 mV
COMP rising, measured at COMP 1.290 V
Default skip cycle threshold
COMP falling, measured at COMP 1.245 V
Skip cycle hysteresis Measured at COMP 40 mV
ERROR AMPLIFIER
VREF FB reference voltage Measured at FB, VFB = VCOMP 1.188 1.2 1.212 V
FB input bias current VFB = VREF 5 nA
ISOURCE = 2 mA, VVCC = 4.5 V 2.75 V
VOH COMP output high voltage
ISOURCE = 2 mA, VVCC = 12 V 3.4 V
VOL COMP output low voltage ISINK = 2 mA 0.25 V
AOL DC gain 80 dB
fBW Unity gain bandwidth 3 MHz
Slave mode threshold FB rising 2.7 3.4 V
OSCILLATOR
fSW1 Switching frequency 1 RT = 20 kΩ 400 450 500 kHz
fSW2 Switching frequency 2 RT = 10 kΩ 775 875 975 kHz
RT output voltage 1.2 V
RT sync rising threshold RT rising 2.5 2.9 V
RT sync falling threshold RT falling 1.6 2 V
Minimum sync pulse width 100 ns
SYNCOUT
SYNCOUT high-state voltage ISYNCOUT = –1 mA 3.3 4.3 V
SYNCOUT low-state voltage ISYNCOUT = 1 mA 0.15 0.25 V
OPT
Synchronization selection OPT rising
2 3 4 V
threshold
SLOPE COMPENSATION
SLOPE output voltage 1.17 1.2 1.23 V
RSLOPE = 20 kΩ, fSW = 100 kHz, 50% duty
1.375 1.65 1.925 V
cycle, TJ = –40°C to 125°C
VSLOPE Slope compensation amplitude
RSLOPE= 20 kΩ, fSW= 100 kHz, 50% duty
1.4 1.65 1.9 V
cycle, TJ = 25°C
SOFT START
ISS-SOURCE SS current source VSS = 0 V 7.5 10 12 µA
SS discharge switch RDS-ON 13 Ω
PWM COMPARATOR
VVCC = 5.5 V 330 400 ns
tLO-OFF Forced LO off-time
VVCC = 4.5 V 560 750 ns
RSLOPE = 20 kΩ 150 ns
tON-MIN Minimum LO on-time
RSLOPE = 200 kΩ 300 ns
TJ = –40°C to 125°C 0.95 1.1 1.25 V
COMP to PWM voltage drop
TJ = 25°C 1 1.1 1.2 V

8 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Electrical Characteristics (continued)

Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference
purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT
Cycle-by-cycle current limit CSP to CSN, TJ = –40°C to 125°C 65.5 75 87.5 mV
VCS-TH1
threshold CSP to CSN, TJ = 25°C 67 75 86 mV
CSP to CSN, rising 7 mV
VCS-ZCD Zero cross detection threshold
CSP to CSN, falling 0.5 6 12 mV
Current sense amplifier gain 10 V/V
ICSP CSP input bias current 12 µA
ICSN CSN input bias current 11 µA
ICSP – ICSN –1.75 1 3.75
Bias current matching µA
ICSP – ICSN (LM5122Z only) –2.5 1 8.75
CS to LO delay Current sense / current limit delay 150 ns
HICCUP-MODE RESTART
VRES Restart threshold RES rising 1.15 1.2 1.25 V
RES rising 4.2 V
VHCP-
Hiccup counter upper threshold RES rising,
UPPER 3.6 V
VVIN = VVCC = 4.5 V
RES falling 2.15 V
VHCP-
Hiccup counter lower threshold RES falling,
LOWER 1.85 V
VVIN = VVCC = 4.5 V
IRES-
RES current source1 Fault-state charging current 20 30 40 µA
SOURCE1
IRES-SINK1 RES current sink1 Normal-state discharging current 5 µA
IRES-
RES current source2 Hiccup-mode off-time charging current 10 µA
SOURCE2
IRES-SINK2 RES current sink2 Hiccup-mode off-time discharging current 5 µA
Hiccup cycle 8 Cycles
RES discharge switch RDS-ON 40 Ω
Ratio of hiccup mode off-time to
122
restart delay time
HO GATE DRIVER
VOHH HO high-state voltage drop IHO = –100 mA, VOHH = VBST –VHO 0.15 0.24 V
VOLH HO low-state voltage drop IHO = 100 mA, VOLH = VHO –VSW 0.1 0.18 V
HO rise time (10% to 90%) CLOAD = 4700 pF, VBST = 12 V 25 ns
HO fall time (90% to 10%) CLOAD = 4700 pF, VBST = 12 V 20 ns
VHO = 0 V, VSW = 0 V, VBST = 4.5 V 0.8 A
IOHH Peak HO source current
VHO = 0 V, VSW = 0 V, VBST = 7.6 V 1.9 A
VHO = VBST = 4.5 V 1.9 A
IOLH Peak HO sink current
VHO = VBST= 7.6 V 3.2 A
IBST BST charge pump sourcing
VVIN = VSW = 9. V , VBST - VSW = 5 V 100 200 µA
current
BST to SW, IBST= –70 μA,
5.3 6.2 6.75 V
VVIN = VSW = 9 V
BST charge pump regulation
BST to SW, IBST = –70 μA,
7 8.5 9 V
VVIN = VSW = 12 V
BST to SW undervoltage 2 3 3.5 V
BST DC bias current VBST – VSW = 12 V, VSW = 0 V 30 45 µA

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Electrical Characteristics (continued)

Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference
purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LO GATE DRIVER
VOHL LO high-state voltage drop ILO = –100 mA, VOHL = VVCC –VLO 0.15 0.25 V
VOLL LO low-state voltage drop ILO = 100 mA, VOLL = VLO 0.1 0.17 V
LO rise time (10% to 90%) CLOAD = 4700 pF 25 ns
LO fall time (90% to 10%) CLOAD = 4700 pF 20 ns
VLO = 0 V, VVCC = 4.5 V 0.8 A
IOHL Peak LO source current
VLO = 0 V 2 A
VLO = VVCC = 4.5 V 1.8 A
IOLL Peak LO sink current
VLO = VVCC 3.2 A
SWITCHING CHARACTERISTICS
No load, 50% to 50% 50 80 115
tDLH LO fall to HO rise delay ns
No load, 50% to 50% (LM5122Z only) 50 80 145
tDHL HO fall to LO rise delay No load, 50% to 50% 60 80 105 ns
THERMAL
TSD Thermal shutdown Temperature rising 165 °C
Thermal shutdown hysteresis 25 °C

10 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

6.6 Typical Characteristics

5.00 6.00

5.00
4.00
HO PEAK CURRENT [A]

LO PEAK CURRENT [A]

4.00
3.00 SINK SINK
3.00
2.00 SOURCE SOURCE
2.00

1.00
VVIN = 12V 1.00
VSW = 0V VVIN = 12V
0.00 0.00
4 5 6 7 8 9 10 11 12 13 14 4 5 6 7 8 9 10 11 12 13 14
VBST - VSW [V] C001 VVCC [V] C001

Figure 1. HO Peak Current vs VBST - VSW Figure 2. LO Peak Current vs VVCC

100.00 100
90.00 95
80.00 90
tDHL
70.00 85
Dead-time [ns]

Dead-time [ns]
60.00 tDHL 80
50.00 75
40.00 70 tDLH
30.00 tDLH 65
VVIN = 12V
20.00 VSW = 12V 60
CLOAD=2600pF
10.00 1V to 1V 55
0.00 50
4 5 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 150
VVCC [V] C001 Temperature [ƒC] C001

Figure 3. Dead Time vs VVCC Figure 4. Dead Time vs Temperature

100.0 20
90.0
80.0
15
70.0 tDHL
Dead-time [ns]

ISHUTDOWN [PA]

60.0
50.0 10
40.0 tDLH
30.0 VVIN = 12V
5
20.0 VVCC = 7.6V
CLOAD=2600pF
10.0 1V to 1V
0.0 0
0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 150
VSW [V] C001 Temperature [ƒC] C001

Figure 5. Dead Time vs VSW Figure 6. ISHUTDOWN vs Temperature

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Typical Characteristics (continued)

8 8

No load

6 6

VVCC [V]
VVCC [V]

4 4

2 2

No load
0 0
0 10 20 30 40 50 60 70 80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
IVCC [mA] C001 VVIN [V] C001

Figure 7. VVCC vs IVCC Figure 8. VVCC vs VVIN

40 180 15

ACL=101, COMP unload ICSP

30 135

10
PHASE [°]
GAIN [dB]

ICSP, ICSN [PA]

PHASE
20 90 ICSN

10 45
5

0 GAIN 0

-10 -45 0
1000 10000 100000 1000000 10000000 -50 -25 0 25 50 75 100 125 150
FREQUENCY [Hz] C002 Temperature [ƒC] C001

Figure 9. Error Amplifier Gain and Phase Figure 10. ICSP, ICSN vs Temperature
vs Frequency
15.0 300
IBST = -70uA 280 VVIN=VSW=9V
BST Charging Current [PA]

260
240
10.0
VBST-SW [V]

220
200
180
5.0
160
140
120
0.0 100
4 9 14 19 -50 -25 0 25 50 75 100 125 150
VSW [V] C001 Temperature [ƒC] C001

Figure 11. VBST-SW vs VSW Figure 12. IBST vs Temperature

12 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Typical Characteristics (continued)

80 90
VVIN=VCSP
85

80
VCS-TH1 [mV]

VCS-TH1 [mV]
75 75

70

65

70 60
4 5 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 150
VVIN [V] C001 Temperature [ƒC] C001

Figure 13. VCS-TH1 vs VVIN Figure 14. VCS-TH1 vs Temperature

12.00
11.00
10.00
VSW = 12V
9.00
8.00
VBST-SW [V]

7.00
6.00
5.00 VSW = 9V
4.00
3.00
VVIN = VSW
2.00
IBST = -70uA
1.00
0.00
-50 -25 0 25 50 75 100 125 150
Temperature [ƒC] C001

Figure 15. VBST-SW vs Temperature

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

7 Detailed Description

7.1 Overview
The LM5122 wide input range synchronous boost controller features all of the functions necessary to implement
a highly efficient synchronous boost regulator. The regulator control method is based upon peak current mode
control. Peak current mode control provides inherent line feedforward and ease of loop compensation. This
highly integrated controller provides strong high-side and low-side N-channel MOSFET drivers with adaptive
dead-time control. The switching frequency is user programmable up to 1 MHz set by a single resistor or
synchronized to an external clock. The 180º-shifted clock output of the LM5122 enables easy multi-phase
configuration.
The control mode of high-side synchronous switch can be configured as either forced PWM (FPWM) or diode-
emulation mode. Fault protection features include cycle-by-cycle current limiting, hiccup mode over load
protection, thermal shutdown and remote shutdown capability by pulling down the UVLO pin. The UVLO input
enables the controller when the input voltage reaches a user selected threshold, and provides a tiny 9-μA
shutdown quiescent current when pulled low. The device is available in a 20 and 24-pin HTSSOP package
featuring an exposed pad to aid in thermal dissipation.

7.2 Functional Block Diagram

VIN

RS
LIN
CIN
VIN CSP CSN LM5122
10 uA

1.2 V
RUV2 STANDBY
-
+
+

VCC
-

UVLO A=10
CS VIN VCC
RUV1 AMP Regulator
0.4V/0.3V -
SHUTDOWN
+
SLOPE BST Charge Pump CVCC
DBST
RSLOPE
SLOPE
Generator 6 u 10
9
VSENSE1
VSLOPE =
RSLOPE u fSW
BST
CHF QH VOUT
1.2 V VSENSE2 CBST
-
COMP + HO
+ -
+ Level Shift
CCOMP RCOMP
750 mV
- ZCD threshold Diode Emulation SW COUT
FB
+
-

-
+ ERR C/L
AMP Comparator VCC
1.2 V + QL
LO
Adaptive
+
-

CSS PWM CLK PWM Timer

Comparator S Q
SS 10 uA

R Q
1.2 V
Skip Cycle RFB2
Comparator 30 uA
700 k 40 mV
20 mV
Hysteresis
- Restart 10 uA
MODE + -
+ Timer
RFB1
1.2 V + Diode CLK Clock Generator
100 k fCLK / 2 RES
- Emulation /SYNC Detector or 5 uA
Diode fCLK CRES
Emulation
Comparator OPT SYNCIN/RT SYNCOUT AGND PGND

RT

Copyright © 2017, Texas Instruments Incorporated

14 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)
The LM5122 features a dual level UVLO circuit. When the UVLO pin voltage is less than the 0.4-V UVLO
standby enable threshold, the LM5122 is in the shutdown mode with all functions disabled. The shutdown
comparator provides 0.1 V of hysteresis to avoid chatter during transition. If the UVLO pin voltage is greater than
0.4 V and below 1.2 V during power up, the controller is in standby mode with the VCC regulator operational and
no switching at the HO and LO outputs. This feature allows the UVLO pin to be used as a remote shutdown
function by pulling the UVLO pin down below the UVLO standby enable threshold with an external open collector
or open drain device.

VIN
UVLO Hysteresis
Current

UVLO
RUV2 Threshold
UVLO -
STANDBY
+

UVLO Standby
RUV1 Enable Threshold
-
STANDBY SHUTDOWN SHUTDOWN
+

Figure 16. UVLO Remote Standby and Shutdown Control

If the UVLO pin voltage is above the 1.2-V UVLO threshold and VCC voltage exceeds the VCC UV threshold, a
startup sequence begins. UVLO hysteresis is accomplished with an internal 10-μA current source that is switched
on or off into the impedance of the UVLO setpoint divider. When the UVLO pin voltage exceeds 1.2 V, the
current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below
the 1.2-V UVLO threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. In
addition to the UVLO hysteresis current source, a 5-μs deglitch filter on both rising and falling edge of UVLO
toggling helps preventing chatter upon power up or down.
An external UVLO setpoint voltage divider from the supply voltage to AGND is used to set the minimum input
operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater
than 1.2 V when the input voltage is in the desired operating range. The maximum voltage rating of the UVLO
pin is 15 V. If necessary, the UVLO pin can be clamped with an external zener diode. The UVLO pin should not
be left floating. The values of RUV1 and RUV2 can be determined from Equation 1 and Equation 2.
VHYS
RUV2 ª: º
10 $ ¬ ¼ (1)
1.2V u RUV2
RUV1 ª: º
VIN(STARTUP) 1.2V ¬ ¼ (2)
where
• VHYS is the desired UVLO hysteresis
• VIN(STARTUP) is the desired startup voltage of the regulator during turn-on.
Typical shutdown voltage during turn-off can be calculated as follows:
VIN(SHUTDOWN) VIN(STARTUP) VHYS [V] (3)

7.3.2 High Voltage VCC Regulator

The LM5122 contains an internal high voltage regulator that provides typical 7.6 V VCC bias supply for the
controller and N-channel MOSFET drivers. The input of VCC regulator, VIN, can be connected to an input
voltage source as high as 65 V. The VCC regulator turns on when the UVLO pin voltage is greater than 0.4 V.
When the input voltage is below the VCC setpoint level, the VCC output tracks VIN with a small dropout voltage.
The output of the VCC regulator is current limited at 50 mA minimum.

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Feature Description (continued)

Upon power-up, the VCC regulator sources current into the capacitor connected to the VCC pin. TI recommends
a capacitance range for the VCC capacitor of 1 μF to 47 μF, and capacitance is recommended to be at least 10
times greater than CBST value. When operating with a VIN voltage less than 6 V, the value of VCC capacitor
must be 4.7 µF or greater.
The internal power dissipation of the LM5122 device can be reduced by supplying VCC from an external supply.
If an external VCC bias supply exists and the voltage is greater than 9 V and below 14.5 V. The external VCC
bias supply can be applied to the VCC pin directly through a diode, as shown in Figure 17.

VCC External
VCC Supply

CVCC

Figure 17. External Bias Supply when 9 V < VEXT< 14.5 V

Shown in Figure 18 is a method to derive the VCC bias voltage with an additional winding on the boost inductor.
This circuit must be designed to raise the VCC voltage above VCC regulation voltage to shut off the internal VCC
regulator.
VCC

+
nuVIN
+
nuVOUT
+
nu(VOUT -VIN)

1:n
VIN VOUT

+ +

Figure 18. External Bias Supply using Transformer

The VCC regulator series pass transistor includes a diode between VCC and VIN that must not be fully forward
biased in normal operation, as shown in Figure 19. If the voltage of the external VCC bias supply is greater than
the VIN pin voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent
the external bias supply from passing current to the input supply through VCC. The need for the blocking diode
should be evaluated for all applications when the VCC is supplied by the external bias supply. Especially, when
the input power supply voltage is less than 4.5 V, the external VCC supply should be provided and the external
blocking diode is required.

16 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Feature Description (continued)

VIN

VIN
LM5122

External
VCC Supply
VCC

Figure 19. VIN Configuration when VVIN < VVCC

7.3.3 Oscillator
The LM5122 switching frequency is programmable by a single external resistor connected between the RT pin
and the AGND pin. The resistor should be located very close to the device and connected directly to the RT pin
and AGND pin. To set a desired switching frequency (fSW), the resistor value can be calculated from Equation 4.
9 u 109
RT ª: º
fSW ¬ ¼ (4)

7.3.4 Slope Compensation

For duty cycles greater than 50%, peak current mode regulators are subject to sub-harmonic oscillation. Sub-
harmonic oscillation is normally characterized by observing alternating wide and narrow duty cycles. This sub-
harmonic oscillation can be eliminated by a technique, which adds an artificial ramp, known as slope
compensation, to the sensed inductor current.

Additional slope

Sensed Inductor Current

tON = ILIN u RS u10

Figure 20. Slope Compensation

The amount of slope compensation is programmable by a single resistor connected between the SLOPE pin and
the AGND pin. The amount of slope compensation can be calculated as follows:
6 u 109
VSLOPE = u D' ª¬ V º¼
fSW u RSLOPE
where
VIN
D' 1
• VOUT (5)

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Feature Description (continued)

RSLOPE value can be determined from Equation 6 at minimum input voltage:
LIN u 6 u 109
RSLOPE ¬ª: ¼º
ªK u VOUT VIN(MIN) º u RS u 10
¬ ¼
where
• K=0.82~1 as a default (6)
From Equation 6, K can be calculated over the input range as follows:
§ LIN u 6 u 109 ·
K = ¨1 + ¸ u D'
¨ VIN u RS u 10 u RSLOPE ¹¸
©
where
VIN
D'
• VOUT (7)
In any case, K should be greater than at least 0.5. At higher switching frequency over 500 kHz, K factor is
recommended to be greater than or equal to 1 because the minimum on-time affects the amount of slope
compensation due to internal delays.
The sum of sensed inductor current and slope compensation should be less than COMP output high voltage
(VOH) for proper startup with load and proper current limit operation. This limits the minimum value of RSLOPE to
be:
5.7 u 109 § VIN MIN ·
RSLOPE ! u ¨ 1.2 ¸ ª: º
fSW ¨ VOUT ¸ ¬ ¼
© ¹
• This equation can be used in most cases
8 u 109
RSLOPE ! ª: º
fSW ¬ ¼
• Consider this conservative selection when VIN(MIN) < 5.5 V
The SLOPE pin cannot be left floating.

7.3.5 Error Amplifier

The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin
voltage and the internal precision 1.2-V reference. The output of the error amplifier is connected to the COMP pin
allowing the user to provide a Type 2 loop compensation network.
RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to achieve a stable voltage
loop. This network creates a pole at DC, a mid-band zero (fZ_EA) for phase boost, and a high frequency pole
(fP_EA). The minimum recommended value of RCOMP is 2 kΩ. See the Feedback Compensation section.
1
fZ _ EA ªHz º
2S u RCOMP u CCOMP ¬ ¼ (9)
1
fP_EA = ¬ªHz ¼º
§C u CHF ·
2S u RCOMP u ¨ COMP ¸
© CCOMP + CHF ¹ (10)

18 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Feature Description (continued)

7.3.6 PWM Comparator
The PWM comparator compares the sum of sensed inductor current and slope compensation ramp to the
voltage at the COMP pin through a 1.2-V internal COMP to PWM voltage drop, and terminates the present cycle
when the sum of sensed inductor current and slope compensation ramp is greater than VCOMP –1.2 V.
ILIN

RS

CSP CSN

+
-
CS A=10
AMP

RSLOPE
SLOPE VOUT
Generator

REF
+ RFB2
- + +
-
- FB
PWM
Error
Comparator 1.2 V Amplifier RCOMP CCOMP
COMP

RFB1
CHF (optional)
Type 2 Compensation Components

Figure 21. Feedback Configuration and PWM Comparator

7.3.7 Soft-Start
The soft-start feature helps the regulator to gradually reach the steady state operating point, thus reducing start-
up stresses and surges. The LM5122 regulates the FB pin to the SS pin voltage or the internal 1.2-V reference,
whichever is lower. The internal 10-μA soft-start current source gradually increases the voltage on an external
soft-start capacitor connected to the SS pin. This results in a gradual rise of the output voltage starting from the
input voltage level to the target output voltage. Soft-start time (tSS) which varies by the input supply voltage and is
calculated from Equation 11.
CSS u 1.2V § VIN ·
tSS u ¨1 ¸ ªsec º¼
10 $ © 9OUT ¹ ¬ (11)
When the UVLO pin voltage is greater than the 1.2-V UVLO threshold and VCC voltage exceeds the VCC UV
threshold, an internal 10-μA soft-start current source turns on. At the beginning of this soft-start sequence, allow
VSS to fall down below 25 mV using the internal SS pulldown switch. The SS pin can be pulled down by external
switch to stop switching, but pulling up to enable switching is not allowed. The start-up delay (see Figure 22)
must be long enough for high-side boot capacitor to be fully charged up by internal BST charge pump.
The value of CSS must be large enough to charge the output capacitor during soft-start time.
10 $ u 9OUT &OUT
CSS ! u ªF º
1.2V IOUT ¬ ¼ (12)

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Feature Description (continued)

Standby

Shut down
1.2V
UVLO 0.4V

VCC UV threshold

VCC
Startup delay

10µA
1.2V current
source
SS

LO

HO-SW

VIN

tSS
VOUT
Figure 22. Startup Sequence

7.3.8 HO and LO Drivers

The LM5122 contains strong N-channel MOSFET gate drivers and an associated high-side level shifter to drive
the external N-channel MOSFET switches. The high-side gate driver works in conjunction with an external boot
diode DBST, and bootstrap capacitor CBST. During the on-time of the low-side N-channel MOSFET driver, the SW
pin voltage is approximately 0 V and the CBST is charged from VCC through the DBST. TI recommends a 0.1-μF
or larger ceramic capacitor, connected with short traces between the BST and SW pin.
The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs
are never enabled at the same time. When the controller commands LO to be enabled, the adaptive dead-time
logic first disables HO and waits for HO-SW voltage to drop. LO is then enabled after a small delay (HO fall to
LO rise delay). Similarly, the HO turnon is delayed until the LO voltage has discharged. HO is then enabled after
a small delay (LO fall to HO rise delay). This technique insures adequate dead-time for any size N-channel
MOSFET device, especially when VCC is supplied by a higher external voltage source. Be careful when adding
series gate resistors, as this may decrease the effective dead-time.
Exercise care when selecting the N-channel MOSFET devices threshold voltage, especially if the VIN voltage
range is below the VCC regulation level or a bypass operation is required. If the bypass operation is required,
especially when output voltage is less than 12 V, a logic level device should be selected for the high-side N-
channel MOSFET. During start-up at low input voltages, the low-side N-channel MOSFET switch’s gate plateau
voltage must be sufficient to completely enhance the N-channel MOSFET device. If the low-side N-channel
MOSFET drive voltage is lower than the low-side N-channel MOSFET device gate plateau voltage during startup,
the regulator may not start up properly and it may stick at the maximum duty cycle in a high power dissipation
state. This condition can be avoided by selecting a lower threshold N-channel MOSFET switch or by increasing
VIN(STARTUP) with the UVLO pin voltage programming.

20 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Feature Description (continued)

7.3.9 Bypass Operation (VOUT = VIN)
The LM5122 allows 100% duty cycle operation for the high-side synchronous switch when the input supply
voltage is equal to or greater than the target output voltage. An internal 200 μA BST charge pump maintains
sufficient high-side driver supply voltage to keep the high-side N-channel MOSFET switch on without the power
stage switching. The internal BST charge pump is enabled when the UVLO pin voltage is greater than 1.2 V and
the VCC voltage exceeds the VCC UV threshold. The BST charge pump generates 5.3-V minimum BST to SW
voltage when SW voltage is greater than 9 V. This requires minimum 9 V boost output voltage for proper bypass
operation. The leakage current of the boot diode should be always less than the BST charge pump sourcing
current to maintain a sufficient driver supply voltage at both low and high temperatures. Forced-PWM mode is
the recommended PWM configuration when bypass operation is required.

7.3.10 Cycle-by-Cycle Current Limit

The LM5122 features a peak cycle-by-cycle current limit function. If the CSP to CSN voltage exceeds the 75-mV
cycle-by-cycle current limit threshold, the current limit comparator immediately terminates the LO output.
For the case where the inductor current may overshoot, such as inductor saturation, the current limit comparator
skips pulses until the current has decayed below the current limit threshold. Peak inductor current in current limit
can be calculated as follows:
75mV
IPEAK(CL) ªA º
RS ¬ ¼ (13)

7.3.11 Clock Synchronization

The SYNCIN/RT pin can be used to synchronize the internal oscillator to an external clock. A positive going
synchronization clock at the RT pin must exceed the RT sync rising threshold and negative going
synchronization clock at RT pin must exceed the RT sync falling threshold to trip the internal synchronization
pulse detector.
In Master1 mode, two types of configurations are allowed for clock synchronization. With the configuration in
Figure 23, the frequency of the external synchronization pulse is recommended to be within +40% and –20% of
the internal oscillator frequency programmed by the RT resistor. For example, 900-kHz external synchronization
clock and 20-kΩ RT resistor are required for 450-kHz switching in master1 mode. The internal oscillator can be
synchronized by AC coupling a positive edge into the RT pin. A 5-V amplitude pulse signal coupled through 100-
pF capacitor is a good starting point. The RT resistor is always required with AC coupling capacitor with the
Figure 23 configuration, whether the oscillator is free running or externally synchronized.
Care should be taken to ensure that the RT pin voltage does not go below –0.3 V at the falling edge of the
external pulse. This may limit the duty cycle of external synchronization pulse. There is approximately 400-ns
delay from the rising edge of the external pulse to the rising edge of LO.

fSYNC

SYNCIN/RT
RT
LM5122

Figure 23. Oscillator Synchronization Through AC Coupling in Master1 Mode

With the configuration in Figure 24, the internal oscillator can be synchronized by connecting the external
synchronization clock into the RT pin through RT resistor with free of the duty cycle limit. The output stage of the
external clock source should be a low impedance totem-pole structure. Default logic state of fSYNC must be low.

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Feature Description (continued)

SYNCIN/RT
CSYNC RT
LM5122

Figure 24. Oscillator Synchronization Through a Resistor in Master1 Mode

In master2 and slave modes, this external synchronization clock should be directly connected to the RT pin and
always provided continuously. The internal oscillator frequency can be either of two times faster than switching
frequency or the same as the switching frequency by configuring the combination of FB and OPT pins (see
Table 1).

7.3.12 Maximum Duty Cycle

When operating with a high PWM duty cycle, the low-side N-channel MOSFET device is forced off each cycle.
This forced LO off-time limits the maximum duty cycle of the controller. When designing a boost regulator with
high switching frequency and high duty-cycle requirements, check the required maximum duty cycle. The
minimum input supply voltage that can achieve the target output voltage is estimated from Equation 14 or
Equation 15.
Use Equation 14 if VVCC is greater than 5.5 V or VVIN is greater than 6 V. For low voltage applications that do not
satisfy either of these conditions use Equation 15.
VIN MIN fSW u VOUT u 400ns margin [V]
(14)
VIN MIN fSW u VOUT u 750ns margin [V]
(15)
In normal operation, about 100 ns of margin is recommended.

7.3.13 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power shutdown
mode, disabling the output drivers, disconnection switch and the VCC regulator. This feature is designed to
prevent overheating and destroying the device.

7.4 Device Functional Modes

7.4.1 MODE Control (Forced-PWM Mode and Diode-Emulation Mode)
A fully synchronous boost regulator implemented with a high-side switch rather than a diode has the capability to
sink current from the output in certain conditions such as light load, overvoltage or load transient. The LM5122
can be configured to operate in either forced-PWM mode (FPWM) or diode emulation mode.
In FPWM, reverse current flow in high-side N-channel MOSFET switch is allowed, and the inductor current
conducts continuously at light or no load conditions. The benefit of the forced PWM mode is fast light load to
heavy load transient response and constant frequency operation at light or no load conditions. To enable FPWM,
connect the MODE pin to VCC or tie to a voltage greater than 1.2 V. In FPWM, reverse current flow is not
limited.
In diode-emulation mode, current flow in the high-side switch is only permitted in one direction (source to drain).
Turnon of the high-side switch is allowed if CSP to CSN voltage is greater than 7 mV rising threshold of zero
current detection during low-side switch on-time. If CSP to CSN voltage is less than 6-mV falling threshold of
zero current detection during high-side switch on-time, reverse current flow from output to input through the high-
side N-channel MOSFET switch is prevented and discontinuous conduction mode of operation is enabled by
latching off the high-side N-channel MOSFET switch for the remainder of the PWM cycle. A benefit of the diode
emulation is lower power loss at light load conditions.
22 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Device Functional Modes (continued)

1.2 V
COMP + -
40mV
Hysteresis

1.2V - SkipCycle
+
700k
20mV
Default
150mV Skip Cycle
MODE + -
Comparator

1.2V Diode
100k Emulation
+
-

Figure 25. MODE Selection

During start-up the LM5122 forces diode emulation, for start-up into a pre-biased load, while the SS pin voltage
is less than 1.2 V. Forced diode emulation is terminated by a pulse from PWM comparator when SS is greater
than 1.2 V. If there are no LO pulses during the soft-start period, a 350-ns one-shot LO pulse is forced at the end
of soft start to help charge the boot strap capacitor. Due to the internal current sense delay, configuring the
LM5122 for diode emulation mode must be carefully evaluated if the inductor current ripple ratio is high and
when operating at very high switching frequency. The transient performance during full load to no load in FPWM
mode should also be verified.

7.4.2 MODE Control (Skip-Cycle Mode and Pulse-Skipping Mode)

Light load efficiency of the regulator typically drops as the losses associated with switching and bias currents of
the converter become a significant percentage of the total power delivered to the load. In order to increase the
light load efficiency the LM5122 provides two types of light load operation in diode-emulation mode.
The skip-cycle mode integrated into the LM5122 controller reduces switching losses and improves efficiency at
light-load condition by reducing the average switching frequency. Skip-cycle operation is achieved by the skip
cycle comparator. When a light-load condition occurs, the COMP pin voltage naturally decreases, reducing the
peak current delivered by the regulator. During COMP voltage falling, the skip-cycle threshold is defined as
VMODE –20 mV and during COMP voltage rising, it is defined as VMODE +20 mV. There is 40mV of internal
hysteresis in the skip cycle comparator.
When the voltage at PWM comparator input falls below VMODE –20 mV, both HO and LO outputs are disabled.
The controller continues to skip switching cycles until the voltage at PWM comparator input increases to VMODE +
20 mV, demanding more inductor current. The number of cycles skipped depends upon the load and the
response time of the frequency compensation network. The internal hysteresis of skip-cycle comparator helps to
produce a long skip cycle interval followed by a short burst of pulses. An internal 700-kΩ pullup and 100-kΩ
pulldown resistor sets the MODE pin to 0.15 V as a default. Because the peak current limit threshold is set to
750 mV, the default skip threshold corresponds to approximately 17% of the peak level. In practice the skip level
is lower due to the added slope compensation. By adding an external pullup resistor to SLOPE or VCC pin or
adding an external pulldown resistor to the ground, the skip cycle threshold can be programmed. Because the
skip cycle comparator monitors the PWM comparator input which is proportional to the COMP voltage, skip-cycle
operation is not recommended when the bypass operation is required.
Conventional pulse-skipping operation can be achieved by connecting the MODE pin to ground. The negative
20-mV offset at the positive input of skip-cycle comparator ensures the skip-cycle comparator does not trigger in
normal operation. At light or no load conditions, the LM5122 skips LO pulses if the pulse width required by the
regulator is less than the minimum LO on-time of the device. Pulse skipping appears as a random behavior as
the error amplifier struggles to find an average pulse width for LO in order to maintain regulation at light or no
load conditions.

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Device Functional Modes (continued)

7.4.3 Hiccup-Mode Overload Protection
If cycle-by-cycle current limit is reached during any cycle, a 30-μA current is sourced into the RES capacitor for
the remainder of the clock cycle. If the RES capacitor voltage exceeds the 1.2-V restart threshold, a hiccup mode
over load protection sequence is initiated; The SS capacitor is discharged to GND, both LO and HO outputs are
disabled, the voltage on the RES capacitor is ramped up and down between 2-V hiccup counter lower threshold
and 4-V hiccup counter upper threshold eight times by 10-μA charge and 5-μA discharge currents. After the
eighth cycles, the SS capacitor is released and charged by the 10-μA soft-start current again. If a 3-V zener
diode is connected in parallel with the RES capacitor, the regulator enters into the hiccup-mode off mode and
then never restarts until UVLO shutdown is cycled. Connect RES pin directly to the AGND when the hiccup-
mode operation is not used.
IRES = 10µA IRES = -5µA

4V
2.0V
1.2V
Count to Eight

RES IRES = 30µA

Restart Delay tRD

SS Hiccup Mode Off-time tRES

HO

LO

Figure 26. Hiccup Mode Overload Protection

7.4.4 Slave Mode and SYNCOUT

The LM5122 is designed to easily implement dual (or higher) phase boost converters by configuring one
controller as a master and all others as slaves. Slave mode is activated by connecting the FB pin to the VCC pin.
The FB pin is sampled during initial power-on and if a slave configuration is detected, the state is latched. In the
slave mode, the error amplifier is disabled and has a high impedance output, 10-μA hiccup-mode off-time
charging current and 5-μA hiccup-mode off-time discharging current are disabled, 5-μA normal-state RES
discharging current and 10-μA soft-start charging current are disabled, 30 μA fault-state RES charging current is
changed to 35 μA. 10-μA UVLO hysteresis current source works the same as master mode. Also, in slave mode,
the internal oscillator is disabled, and an external synchronization clock is required.
The SYNCOUT function provides a 180° phase shifted clock output, enabling easy dual-phase interleaved
configuration. By directly connecting master1 SYNCOUT to slave1 SYNCIN, the switching frequency of slave
controller is synchronized to the master controller with 180º phase shift. In master mode, if OPT pin is tied to
GND, an internal oscillator clock divided by two with 50% duty cycle is provided to achieve an 180º phase-shifted
operation in two phase interleaved configuration. Switching frequency of master controller is half of the external
clock frequency with this configuration. If the OPT pin voltage is higher than 2.7-V OPT threshold or the pin is
tied to VCC, SYNCOUT is disabled and the switching frequency of master controller becomes the same as the
external clock frequency. An external synchronization clock should be always provided and directly connected to
SYNCIN for master2, slave1 and slave2 configurations. See Interleaved Boost Configuration for detailed
information.

Table 1. LM5122 Multiphase Configuration

MULTIPHASE ERROR
FB OPT SWITCHING FREQUENCY SYNCOUT
CONFIGURATION AMPLIFIER
Master1 Feedback GND Enable fSYNC/2, Free running with RT resistor fSYNC/2, fSW –180º
Slave1 VCC GND Disable fSYNC, No free running Disable
Master2 Feedback VCC Enable fSYNC, No free running Disable
Slave2 VCC VCC Disable fSYNC/2, No free running fSYNC/2, fSW –180º

24 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5122 device is a step-up dc-dc converter. The device is typically used to convert a lower dc voltage to a
higher dc voltage. Use the following design procedure to select component values for the LM5122 device.
Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.

8.1.1 Feedback Compensation

The open loop response of a boost regulator is defined as the product of modulator transfer function and
feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator
gain and feedback gain. The modulator transfer function of a current mode boost regulator including a power
stage transfer function with an embedded current loop can be simplified as one pole, one zero, and one right-
half-plane (RHP) zero system.
Modulator transfer function is defined as follows:
§ s · § s ·
¨1 ¸ u ¨1 ¸
VÖ OUT (s) ¨ ¸ ¨
&Z _ ESR ¹ © &Z _ RHP ¸
AM u © ¹
VÖ COMP (s) § s ·
¨1 ¸
¨ &P _ LF ¸
© ¹
where
RLOAD D'
AM (Modulator DC gain) u
• RS _ EQ u A S 2
2
&P _ LF /RDG SROH
• RLOAD u COUT
1
&Z _ ESR (65 ]HUR
• RESR u COUT
RLOAD u (D' )2
&Z _ RHP 5+3 ]HUR
• LIN _ EQ
LIN RS
LIN _ EQ , RS _ EQ
• n n
• n is the number of the phase. (16)
If the equivalent series resistance (ESR) of COUT (RESR) is small enough and the RHP zero frequency is far away
from the target crossover frequency, the modulator transfer function can be further simplified to one pole system
and the voltage loop can be closed with only two loop compensation components, RCOMP and CCOMP, leaving a
single pole response at the crossover frequency. A single pole response at the crossover frequency yields a very
stable loop with 90 degrees of phase margin.
The feedback transfer function includes the feedback resistor divider and loop compensation of the error
amplifier. RCOMP, CCOMP, and optional CHF configure the error amplifier gain and phase characteristics, create a
pole at origin, a low frequency zero and a high frequency pole.
Feedback transfer function is defined as follows:

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Application Information (continued)

s
1
VÖ COMP &Z _ EA
AFB u
VÖ
OUT § s ·
s u ¨1 ¸
¨ & ¸
© P _ EA ¹
where
1
AFB (Feedback DC gain)
• RFB2 u CCOMP CHF
1
&Z _ EA /RZ IUHTXHQF\ ]HUR
• RCOMP u CCOMP
1
&P _ EA +LJK IUHTXHQF\ SROH
• RCOMP u CHF (17)
The pole at the origin minimizes the output steady state error. Place the low frequency zero to cancel the load
pole of the modulator. The high frequency pole can be used to cancel the zero created by the output capacitor
ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an order of
magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at the
crossover frequency. The high frequency pole should be placed beyond the crossover frequency since the
addition of CHF adds a pole in the feedback transfer function.
The crossover frequency (open loop bandwidth) is usually selected between one twentieth and one fifth of the
fSW. In a simplified formula, the estimated crossover frequency can be defined as:
RCOMP
fCROSS u D' [Hz]
S u RS _ EQ u RFB2 u A S u COUT

where
VIN
D'
• VOUT (18)
For higher crossover frequency, RCOMP can be increased, while proportionally decreasing CCOMP. Conversely,
decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero
frequency in the feedback transfer function.
The modulator transfer function can be measured by a network analyzer and the feedback transfer function can
be configured for the desired open loop transfer function. If the network analyzer is not available, step load
transient tests can be performed to verify acceptable performance. The step load goal is minimum
overshoot/undershoot with a damped response.

8.1.2 Sub-Harmonic Oscillation

Peak current mode regulator can exhibit unstable behavior when operating above 50% duty cycle. This behavior
is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin.
Sub-harmonic oscillation can be prevented by adding an additional slope voltage ramp (slope compensation) on
top of the sensed inductor current. By choosing K ≥ 0.82~1, the sub-harmonic oscillation is eliminated even with
wide varying input voltage.
In time-domain analysis, the steady-state inductor current starting from an initial point returns to the same point.
When the amplitude of an end cycle current error (dI1) caused by an initial perturbation (dI0) is less than the
amplitude of dI0 or dI1/dI0 > –1, the perturbation naturally disappears after a few cycles. When dl1/dl0 < –1, the
initial perturbation no longer disappear, it results in sub-harmonic oscillation in steady-state.

26 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Application Information (continued)

Steady-State
Inductor Current

dI0

tON
dI1

Inductor Current with

Initial Perturbation

Figure 27. Effect of Initial Perturbation when dl1/dl0 < -1

dI1/dI0 can be calculated as:

dI1 1
1
dI0 K (19)
The relationship between dI1/dI0 and K factor is illustrated graphically in Figure 28.

Figure 28. dl1/dl0 vs K Factor

The absolute minimum value of K is 0.5. When K < 0.5, the amplitude of dl1 is greater than the amplitude of dl0
and any initial perturbation results in sub-harmonic oscillation. If K = 1, any initial perturbation is removed in one
switching cycle. This is known as one-cycle damping. When –1 < dl1/dl0 < 0, any initial perturbationis under-
damped. Any perturbation is over-damped when 0 < dl1/dl0 < 1.
In the frequency-domain, Q, the quality factor of sampling gain term in modulator transfer function, is used to
predict the tendency for sub-harmonic oscillation, which is defined as:
1
Q
S K 0.5 (20)
The relationship between Q and K factor is shown in Figure 29.

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Application Information (continued)

Figure 29. Sampling Gain Q vs K Factor

The recommended absolute minimum value of K is 0.5. High gain peaking when K is less than 0.5 results sub-
harmonic oscillation at fSW/2. A higher value of K factor may introduce additional phase shift near the crossover
frequency, but has the benefit of reducing noise susceptibility in current loop. The maximum allowable value of K
factor can be calculated by the maximum crossover frequency equation in frequency analysis formulas in
Table 2.

Table 2. Boost Regulator Frequency Analysis

SIMPLIFIED FORMULA COMPREHENSIVE FORMULA (1)

§ s · § s · § s · § s ·
¨1 ¸ u ¨1 ¸ ¨1 ¸ u ¨1 ¸
MODULATOR TRANSER VÖ OUT (s) ¨ ZZ _ ESR ¸ ¨ ZZ _ RHP ¸ VÖ OUT s ¨ &ZESR ¸ ¨© &ZRHP ¸¹
AM u © ¹ © ¹ AM u © ¹
FUNCTION Ö
V (s) § s · VÖ COMP s § s · § s · § s s2 ·
COMP
¨1 ¸ ¨1 ¸ u ¨1 ¸ u ¨1 ¸
¨ ZP _ LF ¸¹ ¨ &P_LF ¸ ¨ & ¸ ¨ &P_HF &n2 ¸¹
© © ¹ © p _ ESR ¹ ©

(2) RLOAD D'

Modulator DC gain AM u
RS _ EQ u A S 2

(2) RLOAD u (D')2

RHP zero &Z _ RHP
LIN _ EQ

1 1
ESR zero &Z _ ESR &Z _ ESR
RESR u COUT RESR1 u COUT1

1
ESR pole Not considered &P _ ESR
RESR1 u COUT1 / /COUT2

2
Dominant load pole &P _ LF
RLOAD u COUT

fSW
&P _ HF
K 0.5
Sampled gain inductor pole Not considered
or
&P _ HF 4 u &n

1
Quality factor Not considered Q
S K 0.5

(1) Comprehensive equation includes an inductor pole and a gain peaking at fSW / 2, which is caused by sampling effect of the current
mode control. Also, it assumes that a ceramic capacitor COUT2 (No ESR) is connected in parallel with COUT1. RESR1 represents ESR of
COUT1.
LIN RS R VOUT
L R LOAD
(2) With multiphase configuration, IN _ EQ n , S _ EQ n , IOUT of each phase u n , and COUT = COUT of each phase x n, where n =
number of phases. As is the current sense amplifier gain.
28 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Application Information (continued)

Table 2. Boost Regulator Frequency Analysis (continued)
SIMPLIFIED FORMULA COMPREHENSIVE FORMULA (1)
&SW
&n S u ISW
2
Sub-harmonic double pole Not considered or
fSW
fn
2

§ LIN u 6 u 109 ·
K factor K=1 K ¨1 ¸ u D'
¨ VIN u RS u 10 u RSLOPE ¸
© ¹
s
1
FEEDBACK TRANSFER VÖ COMP (s) &Z _ EA
AFB u
FUNCTION VÖ OUT(s) § s ·
s u ¨1 ¸
¨ &P _ EA ¸
© ¹

1
Feedback DC gain AFB
RFB2 u (CCOMP CHF )

RCOMP
Mid-band Gain AFB _ MID
RFB2

1
Low frequency zero &Z _ EA
RCOMP u CCOMP

1 1
High frequency pole &P _ EA &P _ EA
RCOMP u CHF RCOMP u CCHF / /CCOMP

§ s · § s · s § s · § s · s
¨1 ¸ u ¨1 ¸ 1 ¨1 ¸ u ¨1 ¸ 1
¨ &Z _ ESR ¸ ¨ &Z _ RHP ¸ &Z _ EA ¨ &Z _ ESR ¸¹ ¨© &Z _ RHP ¸¹
AM u AFB u © ¹ © ¹u © &Z _ EA
OPEN LOOP RESPONSE T s T s AM u AFB u u
§ s · § s · § s · § s · § s s2 · § s ·
¨1 ¸ s u ¨1 ¸ ¨1 ¸ u ¨1 ¸ u ¨1 ¸ s u ¨1 ¸
¨ &P _ LF ¸¹ ¨ &P _ EA ¸ ¨ &P _ LF ¸¹ ¨© &p _ ESR ¸¹ ¨© &PHF &n2 ¸¹ ¨ &P _ EA ¸
© © ¹ © © ¹

Crossover frequency (3) fCROSS

RCOMP
u D' Use graphic tool
(Open loop band width) S u RS _ EQ u RFB2 u A S u COUT

fSW §
fCROSS _MAX u ¨ 1 4 u Q2 1 ·¸
4uQ © ¹
Maximum cross over fSW &Z _RHP or
fCROSS _MAX or whichever is smaller
frequency (4) 5 2u Su 4 &Z _ RHP
2u Su 4
, whichever is smaller
&Z _ RHP RLOAD u COUT VIN
f CCOMP D'
(3) Assuming &Z _ EA &P _ LF, &P _ EA &Z _ ESR, CROSS 2 u S u 10 , 4 u RCOMP , and VOUT .
(4) The frequency at which 45° phase shift occurs in modulator phase characteristics.

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

8.1.3 Interleaved Boost Configuration

Interleaved operation offers many advantages in single output, high current applications such as higher
efficiency, lower component stresses and reduced input and output ripple. For dual phase interleaved operation,
the output power path is split reducing the input current in each phase by one-half. Ripple currents in the input
and output capacitors are reduced significantly since each channel operates 180 degrees out of phase from the
other. Shown in Figure 30 is a normalized (IRMS/IOUT) output capacitor ripple current vs duty cycle for both a
single phase and dual phase boost converter, where IRMS is the output current ripple RMS.

Figure 30. Normalized Output Capacitor RMS Ripple Current

To configure for dual phase interleaved operation, configure one device as a master and configure the other
device in slave mode by connecting FB to VCC. Also connect COMP, UVLO, RES, SS and SYNCOUT on the
master side to COMP, UVLO, RES, SS and SYNCIN on slave side, respectively. The compensation network is
connected between master FB and the common COMP connection. The output capacitors of the two power
stages are connected together at the common output.
VSUPPLY VOUT

CSN VCC BST SW

CSP LO
VIN
HO
UVLO
SLOPE
RES
OPT
SS
SYNCIN/RT
SYNCOUT
FB
COMP

VSUPPLY MASTER

CSN VCC BST SW

CSP
LO
VIN
HO
COMP
SLOPE
SYNCIN/RT
OPT
SS
VCC
RES
FB
UVLO

SLAVE
Figure 31. Dual Phase Interleaved Boost Configuration
30 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

Shown in Figure 32 is a dual phase timing diagram. The 180° phase shift is realized by connecting SYNCOUT on
the master side to the SYNCIN on the slave side.

fSYNC

Free running when no

SYNCIN(MASTER)
external synchronization.
GND

Optional fSYNC
CSYNC Master Internal
SYNCIN/RT CLK(MASTER)
(5VPP)
SYNCOUT
RT OPT=GND
Duty cycle of fSYNC SW(MASTER)
Should be controlled
for RT not to go below GND Slave SYNCOUT(MASTER)
SYNCIN/RT SYNCIN(SLAVE)
(50%Duty-cycle)
OPT=GND
Internal
CLK(SLAVE)

SW(SLAVE)

Figure 32. Dual Phase Configuration and Timing Diagram

Each channel is synchronized by an individual external clock in Figure 33. The SYNCOUT pin is used in
Figure 34 requiring only one external clock source. A 50% duty cycle of external synchronization pulse should be
always provided with this daisy chain configuration.
Current sharing between phases is achieved by sharing one error amplifier output of the master controller with
the 3 slave controllers. Resistor sensing is a preferred method of current sensing to accurately balance the
phase currents.
fSYNC should be always provided
(5VPP) Master
SYNCIN/RT
fSYNC1 OPT=VCC
fSYNC1
SYNCIN_MASTER
Slave1
SYNCIN/RT fSYNC2
fSYNC2 OPT=GND SYNCIN_SLAVE1

fSYNC3
Slave2 SYNCIN_SLAVE2
SYNCIN/RT
fSYNC3 OPT=GND fSYNC4
SYNCIN_SLAVE3

Slave3
SYNCIN/RT
fSYNC4 OPT=GND

Figure 33. 4-Phase Timing Diagram Individual Clock

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 31

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Master
fSYNC should be always provided SYNCIN
SYNCOUT
(5VPP) RT
OPT=GND
fSYNC
D QZ
fSYNC
Slave1
Q SYNCIN SYNCIN_MASTER

OPT=GND
SYNCIN_SLAVE1
Slave2
SYNCIN
RT SYNCOUT
OPT=VCC SYNCIN_SLAVE2

Slave3 SYNCIN_SLAVE3
SYNCIN

OPT=GND

Figure 34. 4-Phase Timing Diagram Daisy Chain

8.1.4 DCR Sensing

For the applications requiring lowest cost with minimum conduction loss, inductor DC resistance (DCR) is used to
sense the inductor current rather than using a sense resistor. Shown in Figure 35 is a DCR sensing configuration
using two DCR sensing resistors and one capacitor.
VOUT

LIN RDCR

VIN
+

+
RCSP

CDCR RCSN

SW HO LO
CSN
CSP

LM5122

Figure 35. DCR Sensing

RCSN and CDCR selection must meet Equation 21 because this indirect current sensing method requires a time
constant matching. CDCR is usually selected to be in the range of 0.1 µF to 2.2 µF.
LIN
CDCR u RCSN
RDCR (21)
Smaller value of RCSN minimizes the voltage drop caused by CSN bias current, but increases the dynamic power
dissipation of RCSN. The DC voltage drop of RCSN can be compensated by selecting the same value of RCSP, but
the gain of current amplifier, which is typically 10, is affected by adding RCSP. The gain of current amplifier with
the DCR sensing network can be determined as:
A CS _ DCR 12.5 k: / (1.25 k: RCSP ) (22)
Due to the reduced accuracy of DCR sensing, TI recommends FPWM operation when DCR sensing is used.

32 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

8.1.5 Output Overvoltage Protection

Output overvoltage protection can be achieved by adding a simple external circuit. The output overvoltage
protection circuit shown in Figure 36 shuts down the LM5122 when the output voltage exceeds the overvoltage
threshold set by the zener diode.

VOUT

LM5122
UVLO

Figure 36. Output Overvoltage Protection

8.1.6 SEPIC Converter Simplified Schematic

VSUPPLY VOUT

LO HO
LM5122
CSN FB
CSP COMP

VIN
RES
SYNCOUT SS
OPT
UVLO
PGND
SLOPE
AGND
SYNCIN/RT

MODE VCC BST SW

Figure 37. Sepic Converter Simplified Schematic

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 33

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

8.1.7 Non-Isolated Synchronous Flyback Converter Simplified Schematic

VSUPPLY 9V ~ 36V VOUT 12V
744851101

COUPLED
+
INDUCTOR

LO HO
LM5122
CSN FB
CSP COMP

VIN
RES
SYNCOUT SS
OPT
UVLO
PGND
SLOPE
AGND
SYNCIN/RT

MODE VCC BST SW

Figure 38. Non-Isolated Synchronous Flyback Converter Simplified Schematic

8.1.8 Negative to Positive Conversion

+VOUT

+
Load
-VIN -VIN
VCC BST SW
-VIN
LO
CSN HO
CSP COMP
VIN FB
UVLO RES
SLOPE SS
SYNCIN/RT MODE
SYNCOUT PGND -VIN -VIN
AGND
LM5122 OPT -VIN

-VIN -VIN
Copyright © 2016, Texas Instruments Incorporated

Figure 39. Negative to Positive Converter Simplified Schematic

34 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

8.2 Typical Application

Figure 40. Single Phase Example Schematic

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 35

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

Typical Application (continued)

8.2.1 Design Requirements

DESIGN PARAMETERS VALUE

Output voltage (VOUT) 24 V
Full load current (IOUT) 4.5 A
Output Power 108 W
Minimum input voltage (VIN(MIN)) 9V
Typical input voltage (VIN(TYP)) 12 V
Maximum input voltage (VIN(MAX)) 20 V
Switching frequency (fSW) 250 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5122 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Timing Resistor RT

Generally, higher frequency applications are smaller but have higher losses. Operation at 250 kHz is selected for
this example as a reasonable compromise between small size and high-efficiency. The value of RT for 250 kHz
switching frequency is calculated as follows:
9 u 109 9 u 109
RT 36.0 k:
fSW 250 kHz (23)
A standard value of 36.5 kΩ is chosen for RT.

8.2.2.3 UVLO Divider RUV2, RUV1

The desired startup voltage and the hysteresis are set by the voltage divider RUV2, RUV1. The UVLO shutdown
voltage should be high enough to enhance the low-side N-channel MOSFET switch fully. For this design, the
startup voltage is set to 8.7 V which is 0.3 V below VIN(MIN). VHYS is set to 0.5 V. This results 8.2 V of
VIN(SHUTDOWN). The values of RUV2, RUV1 are calculated as follows:
VHYS 0.5 V
RUV2 50 k:
IHYS 10 PA (24)
1.2V u RUV2 1.2V u 50 k:
RUV1 8 k:
VIN(STARTUP) 1.2V 8.7V 1.2V (25)
A standard value of 49.9 kΩ is selected for RUV2. RUV1 is selected to be a standard value of 8.06 kΩ.

36 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

8.2.2.4 Input Inductor LIN

The inductor ripple current is typically set between 20% and 40% of the full load current, known as a good
compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor
size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this
example, a ripple ratio (RR) of 0.25, 25% of the input current was chosen. Knowing the switching frequency and
the typical output voltage, the inductor value can be calculated as follows:
VIN 1 § VIN · 12V 1 § 12V ·
LIN u u ¨1 ¸ u u ¨1 10.7 +
IIN u RR fSW © VOUT ¹ 108W 250 kHz © 24V ¸¹
u 0.25
12V (26)
The closest standard value of 10 μH was chosen for LIN.
The saturation current rating of inductor should be greater than the peak inductor current, which is calculated at
the minimum input voltage and full load. 8.7 V startup voltage is used conservatively.
1 VIN § VIN · 24V u 4.5A 1 8.7V § 8.7V ·
IPEAK IIN u u ¨1 ¸ u u 1 13.5 A
2 LIN u fSW © VOUT ¹ 8.7V 2 10 + u N+] ©¨ 9 ¹¸ (27)

8.2.2.5 Current Sense Resistor RS

The maximum peak input current capability should be 20~50% higher than the required peak current at low input
voltage and full load, accounting for tolerances. For this example, 40% is margin is chosen.
VCS TH1 75 mV
RS 3.97 m:
IPEAK(CL) 13.5 A u 1.4 (28)
A closest standard value of 4 mΩ is selected for RS. The maximum power loss of RS is calculated as follows.
PLOSS(RS) I2R (13.5 A u 1.4)2 u 4 m: 1.43 W (29)

8.2.2.6 Current Sense Filter RCSFP, RCSFN, CCS

The current sense filter is optional. 100 pF of CCS and 100 Ω of RCSFP, RCSFN are normal recommendations.
Because CSP and CSN pins are high impedance, CCS should be placed physically as close to the device.
VIN RS

+
RCSFP

RCSFN

CSN
CCS LM5122
CSP

Figure 41. Current Sense Filter

8.2.2.7 Slope Compensation Resistor RSLOPE

The K value is selected to be 1 at the minimum input voltage. RSLOPE should be carefully selected so that the
sum of sensed inductor current and slope compensation is less than COMP output high voltage.
8 u 109 8 u 109
RSLOPE ! 32 k:
fSW 250 kHz (30)
9 9
LIN u 6 u 10 10 + u u
RSLOPE 100 k:
ªK u VOUT VIN(MIN) º u RS u 10 1u 24V 9V u 4m: u 10
¬ ¼ (31)
A closest standard value of 100 kΩ is selected for RSLOPE.

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 37

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

8.2.2.8 Output Capacitor COUT

The output capacitors smooth the output voltage ripple and provide a source of charge during transient loading
conditions. Also the output capacitors reduce the output voltage overshoot when the load is disconnected
suddenly.
Ripple current rating of output capacitor should be carefully selected. In boost regulator, the output is supplied by
discontinuous current and the ripple current requirement is usually high. In practice, the ripple current
requirement can be dramatically reduced by placing high-quality ceramic capacitors earlier than the bulk
aluminum capacitors close to the power switches.
The output voltage ripple is dominated by ESR of the output capacitors. Paralleling output capacitor is a good
choice to minimize effective ESR and split the output ripple current into capacitors.
In this example, three 330 µF aluminum capacitors are used to share the output ripple current and source the
required charge. The maximum output ripple current can be simply calculated at the minimum input voltage as
follows:
IOUT 4.5A
IRIPPLE _ MAX(COUT) 6A
VIN(MIN) 9V
2u 2 u
VOUT 24V (32)
Assuming 60 mΩ of ESR per an output capacitor, the output voltage ripple at the minimum input voltage is
calculated as follows:
IOUT § 1 · 4.5A § 60m: 1 ·
VRIPPLE _ MAX(COUT) u ¨R ¸ u ¸ 0.252V
VIN(MIN) © ESR 4 u COUT u fSW ¹ 9V ¨© 3 4 u 3 u 330 ) u N+] ¹
VOUT 24V
(33)
In practice, four 10-µF ceramic capacitors are additionally placed earlier than the bulk aluminum capacitors to
reduce the output voltage ripple and split the output ripple current.
Due to the inherent path from input to output, unlimited inrush current can flow when the input voltage rises
quickly and charges the output capacitor. The slew rate of input voltage rising should be controlled by a hot-swap
or by starting the input power supply softly for the inrush current not to damage the inductor, sense resistor or
high-side N-channel MOSFET switch.

8.2.2.9 Input Capacitor CIN

The input capacitors smooth the input voltage ripple. Assuming high-quality ceramic capacitors are used for the
input capacitors, the maximum input voltage ripple which happens when the input voltage is half of the output
voltage can be calculated as follows:
VOUT 24V
VRIPPLE _ MAX(CIN) 0.09V
32 u LIN u CIN u fSW 2 32 u 10 + u u )u N+]2 (34)
The value of input capacitor is also a function of source impedance, the impedance of source power supply. The
more input capacitor will be required to prevent a chatter condition upon power up if the impedance of source
power supply is not enough low.

8.2.2.10 VIN Filter RVIN, CVIN

An R-C filter (RVIN, CVIN) on VIN pin is optional. It is not required if CIN capacitors are high-quality ceramic
capacitors and placed physically close to the device. The filter helps to prevent faults caused by high frequency
switching noise injection into the VIN pin. A 0.47 μF ceramic capacitor is used this example. 3 Ω of RVIN and 0.47
µF of CVIN are normal recommendations. A larger filter with 2.2 µ~4.7 µF CVIN is recommended when the input
voltage is lower than 8 V or the required duty cycle is close to the maximum duty cycle limit.

38 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

VIN

VIN
RVIN
CVIN LM5122

Figure 42. VIN Filter

8.2.2.11 Bootstrap Capacitor CBST and Boost Diode DBST

The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side N-
channel MOSFET device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap
diode. These current peaks can be several amperes. The recommended value of the bootstrap capacitor is 0.1
μF. CBST must be a good-quality, low-ESR, ceramic capacitor located at the pins of the device to minimize
potentially damaging voltage transients caused by trace inductance. The minimum value for the bootstrap
capacitor is calculated as follows:
QG
CBST ªF º
û9BST ¬ ¼
where
• QG is the high-side N-channel MOSFET gate charge
• ΔVBST is the tolerable voltage droop on CBST, which is typically less than 5% of VCC or 0.15 V,
conservatively (35)
In this example, the value of the BST capacitor (CBST) is 0.1 µF.
The voltage rating of DBST must be greater than the peak SW node voltage plus 16 V. A low leakage diode is
mandatory for the bypass operation. The leakage current of DBST must be low enough for the BST charge pump
to maintain a sufficient high-side driver supply voltage at high temperature. A low leakage diode also prevents
the possibility of excessive VCC voltage during shutdown, in high output voltage applications. If the leakage is
excessive, a zener VCC clamp or bleed resistor may be required. High-side driver supply voltage must be
greater than the high-side N-channel MOSFET switch’s gate plateau at the minimum input voltage.

8.2.2.12 VCC Capacitor CVCC

The primary purpose of the VCC capacitor is to supply the peak transient currents of the LO driver and bootstrap
diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The value
of CVCC must be at least 10 times greater than the value of CBST and should be a good-quality, low-ESR, ceramic
capacitor. Place CVCC close to the pins of the device to minimize potentially damaging voltage transients caused
by trace inductance. A value of 4.7 µF was selected for this design example.

8.2.2.13 Output Voltage Divider RFB1, RFB2

RFB1 and RFB2 set the output voltage level. The ratio of these resistors is calculated as follows:
RFB2 VOUT
1
RFB1 1.2V (36)
The ratio between RCOMP and RFB2 determines the mid-band gain, AFB_MID. A larger value for RFB2 may require a
corresponding larger value for RCOMP. RFB2 should be large enough to keep the total divider power dissipation
small. 49.9 kΩ in series with 825 Ω was chosen for high-side feedback resistors in this example, which results in
a RFB1 value of 2.67 kΩ for 24-V output.

8.2.2.14 Soft-Start Capacitor CSS

The soft-start time (tSS) is the time for the output voltage to reach the target voltage from the input voltage. The
soft-start time is not only proportional with the soft-start capacitor, but also depends on the input voltage. With
0.1 µF of CSS, the soft-start time is calculated as follows:
CSS u 1.2V § VIN(MAX) · 0.1 ) u 9 § 9·
tSS(MIN) u ¨¨1 ¸¸ u ¨1 2 msec
ISS © VOUT ¹ 10 $ © 9 ¸¹ (37)

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 39

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

CSS u 1.2V § VIN(MIN) · 0.1 ) u 9 § 9 ·

t SS(MAX) u ¨¨ 1 ¸¸ u ¨1 7.5 msec
ISS © VOUT ¹ 10 $ © 9 ¸¹ (38)

8.2.2.15 Restart Capacitor CRES

The restart capacitor determines restart delay time tRD and hiccup mode off time tRES (see Figure 26). tRD must
be greater than tSS(MAX). The minimum required value of CRES can be calculated at the low input voltage as
follows:
IRES u tSS(MAX) 30 $ u PVHF
CRES(MIN) 0.19 PF
VRES 1.2V (39)
A standard value of 0.47 µF is selected for CRES.

8.2.2.16 Low-Side Power Switch QL

Selection of the power N-channel MOSFET devices by breaking down the losses is one way to compare the
relative efficiencies of different devices. Losses in the low-side N-channel MOSFET device can be separated into
conduction loss and switching loss.
Low-side conduction loss is approximately calculated as follows:
2
§ VIN · § IOUT u VOUT ·
PCOND(LS) D u IIN2 u RDS _ ON(LS) u 1.3 ¨1 ¸u¨ ¸ u RDS _ ON(LS) u 1.3 [W]
© VOUT ¹ © VIN ¹ (40)
Where, D is the duty cycle and the factor of 1.3 accounts for the increase in the N-channel MOSFET device on-
resistance due to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-
resistance of the N-channel MOSFET device can be estimated using the RDS(ON) vs temperature curves in the N-
channel MOSFET datasheet.
Switching loss occurs during the brief transition period as the low-side N-channel MOSFET device turns on and
off. During the transition period both current and voltage are present in the channel of the N-channel MOSFET
device. The low-side switching loss is approximately calculated as follows:
PSW(LS) 0.5 u VOUT u IIN u (tR tF ) u fSW [W] (41)
tR and tF are the rise and fall times of the low-side N-channel MOSFET device. The rise and fall times are usually
mentioned in the N-channel MOSFET data sheet or can be empirically observed with an oscilloscope.
An additional Schottky diode can be placed in parallel with the low-side N-channel MOSFET switch, with short
connections to the source and drain in order to minimize negative voltage spikes at the SW node.

40 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

8.2.2.17 High-Side Power Switch QH and Additional Parallel Schottky Diode

Losses in the high-side N-channel MOSFET device can be separated into conduction loss, dead-time loss, and
reverse recovery loss. Switching loss is calculated for the low-side N-channel MOSFET device only. Switching
loss in the high-side N-channel MOSFET device is negligible because the body diode of the high-side N-channel
MOSFET device turns on before and after the high-side N-channel MOSFET device switches.
High-side conduction loss is approximately calculated as follows:
2
§ VIN · § IOUT u VOUT ·
PCOND(HS) (1 D) u IIN2 u RDS _ ON(HS) u 1.3 ¨ ¸u¨ ¸ u RDS _ ON(HS) u 1.3 [W]
© VOUT ¹ © VIN ¹ (42)
Dead-time loss is approximately calculated as follows:
PDT(HS) VD x IIN x (tDLH tDHL ) x fSW [W]

where
• VD is the forward voltage drop of the high-side NMOS body diode. (43)
Reverse recovery characteristics of the high-side N-channel MOSFET switch strongly affect efficiency, especially
when the output voltage is high. Small reverse recovery charge helps to increase the efficiency while also
minimizes switching noise.
Reverse recovery loss is approximately calculated as follows:
PRR(HS) VOUT u QRR u fSW [W] (44)
where
• QRR is the reverse recovery charge of the high-side N-channel MOSFET body diode. (45)
An additional Schottky diode can be placed in parallel with the high-side switch to improve efficiency. Usually, the
power rating of this parallel Schottky diode can be less than the high-side switch’s because the diode conducts
only during dead-times. The power rating of the parallel diode should be equivalent or higher than high-side
switch’s if bypass operation is required, hiccup mode operation is required or any load exists before switching.

8.2.2.18 Snubber Components

A resistor-capacitor snubber network across the high-side N-channel MOSFET device reduces ringing and
spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to
the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First,
make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and
50 Ω. Increasing the value of the snubber capacitor results more damping, but this also results higher snubber
losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the
switch waveform at heavy load. A snubber may not be necessary with an optimized layout.

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 41

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

8.2.2.19 Loop Compensation Components CCOMP, RCOMP, CHF

RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to produce a stable voltage
loop. For a quick start, follow the following 4 steps:
1. Select fCROSS
Select the cross over frequency (fCROSS) at one fourth of the RHP zero or one tenth of the switching
frequency whichever is lower.
fSW
25 kHz
10 (46)
VOUT V
u ( IN )2
fZ _ RHP RLOAD u (D')2 IOUT VOUT
5.3 kHz
4 4 u 2S u LIN _ EQ 4 u 2S u LIN _ EQ (47)
5.3 kHz of the crossover frequency is selected between two. RHP zero at minimum input voltage should be
considered if the input voltage range is wide.
2. Determine required RCOMP
Knowing fCROSS, RCOMP is calculated as follows:
V
RCOMP fCROSS u S u RS u RFB2 u 10 u COUT u OUT 68.5 k:
VIN (48)
A standard value of 68.1 kΩ is selected for RCOMP
3. Determine CCOMP to cancel load pole. Place error amplifier zero at the twice of load pole frequency. Knowing
RCOMP, CCOMP is calculated as follows:
RLOAD x COUT
CCOMP 20.2nF
4 x RCOMP (49)
A standard value of 22 nF is selected for CCOMP
4. Determine CHF to cancel ESR zero.
Knowing RCOMP, RESR and CCOMP, CHF is calculated as follows:
RESR u COUT u CCOMP
CHF 307 pF
RCOMP u CCOMP RESR u COUT (50)
A standard value of 330 pF is selected for CHF.

42 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

8.2.3 Application Curves

C1: FSYNC C2: SW VSUPPLY = 12 V, C1:SW VSUPPLY = 12 V ILOAD = 0 A

FSYNC = 500 kHz

Figure 43. Clock Synchronization Figure 44. Forced PWM

C1:SW VSUPPLY = 12 V ILOAD = 0 A C1:SW VSUPPLY = 12 V ILOAD = 0 A

Figure 45. Pulse Skip Figure 46. Skip Cycle

C1:SW VSUPPLY = 12 V ILOAD = 0 A C1: VSUPPLY, C2: Inductor current VSUPPLY = 12 V

C3: VOUT, C4: SS ILOAD = 0 A
Figure 47. Loop Response
Figure 48. Start-Up

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 43

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

9 Power Supply Recommendations

The LM5122 is a power management device. The power supply for the device is any DC voltage source within
the specified input range.

10 Layout

10.1 Layout Guidelines

In a boost regulator, the primary switching loop consists of the output capacitor and N-channel MOSFET power
switches. Minimizing the area of this loop reduces the stray inductance and minimizes noise. Especially, placing
high quality ceramic output capacitors as close to this loop earlier than bulk aluminum output capacitors
minimizes output voltage ripple and ripple current of the aluminum capacitors.
In order to prevent a dv/dt induced turn-on of high-side switch, connect HO and SW to the gate and source of the
high-side synchronous N-channel MOSFET switch through short and low inductance paths. In FPWM mode, the
dv/dt induced turnon can occur on the low-side switch. Connect LO and PGND to the gate and source of the low-
side N-channel MOSFET, through short and low inductance paths. All of the power ground connections must be
connected to a single point. Also, all of the noise sensitive low power ground connections must be connected
together near the AGND pin, and a single connection must be made to the single point PGND. CSP and CSN
are high-impedance pins and noise sensitive. Route CSP and CSN traces together with kelvin connections to the
current sense resistor as short as possible. If needed, place 100-pF ceramic filter capacitor close to the device.
MODE pin is also high impedance and noise sensitive. If an external pullup or pulldown resistor is used at MODE
pin, place the resistor close to the device. VCC, VIN and BST capacitor must be as physically close as possible
to the device.
The LM5122 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad
helps conduct heat away from the device. The junction to ambient thermal resistance varies with application. The
most significant variables are the area of copper in the PC board, the number of vias under the exposed pad and
the amount of forced air cooling. The integrity of the solder connection from the device exposed pad to the PC
board is critical. Excessive voids greatly decrease the thermal dissipation capacity. The highest power dissipating
components are the two power switches. Selecting N-channel MOSFET switches with exposed pads aids the
power dissipation of these devices.

10.2 Layout Example

Inductor

Controller

Place controller as
close to the switches

QL RSENSE
QH

COUT CIN

COUT CIN

VOUT GND GND VIN

Figure 49. Power Path Layout

44 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 LM5122
www.ti.com SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5122 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 45

Product Folder Links: LM5122
LM5122
SNVS954H – FEBRUARY 2013 – REVISED JUNE 2017 www.ti.com

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

46 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: LM5122

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM5122MH/NOPB ACTIVE HTSSOP PWP 20 73 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM5122
MH
LM5122MHE/NOPB ACTIVE HTSSOP PWP 20 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM5122
MH
LM5122MHX/NOPB ACTIVE HTSSOP PWP 20 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM5122
MH
LM5122ZPWPR ACTIVE HTSSOP PWP 24 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 LM5122Z
MH
LM5122ZPWPT ACTIVE HTSSOP PWP 24 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 LM5122Z
MH

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM5122 :

• Automotive: LM5122-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5122MHE/NOPB HTSSOP PWP 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LM5122MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LM5122ZPWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5122MHE/NOPB HTSSOP PWP 20 250 208.0 191.0 35.0
LM5122MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0
LM5122ZPWPR HTSSOP PWP 24 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LM5122MH/NOPB PWP HTSSOP 20 73 495 8 2514.6 4.06

Pack Materials-Page 3
 PACKAGE OUTLINE
PWP0024J SCALE 2.000
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C
TYP
A 6.2
PIN 1 INDEX 0.1 C
SEATING
AREA 22X 0.65 PLANE
24
1

2X
7.9
7.15
7.7
NOTE 3

12
13
0.30
4.5 24X
B 0.19
4.3
0.1 C A B

SEE DETAIL A
(0.15) TYP

2X 2.08 MAX
NOTE 5 4X 0.3 MAX
4X 0.1 MAX
12 13
NOTE 5

0.25
GAGE PLANE 1.2 MAX
5.26 25
5.11
THERMAL
PAD
0.75 0.15
0 -8 0.50 0.05
DETAIL A
A 20

TYPICAL
1 24

3.20
3.05
4225860/A 04/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
PWP0024J TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.4)
NOTE 9
(3.2)
SYMM METAL COVERED
24X (1.5) BY SOLDER MASK
1
24X (0.45) 24
SEE DETAILS

(R0.05) TYP

(5.26)
22X (0.65)
SYMM 25
(7.8)
NOTE 9
(1.2) TYP
SOLDER MASK
DEFINED PAD

( 0.2) TYP
VIA

12 13

(1.2) TYP

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000

4225860/A 04/2020
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
PWP0024J TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.2)
BASED ON
0.125 THICK METAL COVERED
24X (1.5)
STENCIL BY SOLDER MASK
1
24X (0.45) 24

(R0.05) TYP

22X (0.65) (5.26)

SYMM 25 BASED ON
0.125 THICK
STENCIL

12 13

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 8X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.58 X 5.88
0.125 3.20 X 5.26 (SHOWN)
0.15 2.92 X 4.80
0.175 2.70 X 4.45

4225860/A 04/2020
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA
PWP0020A

MXA20A (Rev C)

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated