8

23
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Total No. of Questions—8 [Total No. of Printed Pages—3

t
sta
Seat

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[5668]-132

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No.

01 91
9:5
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90
S.E. (E & TC/Electronics) (I Sem.) EXAMINATION, 2019

8/1 13
ELECTRONIC DEVICES AND CIRCUITS
8 2 P0
(2015 PATTERN)
.23 G

Time : Two Hours Maximum Marks : 50

CE

N.B. :— (i) Answer Q. No. 1 or 2, Q. No. 3 or 4, Q. No. 5 or 6,

8
23
Q. No. 7 or 8.
(ii) Neat diagrams must be drawn wherever necessary.

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16

(iii) Use of logarithmic tables, slide rule, electronic pocket

tat
8.2

calculator is allowed.

3s
.24

(iv) Assume suitable data, if necessary.

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91
49

9:5
1. (A) Explain the following non-ideal characteristics of E-MOSFET.
30
[6]
90
(i) Finite output resistance
01
01

(ii) Subthreshold conduction.

1/2
GP

(B) For the single stage JFET amplifier if R G = 1 M ,

8/1

RD = 2.2 k , RS = 1 k , IDSS = 8mA, VP = 4V. Draw the

CE

necessary circuit diagram and calculate IDQ and VDSQ for

82

8
VGS = –2V. [7]

23
.23

Or

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16

2. (A) For the circuit diagram shown in Fig. 1. Calcualte Ri, Ro and

tat
8.2

AV. Assume the device parameters : gm = 3.5 mA/V and 3s

yos = 20 uS : [6]
.24

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49

VDD = 10 V
9:5
30
90

1k
10 F
01

VO
01

VP
10 F
1/2
.23 G
P
8/1

2M 200 100 F
16 E
82
8.2C

Fig. 1
P.T.O.
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49
 8
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(B) Explain the short working of N-Channel E-MOSFET with drain

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sta
and transfer characteristics. [7]

3
1:3
01 91
3. (A) Explain Bi-CMOS inverter withcircuit diagram and give the

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1/2 0
advantages of Bi-CMOS technique. [6]

90
8/1 13
(B) For the circuit diagram shown in Fig. 2. Calculate Av,
8 2 P0
Ri, Ro : [6]
.23 G

+ VDD = 10 V
CE

8
RD 1k

23
12 M R1

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VO
16

tat
10 F
8.2

3s
Assume
.24

1:3
10 F
91 Kn = 1.5 mA/V2
49

5.1 m R2
9:5
Vth = 1.5 V
30
90
X=0
01
01
1/2
GP
8/1

Fig. 2
CE
82

Or

8
23
.23

4. (A) Explain the concept of MOSFET scaling and small geometry

ic-
16

effect in VLSI design technology. [6]

tat
8.2

(B) Explain MOSFET as constant current source with neat circuit

3s
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diagram. [6]
1:3
91
49

9:5
30

5. (A) Draw block diagram of different feedback topologies and compare

90

Ri and Ro. [8]

01
01

(B) Draw and design Hartley oscillator for fo = 1000 kHz. Assume
1/2
P

L1 = L2 = L and C = 0.1 uF. [5]

.23 G
8/1
16 E

Or
82
C

6. (A) Explain advantages and disadvantages of feedback amplifier.

[6]
8.2

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49
 8
23
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(B) For voltage amplifier open loop voltage gain is 75, input resistance

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is 100 k , output resistance is 6.8 k . If this amplifier is

3
connected with negative feedback then gain decreases by 20%.

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01 91
Calculate , Avf, Rif and Rof. [7]

9:5
1/2 0
90
8/1 13
7. (A) Explain the concept of current boosting with neat circuit diagram
8 2 P0
in three terminal voltage regulator. [6]
.23 G

(B) Explain any three specifications of LM317 adjustable voltage

CE

regulator. [3]

8
23
(C) Write a short note on low drop out voltage regulator. [4]

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16

Or

tat
8.2

8. (A) Draw the circuit diagram of step up SMPS and explain its

3s
.24

operation. [6]

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91
49

(B) Calculate range of the R2 resistance for the output voltage

9:5
30
0 – 20 V. Assume R1 = 270 and I adjust is 100 uA. Draw
90
01
01

typical connection diagram using adjustable voltage regulator.

1/2

[7]
GP
8/1
CE
82

8
23
.23

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16

tat
8.2

3s
.24

1:3
91
49

9:5
30
90
01
01
1/2
.23 G
P
8/1
16 E
82
C
8.2

[5668]-132 3 P.T.O.
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