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Proposed - BE E & TC 2019 - VLSI Syllabus

This document describes a course on VLSI Design & Technology that is worth 3 credits. It involves 3 hours of lectures and 2 hours of practical work per week. The course objectives are to explore hardware description languages, train students in CMOS circuit design, emphasize testability, and overview ASICs and programmable logic. The course outcomes are that students will be able to write HDL codes, apply digital design skills, model and prototype circuits, design CMOS circuits, analyze ASIC issues, and apply testability knowledge. The syllabus covers HDL design, digital design issues, PLD architectures, CMOS circuits, ASIC design, and VLSI testing over 6 units. Experiments involve writing and implementing VHDL codes and

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Ravindra Dabhade
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79 views

Proposed - BE E & TC 2019 - VLSI Syllabus

This document describes a course on VLSI Design & Technology that is worth 3 credits. It involves 3 hours of lectures and 2 hours of practical work per week. The course objectives are to explore hardware description languages, train students in CMOS circuit design, emphasize testability, and overview ASICs and programmable logic. The course outcomes are that students will be able to write HDL codes, apply digital design skills, model and prototype circuits, design CMOS circuits, analyze ASIC issues, and apply testability knowledge. The syllabus covers HDL design, digital design issues, PLD architectures, CMOS circuits, ASIC design, and VLSI testing over 6 units. Experiments involve writing and implementing VHDL codes and

Uploaded by

Ravindra Dabhade
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VLSI Design & Technology

Credits: 03
Teaching Scheme Examination Scheme
Lecture : 03 Hr/Week In Sem : 30 Marks
Pract : 2 Hr/Week End Sem : 70 Marks

Course Objectives

 To explore Hardware Description Language (HDL) and respective digital design


methodologies.
 To train the students for Complementary Metal Oxide Semiconductor (CMOS) circuit
designs.
 To realize importance of testability in logic circuit design.
 To overview an Application Specific Integrated Circuit (ASIC) issues and to understand
Programmable Logic Devices (PLD) architectures with advanced features.

Course Outcomes

On completion of the course, student will be able to -

1. Write effective HDL codes for digital design.


2. Apply knowledge of real time issues in digital design.
3. Model digital circuit with HDL, simulate, synthesis and prototype in PLDs.
4. Design CMOS circuits for specified applications.
5. Analyze various issues and constraints in design of an ASIC
6. Apply knowledge of testability in design and Build In Self Test (BIST) circuit.

Course Syllabus
Unit I : Design with HDL 7 Hrs
Design Flow, Language constructs, Data objects, Data types, Entity, Architecture & types of
modeling, Sequential statements, Concurrent statements, Packages, Sub programs, Attributes, HDL
modeling of Combinational, Sequential circuits and FSM. Simulations, Synthesis, Efficient coding
styles, Hierarchical and flat designs, Partitioning for synthesis, Pipelining, Resource sharing.
Unit II : Digital Design and Issues 6 Hrs
Sequential synchronous machine design, Moore and Mealy machines, HDL code for Machines,
FIFO. Meta-stability and solutions. Noise margin, Fan-out, Skew, Timing considerations, Hazards,
Clock distribution, Clock jitter, Supply and ground bounce, Power distribution techniques, Power
optimization. Interconnect routing techniques, Wire parasitic, Signal integrity issues. I/O
architecture.
Unit III : PLD Architectures and applications 6 Hrs
Design Flow. CPLD Architecture, Features, Specifications, Applications. FPGA Architecture,
Features, Specifications, Applications. Clock management techniques. The Simulation and
Synthesis Tools, FPGA synthesis and implementation. Comparison of CPLD & FPGA.

1
Unit IV: Digital CMOS circuits 7 Hrs
N-MOS, P-MOS and CMOS. MOSFET parasitic, Technology scaling, Channel length modulation,
Hot electron effect, Velocity saturation. CMOS Inverter, Device sizing, CMOS combinational logic
design, Power dissipations, Power delay product, Body Effect, Rise and fall times, Latch Up effect,
Transmission gates.
Unit V : Application Specific Integrated Circuit 7 Hrs
Design Flow, Cell design specifications, Spice simulation, AC and DC analysis, Transfer
Characteristics, Transient responses, Noise analysis, Lambda rules, Design R ule C heck,
Fabrication methods of circuit elements, Layout of cell, Library cell designing for NAND &
NOR, Circuit Extraction, Electrical Rule Check, Layout Vs. Schematic, Post-layout Simulation and
Parasitic extraction, Design Issues like Antenna effect, Electro migration effect, Cross talk and
Drain punch through, Timing analysis.

Unit VI : VLSI Testing and Analysis 6 Hrs


Types of fault, Need of Design for Testability (DFT), DFT Guideline, Testability, Fault models, Path
sensitizing, Test pattern generation, Sequential circuit test, Built In Self Test, JTAG &
Boundary scan, TAP Controller.

Text Books:
1. Charles H. Roth, “Digital systems design using VHDL”, PWS.
2. Wyane Wolf, “Modern VLSI Design (IP-Based Design)”, 4E, Prentice Hall.
3. Steve Kilts “Advanced FPGA Design Architecture, Implementation and Optimization”,
Wiley.
4. E. Weste, David Money Harris, “CMOS VLSI Design: A Circuit &System Perspective”,
Pearson Publication.

Reference Books:
1. R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation”, 3E, Wiley-IEEE Press.
2. John F. Wakerly, “Digital Design Principles and Practices”, 3E, Prentice Hall.
3. M. Morris Mano , “Digital Design”, 3E , Pearson.
4. Cem Unsalan, Bora Tar, “ Digital System Design with FPGA: Implementation Using
Verilog and VHDL”, McGraw-Hill.

List of Experiments

A. To write VHDL code, simulate with test bench, synthesis, implement on PLD. [Any 5]

1. 4 bit ALU for Add, Subtract, AND, NAND, OR, XOR & XNOR.
2. Universal shift register with mode selection input for SISO, SIPO, PISO, & PIPO.
3. Mod - N Counter
4. FIFO memory
5. LCD Interface
6. Keypad interface

B. To prepare CMOS layout in selected technology, simulate with & without capacitive load, comment
on rise & fall times. [Any 3]
2
1. Inverter, NAND, NOR gates
2. Half Adder & Full Adder
3. 2:1 Mux using logic gates & transmission gates
4. One bit SRAM Cell

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