IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 40. NO. 6.

DECEMBER 1991 925

An Analog Sinusoidal Frequency -to-Voltage

Converter
Wanlop Surakampontorn, Member, ZEEE, Yongyut Chonbodeechalermroong, and Suree Bunjongjit

Abstract-An analog sinusoidal frequency-to-voltage (F/V) phase-locked loop is not generally used for precision F/V
converter, based on the use of nonlinear analog circuits, is in- conversion because VCOs with adequate dynamic range
troduced in this paper. The realization is composed of a dif- and linearity have been hitherto unavailable.
ferentiator, an integrator, and a translinear divider and square-
rooter circuit. The proposed F/V converter can accurately and Recently, many methods have been proposed for the
linearly convert a sinusoidal signal frequency into an output frequency measurement of a purely sinusoidal signal [8]-
voltage, with fast response and low error, over more than two [ 101. The sinusoidal F/V converter has found application
decades of frequency range. The method can also be imple- in communication systems. For example, it is useful in
mented in monolithic integrated form.
improving the transient response of automatic frequency
control (AFC) of power systems or in measuring carrier
frequency drift of RF signals after demodulation. All the
I. INTRODUCTION published circuits perform analog or numerical computa-
N F/V converter is a device that generates an output tion on successive samples of the input signal, which is
A voltage proportional to the frequency of an input sig-
nal. This device is very useful and has many applications
only suitable for a narrow range of input frequencies. In
this paper, an alternative approach for realizing a sinu-
in power system control, in processing of very-low-fre- soidal F/V converter is described. The circuit performs
quency signals, and in many fields of instrumentation. For mathematical operations using nonlinear analog circuits.
example, it can be used as a frequency meter, as a control The realization scheme is suitable for implementation in
unit in a voltage-controlled oscillator (VCO), or as a fre- monolithic integrated form. Experimental results that
quency-measuring device in flowmeters and tachometer demonstrate the accuracy, linearity, and fast response time
read outs in motor-speed controls. The basic requirements of the converter are also included.
for a good F/V converter are low ripple, good linearity,
fast response, and wide frequency range. 11. CIRCUITDESCRIPTION
There are two fundamental approaches that can be em-
A. Basic Principle
ployed to realize F/V converters [1]-[4]. The first ap-
proach is based on low-pass filtering of fixed duration Figure 1 shows the circuit diagram of the proposed F/V
pulses at a rate set by the input frequency. Most of the converter, which comprises three subcircuits, a differen-
inexpensive F/V converters available commercially are tiator, an integrator, and a combined divider and square-
ICs, such as the Analog Devices Models AD 451 and the rooter circuit. Let us assume that the input signal Vi, is a
AD 453, are operated in this mode. The second approach pure sinusoid having peak amplitude A , Vi, = A sin (ut),
is based on counting the number of pulses over a given and that the time constants of the differentiator and inte-
time interval. These conventional frequency-measuring grator circuits are 7 d and T ~ respectively.
, Thus the output
techniques are unsuitable if the frequencies are low or if signals VI and V2 of the integrator and differentiator cir-
transient variations in frequency need to be detected. This cuits, respectively, can be written as
is due to the fact that conventional F/V circuits involve a VI = ( - A / C W ) COS (ut) (1)
time-consuming averaging process. There are many
methods especially designed for low-frequency operation V, = (ATdW) COS (Ut). (2)
[5]-[7]. However, their usefulness is limited to narrow
The absolute values of signals VI and V,, which can be
frequency bands of operation. Further, an F/V converter
achieved by the use of rectifier circuits, are fed into the
can be achieved by using a voltage-to-frequency (V/F)
divider and square-rooter circuit. Therefore, the output
converter, such as the Analog Devices multivibrator type
signal VouT can be given by
VIF Model AD 537 or the charge-balance type V/F Model
AD 650, in a phase-lock loop configuration. However, a VOUT = J l V 2 1 / l V l l = 7u (3)
where 7 = G. We can see from (3) that the output
Manuscript received November 10, 1990; revised October 20, 1991. VouT is a linear function of the input signal angular fre-
The authors are with the Faculty of Engineering, King Mongkut’s Insti-
tute of Technology Ladkrabang, Bangkok 10520, Thailand. quency w , and is not dependent on the amplitude A of the
IEEE Log Number 9105420. input signal.

0018-9456/91$01.00 0 1991 IEEE

926 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL..40. NO. 6, DECEMBER 1991

v2 :&J coswt
DIFFERENTIATOR

Vin * Ash wt

1
9-k: INTEGRATOR
-& COsOt
Fig. 1 . Basic principle of the proposed F/V converter.

’EE
B. Translinear Divider and Square-Rooter Circuit Fig. 2. A translinear divider and square-rooter circuit.
From the block diagram in Fig. 1, it is clear that the
major part that produces the F/V action is the divider and
square-rooter circuit. Usually, an operational amplifier fication factor fl and transistor mismatches. Transistors
(Op-amp) based circuit can be employed to construct the that are particularly closely matched with high values of
divider and square-rooter circuit [ 111. However, in order fl must be employed for Q2 and Q,. This is because at low
that the proposed scheme can be implemented in a and very high frequencies the signal currents I , and Z2,
monolithic form, a translinear-principle based circuit will respectively, can be large. In such cases, the base currents
be described in this section. Consider the translinear cir- of Q2 and Q, cannot be neglected and will cause signifi-
cuit in Fig. 2, which is a single loop employing ten tran- cant departure of ZoUT from the ideal value given in (4).
sistors. By assuming that the transistors of the transistor The error due to transistor mismatching can be reduced
pairs (ei,
Q,), where i = 1, 3 , 4 , 6, are perfectly matched by the adjustment of the gain of the rectifier stages.
and that the transistor’s common emitter current gain fl = In practice, owing to the inevitable presence of the off-
hFE >> 1 or CY z 1, thus the base current 0. Then the set current charging the integrating capacitor, a parallel
translinear principle gives [ 121 resistor RF is needed across the capacitor of the integrator
circuit. Therefore the pole of the integrator circuit cannot
(4) be located exactly on thejw axis. Moreover, in order to
We can see that the current ZoUT is in the form of the reduce amplification of the noise, whose frequency con-
square root of the quotient ratio Z2/Zl. Therefore, the tent may be well above the signal frequencies, by the dif-
translinear circuit in Fig. 2 provides a dividing and square ferentiator, a resistor Rs is required to be connected in
rooting function. series with c d . If a high value of RF is needed in parallel
The complete divider and square-rooter circuit is shown with the integrating capacitor and, without loss of gen-
in Fig. 3. Op-amps A , , A2 and transistor Q2 and op-amps erality, if we let r = ri = Td = RiCi be the integrator and
A,, A4 and transistor Q, operate as full-wave rectifier cir- differentiator time constants, then the effect of RF upon
cuits, converting the input voltages VI and V2into the cur- the output voltage VouT can be written as
rents Z2 and ZI, respectively, where
VouT = +
R L Z ~ T W { ( ~e2/u2r2)/(1 + ~~72s)))”~
12 = I(Ardu) cos (ut)l (5)
- {cos (ut)/cos (ut + y)}II2 (9)
ZI = I ( A / r l u )cos (ut)]. (6)
where rs = RsCd, E = R i / R F << 1, and y = 90 - tan-’
By substituting (5) and (6) into (4), we get ( U T / € ) is a small angle, i.e. for RF = 1 M a , Ri = 2.2 kS2,
Ci = 0.1 p F then y = 0.09’. For u2d<< 1, we can see
= 14 T u . (7) that the main effect is the introduction of a small distor-
Then the output voltage tion of the output-signal amplitude if RF is large. For ex-
ample, a conversion error of about 0.01 % is expected if
VOUT = (RL TZ4) (8) the signal frequency is 1 kHz, RL = 5 kS2, Rs = 1 kS2,
which is a linear function of the input signal frequency, and Z4 = 160 FA.
as is required. The other important sources of nonlinearities that will
give rise to conversion errors in VouT are:
C. Circuit Performance a) The limited accuracies of the full-wave rectifier cir-
For the translinear circuit, the major factors that con- cuits.
tribute to the scaling errors or unwanted nonlinearities are b) Temperature drift of the translinear circuit since it
due to the insufficiently high value of the current ampli- requires 10 matched transistors, which are not
 ~

SURAKAMPONTORN er al.: SINUSOIDAL FREQUENCY-TO-VOLTAGE CONVERTER 921

look 1Ok 1Wk -15v 1Wk lOk lWk

RC RD

Fig. 3 . Complete circuit diagram of the divider and square-rooter.

available in a single integrated monolithic device tegrator output signal can become saturated. At high
(LM3M6). frequencies, the reverse is also true.
Nonzero offset voltages of the integrator, differen-
tiator, rectifiers and translinear circuits. 111. EXPERIMENTAL RESULTSAND DISCUSSIONS
The offset signals from the outputs of the integrator
In this paper, differentiator and integrator circuits
and the differentiator will cause feedthrough of the
designed for the frequency range of 50 Hz to 5 kHz are
fundamental to the output of the divider and square-
employed to demonstrate the performance of the F/V cir-
rooter circuit as well as an increased DC offset volt-
cuit. As shown in Fig. 4 , the integrator is designed for
age.
Vi, = 0.8 Vpeak, it provides V , = 10 I/peak at 50 Hz, and
The dividing circuit will not be very accurate at both
ends of the range, in particular, at very high fre- VI = 0.1 Vppeak at 5 kHz. The differentiator part provides
V, = 50 mVpeakand v2 = 5 Vpeak at 50 HZ and 5 kHZ,
quency, when the output of the integrator or V , has
respectively. The reason V2 is set to 5 Vp/peakr rather than
a value of nearly zero, since the division by a very
to 10 Vpeak,at 5 kHz is to keep the current ratio (Z2/Z1)in
small quantity is not permissible with the divider.
(4) to a small value below 50 in order to reduce the non-
We assume a pure sinusoidal input waveform in our
linearity introduced by the translinear circuit.
mathematical computation and, therefore, harmon-
The complete F/V circuit is constructed on a prototype
ics and noise in the input waveform will cause error.
board in order to experimentally demonstrate the perfor-
This results in an increased level of noise at the out-
mance of the converter. The op-amps employed are
put of the converter.
Error sources (c) through (f) result from the non- monolithic FET input op-amps LF 351’s. The offset volt-
ideal characteristics of both the integrator and the age of each amplifier is minimized to less than f0.2 mV.
differentiator circuits. Therefore, in order that the All n-p-n transistors, except Q2 and Q,, are monolithic
transistor arrays (LM3W6), those that required close
proposed F/V converter give a good performance in
the required frequency range, special attention must matching are contained in the same array package. Q2 and
be taken in the design of the integrator and the dif-
Q, are in the form of supermatched pairs (LM394). All
ferentiator circuits. resistors used are f 0 . 1% tolerance resistors. Currents Z2
The frequency response of the translinear circuit and Z4 are set to 2 mA and 160 PA, respectively. The time
constants of the integrator and the differentiator circuits,
is high, i.e., of the order of 20 MHz [13], if the
T~ = Ri * Cj and 7d = Rd cd, are set to 2.2 x lop4and
signals are in the form of currents. Therefore, the
2.0 x 1 0 - ~S.
overall frequency response of the F/V circuit will
Resistors RA and RB in the circuit of Fig. 3 regulate the
be determined by the frequency response of the in-
put circuits. The bandwidth of the F/V circuit will linearity of the converter. A procedure for adjusting the
be primarily determined by the dynamic ranges and linearity of the divider and square-rooter circuit follows:
the noise levels of both the differentiator and inte- a) Apply Vi, = 0.8 Vppeak with a fixed frequency at 500
grator circuits. This is due to the fact that at very Hz and adjust the current Z4 so that VouT z 500 mV.
low frequency, i.e., 1 / 100 of 1/ 7 d , the differentia- b) Apply Vi, = 0.8 Vp/peak with a fixed frequency at 50
tor output signal can become too low, while the in- Hz and adjust RB such that VouT z 50 mV.
 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 40, NO. 6. DECEMBER 1991

lp 0.1p

Fig. 4. The differentiator and integrator circuits designed for the fre-
quency range from 50 Hz to 5 kHz.

lk ''

- riveted
+ + + + WaMnd

Frequency(Hz)

Fig. 5. Plot of VoUT against frequency.

Apply Vi, = 0.8 Vpeakwith the fixed frequency at 5 fed into the proposed F/V converter and the VouT is mon-
kHz and adjust RA such that VouT z 5 V. itored in order to compare with the input signal of the
Repeat steps (a) through (c) until the measured VouT VCO. Fig. 6(a) shows the response of the VouT to step
errors from steps (a), (b), and (c) are less than k 1% . changes in the input frequency from 50-500 Hz and vice
versa. We can see that the measured VouT (lower trace)
Fig. 5 shows the plot of the measured output voltage can follow the square-wave input signal of the VCO (up-
VouT against the input signal frequency, where the am- per trace) with 2-ms time delay and 10-mV ripple. Fig.
plitude of the input signal is kept constant at Vi, = 0.8 6(b) shows that the conversion circuit can lock to the in-
Vpeak.It is clearly seen that the experimental results agree put frequency within a fraction of a cycle. In contrast, the
very well with the calculated values over more than two conversion time for the AD 537 in a phase-lock configu-
decades of the frequency range. The measured VouT error ration requires three or four cycles [14]. Fig. 6(c) shows
does not exceed f0.5%, where the error is found to be the test that is conducted by continuously sweeping the
less than 0.1 % in the frequency range of 400 Hz to 5 kHz input frequency in the range from 50 Hz to 5 kHz. The
and less than 0.5% in the frequency range of 50-300 Hz. result demonstrates the accuracy of better than 0.1 % and
As already discussed in this section, the bandwidth of the the measured nonlinearity at 99% dynamic range is less
F/V circuit is determined by the dynamic ranges of both than _ + O S % . However, it should be noted that the lin-
the integrator and the differentiator circuits. Therefore, earity and accuracy performance depend strongly on the
for a specific application of the F/V converter, the inte- type of VCO that is used. In addition, it is expected that
grator and the differentiator circuits must be redesigned in the circuit in an actual integrated form will have a much
order to work in the required frequency range. better performance than the performance measured from
Experimental results which illustrate the fast response the bread-boarded circuit.
to a sudden frequency change of the input frequency are
shown in Fig. 6. The circuit response is measured as fol- IV. CONCLUSION
lows: An input signal is applied to a VCO to obtain a In this paper, we have demonstrated the use of a non-
frequency-modulated (FM) signal. The FM signal is then linear analog circuit technique to realize a sinusoidal F/V
 ~

SURAKAMPONTORN ef al. SINUSOIDAL FREQUENCY-TO-VOLTAGE CONVERTER 929

converter. Since the computation is performed through an

analog operation, the converter has a fast response time
to frequency changes. The performance of the F/V con-
verter for the frequency range from 50 Hz to 5 kHz has
been presented. Experimental results showing the linear
F/V characteristic, the rapid step response and the low
ripple are given. It should be noted that, for applications
that require simultaneous detection of both amplitude and
frequency the proposed F/V can easily be combined with
the peak amplitude detection scheme discussed in [15].

ACKNOWLEDGMENT
The authors would like to thank the editor and the
reviewers for their constructive comments and detailed
editing of this paper.

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