ASCII

The following is a partial listing of ASCII code, in which each bit pattern has
been extended with a 0 on its left to produce the 8-bit pattern commonly used
today. The hexadecimal value of each 8-bit pattern is given in the third column.
Symbol ASCII Symbol ASCII Symbol
ASCII

line feed 00001010 carriage return

00001011 space 00100000 20
01000000 40 01100000 60 00100001
21 01000001 41 a 01100001
61
00100010 22 B 01000010 42
01100010 62
00100011 23 c 01000011 43
01100011 63
00100100 24 D 01000100 44
01100100 64
00100101 25 E 01000101 45
01100101 65
00100110 26 F 01000110 46
01100110 66
00100111 27 G 01000111 47
01100111 67
00101000 28 H 01001000 48
01101000 68
00101001 29 01001001 49
01101001 69
00101010 J 01001010
01101010
00101011 2B K 01001011 4B
01101011 6B
00101100 L 01001100
01101100
00101101 M 01001101 m 01101101 00101110 N
 01001110 n 01101110
0 O o
1 00110000 30 p 01010000 50 p
01110000 70
2 00110001 31 01010001 51 q
01110001 71
3 00110010 32 R 01010010 52
01110010 72
4 00110011 33 s 01010011 53 s
01110011 73
5 00110100 34 01010100 54
01110100 74
6 00110101 35 01010101 55 u
01110101 75
7 00110110 36 01010110 56
01110110 76
8 00110111 37 w 01010111 57
01110111 77
9 00111000 38 x 01011000 58
x78
00111001 39 01011001 59 79
00111010 z
01011010 z
00111011 3B 01011011 5B7B
01011100
3D 01011101

577

Circuits to Manipulate Two's Complement

Representations
This appendix presents circuits for negating
and adding values represented in two's
complement notation. We begin with the
 circuit in Figure B. 1 that converts a four-bit
two's complement representation to the
representation for the negative of that value.
For example, given the two's complement
representation of 3, the circuit produces the
representation for —3. It does this by
following the same algorithm as presented in
the text. That is, it copies the pattern from
right to left until a 1 has been copied and then
complements each remaining bit as it is
moved from the input to the output. Because
one input of the rightmost XOR gate is fixed
at 0, this gate will merely pass its other input
to the output. However, this output is also
passed to the left as one of the inputs to the
next XOR gate. If this output is 1, the next
XOR gate will complement its input bit as it
passes to the output. Moreover, this 1 will
also be passed to the left through the OR gate
to affect the next gate as well. In this manner,
the first 1 that is copied to the output will also
be passed to the left, where it will cause all
the remaining bits to be complemented as
they are moved to the output.

Figure B. I A circuit that negates a two's complement pattern

Input

Output

578

579

Next, let us consider the process of adding

two values represented in two's complement
notation. In particular, when solving the
problem
+ 0110
+ 1011
we proceed from right to left in a column-by-
column manner, executing the same algorithm
for each column. Thus once we obtain a
circuit for adding one column of such a
problem, we can construct a circuit for adding
many columns merely by repeating the single-
column circuit.
The algorithm for adding a single
column in a multiple-column addition
problem is to add the two values in the
current column, add that sum to any carry
from the previous column, write the least
significant bit of this sum in the answer,
and transfer any carry to the next column.
The circuit in Figure B. 2 follows this
same algorithm. The upper XOR gate
determines the sum of the two input bits.
The lower XOR gate adds this sum to the
value carried from the previous column.
The two AND gates together with the OR
gate pass any carry to the left. In
particular, a carry of 1 will be produced if
the original two input bits in this column
were 1 or if the sum of these bits and the
carry were both 1.

Figure B.2 A circuit to add a single column in a multiple-column addition problem

Upper bit Lower bit from
column from column

Carry to
next column Carry from
 previous column

Sum
580 Appendixes

Figure B.3 shows how copies of this

single-column circuit can be used to produce a
circuit that computes the sum of two values
represented in a four-bit two's complement
system. Each rectangle represents a copy of
the single-column addition circuit. Note that
the carry value given to the rightmost
rectangle is always 0 because there is no carry
from a previous column. In a similar manner,
the carry produced from the leftmost rectangle
is ignored.
The circuit in Figure B.3 is known as a
ripple adder because the carry information
must propagate, or ripple, from the rightmost
to the leftmost column. Although simple in
composition, such circuits are slower to
perform their functions than more clever
versions, such as the lookahead carry adder,
which minimize this column-to-column
propagation. Thus the circuit in Figure B.3,
although sufficient for our purposes, is not the
circuit that is used in today's machines.

Figure 8.3 A circuit for adding two values in a two's

complement notation using four copies of the circuit in
Figure B.2
A Simple Machine Language
In this appendix we present a simple but
representative machine language. We begin
by explaining the architecture of the machine
itself.

The Machine's Architecture

The machine has 16 general-purpose registers
numbered 0 through F (in hexadecimal). Each
register is one byte (eight bits) long. For
identifying registers within instructions, each
register is assigned the unique four-bit pattern
that represents its register number. Thus
 register 0 is identified by 0000 (hexadecimal
0), and register 4 is identified by 0100
(hexadecimal 4).
There are 256 cells in the machine's main
memory. Each cell is assigned a unique
address consisting of an integer in the range
of 0 to 255. An address can therefore be
represented by a pattern of eight bits ranging
from 00000000 to

Floating-point values are assumed to be

stored in an eight-bit format discussed in
Section 1.7 and summarized in Figure 1.24.

The Machine's Language

Each machine instruction is two bytes long.
The first 4 bits provide the op-code; the last
12 bits make up the operand field. The table
that follows lists the instructions in
hexadecimal notation together with a short
description of each. The letters R, S, and T are
used in place of hexadecimal digits in those
fields representing a register identifier that
varies depending on the particular application
of the instruction. The letters X and Y are
used in lieu of hexadecimal digits in variable
fields not representing a register.
Op-code Operand Description
1 RXY LOAD the register R with the bit pattern found in the
memory cell whose address is XY.
Example: 14A3 would cause the contents of the memory cell
located at address A3 to be placed in register 4.
2 RXY LOAD the register R with the bit pattern XY.
Example: 20A3 would cause the value A3 to be placed in
register O.
581
582 Appendixes

Op-code Operand Description

3 RXY STORE the bit pattern found in register R in the memory cell
whose address is XY.
Example: 35B 1 would cause the contents of register 5 to be
placed in the memory cell whose address is B 1.
4 ORS MOVE the bit pattern found in register R to register S.
Example: 40A4 would cause the contents of register A to be
copied into register 4.
5 RST ADD the bit patterns in registers S and T as though they
were two's complement representations and leave the result
in register R.
Example: 5726 would cause the binary values in registers 2 and
6 to be added and the sum placed in register 7.

6 RST ADD the bit patterns in registers S and T as though they

represented values in floating-point notation and leave the
floating-point result in register R.
Example: 634E would cause the values in registers 4 and E to
 be added as floating-point values and the result to be placed in
register 3.
7 RST OR the bit patterns in registers S and T and place the result in
register R.
Example: 7CB4 would cause the result of ORing the contents of
registers B and 4 to be placed in register C.

8 RST AND the bit patterns in registers S and T and place the result in
register R.
Example: 8045 would cause the result of ANDing the contents
of registers 4 and 5 to be placed in register O.

9 RST EXCLUSIVE OR the bit patterns in registers S and T and place

the result in register R.
Example: 95F3 would cause the result of EXCLUSIVE ORing
the contents of registers F and 3 to be placed in register 5.
ROX ROTATE the bit pattern in register R one bit to the right X
times. Each time place the bit that started at the low-order end
at the high-order end.
Example: A403 would cause the contents of register 4 to be
rotated 3 bits to the right in a circular fashion.
RXY JUMP to the instruction located in the memory cell at address
XY if the bit pattern in register R is equal to the bit pattern in
register number O. Otherwise, continue with the normal
sequence of execution. (The jump is implemented by copying
XY into the program counter during the execute phase.)
Example: B43C would first compare the contents of register 4
with the contents of register O. If the two were equal, the