10

HDL Based Design

In this chapter we show a design done in Verilog and implemented on UP2. We describe a circuit at the behavioral level and test it with an HDL simulator. The tested design is then brought into Quartus II and incorporated into a complete design. The Quartus II compiler synthesizes our behavioral code and generates a device programming file that contains the synthesized parts as well as other components used in the complete design. The final design is used to program the MAX device of the UP2 board.

10.1 High Level Description and Simulation

The design that will be used in this chapter is a sequence detector. After describing the functionality of this circuit we will describe it in Verilog test our synthesizable Verilog design with an HDL simulator and ready it for being used in programming a programmable device. This section describes the design of the sequence detector and the next section discusses its preparation for device programming.
10.1.1 State Machine Description

The core of the design that will be used to program the MAX device of UP2 is a sequence detector that detects a sequence of 1011 on its x serial input. When this sequence is detected it generates a complete one clock duration pulse on its z output. The machine has a reset input (rst) that forces the machine into its initial or reset state. The state machine for implementing this design is a Moore machine the state diagram of which is shown in Figure 10.1.

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Figure 10.1 Moore 1011 State Diagram

'timescale 1ns/100ps module moore1011 ( x rst clk z ); input x rst clk; output z; parameter [2:0] a= 0 b = 1 c = 2 d = 3 e = 4; reg [2:0] p_state n_state; always @( p_state or x ) begin: combinational case ( p_state ) a: if( x == 1 ) n_state = b; else n_state = a; b: if( x == 0 ) n_state = c; else n_state = b; c: if( x == 1 ) n_state = d; else n_state = a; d: if( x == 1 ) n_state = e; else n_state = c; e: if( x == 1 ) n_state = b; else n_state = c; default: n_state = a; endcase end assign z = (p_state == e); always @( posedge clk ) begin: sequential if( rst ) p_state = a; else p_state = n_state; end endmodule

Figure 10.2 Moore Detector Verilog Code

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10.1.2 Moore Machine Verilog Code

The synthesizable Verilog code of our Moore machine is shown in Figure 10.2. As shown three concurrent statements describe transitions output and clocking of this machine. The combinational always block describes the transitions shown in the state diagram of Figure 10.1 while the sequential always block describes the clocking of our machine. The other concurrent statement in this description is an assign statement that is used for assigning values to the z output of the circuit. The description shown uses p_state for the present state of the machine and n_state for its next state. Because our machine has five states parameter and reg declarations are three bits wide.
10.1.3 Moore Machine Verilog Testbench

The testbench of Figure 10.3 is used for testing the Verilog code of Figure 10.2. In this testbench a 19-bit wide buffer holds serial data that are applied to the x input of the circuit being tested. Two concurrent always blocks in this description produce the circuit clock and simultaneously rotate buffer bits out into x.
'timescale 1ns/100ps module test_moore1011; reg x, rst, clk; wire z; reg [18:0] buffer; moore1011 uut( x, rst, clk, z ); initial buffer = 19'b0001101101111001001; initial begin clk = 0;x = 0; rst = 1; #29 rst = 0; #500 $stop; end always @(posedge clk) #1 {x, buffer} = {buffer, x}; always #5 clk = ~clk; endmodule

Figure 10.3 Moore Detector Testbench

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10.1.4 Behavioral Simulation

The Moore1011.v (Figure 10.2) design description file and its testbench, Moore1011Tester.v (Figure 10.3) are simulated in a ModelSim 5.7c project. The simulation run waveform is shown in Figure 10.4. The present state of the machine (p_state) is displayed in the waveform shown. The output of the machine becomes 1 when p_state is 100 that correspond to state e of our Moore machine.

10.2 Design Implementation

This section discusses how Quartus II environment is used for hardware implementation of the Moore design of the previous section. Steps involved in this implementation include project creation in Quartus II. generation of proper interfaces for our tested description of Moore machine porting or adapting the Verilog code of our design to the Quartus II environment design compilation and device programming. After completion of these steps using UP2 pushbuttons and LEDs our UP2 prototype will be able to verify waveforms shown in Figure 10.4.

Figure 10.4 Moore Machine Simulation Run (Partial View)

10.2.1 Project Definition

The Quartus II project for harware implementation of our Moore machine is Detector. This project uses our BookLibrary as its pre-defined user library. A user library can either be specified during creation of a project or in the Settings window after a project is created. To add a user library in the Settings window open the Assignments pull-down menu from the Quartus II main window and select Settings. When the Settings window opens under Files & Directories click on User Libraries to set your libraries.
10.2.2 Symbol Generation from Verilog Code

In order to be able to use our tested Verilog code of Figure 10.2 in Quartus a symbol has to be created for it. The generated symbol becomes available in the Project library and can be used like any other symbol is a block diagram.

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For generating a symbol for Moore1011 module of Figure 10.2, copy its code to the directory of the Quartus II Detector project. Then open this file using Quartus II text editor (File Open and select Moore1011.v to open it). While this file is open open the File pull-down menu and follow links to create symbol for the current file. As with other symbols we can edit the symbol that is so generated. The edited symbol for our Moore1011 Verilog code is shown Figure 10.5.
10.2.3 Schematic Entry

The schematic file for Quartus II Detector project is Detector.bdf. In this schematic the moore1011 symbol of Figure 10.5 its necessary interfaces for UP2 resources and the Detector pins are entered and proper interconnections made. Components from BookLibrary are used for interfacing pushbuttons of UP2 to the inputs of moore1011 circuit. Figure 10.6 shows the complete schematic of the Detector circuit for programming a UP2 device.

Figure 10.5 Moore Detector Symbol

Figure 10.6 Detector System Description

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After the completion of design entry phase the design is compiled in Quartus II. This phase synthesizes the Verilog parts of the design and pulls together other cell-based and gate-level parts into a complete device programming file.
10.2.4 Compilation and Synthesis

By compiling the design of Figure 10.6 it is synthesized and proper programming files are created for it. In addition various timing and floorplan views become available. For the moore1011 component a portion of its RTL view that is its post-synthesis netlist is shown in Figure 10.7. This netlist is generated for the FLEX 10K device being used as the synthesis target. This schematic shows the use of three flip-flops for implementing states of our detector circuit. AND-OR logic is used for flip-flop inputs.

Figure 10.7 RTL View of moore1011

10.2.5 Device Programming and Testing As previously discussed either of the two UP2 devices can be programmed with the hardware of Figure 10.6. We have chosen the EPM7128S device for this design and Table 10.1 shows its corresponding pin settings. Pin numbers are also shown in Figure 10.6 in block IO tables. The complete design of Detector including moore1011 and its pushbutton interfaces uses 34 of the 128 macrocells of the EPM7128S device. For testing the design the input and the clock are connected to UP2 pushbuttons and the circuit reset is connected to a UP2 switch. Use of a pushbutton for the clock allows manual slow operation of the circuit and thus

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pushbuttons are debounced by using Pulser2 from our BookLibrary. The debounced PB2 is put into OnePulser so that with each release of the pushbutton a positive pulse is generated. This output provides the clock signal for moore1011. The other debounced output of Pulser2 that corresponds to PB1 is directly connected to the Moore machines Xin input (this is a level input). The circuit operates when its reset input switch is in the off position (SW1 must be down).

To test the circuit hold down both pushbuttons and release and push PB2 several times to make sure the machine is in its initial state. Then release PB1 (this puts a 1 on Xin) and release and push PB2 to clock the circuit. Repeat this process for clocking a 0 and then two 1s into the circuit through its Xin release of PB2 (rising edge of the clock) the a-segment of input. With the SSD1 of MAX turn off which means that Zout has become 1. Since the circuit is clocked and all Xin values are taken on the edge of Clk, we could test the circuit without using a debouncer for PB1 (the Xin input).

10.3 Summary
This chapter used a state machine example to demonstrate how a behavioral Verilog that is synthesizable could be used in a design and after synthesis incorporated with the other components of the design. We showed the procedure for simulating our behavioral design outside of Quartus II and after verifying it bringing it into Quartus II.