2020 International Conference on Advanced Computing and Applications (ACOMP)

Advanced On-Chip Variation in Static Timing

Analysis for Deep Submicron Regime*
1st Duy Manh Thi Nguyen 2nd Van Quang Tran
2020 International Conference on Advanced Computing and Applications (ACOMP) | 978-1-7281-8167-7/20/$31.00 ©2020 IEEE | DOI: 10.1109/ACOMP50827.2020.00026

Faculty of Electronics and Telecommunications Faculty of Computer Engineering

VNUHCM-University of Science VNUHCM-University of Information Technology
Ho Chi Minh City, Vietnam Ho Chi Minh City, Vietnam
[email protected] [email protected]

3rd Anh Hai Nguyen 4th Minh Son Nguyen

Faculty of Computer Engineering Faculty of Computer Engineering
VNUHCM-University of Information Technology VNUHCM-University of Information Technology
Ho Chi Minh City, Vietnam Ho Chi Minh City, Vietnam
[email protected] [email protected]

Abstract—As technology scales into the deep submicron Based on the derate factors calculated in advance, AOCV is
regime, On-Chip Variation (OCV) has become a dominant factor introduced in this work for static timing analysis at nanometer
which influences the performance and yield of the circuits. process. AOCV provides an incremental step between the
Considering OCV analysis in Static Timing Analysis (STA) tools
is therefore one of the most crucial issues in VLSI designs global OCV margins and the true statistical analysis based
nowadays. Advanced OCV (AOCV) technique is widely deployed on actual variations. Although it is not the solution for the
in industry to account for OCV effects at smaller geometries. In burden of the growing STA scenario matrix, AOCV does
this paper, the first incremental AOCV methodology is proposed provide design teams a tool to reduce the number of timing
to implement variation parameters for On-Chip deep submicron. fixes per scenario. This is a good solution between OCV
This approach has been implemented in an industrial place-
and-route tool with high speed design consisting of data and and Statistical Static Timing Analysis (SSTA) with the right
clock paths. The experimental results on industrial designs show balance of accuracy and run-time [3].
that the optimization flow of path-based AOCV technique can In this work, in-depth analysis on AOCV model will be
significantly reduce the pessimism and improve the final Quality discussed focusing deeper on the path-based approach which
of Results (QoR) compared to the traditional OCV. Specifically, enhances the pessimism reduction capability of the AOCV.
evaluation results show that the proposed AOCV model has over
30% with clock only and 25% with clock and data lesser than
Only single derate value is used for the path-based OCV whilst
the traditional OCV in total violation paths. Furthermore, the AOCV derate table is implemented for the path-based AOCV.
proposed AOCV model also performs about 37% with clock only The rest of this paper is organized as follows. In Section II
and 26% with clock and data lesser than the traditional OCV is the model of the path-based AOCV. Section III describes
in total violation endpoints. the setting of the simulation environment. Simulation results
Index Terms—Deep Submicron, Static Timing Analysis (STA),
On-Chip Variation (OCV), Advanced OCV (AOCV), Global OCV
and evaluation then come in Section IV. Finally, in Section V
(GOCV) is the conclusion.
II. PATH-BASED AOCV MODEL
I. I NTRODUCTION
A. Path-based Analysis (PBA)
On-chip variation (OCV) analysis for 130nm technology
The AOCV analysis solutions can be categorized into path-
was used to add margin to the timing paths to account for
based analysis (PBA) and graph-based analysis (GBA) [9],
the aggregate number of total variations from a plethora of
[10], which are refinement strategies over traditional STA.
variation sources. It is also known as a single derate OCV. The
The recommended flow for timing signoff is to perform both
OCV derate factor bounds the timing delay within a specified
graph-based AOCV solution and path-based AOCV solution
range such as the worst-case early bound at 3 nanoseconds and
for refinement of critical paths. PBA is commonly performed
worst-case late bound at 6 nanoseconds for the third buffer.
after few iterations of GBA for additional pessimism reduction,
However, the OCV derate bounding becomes too pessimistic
especially when there are still violating critical paths to be
at nanometer process node. Implementation of global OCV
analyzed. PBA performs path-specific recalculation on crit-
on a design circuit highly requires design knowledge and
ical paths using path-specific path-depth and location-based
justification [1], [2].
bounding box values to determine path-specific derate values
*This work is supported by the University of Information Technology - [3]. The relative pessimism of each OCV method is shown in
Vietnam National University Ho Chi Minh City under grant No. D1-2020-14. Figure 1.

2688-0202/20/$31.00 ©2020 IEEE 130

DOI 10.1109/ACOMP50827.2020.00026

Authorized licensed use limited to: San Francisco State Univ. Downloaded on June 25,2021 at 06:01:28 UTC from IEEE Xplore. Restrictions apply.
 corner. Libraries and AOCV derate tables are all provided by
the foundry.
Simulations are carried out for path-based analysis using
both OCV method and AOCV method. Only one OCV derate
is chosen in this case. AOCV derate table used for path-based
analysis is shown in TABLE I. This table also depicts selection
of different derate values from different points or cells.
Fig. 1. Pessimism reduction for different On Chip Variation methods [3].
Subsequently, the conditions for two test cases are stated in
TABLE II. The condition for both cases is similar except for
B. Depth-based AOCV the derate factor as only one value is needed for OCV.
AOCV approach can be further refined as depth-based and AOCV derate table is shown in Figure 3.
distance-based analyses [3]–[6]. Figure 2 shows an example of
circuit with launch cell path depth of six and capture cell path
depth of three from a common point. From the path depths
determined by Prime Time tool, the appropriate values from
AOCV table can be annotated.
In a timing path, the launch signal is the same as the
capture one which passes through a common point. Thus,
without loss of generality the common point is assumed as zero
variation. From the common point, Prime Time tool counts
the cell path depths and is looking up the AOCV derate on
the derate table corresponding to the determined path depths.
By assuming zero variation in the common path, a net path
Fig. 3. AOCV table with derate factor applied for clock path and data path.
distance can be determined by the diagonal of a box that
encompasses all the nets in the path. Subsequently, the cell
path distance is determined by computing the diagonal of a IV. R ESULT AND D ISCUSSION
box that encompasses all the cells in the path.
TABLE III and TABLE IV show the number of violation
Path-based AOCV analysis performs recalculation on spe-
paths for OCV analysis and AOCV analysis whilst the range
cific critical paths with advanced algorithm to reduce pes-
signifies the different ranges of data as indicated by the
simism. However, as the number of paths analyzed increases
number in bracket. As shown in tables the OCV and AOCV
the run time can increase exponentially. Therefore, the AOCV
analysis results are very comparable. However, the results
path-based analysis should be used only after a few iterations
clearly indicate distinct advantages; namely, AOCV has about
of the graph-based analysis and timing fixing, where the design
30% for clock only and 25% for clock and data lesser than
is already brought closest to the timing closure. If there still
OCV in the total violation paths.
exist too many violating paths needing analyzing in AOCV
Figure 4 and Figure 5 show the number of violation end-
path-based mode, the run time could be too long for real chip
points for OCV analysis and AOCV analysis whilst the range
synthesis [6]–[8].
signifies the different ranges of data as indicated by the number
in bracket. The results clearly indicate distinct advantages of
AOCV compared with OCV. Specifically, AOCV is about 37%
(OCV: 89 endpoints, AOCV: 56 endpoints) with clock only
and 26% (OCV: 122 endpoints, AOCV: 102 endpoints) with
clock and data lesser than OCV in total violation endpoints.
Besides the slack violation rate of AOCV is much lower than
OCV.
Because the data of the design is not complete yet, timing
analysis based on the AOCV model has not been highly
accurate. The proof is that in Figure 4 and Figure 5 there
are several intervals where the number of violation endpoints
of AOCV is greater than that of OCV.
Fig. 2. Depth-based AOCV [4].
For further comparison, the results of the proposed AOCV
in [1] are expressed in Figure 6. Note that, for the ease of
III. DESIGN SETUP OF AOCV MODEL understanding, we converted the results in tabular form in [1]
The timing analysis is simulated using Synopsys Prime to the chart form. Figure 6 shows that the number of violation
Time static timing analysis tool. PVT corners are covered for endpoints with AOCV model in [1] is not much better than
timing closure including fast corner, slow corner, and typical the OCV model. This indicates that the derate factor applied

131

Authorized licensed use limited to: San Francisco State Univ. Downloaded on June 25,2021 at 06:01:28 UTC from IEEE Xplore. Restrictions apply.
 TABLE I Point Derate Increment Path
A NNOTATED AOCV DERATE TABLE WITH TIMING REPORT I CLOCK GEN/
1.0000 0.0516 & 0.4617 f
invbdkG2B2I1/I (invbdk)
Point Derate Increment Path I CLOCK GEN/
clock SDRAM CLK invbdkG2B2I1/ZN 1.0670 0.0370 & 0.4987 r
0.0000 0.0000
(rise edge) (invbdk)
clock network delay I CLOCK GEN/U18/I
0.0000 0.0000 1.0000 0.0506 & 0.5492 r
(propagated) (invbdk)
input external delay 0.2000 0.2000 f I CLOCK GEN/U18/ZN
sd DQ [15] (inout) 0.0000 0.2000 f 1.0670 0.0470 & 0.5962 f
(invbdk)
sdram DQ iopad 15/PAD I CLOCK GEN/U15/I
1.0000 0.0478 0.2478 f 1.0000Z 0.0505 & 0.6467 f
(pc3b05) (invbdk)
sdram DQ iopad 15/CIN I CLOCK GEN/U15/ZN
0.9140 0.4716& 0.7194 f 1.0670 0.0305 & 0.0772 r
(pc3b05) (invbdk)
I ORCA TOP/ I CLK SOURCE SDRAM CLK/I
I SDRAM IF/ 1.0000 0.0074 & 0.6846 r
(bufbda)
sdram DQ iopad 1.0000 0.0042 & 0.7236 f I CLK SOURCE SDRAM CLK/Z
15ASTfhIns938/ I 1.0670 0.1966 & 0.8812 r
(bufbda)
(buffd1) bufbdaG5B1I6/I (bufbda) 1.0000 0.0421& 0.9233 r
I ORCA TOP/ bufbdaG5B1I6/Z (bufbda) 1.0950 0.1676 & 1.0909 r
I SDRAM IF/ I ORCA TOP/
sdram DQ iopad 0.9140 0.0898 & 0.8134 f bufbdaG5B2I38/I 1.0000 0.0339 & 1.1248 r
15ASTfhIns938/Z (bufbda)
(buffd1) I ORCA TOP/
I ORCA TOP/ bufbdaG5B2I38/Z 1.1000 0.1633 & 1.2881 r
I SDRAM IF/ (bufbda)
sdram DQ iopad 1.0000 0.0042 & 0.8177 f I ORCA TOP/I SDRAM
15ASTfhIns1079/I IF/DQ in 0 reg [15]/CP 1.0000 0.0942 & 1.3823 r
(buffd1) (sdnrb1)
I ORCA TOP/ libraries hold time 1.0000 -0.0495 1.3328
I SDRAM IF/
data required time 1.3328
sdram DQ iopad 0.9140 0.0848 & 0.9024 f
slack -04224
15ASTfhIns1079/Z
(buffd1)
I ORCA TOP/
I SDRAM IF/
1.0000 0.0080 & 0.9104 f
DQ in 0 reg [15]/D
(sdnrb1)
data arrival time 0.9104 TABLE II
Clock SDRAM CLK S IMULATION CONDITIONS FOR PATH - BASED ANALYSIS OCV AND AOCV
0.0000 0.0000
(rise edge)
sdr clk (in) 0.0000 0.0000r Test case Corner Derate Analysis type
sdr clk iopad/PAD Fast corner, 3V, OCV 1.1 late –
1.0000 0.0465 0.0465 r 1 PBA
(pc3d01) -40C 0.9 early
sdr clk iopad/CIN Fast corner, 3V,
1.0670 0.8129 & 0.8594 r 2 AOCV table PBA
(pc3d01) -40C
I CLOCK GEN/
I PLL SD/ REF CLK 1.0000 0.0322 & 0.8916 r
(PLL)
I CLOCK GEN/
1.0670 -1.0648 * -0.1732 r
I PLL SD/ CLK (PLL)
I CLOCK GEN/
invbdkG1B1I1 2/I 1.0000 0.0575 & -0.1157 r TABLE III
(invbdk) V IOLATION PATHS OF OCV AND AOCV WITH CLOCK ONLY
I CLOCK GEN/
OCV clock only AOCV clock only
invbdkG1B1I1 2/ZN 1.0670 0.0616 & -0.0541 f
Setup Hold Setup Hold
(invbdk)
1 110 1 110
I CLOCK GEN/
1.0000 0.0514 & -0.0027 f
invbdkG1B2I1/I (invbdk)
I CLOCK GEN/
invbdkG1B2I1/ZN 1.0670 0.0310 & 0.0284 r
(invbdk)
I CLOCK GEN/U22/I0
1.0000 0.0039 & 0.0323 r
(mx02d2) TABLE IV
I CLOCK GEN/U22/Z V IOLATION PATHS OF OCV AND AOCV WITH CLOCK AND DATA
1.0670 0.2573 & 0.2895 r
(mx02d2)
I CLOCK GEN/ OCV clock and data AOCV clock and data
invbdkG2B1I1 2/I 1.0000 0.0565 & 0.3460 r Setup Hold Setup Hold
(invbdk) 14 126 6 112
I CLOCK GEN/
invbdkG2B1I1 2/ZN 1.0670 0.0641 & 0.4101 f
(invbdk)

132

Authorized licensed use limited to: San Francisco State Univ. Downloaded on June 25,2021 at 06:01:28 UTC from IEEE Xplore. Restrictions apply.
 Fig. 6. Results of AOCV model in [6]

Fig. 4. Number of violation endpoints of OCV and AOCV with clock only
than OCV. Positive results obtained indicate that our AOCV
model has potential to create better margin timing to calculate
delay of design by simulation tools compared to actual designs
running in the environment. With better margin timing, the
engineer will be able to analyze and fix timing for the STA
phase easier, and therefore the project schedule is reduced.
Since the resources involved are limited and the physical
file does not contain enough information about the location of
cells, nets, and flip flops, the proposed AOCV model lacks a
bit of accuracy. In the future, the data will be improved with a
more complete design resource to give the most comprehensive
assessment of this model.
ACKNOWLEDGMENT
This work is supported by the University of Information
Technology - Vietnam National University Ho Chi Minh City
under grant No. D1-2020-14.
R EFERENCES
[1] Chunyang Feni, Ritesh Shyamsukha, Shankar Radhakrishnan, Jianquan
Fig. 5. Number of violation endpoints of OCV and AOCV with clock and Zheng, Alice Gao, ”Accelerating Timing Closure Using Incremental
data Advanced OCV”, China Semiconductor Technology International Con-
ference, pp. 2158-2297, Shanghai, China, 15-16 March 2015.
[2] Pua Siaw Fuang, Nor Muzlifah Mahyuddin , ”Implementation Study of
Path-Based AOCV Model on Pessimism Reduction for 20nm Technol-
to the calculation for the AOCV model in [1] is not as good ogy,” IEEE International Conference on Control System, Computing and
as for our proposed AOCV model. Engineering, Penang, Malaysia, pp. 28 – 30, November 2014.
[3] Sunil Walia, ”PrimeTime® Advanced OCV Technology,” Synopsys,
V. C ONCLUSION April 2009.
[4] Mutlu, K. Le, M. Celik, D. Tsien, G. Shyu, L.C. Yeh, ”An exploratory
In this paper, we have introduced an advanced model of study on statistical timing analysis and parametric yield optimization”,
AOCV for static timing analysis at nanometer process. The ISQED Proceedings, pp. 677-684, 2007.
[5] P.S. Fuang and N.M. Mahyuddin, “Implementation Study of Path-
results clearly indicate distinct advantages of the proposed Based AOCV Model on Pessimism Reduction for 20nm Technology”,
AOCV model compared with the traditional OCV. Namely, the IEEE International Conference on Control System, Computing and
proposed AOCV shows about 30% with clock only and 25% Engineering, pp. 28 – 30, November 2014.
[6] G. Petrosyan, S. Abovyan, and T. Harutyunyan, “Modelling on-chip vari-
with clock and data lesser than OCV in total violation paths. ations in digital circuits using statistical timing analysis,” In proceedings
Besides, it is advantageous that our AOCV model has over of Design Test Symposium, pp. 37-39, 2010.
37% with clock only and 26% with clock and data lesser than [7] E.E. Rabab, M. Ali, and H. Hamed, “Analysis and Design of Networks-
on-Chip under High Process Variation”, Springer, pp. 57-68, 2015.
OCV in total violation endpoints. Furthermore, the large slack [8] J. Bhasker and R. Chadha, “Static Timing Analysis for Nanometer
violation rate of the proposed AOCV model is much lower Designs: A Practical Approach”, Springer, pp. 365 – 466, 2009.

133

Authorized licensed use limited to: San Francisco State Univ. Downloaded on June 25,2021 at 06:01:28 UTC from IEEE Xplore. Restrictions apply.
 [9] W. Huang and M. Wong, “Accelerated path-based timing analysis with
MapReduce,” ISPD, pp. 103-110, Mar. 2015.
[10] R. Shaikh and V. Rajan, “Gradient AOCV methodology enabling graph-
based timing closure with AOCV timing models,” U.S. Patent No. 8806,
413, 12 Aug. 2014.

134

Authorized licensed use limited to: San Francisco State Univ. Downloaded on June 25,2021 at 06:01:28 UTC from IEEE Xplore. Restrictions apply.