Computer Organization

Fall 2021
Lecture 11
 Memory Organization
(

• The memory unit is an essential component in any digital computer since it is needed for storing
programs and data.
• The memory unit that communicates directly with the CPU is called the main memory.
• Devices that provide backup storage are called auxiliary memory.
• They are used for storing system programs, large data files, and other backup information.
• Only programs and data currently needed by the processor reside in main memory.
• All other information is stored in auxiliary memory and transferred to main memory when
needed.
• A special very-high-speed memory called a cache is sometimes used to increase the speed of
processing by making current programs and data available to the CPU at a rapid rate.
 Memory Hierarchy
(

 Fig.1 shows the Memory Hierarchy:

Auxiliary memory
Magnetic
tapes I/O Main
processor memory
Magnetic
disks

CPU Cache
memory
 Main Memory
(

 The main memory is the central storage unit in a computer system.

 It is a relatively large and fast memory used to store programs and data during the computer operation.

 The principal technology used for the main memory is based on semiconductor integrated circuits.

 Integrated circuit RAM chips are available in two possible operating modes:

 The static RAM consists essentially of internal flip-flops that store the binary information.

 The dynamic RAM stores the binary information in the form of electric charges that are applied to capacitors.
 Access Methods

 Random

 Individual addresses identify locations exactly

 Access time is independent of location or previous access

 e.g. RAM

 Associative

 Data is located by a comparison with contents of a portion of the store

 Access time is independent of location or previous access

 e.g. cache
 Block diagram of RAM

❑ This block diagram introduces RAM.

2k x n memory
 A Chip Select, CS, enables or disables the RAM.
k n
ADRS specifies the address or location to read from or write to. ADRS OUT
 n
DATA
 WR selects between reading from or writing to the memory. CS
WR
To read from memory, WR should be set to 0.
OUT will be the n-bit value stored at ADRS.
CS WR Memory operation
To write to memory, we set WR = 1. 0 x None
DATA is the n-bit value to save in memory. 1 0 Read selected word
1 1 Write selected word
 Memory sizes
❑ We refer to this as a 2k x n memory. 2k x n memory
 There are k address lines, which can specify one of 2k addresses.
k n
ADRS OUT
 Each address contains an n-bit word. n
DATA
CS
WR

❑ For example, a 224 x 16 RAM contains 224 = 16M words, each 16 bits long.
 The RAM would need 24 address lines.
 The total storage capacity is 224 x 16 = 228 bits.

❑ With the abbreviations below

Prefix Base 2 Base 10
10 3
K Kilo 2 = 1,024 10 = 1,000
M Mega 220 = 1,048,576 106 = 1,000,000
G Giga 230 = 1,073,741,824 109 = 1,000,000,000
 Reading RAM

❑ To read from this RAM, the controlling circuit must:

2k x n memory
 Enable the chip by ensuring CS = 1.
k n
ADRS OUT
n
 Select the read operation, by setting WR = 0. DATA
CS
 Send the desired address to the ADRS input. WR

 The contents of that address appear on OUT after a little while.

❑ Notice that the DATA input is unused for read operations.

 Writing RAM

❑ To write to this RAM, you need to: 2k x n memory

k n
 Enable the chip by setting CS = 1. ADRS OUT
n
DATA
 Select the write operation, by setting WR = 1. CS
WR
 Send the desired address to the ADRS input.

 Send the word to store to the DATA input.

❑ The output OUT is not needed for memory write operations.

 Associative Memory

 Many data-processing applications require the search of items in a table stored in memory.

 A memory unit accessed by content is called an associative memory or content addressable

memory (CAM).

 When a word is written in an associative memory is capable of finding an empty unused

location to store the word.

 When a word is to be read from an associative memory, the content of the word, or part of

the word, is specified.

 The memory locates all words which match the specified content and marks them for reading.
 Associative Memory
 The block diagram of an associative memory is shown in Fig(30):
 Example

• suppose that the argument register A and the key register K have the bit configuration shown below.
• Only the three left most bits of A are compared with memory words because K has l's in these
positions.
 Cache Memory
 If the active portions of the program and data are placed in a fast small memory, the average
memory access time can be reduced, thus reducing the total execution time of the program.

 Such a fast small memory is referred to as a cache memory.

 It is placed between the CPU and main memory.

 The basic operation of the cache is as follows.

 When the CPU needs to access memory, the cache is examined.

 If the word is found in the cache, it is read from the fast memory.

 If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the
word.

 The performance of cache memory is frequently measured in terms of a quantity called hit ratio.
 When the CPU refers to memory and finds the word in cache, it is said to produce a hit.

 If the word is not found in cache, it is in main memory and it counts as a miss.
Cache Read Flowchart
Cache and Main Memory
 Cache and Main Memory
Year of
Processor Type L1 cache L2 cache L3 cache
Introduction
IBM 360/85 Mainframe 1968 16 to 32 KB — —
PDP-11/70 Minicomputer 1975 1 KB — —
VAX 11/780 Minicomputer 1978 16 KB — —
IBM 3033 Mainframe 1978 64 KB — —
IBM 3090 Mainframe 1985 128 to 256 KB — —
Intel 80486 PC 1989 8 KB — —
Pentium PC 1993 8 KB/8 KB 256 to 512 KB —
PowerPC 601 PC 1993 32 KB — —
PowerPC 620 PC 1996 32 KB/32 KB — —
PowerPC G4 PC/server 1999 32 KB/32 KB 256 KB to 1 MB 2 MB
IBM S/390 G4 Mainframe 1997 32 KB 256 KB 2 MB
IBM S/390 G6 Mainframe 1999 256 KB 8 MB —
Pentium 4 PC/server 2000 8 KB/8 KB 256 KB —
High-end server/
IBM SP 2000 64 KB/32 KB 8 MB —
supercomputer
CRAY MTAb Supercomputer 2000 8 KB 2 MB —
Itanium PC/server 2001 16 KB/16 KB 96 KB 4 MB
SGI Origin 2001 High-end server 2001 32 KB/32 KB 4 MB —
Itanium 2 PC/server 2002 32 KB 256 KB 6 MB
IBM POWER5 High-end server 2003 64 KB 1.9 MB 36 MB
CRAY XD-1 Supercomputer 2004 64 KB/64 KB 1MB —
Thank you