PICOBLAZE DESIGN

Intro. to Embedded Systems - EHB326E

SERDAR DURAN
ITU Embedded System Design Laboratory

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 Picoblaze Design Steps
I. Write your algorithm as an Assembly Code
II. Simulate your Assembly Code in Fidex IDE
III.Generate your instruction memory from Fidex IDE
IV. Combine your instruction memory and picoblaze design in Vivado
(implementation of the picoblaze in an FPGA)
V. Write a testbench file to make a simulation.
VI. Make your simulations in Xilinx Vivado

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 Vivado and Fidex Environments
• Install one of the recent version of Xilinx Vivado:
https://www.xilinx.com/support/download.html

• Install Fidex IDE – FIDEx 2016-01.0:

https://www.fautronix.com/en/en-fidex-downloads

• Download the ‘‘PicoBlaze for UltraScale, 7-series, 6-series FPGAs’’ design files:
https://www.xilinx.com/products/intellectual-property/picoblaze.html#design

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 Picoblaze Overview

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 Picoblaze
• The PicoBlaze processor is a simple 8-bit microcontroller specifically designed and
optimized for Xilinx FPGA devices.
• Basic Features:
• 8-bit data width,
• 8-bit ALU with carry and zero flags,
• 16 8-bit general-purpose registers,
• 64-byte data memory (Scratchpad RAM, 64*8 bit),
• 8 input and 8 output pins,
• 8 bit port identifier, meaning 256 addressable input and output ports,
• 2 clock cycles per each instruction.

*Link: PicoBlaze 8-bit Embedded Microcontroller User Guide

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 Interfaces
• IN_PORT [7:0] : 8-bit data
• OUT_PORT [7:0] : 8-bit data
• PORT_ID [7:0] : port address for both
INPUT and OUTPUT pins

• READ_STROBE : indicating input

operation is done
• WRITE_STROBE : indicating output
operation is done

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 Instruction Format
• Instruction Format:
• op sX,sY ; register-register format. sX = sX op sY
• op sX,KK ; register-constant format. sX = sX op KK
• op sX ; single-register format. sX = op sX
• op AAA ; single-address format (jump and call operations).

• Instruction Types:
• Arithmetic
• Logical
• Shift and Rotate
• Data Transfer
• Branch Instructions

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 Instruction Set
• Arithmetic Instructions: ADD, ADDC, SUB, SUBC
• ADD sX, constant ; sX = sX + constant
• ADD sX, sY ; sX = sX + sY

• ADDC sX, constant ; sX = sX + constant + carry bit

• ADDC sX, sY ; sX = sX + sY + carry bit

• Logical Instructions: AND, OR, XOR

• AND sX, constant ; sX = sX & constant
• AND sX, sY ; sX = sX & sY

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 Instruction Set
• Comparison Instructions: COMP, COMPC, TEST, TESTC
• COMP sX, sY ; if regY > regX, then set CARRY, if regY = regX then set ZERO flag.
• COMP sX, const ; if regY > const, then set CARRY, if regY = regX then set ZERO flag.

• Shift and Rotate: SL0, SL1, SLA, SLX, SR0, SR1, SRA, SRX, RL, RR
• SL0 sX ; shift register sX left, zero fill
• SR1 sX ; shift register sX right, one fill

• Branch Instructions: JUMP, RETURN

• JUMP aaa ; Unconditionally jump to aaa label
• JUMP C aaa ; If CARRY flag set, jump to aaa label
• JUMP Z aaa ; If ZERO flag set, jump to aaa label

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 Instruction Set
• Data Transfer Instructions: LOAD, FETCH, STORE, INPUT, OUTPUT
• LOAD sX, constant ; Load register sX with constant
• LOAD sX, sY ; Load register sX with sY

• WRMEM sX, scrpdAddr ; store regX into the memory at address scrpdAddr.
• WRMEM sX, ( sY ) ; store regX into the memory at address (sY).

• RDMEM sX, scrpdAddr ; fetch the value at address scrpdAddr into the sX.
• RDMEM sX, ( sY ) ; fetch the value at address (sY) into the sX.

• WRPRT sX, busAddr ; output value on output port busAddr

• RDPRT sX, (sY) ; input value on input port (sY)

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 Fidex Part

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 Default Specifications for Verilog
#ifDef proc::xPblze6
Picoblaze 6 Configs
; PICOBLAZE 6 CONFIGs
• Scratchpad RAM size
#set proc::xPblze6:: scrpdSize, 64 ; [64, 128, 256]
#set proc::xPblze6:: clkFreq, 100000000 ; in Hz
• Clock frequency

; INST MEMORY SPECs

#set IOdev::BRAM0:: en, TRUE
#set IOdev::BRAM0:: type, mem
Instruction Memory Settings
#set IOdev::BRAM0:: size, 4096
• Page Size
#set instmem:: pageSize, 4096
#set instmem:: pageCount, 1
• Page number
#set instmem:: sharedMemLocation, loMem ;[ hiMem, loMem ]
#set IOdev::BRAM0:: value, instMem

; VERILOG OUTPUT FILES

#set IOdev::BRAM0:: verilogEn, TRUE
#set IOdev::BRAM0:: verilogEntityName, "BRAM0" Verilog Output File Settings
#set IOdev::BRAM0:: verilogTmplFile, "ROM_form.v" • ROM_form.v is a template
#set IOdev::BRAM0:: verilogTargetFile, "BRAM0.v" • BRAM0.v is the Verilog output for
#endIf instruction memory

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 Default Specifications for VHDL
#ifDef proc::xPblze6
; PICOBLAZE 6 CONFIGs
#set proc::xPblze6:: scrpdSize, 64 ; [64, 128, 256]
#set proc::xPblze6:: clkFreq, 100000000 ; in Hz

; INST MEMORY SPECs

#set IOdev::BRAM0:: en, TRUE
#set IOdev::BRAM0:: type, mem
#set IOdev::BRAM0:: size, 4096
#set instmem:: pageSize, 4096
#set instmem:: pageCount, 1
#set instmem:: sharedMemLocation, loMem ;[ hiMem, loMem ]
#set IOdev::BRAM0:: value, instMem

; VERILOG OUTPUT FILES

#set IOdev::BRAM0:: vhdlEn, TRUE
#set IOdev::BRAM0:: vhdlEntityName, "BRAM0" VHDL Output File Settings
#set IOdev::BRAM0:: vhdlTmplFile, "ROM_form.vhd" • ROM_form.vhd is a template
#set IOdev::BRAM0:: vhdlTargetFile, "BRAM0.vhd" • BRAM0.vhd is the VHDL output for
#endIf instruction memory

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 Example - Fidex
Program Counter

Flags (Carry, Zero, Interrupt_Enable)

; starting address
#ORG ADDR, 0

LOAD s0, 0
LOAD s1, 1

loop: ADD s0, s1

COMP s0, 63
WRMEM s0,(s0)
JUMP C, loop
General Purpose Registers
Simulation
end: JUMP end

; fill the scratchpad RAM with

values 0 to 63 (0x3F)

Scratchpad RAM

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 Instruction Set
Manual
help->content

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 Generate the HDL output Reset Run all the
of instruction memory Simulation codes

Run Simulate Give an Simulate Next Change the

Assembler your code external instruction numeric base
interrupt

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 Coding Steps
1) Open or Create a new project
2) Make a configuration for your project
• Xilinx Picoblaze 6
• Scratchpad Size 64
• Interrupt vector address 1023
• Clock frequency 100 MHz
3) Write the default specifications (Verilog or VHDL)
4) Write your Assembly code
5) Run Assembler
6) Make a Simulation
7) Generate the HDL file if there is no problem with your code.
8) BRAM0.v or BRAM0.vhd will be your instruction memory file.

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 Vivado Part

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 Creating Project
• Create a new project in Vivado and use either Nexys4 DDR board or xc7a100tcsg324-1 chip. (they
are same)
• Please look at the online tutorial here!

• To install the NEXSYS 4 DDR

boardfile click here!

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 Creating Project

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 Vivado Part
• Fidex IDE generates instruction memory according to your assembly code.
• Picoblaze projects are implemented by combining generated instruction memory and picoblaze
design file.
• You can write a top entity that combine BRAM0 (inst memory) and KCPSM6 (picoblaze) files.

BRAM0.vhd kcpsm6.vhd

top.vhd

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 • Include the generated BRAM0.vhd, kcpsm6.vhd and top.vhd as Design Sources.

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 Vivado Part
• After adding Design Files you can see the hierarchy between these files.
• To see your design works as expected you need to write a testbench file and add
it as a Simulation Source File.

Top entity includes inst_memory and picoblaze

Picoblaze (kcpsm6.vhd)

instruction memory (BRAM0.vhd)

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 • Include the top_tb.vhd as a Simulation Source.

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 Vivado Part
• Hierarchy between these entities (files):

Top entity includes inst_memory and picoblaze

Picoblaze (kcpsm6.vhd)

instruction memory (BRAM0.vhd)

Testbench file for simulation (top_tb.vhd)

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 Vivado Part
• If the top_tb.vhd testbench is not seen as top entity (bald) ‘‘ right click->Set as Top’’ this
entity.

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 • After adding the design files and top_tb.vhd simulation file you can make a simulation
for your design.

To add design and simulation files

Click Run Behavioral Simulation

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 • After running behavioral simulation you can see the waveform of the ports and signals of the
picoblaze.

Picoblaze and Inst_memory

entities inside the top entity Ports and Signals waveform

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 Advance the simulation(waveform)
for 1 us more Restart the Simulation

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 • Values of registers, buses, ports, ram etc. can be found from the scope and objects section
• Drag these objects to the waveform and restart the simulation.

Spad Memory Values Spad Memory Values in the time diagram

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 library IEEE;
use IEEE.STD_LOGIC_1164.ALL; top_tb.vhd - Testbench File
entity top_tb is
end top_tb;

architecture Behavioral of top_tb is

component top is
Port ( clk : in STD_LOGIC;
in_port : in STD_LOGIC_VECTOR (7 downto 0);
port_id : out STD_LOGIC_VECTOR (7 downto 0);
out_port : out STD_LOGIC_VECTOR (7 downto 0);
Ports of the top file
write_strobe : out STD_LOGIC;
read_strobe : out STD_LOGIC;
interrupt : in STD_LOGIC;
interrupt_ack : out STD_LOGIC );
end component top;

signal clk : STD_LOGIC;

signal in_port : STD_LOGIC_VECTOR(7 downto 0);
signal port_id : STD_LOGIC_VECTOR(7 downto 0);
signal out_port : STD_LOGIC_VECTOR(7 downto 0);
signal write_strobe : STD_LOGIC;
signal read_strobe : STD_LOGIC;
signal interrupt : STD_LOGIC;
signal interrupt_ack : STD_LOGIC;

begin
uut: top
port map( clk => clk, in_port => in_port, port_id => port_id, out_port => out_port, write_strobe =>
write_strobe, read_strobe => read_strobe, interrupt => interrupt, interrupt_ack => interrupt_ack ); Port connections
process
begin
clk <= '0'; wait for 5ns;
clk <= '1'; wait for 5ns; Clock signal 10ns period
end process;

end Behavioral;

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 `timescale 1ns / 1ps top_tb.v - Testbench File

module top_tb();
reg clk = 1'b0;
reg [7:0] in_port;
wire [7:0] port_id;
wire [7:0] out_port;
wire write_strobe;
wire read_strobe;
reg interrupt;
wire interrupt_ack;
Clock signal 10ns period
always #5 clk = ~clk;

top UUT(
.clk(clk),
.in_port(in_port),
.port_id(port_id),
.out_port(out_port), Port connections of the top file
.write_strobe(write_strobe),
.read_strobe(read_strobe),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack)
);

endmodule

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 Implementation of the Picoblaze in an FPGA
1) Create a new project in Vivado.
2) Take kcpsm6.vhd and BRAM0.vhd (generated from Fidex IDE) design files and
add them as design sources.
3) Take top.vhd file that provided for you or write a new one and add it as a
Design Source.
4) Take top_tb.vhd or top_tb.v file that provided for you or write a new one and
add it as a Simulation Source.
5) Run Behavioral Simulation and check the objects and waveform to see your
algorithm works properly.

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 Vivado Block Design

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 Vivado Block Design
• Any blocks (entities) can be included into a project alongside with the Picoblaze.
• You can add predefined IP Blocks in Vivado (like Block RAM).
• You can also add your own designed entities.

• An Example:

Com.
Block RAM #1 Picoblaze Interface #2 Picoblaze
(e.g. UART)

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 Vivado Block Design
• Create a project and add BRAM0.vhd, kcpsm6.vhd and top.vhd files into this project as Design
Sources.
• Then click ‘‘Create Block Design’’ .

• Let the design

name as top.

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 • Drag top.vhd file into the Diagram window.

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 • To create the ports ‘’right click->make external’’

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 • You can change the names of the ports.

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 Including a Block RAM
• Click IP Catalog
• Type Block Memory Generator

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 • Add IP to Block Design

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 • Double click to customize Block RAM

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 • Change the default specifications:

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 • We have 8-bit bus.
( Picoblaze is an 8-bit
microcontroller )
• 256 different locations
can be addressable.
(Port id is 8 bit)

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 • After customizing Block RAM, make the following connections:
• port_id to addra
• out_port to dina
• in_port to douta
• Create ena and wea ports.

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 • Right click on design_1 -> Create HDL Wrapper

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 • A top entity called design_1_wrapper is generated by Vivado.
• design_1_wrapper combines the top (picoblaze + inst memory) and Block RAM.

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 BRAM0.vhd kcpsm6.vhd

top.vhd Block RAM

design_1_wrapper

Testbench

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 • Write a testbench file and add it as a Simulation Source File.
`timescale 1ns / 1ps block_design_verilog_tb.v - Testbench File

module block_design_verilog_tb();
reg clk = 1'b0;
reg ena;
reg [0:0] wea;
reg interrupt;
wire interrupt_ack;
wire read_strobe;
wire write_strobe;
wire k_write_strobe;
Clock signal 10ns period
always #5 clk = ~clk;

design_1_wrapper UUT(
.clk(clk),
.ena(ena),
.wea(wea),
.interrupt(interrupt), Port connections of the
.interrupt_ack(interrupt_ack),
design_1_wrapper file
.read_strobe(read_strobe),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe)
);

endmodule

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 library IEEE;
use IEEE.STD_LOGIC_1164.ALL; block_design_tb.vhd - Testbench File
entity block_design_tb is
end block_design_tb;

architecture Behavioral of block_design_tb is

component design_1_wrapper is
port ( clk : in STD_LOGIC;
ena : in STD_LOGIC;
interrupt : in STD_LOGIC;
interrupt_ack : out STD_LOGIC;
Ports of the
k_write_strobe : out STD_LOGIC; desing_1_wrapper file
read_strobe : out STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
write_strobe : out STD_LOGIC
);
end component design_1_wrapper;

signal clk : STD_LOGIC;

signal ena : STD_LOGIC;
signal interrupt : STD_LOGIC;
signal interrupt_ack : STD_LOGIC;
signal k_write_strobe : STD_LOGIC;
signal read_strobe : STD_LOGIC;
signal wea : STD_LOGIC_VECTOR ( 0 to 0 );
signal write_strobe : STD_LOGIC;

begin
uut: design_1_wrapper
port map( clk => clk, ena => ena, interrupt => interrupt, interrupt_ack => interrupt_ack,
k_write_strobe => k_write_strobe, read_strobe => read_strobe, wea => wea, write_strobe => write_strobe); Port connections
process
begin
clk <= '0'; wait for 5ns;
clk <= '1'; wait for 5ns; Clock signal 10ns period
end process;

end Behavioral;

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 References
• Picoblaze user guide

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