ALPHA COLLEGE OF ENGINEERING

Approved by AICTE & affiliated to Anna University & ISO Certified

Thirumazhisai, Chennai-600 124

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

LAB MANUAL

CS3352 – DIGITAL PRINCIPLES & COMPUTER ORGANIZATION

LABORATORY
(II YEAR CSE/ III SEMESTER)

(REGULATION 2021)

PREPARED BY

Ms SUSHMITHA, ASSOCIATE PROFESSOR,

Department of Electronics & Communication

Engineering,

Alpha College of Engineering.

1
 INDEX
INDEX
EXPT.NO DATE NAME OF THE EXPERIMENT MARKS SIGN

STUDY OF LOGIC GATES

1. VERIFICATION OF BOOLEAN THEOREMS

DESIGN AND IMPLEMENTATION OF
2. COMBINATIONAL CIRCUITS USING GATES
ARBITARY FUNCTIONS

IMPLEMENTATION OF 4 – BIT BINARY

3.
ADDER/SUBTRACTOR

4. IMPLEMENTATION OF CODE COVERTERS

IMPLEMENTATION OF BCD ADDER, ENCODER,

5.
DECODER CIRCUITS

IMPLEMENTATION OF FUNCTIONS USING

6.
MULTIPLEXERS

7. IMPLEMENTATION OF SYNCHRONOUS COUNTERS

SIMULATION BASED STUDY OF COMPUTER

9.
ARCHITECTURE

IMPLEMENTATION OF A UNIVERSAL SHIFT

8.
REGISTER

2
AND gate:

3- Input AND gate:

3
AIM:

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. 2- I/P AND gate IC 7408 1
2. 3-I/P AND gate IC7411 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. 2- I/P NAND gate IC7400 1
6. 3-I/P NAND gate IC7410 1
7. NOR gate IC7402 1
8. EX-OR gate IC7486 1
9. IC Trainer Kit - 1
10. Patch cords - Few

THOERY:

Logic gates are the basic elements that make up a digital system. The gate is a digital
circuit with one or more inputs, but only one output. By connecting the different gates in
different ways, we can build circuits that perform arithmetic and other functions.
The operation of a logic gate can be easily understood with the help of “truth table”. A
truth table is a table that shows all the input-output possibilities of a logic circuit ie., the truth
table indicates the outputs for different possibilities of the inputs.
The types of gates available are the AND, OR, NOT, NAND, NOR, exclusive-OR and
the exclusive-NOR. Except for the exclusive-NOR gate they are available in monolithic
integrated form.
AND gate:
The AND gates has two or more inputs. It performs a logical multiplication. The output
is HIGH (1), when both the inputs are 1; otherwise the output from the gate is LOW (0). The
output from the AND gate is written as A.B.

4
OR gate:

NOT gate:

5
OR gate:
The OR gates has two or more inputs. It performs a logical addition. The output is
HIGH (1), if any of the inputs are 1; the output is LOW (0) if and only if all the inputs are 0.
The output from the OR gate is written as A+B.

NOT gate:
The NOT gate has only one input. It performs a basic logic function called inversion.
The output is HIGH (1), when the input is 0; the output is LOW (0) when the input is 1. The
output from the NOT gate is written as A’.

NAND gate:
The NAND gate is a contraction of AND-NOT. It has two or more inputs. The output
is HIGH (1), when any of the inputs are 0; the output is LOW (0), if and only if all the inputs
are 1. The output from the NAND gate is written as (A.B)’. It is a universal gate.

NOR gate:
The NOR gate is a contraction of OR-NOT. It has two or more inputs. The output is
HIGH (1), when all inputs are 0; the output is LOW (0), when any of the inputs are 1. The
output from the NOR gate is written as (A+B)’. It is a universal gate.

EX-OR gate:
The EX-OR gate has two or more inputs. The output is HIGH (1), when odd number of
inputs is 1. The output from the EX-OR gate is written as (AB).

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth table.

6
2- Input NAND gate:

3- Input NAND gate:

7
NOR gate:

EX-OR gate:

RESULT:
Thus the logic gates were studied and their truth tables were verified.

8
COMMUTATIVE LAW:
• AND: ( A.B = B.A )

VERIFICATION TABLE:

A B A.B B.A
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1

• OR: ( A+B = B+A )

VERIFICATION TABLE:
A B A+B B+A
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1

DEMORGAN’S LAW:
(A+B)’ = A’. B’

VERIFICATION TABLE:
A B (A+B)’ A’. B’
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

9
AIM:

To verify the following Boolean theorems using logic gates

1. Commutative Laws,
2. De Morgan ’s Laws,
3. Associative Laws,
4. Absorption Laws &
5. Distributive Laws.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1 IC Trainer Kit - 1
2 AND Gate IC 7408 1
3 OR Gate IC 7432 1
4 NOT Gate IC 7404 1
5 Patch cords - Few

THEORY:
Commutative property:
Boolean addition is commutative, given by

A+ B = B+ A

According to this property, the order of the OR operation conducted on the variables
makes no difference.
Boolean algebra is also commutative over multiplication given by,

A. B = B. A

This means that the order of the AND operation conducted on the variables makes no
difference.

10
(A. B)’ = A’ + B’

VERIFICATION TABLE:
A B (A.B)’ A’+B’
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

ASSOCIATIVE LAW:
• AND: (A.B).C = A.(B.C)

VERIFICATION TABLE:
A B C A.(B.C) (A.B).C
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

• OR: (A+B)+C = A+(B+C)

11
DeMorgan’s Theorems:
Two theorems that are an important part of Boolean algebra were proposed by
DeMorgan.
The first theorem states that the complement of a product is equal to the sum of the
complements.

(AB)’ = A’+ B’

The second theorem states that the complement of a sum is equal to the product of the
complements.

(A+ B)’ = A’. B’

Associative property:
The associative property of addition is given by,

A+ (B+ C) = (A+B) + C

The OR operation of several variables results in the same, regardless of the grouping of the
variables.
The associative law of multiplication is given by,

A. (B. C) = (A.B) . C

It makes no difference in what order the variables are grouped during the AND operation of
several variables.

Distributive property:
The Boolean addition is distributive over Boolean multiplication, given by

A+ BC = (A+B) (A+C)

The Boolean addition is distributive over Boolean addition, given by

A. (B+C) = (A.B)+ (A.C)

12
VERIFICATION TABLE:

A B C A+(B+C) (A+B)+C
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

ABSORPTION LAW:
A+ (A.B) = A A. (A+B) = A

VERIFICATION TABLE:

A B A+(A.B) A.(A+B)
0 0 0 0
0 1 0 0
1 0 1 1
1 1 1 1

DISTRIBUTIVE LAW:
A.(B+C) = (A.B) + (A.C)

13
VERIFICATION TABLE:
A B C A.(B+C) (A.B)+(A.C)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

A+(B.C) = (A+B).(A+C)

VERIFICATION TABLE:
A B C A+(B.C) (A+B).(A+C)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

RESULT:
Thus the Boolean theorems using logic gates were verified.

14
1. F = W’XZ+WY’

TRUTH TABLE:

W X Y Z F= W’XZ+WY’
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0

2. Y = (A+B).(C+D)

15
 EXP NO: 2 DESIGN AND IMPLEMENTATION OF
COMBINATIONAL CIRCUITS USING GATES FOR
ARBITARY FUNCTIONS
DATE:

AIM:
To design and implement the following Boolean expressions using basic gates.
1. F = W’XZ+WY’
2. Y = (A+B).(C+D)
3. Y = (A+B).C + (A.B)
4. Y = (A.B)+(C.D)+(E.F)

APPARATUS REQUIRED:
SL.NO COMPONENTS SPECIFICATION QUANTITY
1 IC Trainer Kit - 1
2 AND Gate IC 7408 1
3 OR Gate IC 7432 1
4 3 Input AND Gate IC 7411 1
5 NOT Gate IC 7404 1
6 Connecting Wires - Few

THEORY:
Combinational circuit consists of logic gates whose output at any time is determined
from the present combination of inputs. The logic gate is the most basic building block of
combinational logic. The logical function performed by a combinational circuit is fully defined
by a set of Boolean expressions.
A combinational circuit consists of input variables, logic gates, and output variables.
The logic gates accept signals from inputs and output signals are generated according to the
logic circuits employed in it.
The following guidelines should be followed while choosing the preferred form for
hardware implementation:
1. The implementation should have the minimum number of gates, with the gates used
having the minimum number of inputs.
2. There should be a minimum number of interconnections.
3. Limitation on the driving capability of the gates should not be ignored.

16
TRUTH TABLE:

A B C D Y= (A+B).(C+D)
0 0 0 0 0
0 1 0 1 1
0 1 1 0 1
0 0 1 0 0
0 0 1 1 0
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1

3. Y = (A+B).C + (A.B)

TRUTH TABLE:

A B C Y= (A+B).C + (A.B)
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

17
4. Y = (A.B)+(C.D)+(E.F)

TRUTH TABLE:

A B C D E F Y= (A.B)+(C.D)+(E.F)
0 0 0 0 0 0 0
0 0 1 1 0 0 1
1 1 1 1 1 1 1

PROCEDURE:

1. Connections are given as per the circuit diagram

2. Logic inputs are given as per the truth table
3. Observe the logic output and verify with the truth tables.

RESULT:
Thus the following Boolean expressions were implemented using basic gates
successfully.
1. F = W’XZ+WY’
2. Y = (A+B).(C+D)
3. Y = (A+B).C + (A.B)
4. Y = (A.B)+(C.D)+(E.F)

18
.4 - BIT BINARY ADDER/ SUBTRACTOR:

PIN DIAGRAM:

LOGIC DIAGRAM;

19
 EXP NO: 3 IMPLEMENTATION OF 4-BIT BINARY
ADDER/SUBSTRACTOR CIRCUITS
DATE:

AIM:
To Design and implement the 4-bit adder/ subtractor using IC 7483.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 4-bit binary full IC 7483 2
adder
3. EX-OR gate IC 7486 1
4. Patch cords - Few

THEORY:
4- Bit binary adder/ subtractor:
The 4-bit binary adder/ subtractor circuit performs the operation of both addition and
subtraction. It has two 4-bit inputs A0, A1, A2, A3 and B0, B1, B2, B3. The mode input M controls
the operation of the circuit. When M= 0, the circuit is an adder and when M=1, the circuit
becomes a Subtractor. Each exclusive-OR gate receives input M and one of the inputs of B.
When M=0, the operation is B 0= B. The full adders receive the value of B and the
input carry is 0, and the circuit performs the addition operation, A+ B.
When M=1, the operation is B 1= B’ and C0=1. The B inputs are all complemented
and a 1 is added through the input carry. Thus the circuit performs the subtraction operation,
i.e., A+ (2’s complement of B) = A- B.

20
VERIFICATION TABLE:

Input data A Input data B Addition Output Subtraction Output

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0 B D3 D2 D1 D0

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

21
RESULT:
Thus the 4-bit adder/ subtractor using IC 7483 was designed and implemented.

22
BINARY TO GRAY CODE CONVERTER:
TRUTH TABLE:

Binary code Gray code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K- Map Simplification:

23
 EXP NO: 4 IMPLEMENTATION OF CODE CONVERTERS

DATE:

AIM:
To design and implement the following code converters using logic gates.
1. Binary to Gray code Converter,
2. Gray to Binary code Converter,
3. BCD to Excess-3 code Converter,
4. Excess-3 to BCD code Converter &
5. BCD to Gray code converter.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. EX-OR gate IC7486 1
3. NOT gate IC7404 1
4. OR gate IC7432 1
5. 2- Input AND gate IC7408 1
6. 3- Input AND gate IC7411 1
7. Patch cords - As Required

THEORY:
An availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be inserted
between the two systems if each uses different codes for the same information. Thus, code
converter is a circuit that makes the two systems compatible even though each uses different
binary code.
The input variable are designed as B3,B2,B1,B0 and the output variables are designed as
G3,G2,G1,G0. From the truth table, combinational circuit is designed. The Boolean functions
are obtained from K-Map for each output variable.

24
Logic Diagram:

GRAY TO BINARY CODE CONVERTER:

TRUTH TABLE:

Gray code Binary code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

25
 To convert from binary code to Excess-3 code, the input lines must supply the bit
combination of elements as specified by code and the output lines generate the corresponding
bit combination of code. Each one of the four maps represents one of the four outputs of the
circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit.

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

26
K-Map Simplification:

Logic Diagram:

27
BCD TO EXCESS-3 CODE CONVERTER:
TRUTH TABLE:

BCD code Excess-3 code

B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

K-Map Simplification:

28
Logic Diagram:

29
EXCESS-3 TO BCD CODE CONVERTER:
TRUTH TABLE:

Excess-3 code BCD code

E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

K-Map Simplification:

30
Logic Diagram:

31
BCD TO GRAY CODE CONVERTER:
TRUTH TABLE:

BCD code Gray code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1

K-Map Simplification:

32
Logic Diagram:

33
RESULT:

Thus the 4-bit

1. Binary to Gray code Converter,
2. Gray to Binary code Converter,
3. BCD to Excess-3 code Converter,
4. Excess-3 to BCD code Converter &
5. BCD to Gray code Converter was designed and implemented using logic gates.

34
 EXP NO: 5(i) IMPLEMENTATION OF BCD ADDER

DATE:

AIM:
To Design and implement the BCD adder using IC 7483.

APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 4-bit binary full adder IC 7483 2
3. EX-OR gate IC 7486 1
4. AND gate IC 7408 1
5. OR gate IC 7432 1
6. Patch cords - Few

35
BCD ADDER:

LOGIC DIAGRAM:

4- Bit BCD Adder:

The digital system handles the decimal number in the form of binary coded decimal
numbers (BCD). A BCD adder is a circuit that adds two BCD bits and produces a sum digit
also in BCD.
In examining the contents of the table, it is apparent that when the binary sum is equal
to or less than (1001)2, the corresponding BCD number is identical, and therefore no conversion
is needed. When the binary sum is greater than 9 (1001)2, we obtain a non-valid BCD
representation. The addition of binary 6 (0110)2 to the binary sum converts it to the correct
BCD representation and also produces an output carry as required.
PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

36
Truth table:

RESULT:

Thus BCD adder using IC 7483 was designed andimplemented.

37
Logic Diagram ( 2-to-4- Line Decoder with Enable Input):

Truth Table:

INPUTS OUTPUTS
E A B D0 D1 D2 D3
1 x x 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

38
 EXP NO: 5(ii) IMPLEMENTATION OF ENCODERS AND DECODERS

DATE:

AIM:

To design and implementation encoder and decoder using logic gates.

APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 3-I/P NAND gate IC7410 2
3. NOT gate IC7404 1
4. OR gate IC7432 3
5. Patch cords - Few

THEORY:
Encoder:
An encoder is a digital circuit that performs inverse operation of a decoder. An encoder
has 2n input lines and ‘n’ output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three output that generates the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero
outputs can also be generated when D0=1.

Decoder:
A decoder is a multiple output logic circuit which converts input into coded output
where input and output codes are different. The input code generally has few bits than the
output code. Each input code word produces a different output code word i.e., there is one to
one mapping can be expressed in truth table. In block diagram of decoder circuit the encoded
information is present as n input producing 2n possible outputs. The 2n output values are from
0 through out 2n-1.

39
ENCODER:

Logic Diagram:

Truth Table:

INPUTS OUTPUTS
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

40
PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

RESULT:

Thus the encoder and decoder were designed and implemented using logic gates.

41
 EXP NO: 6 IMPLEMENTATION OF FUNCTIONS USING
MULTIPLEXERS

DATE:

AIM:
To design and implement the following Boolean function and Combinational circuit
using IC 74151.
1. F(A, B, C, D) = ∑m (1, 3, 4, 5, 6, 11, 15) ,
2. Full Adder.

APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 8:1 Multiplexer IC74151 1
3. NOT GATE IC7404 1
4. Patch cords - Few

THEORY:
Multiplexer:
Multiplexer means transmitting a large number of information units over a small number
of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of
a particular input line is controlled by a set of selection lines. Normally there are 2n input line
and ‘n’ selection lines whose bit combination determine which input is selected. It is called as
data selector, because the output depends on the input data bit that is selected.

42
1. F(A, B, C, D) = ∑m (1, 3, 4, 5, 6, 11, 15)

LOGIC DIAGRAM:

43
VERIFICATION TABLE:

Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

2. Full Adder:

TRUTH TABLE:

Inputs Outputs
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

44
LOGIC DIAGRAM: (Sum)

45
LOGIC DIAGRAM: (Carry)

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

RESULT:
Thus the Combinational circuit was designed and implemented using IC 74151.

46
SYNCHRONOUS COUNTERS:
PIN DIAGRAM: (JK Flip-Flop)

FUNCTION TABLE: (7476)

Inputs Outputs
Preset’ Clear’ Clock’ J K Q Q’
0 1 X X X 1 0
1 0 X X X 0 1
0 0 X X X 1 1
1 1 0 0 No Change
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 Toggle

47
 EXP NO: 7 IMPLEMENTATION OF SYNCHRONOUS
COUNTERS
DATE:

AIM:

To design and implement the 4 – Bit synchronous binary up and down counters using
flip - flops.

APPARATUS REQUIRED:
SL.NO COMPONENTS SPECIFICATION QUANTITY
1 IC Trainer Kit - 1
2 JK FlipFlop IC 7476 2
Quad 2 – Input AND
3 IC 7408 1
Gate
4 Connecting Wires - Few

THEORY:
In the synchronous counter, the input pulses are applied to all clock inputs of all
flipflops. The change of state of a particular flipflop is dependent on the present state of other
flipflops. The common clock pulse triggers all the flipflops simultaneously, rather than on at
a time in succession as in a ripple counter.

PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the logic diagram.
3. Observe the logic output and verify with the truth tables.

48
4 – BIT SYNCHORONOUS BINARY UP COUNER:
LOGIC DIAGRAM:

TRUTH TABLE:

Count CLK’ QD QC QB QA
Enable
0 X 0 0 0 0
1 1 0 0 0 1

1 2 0 0 1 0

1 3 0 0 1 1

1 4 0 1 0 0

1 5 0 1 0 1

1 6 0 1 1 0

1 7 0 1 1 1

1 8 1 0 0 0

1 9 1 0 0 1

1 10 1 0 1 0

1 11 1 0 1 1

1 12 1 1 0 0

1 13 1 1 0 1

1 14 1 1 1 0

1 15 1 1 1 1

1 16 0 0 0 0

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4 – BIT SYNCHORONOUS BINARY DOWN COUNER:
LOGIC DIAGRAM:

TRUTH TABLE:
Count CLK’ QD QC QB QA
Enable
0 X 0 0 0 0
1 1 1 1 1 1

1 2 1 1 1 0
1 3 1 1 0 1

1 4 1 1 0 0

1 5 1 0 1 1
1 6 1 0 1 0

1 7 1 0 0 1

1 8 1 0 0 0
1 9 0 1 1 1

1 10 0 1 1 0

1 11 0 1 0 1
1 12 0 1 0 0

1 13 0 0 1 1

1 14 0 0 1 0
1 15 0 0 0 1

1 16 0 0 0 0

RESULT:
Thus the 4 – Bit synchronous binary up and down counters was designed and
implemented using flip – flops.

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PIN DIAGRAM

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CIRCUIT DIAGRAM

TRUE TABLE

A B MODE OF OPERATION

0 0 LOCKED STATE(NO CHANGE)

0 1 SHIFT-LEFT

1 0 SHIFT-RIGHT

1 1 PARALLEL LOADING

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EXP NO: 8 DESIGN AND INPLEMENTATION OF UNIVERSAL SHIFT
REGISTER

AIM:
To design and implement Universal shift register

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. D-Flip flop IC7474 2
3. Quad 2-Line to 1-Line IC74153 2
Multiplexer
4. Patch cords - Few

THEORY:
A Universal shift register is a register which has both the right shift and left shift with parallel
load capabilities. Universal shift registers are used as memory elements in computers. A
Unidirectional shift register is capable of shifting in only one direction

UNIVERSAL SHIFT REGISTER WORKING

1) From the above figure, selected pins the mode of operation of the universal shift
register. Serial input shifts the data towards the right and left and stores the data
within the register.
2) Clear pin and CLK pin are connected to the flip-flop.
I0,I1,I2,I3 are the parallel inputs.
3) When the input pin is active HIGH, then the universal shift register loads / retrieve the
data in parallel. In this case, the input pin is directly connected to 4×1 MUX.
4) When the input pin (mode) is active LOW, then the universal shift register shifts the
data. In this case, the input pin is connected to 4×1 MUX via NOT gate.
5) When the input pin (mode) is connected to GND (Ground), then the universal shift
register acts as a Bi-directional shift register.
6) To perform the shift-right operation, the input pin is fed to the 1st AND gate of the 1st
flip-flop via serial input for shit-right.
7) To perform the shift-left operation, the input pin is fed to the 8th AND gate of the last
flip-flop via input M.
8) If the selected pins A= 0 and B = 0, then this register doesn’t operate in any mode.
That means it will be in a Locked state or no change state even though the clock
pulses are applied.

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 9) If the selected pins A = 0 and B = 1, then this register transfers or
shifts the data to leftand stores the data.
10) If the selected pins A = 1 and B = 0, then this register shifts
the data to right andhence performs the shift-right
operation.
11) If the selected pins A = 1 and B = 1, then this register loads the
data in parallel. Henceit performs the parallel loading operation
and stores the data.

From the above table, we can observe that this register

operates in all modes withserial/parallel inputs using 4×1
multiplexers and flip-flops

RESULT
Thus the Universal shift register were designed and implemented
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 using flip flops.

EXP NO:9 STIMULATION BASED STUDY ON COMPUTER

ARCHITECTURE

AIM:
To study computer architecture.

THEORY:
Historically there have been 2 types of Computers:
1. Program Computers – Their function is very specific and they couldn’t
be reprogrammed, e.g. Calculators.
2. Stored Program Computers – These can be programmed to carry out many
different tasks, applications are stored on them, hence the name.
Modern computers are based on a stored-program concept introduced by
John Von Neumann. In this stored-program concept, programs and data
are stored in a separate storage unit called memories and are treated the
same. This novel idea meant that a computer built with this architecture
would be much easier to reprogram.
The basic structure is like this ,

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 It is also known as ISA (Instruction set architecture) computer and is having three basic
units:
1. The Central Processing Unit (CPU)
2. The Main Memory Unit
3. The Input/Output Device
Let’s consider them in detail.
• Control Unit –
A control unit (CU) handles all processor control signals. It directs all input and output flow,
fetches code for instructions, and controls how data moves around the system.
• Arithmetic and Logic Unit (ALU) –
The arithmetic logic unit is that part of the CPU that handles all the calculations the CPU may
need, e.g. Addition, Subtraction, Comparisons. It performs Logical Operations, Bit Shifting
Operations, and Arithmetic operations.

• Main Memory Unit (Registers) –

1. Accumulator: Stores the results of calculations made by ALU.
2. Program Counter (PC): Keeps track of the memory location of the
next instructions to be dealt with. The PC then passes this next
address to the Memory Address Register (MAR).
3. Memory Address Register (MAR): It stores the memory locations of
instructions that need to be fetched from memory or stored in memory.
4. Memory Data Register (MDR): It stores instructions fetched from
memory or any data that is to be transferred to, and stored in, memory.
5. Current Instruction Register (CIR): It stores the most recently
fetched instructions while it is waiting to be coded and executed.

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 6. Instruction Buffer Register (IBR): The instruction that is not to be
executed immediately is placed in the instruction buffer register IBR.

• Input/Output Devices – Program or data is read into main memory from

the input device or secondary storage under the control of CPU input
instruction. Output devices are used to output information from a computer.
If some results are evaluated by the computer and it is stored in the computer,
then with the help of output devices, we can present them to the user.
• Registers – Registers refer to high-speed storage areas in the CPU. The data
processed by the CPU are fetched from the registers. There are different
types of registers used in
architecture.
MAR (Memory Address Register) – This register holds the memory
location of the data that needs to be accessed.
MDR (Memory Data Register) – This register holds the data that is being
transferred to or from memory.
AC (Accumulator) – This register holds the intermediate arithmetic and
logic results.
PC (Program Counter) – This register contains the address of the next
instruction to be executed.
CIR (Current Instruction Register) – This register contains the current
instruction during processing.
• Buses – Data is transmitted from one part of a computer to another,
connecting all major internal components to the CPU and memory, by the
means of Buses. Types:
1. Data Bus: It carries data among the memory unit, the I/O devices,
and the processor.
2. Address Bus: It carries the address of data (not the actual data)
between memory and processor.
3. Control Bus: It carries control commands from the CPU (and status
signals from other devices) in order to control and coordinate all the
activities within the computer.
Von Neumann bottleneck –
Whatever we do to enhance performance, we cannot get away from the fact
that instructions can only be done one at a time and can only be carried out
sequentially. Both of these factors hold back the competence of the CPU. This is
commonly referred to as the ‘Von Neumann bottleneck’. We can provide a Von
Neumann processor with more cache, more RAM, or faster components but if
original gains are to be made in CPU performance then an influential inspection
needs to take place of CPU configuration.
This architecture is very important and is used in our PCs and even in Super
Computers.

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