5 4 3 2 1

Z8E AMD A3 Platform Block Diagram 01

Vinafix.com
AMD A3 Dali VRAM
D DDR4 24000/2666/3200 MT/s GPU D

DDR
GDDR5 x32*2pcs
R19M-P18-50 P23
PCIE 1~4
DDR4-Memory Down DDR4-SoDIMM PCI-e 27MHz
CH. B P10 CH. A P09
P19-22 BIOS ROM
SATA MX25L2006EM1I-12G
SATA0 SATA1 (Reserve)
Re-Driver SATA - ODD SSD DDI
SATA - HDD SN75LVCP601RTJR (Reserve) M.2 PCIe-SSD
P27 P27 P27 P33
HDMI 1.4 4K2K HDMI
PS8203 P27 P27
PCIE 9~12
PCI-e
USB 3.0
PCIE 5 PCIE 6 USB3 3 USB3 2 USB3 1 eDP LCD Panel
4 Lane for 4K2K
LAN M/B Type-C MUX+Re Driver UB3/MB Port2 UB3/MB Port1 eDP P25
RTL8111HSH-CG
Wifi / BT RTS5441+PS8713
25MHz P28 M.2 P33 P29 P29 P24 P24
USB2 4 USB2 1 USB2 3 USB2 2 Battery
RJ45 USB 2.0 P13
C
P28
USB2 6 USB2 5 C

USB HUB Processor : Daul Core

1 to 2 32.768kHz
D/B USB 2.0 Power : 15 (Watt)
P35
CCD MCP 1526pins
P25
Touch Screen 48MHz
LED D/B Head Phone Size : 50 X 25 (mm)
P25 P35 P35
DMIC Integrated PCH
Daughter Board
P25 ESPI Interface

Audio Codec HDA

ALC255-CG
TPM FAN P30
Speaker NPCT750AAAYX
P26 P26
(Reserve) P31
Embedded Controller Keyboard BL P30
I2C Touch Pad P31
IT5571 Keyboard P30
eMMC eMMC G-sensor P31
(Reserve)
Hall Sensor P35
B B
SPI SPI ROM P34
P10

Power solution

Batery Charger +VCCIN_AUX +VGPU_CORE

BQ24780SRUYRP37 RT9610CGQW P42 RT8813DGQW P46

+3VPCU/+5VPCU +VCCIN_and +1.35V_GFX

RT6258CGQUF P38 RT9610CGQW P43 G5335QT2U P47

+3V/+5V +VCCSA +1V8_AON

JW7110DFNC P38 RT9610CGQW P43 JW7110DFNC P48

+1V_S5 +1.8V_S5 +1.03_GFX

G5335QT2U P39 JW5213DFND P44 G9336ADJTP1U P48

+1.2VSUS +1.5V Thermal protection

A
RT8231BGQW JW5222RSOTBP44 TMP708AIDBVR P44 A

G9661MF11U P40

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
Block Diagram
Date: Wednesday, March 18, 2020 Sheet 1 of 44
5 4 3 2 1
 5 4 3 2 1

APU PCIE
02
D
Vinafix.com U2030B D

PCIE

P8 P_GFX_RXP0 P_GFX_TXP0 N1 GFX_TX0P_C C2652 0.22u/6.3V_2

[12] PEG_RXP0 GFX_TX0N_C PEG_TXP0 [12]
P9 P_GFX_RXN0 P_GFX_TXN0 N3 C2653 0.22u/6.3V_2
[12] PEG_RXN0 PEG_TXN0 [12]
N6 P_GFX_RXP1 P_GFX_TXP1 M2 GFX_TX1P_C C2650 0.22u/6.3V_2
[12] PEG_RXP1 GFX_TX1N_C PEG_TXP1 [12]
N7 P_GFX_RXN1 P_GFX_TXN1 M4 C2651 0.22u/6.3V_2
[12] PEG_RXN1 PEG_TXN1 [12]
dGPU M8 L2 GFX_TX2P_C
P_GFX_RXP2 P_GFX_TXP2 C2648 0.22u/6.3V_2 PEG_TXP2 [12]
[12] PEG_RXP2 M9 L4 GFX_TX2N_C
P_GFX_RXN2 P_GFX_TXN2 C2649 0.22u/6.3V_2
[12] PEG_RXN2 PEG_TXN2 [12]
L6 P_GFX_RXP3 P_GFX_TXP3 L1 GFX_TX3P_C C2646 0.22u/6.3V_2
[12] PEG_RXP3 GFX_TX3N_C PEG_TXP3 [12]
L7 P_GFX_RXN3 P_GFX_TXN3 L3 C2647 0.22u/6.3V_2
[12] PEG_RXN3 PEG_TXN3 [12]
K11 P_GFX_RXP4 P_GFX_TXP4 K2
J11 P_GFX_RXN4 P_GFX_TXN4 K4

H6 P_GFX_RXP5 P_GFX_TXP5 J2
H7 P_GFX_RXN5 P_GFX_TXN5 J4

G6 P_GFX_RXP6 P_GFX_TXP6 H1
F7 P_GFX_RXN6 P_GFX_TXN6 H3
C C

G8 P_GFX_RXP7 P_GFX_TXP7 H2
F8 P_GFX_RXN7 P_GFX_TXN7 H4

N10 N2 PCIE_TXP0_SSD_C C2654 0.22u/6.3V_2

P_GPP_RXP0 P_GPP_TXP0 PCIE_TXP0_SSD [28]
[28] PCIE_RXP0_SSD N9 P3 PCIE_TXN0_SSD_C
P_GPP_RXN0 P_GPP_TXN0 C2633 0.22u/6.3V_2 PCIE_TXN0_SSD [28]
[28] PCIE_RXN0_SSD
L10 P_GPP_RXP1 P_GPP_TXP1 P4 PCIE_TXP1_SSD_C C2634 0.22u/6.3V_2
[28] PCIE_RXP1_SSD PCIE_TXN1_SSD_C PCIE_TXP1_SSD [28]
L9 P_GPP_RXN1 P_GPP_TXN1 P2 C2635 0.22u/6.3V_2
[28] PCIE_RXN1_SSD PCIE_TXN1_SSD [28]
L12 P_GPP_RXP2 P_GPP_TXP2 R3 PCIE_TXP2_SSD_C C2636 0.22u/6.3V_2
[28] PCIE_RXP2_SSD PCIE_TXN2_SSD_C PCIE_TXP2_SSD [28]
TO SSD M2 CN M11 P_GPP_RXN2 P_GPP_TXN2 R1 C2637 0.22u/6.3V_2 TO SSD M2 CN
[28] PCIE_RXN2_SSD PCIE_TXN2_SSD [28]
P12 P_GPP_RXP3 P_GPP_TXP3 T4 PCIE_TXP3_SSD_C C2638 0.22u/6.3V_2
[28] PCIE_RXP3_SSD PCIE_TXN3_SSD_C PCIE_TXP3_SSD [28]
P11 P_GPP_RXN3 P_GPP_TXN3 T2 C2639 0.22u/6.3V_2
[28] PCIE_RXN3_SSD PCIE_TXN3_SSD [28]

V6 P_GPP_RXP4 P_GPP_TXP4 W2 PCIE_TXP4_LAN_C C2640 0.1u/6.3V_2

[23] PCIE_RXP4_LAN PCIE_TXN4_LAN_C PCIE_TXP4_LAN [23]
V7 W4 C2641 0.1u/6.3V_2
LAN [23] PCIE_RXN4_LAN P_GPP_RXN4 P_GPP_TXN4 PCIE_TXN4_LAN [23] LAN
B T8 P_GPP_RXP5 P_GPP_TXP5 W3 PCIE_TXP5_WLAN_C C2631 0.1u/6.3V_2 B
[28] PCIE_RXP5_WLAN PCIE_TXN5_WLAN_C PCIE_TXP5_WLAN [28]
WLAN T9 P_GPP_RXN5 P_GPP_TXN5 V2 C2632 0.1u/6.3V_2 WLAN
[28] PCIE_RXN5_WLAN PCIE_TXN5_WLAN [28]

[27] SATA_RXP0 R6 P_GPP_RXP6/SATA_RXP0 P_GPP_TXP6/SATA_TXP0 V1

R7 V3 SATA_TXP0 [27]
HDD [27] SATA_RXN0 P_GPP_RXN6/SATA_RXN0 P_GPP_TXN6/SATA_TXN0
SATA_TXN0 [27] HDD
R9 P_GPP_RXP7/SATA_RXP1 P_GPP_TXP7/SATA_TXP1 U2
[27] SATA_RXP1 SATA_TXP1 [27]
R10 U4
ODD [27] SATA_RXN1 P_GPP_RXN7/SATA_RXN1 P_GPP_TXN7/SATA_TXN1
SATA_TXN1 [27] ODD
FP5 REV 0.90
PART 2 OF 13

FP5

AMD APU TOP BSQ QBCON

A Ryzen 5-2500U AJ02500UT03 AJ02500UT02 A

Ryzen 3-2300UQ AJ02300UT04 AJ02300UT05

Ryzen 3-2200U AJ02200RT01 AJ02200RT02 Quanta Computer Inc.
PROJECT : Z8E
Size Document Number Rev
1A
RR 1/7(PCIE)
Date: Wednesday, March 18, 2020 Sheet 2 of 44
5 4 3 2 1
 5 4 3 2 1

APU MEMORY

U2030A
U2030I
03
MEMORY A MEMORY B
M_A_DQ[0..63] [9] M_B_DQ[0..63] [10]
[9] M_A_A[13:0] M_A_A0 AF25 [10] M_B_A[13:0] M_B_A0 AG30

Vinafix.com
MA_ADD0 MB_ADD0
M_A_A1 AE23 MA_ADD1 MA_DATA0 J21 M_A_DQ0 M_B_A1 AC32 MB_ADD1 MB_DATA0 B21 M_B_DQ0
M_A_A2 AD27 MA_ADD2 MA_DATA1 H21 M_A_DQ1 M_B_A2 AC30 MB_ADD2 MB_DATA1 D21 M_B_DQ1
M_A_A3 AE21 MA_ADD3 MA_DATA2 F23 M_A_DQ2 M_B_A3 AB29 MB_ADD3 MB_DATA2 B23 M_B_DQ2
D M_A_A4 AC24 H23 M_A_DQ3 M_B_A4 AB31 D23 M_B_DQ3 D
MA_ADD4 MA_DATA3 MB_ADD4 MB_DATA3
M_A_A5 AC26 G20 M_A_DQ4 M_B_A5 AA30 A20 M_B_DQ4
MA_ADD5 MA_DATA4 MB_ADD5 MB_DATA4
M_A_A6 AD21 MA_ADD6 MA_DATA5 F20 M_A_DQ5 M_B_A6 AA29 MB_ADD6 MB_DATA5 C20 M_B_DQ5
M_A_A7 AC27 MA_ADD7 MA_DATA6 J22 M_A_DQ6 M_B_A7 Y30 MB_ADD7 MB_DATA6 A22 M_B_DQ6
M_A_A8 AD22 MA_ADD8 MA_DATA7 J23 M_A_DQ7 M_B_A8 AA31 MB_ADD8 MB_DATA7 C22 M_B_DQ7
M_A_A9 AC21 M_B_A9 W29
MA_ADD9 MB_ADD9
M_A_A10 AF22 G25 M_A_DQ8 M_B_A10 AH29 D24 M_B_DQ8
MA_ADD10 MA_DATA8 MB_ADD10 MB_DATA8
M_A_A11 AA24 MA_ADD11 MA_DATA9 F26 M_A_DQ9 M_B_A11 Y32 MB_ADD11 MB_DATA9 A25 M_B_DQ9
M_A_A12 AC23 MA_ADD12 MA_DATA10 L24 M_A_DQ10 M_B_A12 W31 MB_ADD12 MB_DATA10 D27 M_B_DQ10
M_A_A13 AJ25 MA_ADD13_BANK2 MA_DATA11 L26 M_A_DQ11 M_B_A13 AL30 MB_ADD13_BANK2 MB_DATA11 C27 M_B_DQ11
AG27 L23 M_A_DQ12 AK30 C23 M_B_DQ12
MA_WE_L_ADD14 MA_DATA12 MB_WE_L_ADD14 MB_DATA12
[9] M_A_WE# AG23 F25 M_A_DQ13 [10] M_B_WE# AK32 B24 M_B_DQ13
MA_CAS_L_ADD15 MA_DATA13 MB_CAS_L_ADD15 MB_DATA13
[9] M_A_CAS# M_A_DQ14 [10] M_B_CAS# M_B_DQ14
AG26 MA_RAS_L_ADD16 MA_DATA14 K25 AJ30 MB_RAS_L_ADD16 MB_DATA14 C26
[9] M_A_RAS# M_A_DQ15 [10] M_B_RAS# M_B_DQ15
MA_DATA15 K27 MB_DATA15 B27

AF21 M25 M_A_DQ16 AH31 C30 M_B_DQ16

MA_BANK0 MA_DATA16 MB_BANK0 MB_DATA16
[9] M_A_BS#0 AF27 M27 M_A_DQ17 [10] M_B_BS#0 AG32 E29 M_B_DQ17
MA_BANK1 MA_DATA17 MB_BANK1 MB_DATA17
[9] M_A_BS#1 M_A_DQ18 [10] M_B_BS#1 M_B_DQ18
MA_DATA18 P27 MB_DATA18 H29
AA21 MA_BG0 MA_DATA19 R24 M_A_DQ19 V31 MB_BG0 MB_DATA19 H31 M_B_DQ19
[9] M_A_BG#0 M_A_DQ20 [10] M_B_BG#0 M_B_DQ20
AA27 MA_BG1 MA_DATA20 L27 V29 MB_BG1 MB_DATA20 A28
[9] M_A_BG#1 M_A_DQ21 [10] M_B_BG#1 M_B_DQ21
MA_DATA21 M24 MB_DATA21 D28
AA22 P24 M_A_DQ22 V30 F31 M_B_DQ22
MA_ACT_L MA_DATA22 MB_ACT_L MB_DATA22
[9] M_A_ACT# M_A_DQ23 [10] M_B_ACT# M_B_DQ23
MA_DATA23 P25 MB_DATA23 G30
[9] M_A_DM[7..0] M_A_DM0 F21 MA_DM0 C21 MB_DM0
M_A_DM1 M_A_DQ24 [10] M_B_DM0 M_B_DQ24
G27 MA_DM1 MA_DATA24 M22 C25 MB_DM1 MB_DATA24 J29
M_A_DM2 M_A_DQ25 [10] M_B_DM1 M_B_DQ25
N24 MA_DM2 MA_DATA25 N21 E32 MB_DM2 MB_DATA25 J31
M_A_DM3 N23 T22 M_A_DQ26 [10] M_B_DM2 K30 L29 M_B_DQ26
MA_DM3 MA_DATA26 MB_DM3 MB_DATA26
M_A_DM4 M_A_DQ27 [10] M_B_DM3 M_B_DQ27
AL24 MA_DM4 MA_DATA27 V21 AP30 MB_DM4 MB_DATA27 L31
M_A_DM5 M_A_DQ28 [10] M_B_DM4 M_B_DQ28
AN27 MA_DM5 MA_DATA28 L21 AW31 MB_DM5 MB_DATA28 H30
M_A_DM6 M_A_DQ29 [10] M_B_DM5 M_B_DQ29
AW25 MA_DM6 MA_DATA29 M20 BB26 MB_DM6 MB_DATA29 H32
M_A_DM7 M_A_DQ30 [10] M_B_DM6 M_B_DQ30
C AT21 MA_DM7 MA_DATA30 R23 BD22 MB_DM7 MB_DATA30 L30 C
T27 T21 M_A_DQ31 [10] M_B_DM7 N32 L32 M_B_DQ31
RSVD_36 MA_DATA31 RSVD_21 MB_DATA31

F22 MA_DQS_H0 MA_DATA32 AL27 M_A_DQ32 D22 MB_DQS_H0 MB_DATA32 AP29 M_B_DQ32
[9] M_A_DQSP0 M_A_DQ33 [10] M_B_DQSP0 M_B_DQ33
G22 MA_DQS_L0 MA_DATA33 AL25 B22 MB_DQS_L0 MB_DATA33 AP32
[9] M_A_DQSN0 M_A_DQ34 [10] M_B_DQSN0 M_B_DQ34
H27 MA_DQS_H1 MA_DATA34 AP26 D25 MB_DQS_H1 MB_DATA34 AT29
[9] M_A_DQSP1 H26 AR27 M_A_DQ35 [10] M_B_DQSP1 B25 AU32 M_B_DQ35
MA_DQS_L1 MA_DATA35 MB_DQS_L1 MB_DATA35
[9] M_A_DQSN1 M_A_DQ36 [10] M_B_DQSN1 M_B_DQ36
N27 MA_DQS_H2 MA_DATA36 AK26 F29 MB_DQS_H2 MB_DATA36 AN30
[9] M_A_DQSP2 M_A_DQ37 [10] M_B_DQSP2 M_B_DQ37
N26 MA_DQS_L2 MA_DATA37 AK24 F30 MB_DQS_L2 MB_DATA37 AP31
[9] M_A_DQSN2 M_A_DQ38 [10] M_B_DQSN2 M_B_DQ38
R21 MA_DQS_H3 MA_DATA38 AM24 K31 MB_DQS_H3 MB_DATA38 AR30
[9] M_A_DQSP3 M_A_DQ39 [10] M_B_DQSP3 M_B_DQ39
P21 MA_DQS_L3 MA_DATA39 AP27 K29 MB_DQS_L3 MB_DATA39 AT31
[9] M_A_DQSN3 AM26 [10] M_B_DQSN3 AR29
MA_DQS_H4 MB_DQS_H4
[9] M_A_DQSP4 M_A_DQ40 [10] M_B_DQSP4 M_B_DQ40
AM27 MA_DQS_L4 MA_DATA40 AM23 AR31 MB_DQS_L4 MB_DATA40 AU29
[9] M_A_DQSN4 M_A_DQ41 [10] M_B_DQSN4 M_B_DQ41
AN24 MA_DQS_H5 MA_DATA41 AM21 AW30 MB_DQS_H5 MB_DATA41 AV30
[9] M_A_DQSP5 M_A_DQ42 [10] M_B_DQSP5 M_B_DQ42
AN25 MA_DQS_L5 MA_DATA42 AR25 AW29 MB_DQS_L5 MB_DATA42 BB30
[9] M_A_DQSN5 M_A_DQ43 [10] M_B_DQSN5 M_B_DQ43
AU23 MA_DQS_H6 MA_DATA43 AU27 BC25 MB_DQS_H6 MB_DATA43 BA28
[9] M_A_DQSP6 AT23 AL22 M_A_DQ44 [10] M_B_DQSP6 BA25 AU30 M_B_DQ44
MA_DQS_L6 MA_DATA44 MB_DQS_L6 MB_DATA44
[9] M_A_DQSN6 M_A_DQ45 [10] M_B_DQSN6 M_B_DQ45
AV20 MA_DQS_H7 MA_DATA45 AL21 BC22 MB_DQS_H7 MB_DATA45 AU31
[9] M_A_DQSP7 M_A_DQ46 [10] M_B_DQSP7 M_B_DQ46
AW20 MA_DQS_L7 MA_DATA46 AP24 BA22 MB_DQS_L7 MB_DATA46 AY32
[9] M_A_DQSN7 M_A_DQ47 [10] M_B_DQSN7 M_B_DQ47
V24 RSVD_41 MA_DATA47 AP23 N31 RSVD_20 MB_DATA47 AY29
V23 RSVD_40 N29 RSVD_18
AW26 M_A_DQ48 BA27 M_B_DQ48
MA_DATA48 MB_DATA48
AD25 MA_CLK_H0 MA_DATA49 AV25 M_A_DQ49 AC31 MB_CLK_H0 MB_DATA49 BC27 M_B_DQ49
[9] M_A_CLKP0 M_A_DQ50 [10] M_B_CLKP0 M_B_DQ50
AD24 MA_CLK_L0 MA_DATA50 AV22 AD30 MB_CLK_L0 MB_DATA50 BA24
[9] M_A_CLKN0 M_A_DQ51 [10] M_B_CLKN0 M_B_DQ51
AE26 MA_CLK_H1 MA_DATA51 AW22 AD29 MB_CLK_H1 MB_DATA51 BC24
[9] M_A_CLKP1 M_A_DQ52 M_B_DQ52
AE27 MA_CLK_L1 MA_DATA52 AU26 AD31 MB_CLK_L1 MB_DATA52 BD28
[9] M_A_CLKN1 AV27 M_A_DQ53 AE30 BB27 M_B_DQ53
MA_DATA53 MB_CLK_H2 MB_DATA53
MA_DATA54 AW23 M_A_DQ54 AE32 MB_CLK_L2 MB_DATA54 BB25 M_B_DQ54
MA_DATA55 AT22 M_A_DQ55 AF29 MB_CLK_H3 MB_DATA55 BD25 M_B_DQ55
AF31 MB_CLK_L3
B AW21 M_A_DQ56 BC23 M_B_DQ56 B
MA_DATA56 MB_DATA56
AG21 AU21 M_A_DQ57 AJ31 BB22 M_B_DQ57
[9] M_A_CS#0 MA_CS_L0 MA_DATA57
M_A_DQ58 [10] M_B_CS#0 MB0_CS_L0 MB_DATA57
M_B_DQ58
[9] M_A_CS#1 AJ27 MA_CS_L1 MA_DATA58 AP21 AM31 MB0_CS_L1 MB_DATA58 BC21
MA_DATA59 AN20 M_A_DQ59 AJ29 MB1_CS_L0 MB_DATA59 BD20 M_B_DQ59
MA_DATA60 AR22 M_A_DQ60 AM29 MB1_CS_L1 MB_DATA60 BB23 M_B_DQ60
AN22 M_A_DQ61 BA23 M_B_DQ61
MA_DATA61 MB_DATA61
AT20 M_A_DQ62 BB21 M_B_DQ62
MA_DATA62 MB_DATA62
MA_DATA63 AR20 M_A_DQ63 MB_DATA63 BA21 M_B_DQ63
[9] M_A_CKE0 Y23 MA_CKE0 [10] M_B_CKE0 U29 MB0_CKE0

[9] M_A_CKE1 Y26 MA_CKE1 RSVD_34 T24 T30 MB0_CKE1 RSVD_17 M31
RSVD_35 T25 V32 MB1_CKE0 RSVD_19 N30
RSVD_51 W25 U31 MB1_CKE1 RSVD_26 P31
RSVD_52 W27 RSVD_29 R32
[9] M_A_ODT0 AG24 MA_ODT0 RSVD_27 R26 [10] M_B_ODT0 AL31 MB0_ODT0 RSVD_16 M30
[9] M_A_ODT1 AJ22 MA_ODT1 RSVD_28 R27 AM32 MB0_ODT1 RSVD_15 M29
RSVD_43 V27 AL29 MB1_ODT0 RSVD_25 P30
RSVD_42 V26 AM30 MB1_ODT1 RSVD_24 P29

M_A_ALERT# AA25 M_B_ALERT# W30

[9] M_A_ALERT# MA_ALERT_L
M_A_PARITY [10] M_B_ALERT# MB_ALERT_L
M_B_PARITY
MA_PAROUT AF24 M_A_PARITY [9] MB_PAROUT AG31 M_B_PARITY [10]
AE24 R6644 1K_1%_2 AG29
[9] M_A_EVENT# MA_EVENT_L +1.2VSUS MB_EVENT_L
Y24 T31
[9] M_A_RST# MA_RESET_L [10] M_B_RST# MB_RESET_L
FP5 REV 0.90 FP5 REV 0.90
PART 1 OF 13 PART 9 OF 13
FP5
AJ1901CUT00 FP5
AJ1901CUT00

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
RR 2/7(MEM)
Date: Wednesday, March 18, 2020 Sheet 3 of 44
5 4 3 2 1
 5 4 3 2 1

APU DISPLAY and MISC [5,6,7,11,21,24,26,29,35,37]

[5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,33,34,35,37,41]
[7,33,37]
[5,6,7,24,26,29,37]
[5,6,7,11,23,25,28,29,32,37,38]
+1.8V
+3V
VDDP
+1.8V_S5
+3V_S5
04
U2030C
Vinafix.com +3V

DISPLAY /SVI2/JTAG/TEST
D D
C8 DP0_TXP0 1.8V DP_BLON G15 APU_LVDS_BLON_R
[20] INT_EDP_TXP0
A8 DP0_TXN0 1.8V DP_DIGON F15 APU_DISP_ON_R ULT_EDP_HPD R6590 100K_1%_2 +1.8V
[20] INT_EDP_TXN0
1.8V DP_VARY _BL L14 APU_DPST_PWM_R R2546 R2547
D8 DP0_TXP1 2.2K_5%_4 2.2K_5%_4
[20] INT_EDP_TXP1

5
B8 D9
eDP Panel [20] INT_EDP_TXN1 DP0_TXN1 DP0_AUXP
DP0_AUXN B9
INT_eDP_AUXP
INT_eDP_AUXN
[20]
[20]
eDP
B6 DP0_TXP2 DP0_HPD C10 ULT_EDP_HPD APU_LVDS_BLON_R 4 3 APU_LVDS_BLON [20]
[20] INT_EDP_TXP2 ULT_EDP_HPD [20]
C7 DP0_TXN2 Q2032A
[20] INT_EDP_TXN2
DP1_AUXP G11 DMN5L06DWK-7 2 1
INT_HDMI_AUXP [22]
C6 DP0_TXP3 DP1_AUXN F11 D2038 RB500V-40
[20] INT_EDP_TXP3 INT_HDMI_AUXN [22] PCIE_RST# [5,11,12,23,26,28,29,30]
D6 G13 Q2032B 2 1
[20] INT_EDP_TXN3 DP0_TXN3 DP1_HPD
HDMI_HPD_Q [22] HDMI DMN5L06DWK-7 D2039 RB500V-40
E6 J12 APU_DISP_ON_R 1 6
DP1_TXP0 DP2_AUXP APU_DISP_ON [20]
[22] IN_D2
D5 DP1_TXN0 DP2_AUXN H12
[22] IN_D2#
DP2_HPD K13
E1 DP1_TXP1
[22] IN_D1

2
C1 J10
HDMI [22] IN_D1# DP1_TXN1 DP3_AUXP
DP3_AUXN H10
F3 DP1_TXP2 DP3_HPD K8 +1.8V
[22] IN_D0 E4 DP1_TXN2
[22] IN_D0# K15 DP_STEREOSYNC
DP_STEREOSY NC R2549 1K_1%_2 +1.8V 11/15 delet double PU change gate to +3V
F4 DP1_TXP3 R2550 *1K_1%_2
[22] IN_CLK
F2 DP1_TXN3 RSVD_4 F14
[22] IN_CLK#
RSVD_3 F12
+3V
RSVD_2 F10

5
+1.8V
APU_TEST14 R2551 *10K_1%_2
APU_TEST15 R2543 *10K_1%_2 3 4 APU_SIC
APU_RST# APU_TEST16 +1.8V [15,21,29] 2ND_MBCLK APU_SIC [6]
R2538 300_5%_4 R2544 *10K_1%_2 Q2031A
APU_TEST17 R2545 *10K_1%_2 DMN5L06DWK-7
R2519 APU_PWRGD
300_5%_4 Q2031B
DMN5L06DWK-7
APU_RST# TEST4 AP14 APU_TEST4 TP2051 6 1 APU_SID
[15,21,29] 2ND_MBDATA APU_SID [6]
TEST5 AN14 APU_TEST5 TP2052
APU_PWRGD
C TEST6 F13 C

2
C2593 C2594 G18 APU_TEST14 +3V
TEST14
H19 APU_TEST15 +3V
150p/50V_4 150p/50V_4 TEST15
F18 APU_TEST16
TEST16
F19 APU_TEST17
TEST17

TEST31 W24 APU_TEST31 R2520 *1K_1%_2 +1.8V R2522 R2523

R2521 *0_5%_2 2.2K_5%_4 1K_1%_2
+3V TEST41 AR11 APU_TEST41 TP2053
APU_PROCHOT# R2525 *Short_0201 APU_PROCHOT#_R
APU_TDI AU2 AJ21 APU_TEST470 TP2054
TDI TEST470
R2524 1K_5%_2 APU_ALERT# APU_TDO AU4 TDO TEST471 AK21 APU_TEST471 TP2055
APU_TCK AU1 Q2033
TCK
R2526 1K_5%_2 APU_THERMTRIP# APU_TMS AU3 TMS
2N7002K
APU_TRST# AV3 3 1 APU_DPST_PWM_R
TRST_L
[20] APU_DPST_PWM
R2527 1K_5%_2 APU_SIC APU_DBREQ# AW3 DBREQ_L

R2499 1K_5%_2 APU_SID

2
APU_RST# AW4 V4 SMU_ZVDDP R2509 196_1%_4
RESET_L SMU_ZVDD VDDP
[29] APU_RST# APU_PWRGD AW2 PWROK
APU_PWRGD_D R77835 *HDT@0_5%_2 +1.8V
APU_SIC H14 AW11 APU_CORETYPE R2510 *1K_1%_2
SIC DUAL CORETY PE +3V_S5
APU_SID J14 SID DUAL
APU_ALERT# J15 ALERT_L 3V
APU_THERMTRIP# AP16 THERMTRIP_L VDDP_SENSE AN11 APU_VDDP_RUN_FB_H +1.8V
APU_PROCHOT#_R L19 3V APU_VDDP_RUN_FB_H [33]
PROCHOT_L 3V VDDCR_SOC_SENSE J19 CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_H [35]
K18 CPU_VDD_RUN_FB_H
APU Serial VID
VDDCR_SENSE CPU_VDD0_RUN_FB_H [35]
SVC_APU F16 SVC0
connect to thermal shutdown circuit , OD 1K PU to VDD_33 SVD_APU H16 SVD0 VSS_SENSE_A J18 R2511 R2512 R2513
SVT_APU CPU_VDD0_RUN_FB_L [35]
J16 SVT0 FP5 REV 0.90 VSS_SENSE_B AM11 APU_VDDP_RUN_FB_L *1K_1%_2 *1K_1%_2 *1K_1%_2
APU_VDDP_RUN_FB_L [33]
PART 3 OF 13

FP5 CPU_VDDNB_RUN_FB_H SVT_APU R2514 *Short_0201

CPU_VDD_RUN_FB_H TP2044 APU_SVT [35]
AJ1901CUT00
APU_VDDP_RUN_FB_H TP2045 SVC_APU
TP9091 R2515 *Short_0201 APU_SVC [35]
B APU_VDDP_RUN_FB_L B
TP9092 SVD_APU R2516 *Short_0201 APU_SVD [35]
APU_PWRGD R2517 *Short_0201
APU_PWRGD_SVID_REG [35]

R2505 R2502 R2503

*220_5%_2 *220_5%_2 *220_5%_2

Boot-VID code
SVC SVD VOLTAGE

HDT+ Connector for Debug only 0 0 1.1 EC H_PROCHOT#

0 1 1.0
R2508 *Short_0201
[31,35] CORE_PWM_PROCHOT#
+1.8V_S5 +1.8V_S5 1 0 0.9
+1.8V_S5 R2496 *Short_0201 APU_PROCHOT#
[29] H_PROCHOT#
CN2021
1 1 0.8 C2596 220p/25V_2
R554 1 2 APU_TCK R12314 *HDT@1K_1%_2
3 4 APU_TMS R12313 *HDT@1K_1%_2
*HDT@1K_1%_2
5 6 HDT_APU_TDI R12315 *HDT@0_5%_2 APU_TDI R626 *HDT@1K_1%_2
7 8 APU_TDO
APU_TRST# R12316 *HDT@33_5%_2 HDT_TRST# 9 10 APU_PWROK_BUF R569 *HDT@1K_1%_2 +3V
R560 *HDT@10K_1%_2 DBRDY3 11 12 APU_RST_L_BUF R568 *HDT@1K_1%_2
R12317 *HDT@10K_1%_2 DBRDY2 13 14 APU_DBRDY
HDT_DBREQ# R567 TP9104 APU_DBREQ#
C869 R575 *HDT@10K_1%_2 DBRDY1 15 16 *HDT@33_5%_2 R129 *HDT@1K_1%_2
17 18 APU_TEST19 +1.8V_S5 R128
*[email protected]/10V_2 TP8547
19 20 APU_TEST18
TP8548 *10K_1%_4

A A
*HDT@HDT CONN C926 C8164 R130 *100K_1%_4
[5,29,35] VRM_PWRGD
*[email protected]/10V_2 *[email protected]/10V_2 C8165
*[email protected]/10V_2
PLACE HDT CONNECTOR ON BOT U8022
R131
1K_1%_4
APU_RST# 1 A1 Y1 6 APU_RST_L_BUF
2

2 5 Q14
GND VCC
APU_PWRGD_D 3 4 APU_PWROK_BUF APU_THERMTRIP# 1 3 SYS_SHDN# [6,29,32,37] Quanta Computer Inc.
A2 Y2
METR3904-G
PROJECT : Z8E
*HDT@SN74LVC2G07DCKR Size Document Number Rev
1A
RR 3/7(DIS/MISC)
Date: Wednesday, March 18, 2020 Sheet 4 of 44
5 4 3 2 1
 5 4 3 2 1

APU GPIO/AZ/UART
05
[4,6,7,24,26,29,37] +1.8V_S5
[4,6,7,11,23,25,28,29,32,37,38] +3V_S5
[4,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,33,34,35,37,41] +3V

+3V

CLR_REQ5# U2030D
R2449 *10K_5%_2
R2463 2.2K_5%_2 SMB_RUN_CLK
ACPI/AUDIO/I2C/GPIO/MISC
R2464 2.2K_5%_2 SMB_RUN_DAT

Vinafix.com
R6647 *10K_5%_2 GPU_CLR_REQ6# C2578 150p/50V_4 EGPIO41/SFI_S5_EGPIO41 AW12
3V_S5
R2465 10K_5%_2 PCIE_CLKREQ_LAN# AU12
3V_S5 AGPIO39/SFI_S5_AGPIO39
R2447 10K_5%_2 PCIE_CLKREQ_WLAN# PCIE_RST# R2462 33_5%_2 PCIE_RST#_R BD5
[4,11,12,23,26,28,29,30] PCIE_RST# PCIE_RST0_L/EGPIO26 3V_S5
R2448 10K_5%_2 GPU_CLR_REQ4# PCIE_RST1# BB6 AR13
[28] PCIE_RST1# PCIE_RST1_L/EGPIO27 3V_S5 1V8_S5 I2C0_SCL/SFI0_I2C_SCL/EGPIO151
R2450 10K_5%_2 SSD_PCIE_CLKREQ# AT16 RSMRST_L I2C0_SDA/SFI0_I2C_SDA/EGPIO152 AT13 If unused, enable internal pull up or pull down by software
D 1.8V_S5 1V8_S5 D
R2451 *10K_5%_2 LPCCLK_RUN_L RSMRST#_R
[29] DNBSWON# DNBSWON# AR15 PWR_BTN_L/AGPIO0 3V_S5 1V8_S5 I2C1_SCL/SFI1_I2C_SCL/EGPIO149 AN8
SYS_PWRGD AV6 AN9 If unused, enable internal pull up or pull down by software
PWR_GOOD 3V_S5 1V8_S5 I2C1_SDA/SFI1_I2C_SDA/EGPIO150
+3V_S5 SYS_RST# AP10 SY S_RESET_L/AGPIO1 3V_S5
[6] SYS_RST# PCIE_WAKE# SMB_RUN_CLK
[23,28] PCIE_WAKE#
AV11 WAKE_L/AGPIO2 3V_S5 S0 I2C2_SCL/EGPIO113/SCL0 BC20
SMB_ALW_CLK SMB_RUN_DAT SMB_RUN_CLK [9,26]
R2453 2.2K_5%_2 C2579 *100p/50V_4 S0 I2C2_SDA/EGPIO114/SDA0 BA20
SMB_ALW_DAT SMB_RUN_DAT [9,26]
R2454 2.2K_5%_2 [29] AV13 SLP_S3_L 3V_S5
SUSB# SMB_ALW_CLK
R2455 10K_5%_2 DNBSWON# AT14 SLP_S5_L I2C3_SCL/AGPIO19/SCL1 AM9
PCIE_WAKE# [29] SUSC# 3V_S5 S5
SMB_ALW_DAT SMB_ALW_CLK [25]
R2438 10K_5%_2 S5 I2C3_SDA/AGPIO20/SDA1 AM10
DGPU_PWROK S0A3_GPIO SMB_ALW_DAT [25]
R2439 *10K_5%_2 R2452 *Short_0201 AR8 S0A3_GPIO/AGPIO10 3V_S5
SSD_DET# [41] DGPU_PWROK
R2440 10K_5%_2 VDD_18 PSA_I2C_SCL L16
R77882 10K_5%_2 SIO_EXT_SCI# AT10 M16
[15,29] AC_PRESENT_EC AC_PRES/AGPIO23 3V_S5 VDD_18 PSA_I2C_SDA
LLB# AN6 LLB_L/AGPIO12
TP2038 3V_S5

S5 AGPIO3 AT15 AGPIO3 TP2039

AW8 AW10 SSD_DET#
EGPIO42 S5 3V_S5 AGPIO4/SATAE_IFDET SSD_DET# [28]

AGPIO5/DEVSLP0 AP9
3V_S5
RAM_ID1 DEVSLP0 [27]
3V_S5 AGPIO6/DEVSLP1 AU10
AV15 RAM_ID1 [6]
3V_S0 SATA_ACT_L/AGPIO130 AGPIO130 TP9100
AGPIO9 AU7 TP_INTH#
S5 TP_INTH# [25]
AU6 RAM_ID2
AGPIO40
S5
RAM_ID3 RAM_ID2 [6]
S5 AGPIO69 AW13
RAM_ID3 [6]
S0 AGPIO86 AW15 R2444 *Short_0201 [12]
ACZ_BCLK_R VGA_RSTB
AR2 AZ_BITCLK/TDM_BCLK_MIC
ACZ_SDIN0 AP7 AZ_SDIN0/CODEC_GPI
AP1 AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAY BACK INTRUDER_ALERT AU14
AP4 AZ_SDIN2/SW_DATA2/TDM_DATA_PLAY BACK 3V_S0 SPKR/AGPIO91 AU16
ACZ_RST#_R RAM_ID0 ACZ_SPKR [21]
AP3 AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC 3V_S5 BLINK/AGPIO11 AV8
ACZ_SYNC_R RAM_ID0 [6]
AR4 AZ_SY NC/TDM_FRM_MIC
ACZ_SDOUT_R AR3 AW16 ACCEL_INT1
AZ_SDOUT/TDM_FRM_PLAY BACK 3V_S0 GENINT1_L/AGPIO89
BD15 ACCEL_INT1 [26]
GENINT2_L/AGPIO90 PIRQA#
3V_S0 PIRQA# [26] +1.8V_S5
[30]
AT2 SW_MCLK/TDM_BCLK_BT
DMIC_CLK_2
[30] AT4 SW_DATA0/TDM_DOUT_BT
DMIC_DAT_2
AR6 AGPIO7/FCH_ACP_I2S_SDIN_BT S5 3V_S0 FANIN0/AGPIO84 AR18 [27]
AP6 AT18 DGPU_PWREN ODD_PRSNT# APU_SPI_SI
R2445 *10K_5%_2
HDA INTERFACE
AGPIO8/FCH_ACP_I2S_LRCLK_BT S5 3V_S0 FANOUT0/AGPIO85 [12,41]
DGPU_PWREN
C FP5 REV 0.90 C
PART 4 OF 13 R2425 *10K_5%_2 APU_SPI_CS0#

FP5 R2427 10K_5%_2 SPI_TPM_CS

RESERVE FOR WLAN AJ1901CUT00
ESPI_CS#
Q6565A R77857 10K_5%_2
*DMN5L06DWK-7
ESPI_RESET#_Q 4 3 KBRST# [29]
[21] ACZ_SDOUT_AUDIO R2443 33_5%_2 ACZ_SDOUT_R +3VPCU
+3V R77868 10K_5%_2
U2039
R2446 33_5%_2 ACZ_SYNC_R R2430 *10K_5%_2 APU_SPI_CLK
[21] ACZ_SYNC_AUDIO

5
1 5
R2426 33_5%_2 ACZ_BCLK_R RTC_CLK_APU_C 2 NC VCC
[21] BIT_CLK_AUDIO A
3 4 +1.8V R77869 *10K_5%_2
GND Y SUSCLK_WLAN [28]

2
C2580 15p/50V_4 +3V R77876 10K_5%_2

[21] ACZ_RST#_AUDIO
R2429 33_5%_2 ACZ_RST#_R *74LVC1G17GW ESPI_ALERT#_Q 1 6 ESPI_ALERT# [29]
SPI TPM Need install RX149/RX168
ACZ_SDIN0 *DMN5L06DWK-7
[21] ACZ_SDIN0 Note: If TPM in on a S0 rail, disable the integrated
Q6565B
pull-up and populate an external pull-up resistor to
U2030E VDD_18_S0 rail.
CLK/LPC/EMMC/SD/SPI/eSPI/UART
R77883 10_1%_2
CLK_LPC_DEBUG [28]
R6552 10_1%_2 LPC_PD_L [29]
ODD_PWR AV18 R6553 10_1%_2 +1.8V
TP2032 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 3V_S0 LAD0 [28,29]
PCIE_CLKREQ_LAN# AN19 CLK_REQ1_L/AGPIO115 R6554 10_1%_2 12/21 add PU 10k AMD workaround
[23] PCIE_CLKREQ_LAN# PCIE_CLKREQ_WLAN# 3V_S0 LAD1 [28,29]
AP19 CLK_REQ2_L/AGPIO116 3V_S0 R6555 10_1%_2 LAD2 [28,29]
[28] PCIE_CLKREQ_WLAN# SSD_PCIE_CLKREQ# AT19 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 3V_S0 R6556 10_1%_2 LAD3 [28,29] R77880 *MMC@10K_4 EMMC_CMD_R
[28] SSD_PCIE_CLKREQ# GPU_CLR_REQ4# AU19 CLK_REQ4_L/OSCIN/EGPIO132 3V_S0 R6557 10_1%_2
[12] GPU_CLR_REQ4# CLR_REQ5# LPCCLK [29]
AW18 CLK_REQ5_L/EGPIO120 R6558 10_1%_2
GPU_CLR_REQ6#
3V_S0 LPCCLK_RUN_L [29]
AW19 CLK_REQ6_L/EGPIO121 3V_S0 R6559 10_1%_2
SERIRQ [29]
R6560 10_1%_2
EMMC_CLK_R LFRAME_L [28,29]
S0 EGPIO70/SD_CLK BD13 R6579 *MMC@10_1%_2 EMMC_CLK [11]
LPC_PD_L/SD_CMD/AGPIO21 BB14 EMMC_CMD_R R6580 *MMC@10_1%_2
3V_S5
EMMC_DAT0_R EMMC_CMD [11]
AK1 GPP_CLK0P LAD0/SD_DATA0/EGPIO104 BB12 R6581 *MMC@10_1%_2
S0
EMMC_DAT1_R EMMC_DAT0 [11]
AK3 GPP_CLK0N S0 LAD1/SD_DATA1/EGPIO105 BC11 R6582 *MMC@10_1%_2 EMMC_DAT1 [11]
LAD2/SD_DATA2/EGPIO106 BB15 EMMC_DAT2_R R6583 *MMC@10_1%_2
B S0 EMMC_DAT2 [11] B
[23] CLK_PCIE_LANP R2433 *Short_0201 CLK_PCIE_LANP_R AM2 GPP_CLK1P S0 LAD3/SD_DATA3/EGPIO107 BC15 EMMC_DAT3_R R6584 *MMC@10_1%_2 EMMC_DAT3 [11]
[23] CLK_PCIE_LANN R2413 *Short_0201 CLK_PCIE_LANN_R AM4 GPP_CLK1N 3V_S0 LPCCLK0/EGPIO74 BA15 EMMC_DAT4_R R6585 *MMC@10_1%_2 EMMC_DAT4 [11]
BC13 EMMC_DAT5_R R6586 *MMC@10_1%_2
3V_S0 LPC_CLKRUN_L/AGPIO88 EMMC_DAT5 [11]
R2416 *Short_0201 CLK_PCIE_WLANP_R AM1 GPP_CLK2P LPCCLK1/EGPIO75 BB13 EMMC_DAT6_R R6587 *MMC@10_1%_2
[28] CLK_PCIE_WLANP 3V_S0 EMMC_DAT6 [11]
[28] CLK_PCIE_WLANN R2418 *Short_0201 CLK_PCIE_WLANN_R AM3 GPP_CLK2N 3V_S0 SERIRQ/AGPIO87 BC12 EMMC_DAT7_R R6588 *MMC@10_1%_2 EMMC_DAT7 [11]
BA12 EMMC_RCLK_R R6589 *MMC@10_1%_2
RSMRST_GATE# from EC [28] CLK_PCIE_SSDP R2419
R2420
*Short_0201 CLK_PCIE_SSDP_R
*Short_0201 CLK_PCIE_SSDN_R
AL2
AL4
GPP_CLK3P
GPP_CLK3N
3V_S0 LFRAME_L/EGPIO109

LPC_RST_L/SD_WP_L/AGPIO32 BD11 KBC_RST#_C R2421 33_5%_2

C2573 150p/50V_4
EMMC_RCLK [11]

[28] CLK_PCIE_SSDN 3V_S5

BOARD_ID9 LPC_RST# [29]
3V_S5 AGPIO68/SD_CD BA11
BOARD_ID9 [6]
[12] CLK_PCIE_VGA_P R2401 *Short_0201 CLK_GFX_P_R AN2 GPP_CLK4P 3V_S5 LPC_PME_L/SD_PWR_CTRL/AGPIO22 BA13 SIO_EXT_SCI#
SIO_EXT_SCI# [29]
+1.8V_S5
[12] CLK_PCIE_VGA_N R2402 *Short_0201 CLK_GFX_N_R AN4 GPP_CLK4N

AN3 GPP_CLK5P TBD connect to EC for share ROM function

AP2 GPP_CLK5N SPI_ROM_REQ/EGPIO67 BC8 SPI_ROM_REQ
1.8V_S5
SPI_ROM_GNT TP9097
R2400 1.8V_S5 SPI_ROM_GNT/AGPIO76 BB8 TP9098
47K_1%_2 AJ2 GPP_CLK6P
AJ4 GPP_CLK6N ESPI_RESET_L/KBRST_L/AGPIO129 BB11 ESPI_RESET#_Q
DUAL_S0
BC6 ESPI_ALERT#_Q
ESPI_ALERT_L/LDRQ0_L/EGPIO108
D2026 DUAL_S0
AJ3 48M_OSC
12 RSMRST#_R SPI_CLK/ESPI_CLK BB7 APU_SPI_CLK R2403 *0_5%_2
[29] RSMRST# 1.8V_S5 ESPI_CLK [29]
SPI_DI/ESPI_DATA BA9 APU_SPI_SI R6540 *0_5%_2
48M_X1 1.8V_S5
APU_SPI_SO ESPI_1 [29]
C2575 3.9p/50V_4 BB3 X48M_X1 1.8V_S5 SPI_DO BB10 R6541 *0_5%_2 ESPI_0 [29]
RB500V-40 BA10 APU_SPI_WP R6542 *0_5%_2
1.8V_S5 SPI_WP_L/ESPI_DAT2 ESPI_2 [29]
SPI_HOLD_L/ESPI_DAT3 BC10 APU_SPI_HOLD# R6543 *0_5%_2
1.8V_S5 ESPI_3 [29]
2
1

C2574 BC9 APU_SPI_CS0#

1.8V_S5 SPI_CS1_L/EGPIO118 APU_SPI_CS0# [29]
Y2002 48M_X2 BA5 BA8 ESPI_CS#
*1u/6.3V_2 X48M_X2 1.8V_S5 SPI_CS2_L/ESPI_CS_L/AGPIO30 ESPI_CS# [29]
R2404 1.8V_S5 SPI_CS3_L/AGPIO31 BA6
48MHZ/15ppm 1M_5%_2 BD8 SPI_TPM_CS
1.8V_S5 SPI_TPM_CS_L/AGPIO29 SPI_TPM_CS [26]
4
3

AF8 RSVD_76
C2576 3.9p/50V_4 AF9 RSVD_77 UART0_RXD/EGPIO136 BA16 UART0_RXD
1.8V_S0
UART0_TXD TP9106 APU_SPI_CLK
1.8V_S0 UART0_TXD/EGPIO138 BB18 TP9107
UART0_RTS APU_SPI_SI APU_SPI_CLK [6,26,29]
UART0_RTS_L/UART2_RXD/EGPIO137 BC17
+3V
1.8V_S0
UART0_CTS TP9108 APU_SPI_SO APU_SPI_SI [26,29]
BA18
PWRGD CIRCUIT 1.8V_S0 UART0_CTS_L/UART2_TXD/EGPIO135 TP9109 APU_SPI_SO [26,29]
RTC_CLK_APU_C R6640 *0_5%_2 RTC_CLK_APU AW14 BD18 UART0_INTR APU_SPI_WP
RTCCLK 1.8V_S5 1.8V_S0 UART0_INTR/AGPIO139 TP9110 APU_SPI_WP [29]
APU_SPI_HOLD#
APU_SPI_HOLD# [29]
A R2406 C2577 15p/50V_4 32K_X1 AY1 3V_S0 BC18 BOARD_ID0 A
X32K_X1 EGPIO141/UART1_RXD
BOARD_ID1 BOARD_ID0 [6]
8.2K_5%_4 3V_S0 EGPIO143/UART1_TXD BA17
BOARD_ID1 [6]
1

SYS_RST# *B0530WS-7-F 12 D2024SYS_PWRGD 3V_S0 BC16 BOARD_ID2

EGPIO142/UART1_RTS_L/UART3_RXD
BB19 BOARD_ID3 BOARD_ID2 [6]
Y2003 3V_S0 EGPIO140/UART1_CTS_L/UART3_TXD
32K_X2 AY4 3V_S0 BB16 BOARD_ID4 BOARD_ID3 [6]
X32K_X2 AGPIO144/UART1_INTR
BOARD_ID4 [6,20]
D2025 R2408
2 32.768KHZ/20ppm 20M_5%_4
[4,29,35] VRM_PWRGD 3 SYS_PWRGD_R SYS_PWRGD
R2407 *Short_0201 FP5 REV 0.90

[29] 1 PART 5 OF 13
EC_PWROK
2

C2568 18p/50V_4
BAT54AW-L FP5
R2390 AJ1901CUT00 Quanta Computer Inc.
C2567 100K_5%_2
*1u/6.3V_4
PROJECT : Z8E
Size Document Number Rev
1A
RR 4/7(GPIO/HDA/SPI/I2C)
Date: Wednesday, March 18, 2020 Sheet 5 of 44
5 4 3 2 1
 5 4 3 2 1

RR 5/7(USB/STRAP)
[4,5,7,11,23,25,28,29,32,37,38]
[4,5,7,24,26,29,37]
[4,5,7,11,21,24,26,29,35,37]
+3V_S5
+1.8V_S5
+1.8V
USB3 Port Function
06
USB0/0 TYPE-C

USB0/1 TYPE-A
Vinafix.com USB0/2 TYPE-A
D D
USB0/3 USB TO SATA
U2030JUSB3 and USB2 Port Mapping
R77836 *0_5%_2 USB1/0 NC
[24] USBP0+
R77837 *0_5%_2
USB2 Port Function [24] USBP0- USB

R77838 0_5%_2 USBP0+_R AE7 AD2

USB_0_DP0 USBC0_A2/USB_0_TXP0/DP3_TXP2
[20] USBP5+_CAM USBP0-_R USB30_TX0+ [24]
R77839 0_5%_2 AE6 USB_0_DM0 USBC0_A3/USB_0_TXN0/DP3_TXN2 AD4
[20] USBP5-_CAM USB30_TX0- [24]
AG10 AC2
USB TYPE C1
USB0/0 TYPE-C [19] USBP1+
AG9
USB_0_DP1 USBC0_B11/USB_0_RXP0/DP3_TXP3
AC4 USB30_RX0+ [24]
USB_0_DM1 USBC0_B10/USB_0_RXN0/DP3_TXN3
[19] USBP1- USB30_RX0- [24]

USB0/1 TYPE-A AF12 AF4

[19]
[19]
USBP2+
USBP2-
AF11
USB_0_DP2
USB_0_DM2
USBC0_B2/DP3_TXP1
USBC0_B3/DP3_TXN1 AF2
+3V_S5
BOARD ID
USB0/2 TYPE-A AE10 USB_0_DP3 USBC0_A11/DP3_TXP0 AE3
[28] USBP3+ BOARD_ID0
AE9 USB_0_DM3 USBC0_A10/DP3_TXN0 AE1 R2376 *10K_5%_2 R2357 10K_5%_2
[28] USBP3- BOARD_ID1
R2358 10K_5%_2 R2359 *10K_5%_2
USB0/3 BT R77840 *0_5%_2 USBP7+_FP_APU AJ12 USB_1_DP0 USB_0_TXP1 AG3 R2360 *10K_5%_2 BOARD_ID2 R2361 10K_5%_2
[26] USBP7+_FP USB30_TX1+ [19]
R77841 *0_5%_2 USBP7-_FP_APU AJ11 USB_1_DM0 USB_0_TXN1 AG1 R2362 *10K_5%_2 BOARD_ID3 R2363 10K_5%_2
[26] USBP7-_FP USB30_TX1- [19] BOARD_ID4
R2364 10K_5%_2 R2365 *10K_5%_2
AD9 AJ9 R77872 *10K_5%_2 BOARD_ID9 R77873 10K_5%_2
USB1/0 HUB [30] USBP4+_DB
AD8
USB_1_DP1 USB_0_RXP1
AJ8 USB30_RX1+ [19] U3B NORMAL
[30] USB_1_DM1 USB_0_RXN1
USBP4-_DB USB30_RX1- [19]

USB1/1 DB USB2 USB_0_TXP2 AG4

USB30_TX2+ [19]
USB_0_TXN2 AG2 +3V
USB30_TX2- [19]
R77842 *0_5%_2 USB_0_RXP2 AG7 U3B NORMAL R2349 10K_5%_2 BOARD_ID5 R2350 *10K_5%_2
[11] USB1_DP0+_HUB USB30_RX2+ [19] BOARD_ID6
R77843 *0_5%_2 AM6 USBC_I2C_SCL USB_0_RXN2 AG6 R2351 10K_5%_2 R2352 *10K_5%_2
[11] USB1_DM0-_HUB USB30_RX2- [19] BOARD_ID7
R2354 *10K_5%_2 R2355 10K_5%_2
STRAPS PINS AM7 USBC_I2C_SDA USBC1_A2/USB_0_TXP3/DP2_TXP2 AA2 USB30_TX3+
USB30_TX3- TP2027 R77862 *10K_5%_2 BOARD_ID8 R77863 10K_5%_2
USBC1_A3/USB_0_TXN3/DP2_TXN2 AA4 TP2028
Y1 USB30_RX3+
USBC1_B11/USB_0_RXP3/DP2_TXP3 TP2025
Y3 USB30_RX3-
+1.8V_S5 +1.8V +1.8V_S5_1V8
USBC1_B10/USB_0_RXN3/DP2_TXN3 TP2026 default Low High
USBC1_B2/DP2_TXP1 AC1
AC3
C
R2306 *0_5%_2 USB_OCP_ALL# AK10
USBC1_B3/DP2_TXN1
L BOARD_ID0 Non eMMC eMMC S5 C
USB_OC0_L/AGPIO16
BOARD_ID5 AK9 AB2
USB_OC1_L/AGPIO17 USBC1_A11/DP2_TXP0
R2307 *Short_0201 BOARD_ID6 AL9 AB4
[20] BOARD_ID6 BOARD_ID7 AL8
USB_OC2_L/AGPIO18 USBC1_A10/DP2_TXN0
H BOARD_ID1 HDMI_N@ HDMI_R@ S5
USB_OC3_L/AGPIO24
AW7 AH4 BOARD_ID0
AGPIO14/USB_OC4_L USB_1_TXP0
[12] DGPU_PW_CTRL# BOARD_ID8 [5] BOARD_ID0 BOARD_ID1
AT12 AH2 BOARD_ID2 Non G-sensor(GS_N@) G-sensor(GS@)
AGPIO13/USB_OC5_L USB_1_TXN0
[5] BOARD_ID1 BOARD_ID2 L S5
AK7 [5] BOARD_ID2 BOARD_ID3
USB_1_RXP0
+1.8V_S5_1V8 +3V_S5 [5] BOARD_ID3 BOARD_ID4
AK6
USB_1_RXN0
[5,20] BOARD_ID4 BOARD_ID9 L BOARD_ID3 Non TPM(TPM_N@) TPM(TPM@) S5
FP5 REV 0.90
+3V_S5 [5] BOARD_ID9
PART 10 OF 13
Touch panel-USB
FP5 cable BOARD_ID4 Non Touch panel (Control by Cable) S5
AJ1901CUT00
R2308 R2309
10K_1%_2 10K_1%_2 R6650 200K_1%_2 USB_OCP_ALL# H BOARD_ID5 Non Type-C(TPC_N@) Type-C(TPC@) S0
[5,26,29] APU_SPI_CLK cable BOARD_ID6 Single MIC(Cable control) Dual MIC (DMIC@)S0
[5] SYS_RST#
D8511 1 21N4148WS
[19] USB_OC0#
D8512 1 21N4148WS
L BOARD_ID7 GEN2 GEN3 S0
[19] USB_OC1#
D8513 1 21N4148WS
[30] USB_OC2#
R2310 R2311
L BOARD_ID8 14" 15" S0
*2K_1%_2 *2K_1%_2
L DGPU_PW_CTRL# dGPU UMA S0
L BOARD_ID9 DALI R3 PICASSO
REQUIRED STRAPS
APU_SPI_CLK SYS_RST# RAM_ID0
Int Pull-Up
[5] RAM_ID0 RAM_ID1
Use 48Mhz crystal clock [5] RAM_ID1
normal reset mode RAM_ID2
B PULL and generate both internal [5] RAM_ID2 RAM_ID3 B
HIGH and external clocks [5] RAM_ID3
DEFAULT DEFAULT

PULL Use 100Mhz PCIE clock as short reset mode

LOW reference clock and generate
+3V_S5
internal clocks only RAM ID
R730 MD@10K_5%_2 RAM_ID0 R763 MD@10K_5%_2
R385 MD@10K_5%_2 RAM_ID1 R392 MD@10K_5%_2
R732 MD@10K_5%_2 RAM_ID2 R731 MD@10K_5%_2
CPU Thermal Sensor R376 MD@10K_5%_2 RAM_ID3 R389 MD@10K_5%_2
R67855
*Short_0603
+3V C96269 0.1u/16V_2
ID3 ID2 ID1 ID0 Vendor Vendor PN Quanta PN
Base: PIN 1
Emitter: PIN 2
Collector: PIN 3 0 0 0 0 Hynix 8Gb H5AN8G6NCJR-VKC AKD5QGSTW13
U5400
0 0 0 1 Micron 8Gb MT40A512M16LY-075:E AKD5LZSTL24
8 1 3 0 0 1 0 Micron 8Gb MT40A512M16TB-062E:J AKD5QGSTL23
[4] APU_SIC SMBCLK VCC H_THRMDA1 2 Q6544
7 2 *METR3904-G 0 0 1 1 Samsung 8Gb K4A8G165WC-BCTD AKD5QGST512
[4] APU_SID SMBDATA DXP C96270 1
6 3 2200p/25V_2 H_THRMDC1
ALERT DXN 1 1 1 1 With out on board memory
R67418 *0_5%_2 4 5
[4,29,32,37] SYS_SHDN# THERM GND

G781-1P8

Address 9AH
A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
RR 5/7(USB/STRAP)
Date: Wednesday, March 18, 2020 Sheet 6 of 44
5 4 3 2 1
 5 4 3 2 1

APU POWER
[3,9,10,34]
[4,5,6,11,21,24,26,29,35,37]
[4,5,6,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,33,34,35,37,41]
[4,5,6,11,23,25,28,29,32,37,38]
+1.2VSUS
+1.8V
+3V
+3V_S5
07
[35,36] +VCC_CORE
[4,5,6,24,26,29,37] +1.8V_S5
[4,33,37] VDDP
[5,20,21,23,26,29,30,31,32,41] +3VPCU

BOTTOM SIDE DECOUPLING UNDER APU Vinafix.com RR DG: 7*22UF+1*1UF+1*180PF +VDDCR_SOC

D D
+VDDCR_SOC U2030F +VCC_CORE
POWER
C2471 C2472 C2473 C2474 C2475 C2476 C2477 C2478 C2479 M15 VDDCR_SOC_1 VDDCR_1 G7
180p/25V_2 1u/6.3V_4 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 M18 VDDCR_SOC_2 13A 70A VDDCR_2 G10
M19 VDDCR_SOC_3 VDDCR_3 G12
N16 VDDCR_SOC_4 VDDCR_4 G14
N18 VDDCR_SOC_5 VDDCR_5 H8 C2546 C2547 C2548 C2549 C2550
N20 VDDCR_SOC_6 VDDCR_6 H11 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6
P17 VDDCR_SOC_7 VDDCR_7 H15
P19 VDDCR_SOC_8 VDDCR_8 K7
R18 VDDCR_SOC_9 VDDCR_9 K12
R20 VDDCR_SOC_10 VDDCR_10 K14 RR DG: 16*22UF+1*180PF
T19 VDDCR_SOC_11 VDDCR_11 L8
U18 VDDCR_SOC_12 VDDCR_12 M7
U20 VDDCR_SOC_13 VDDCR_13 M10
RR DG: 9*22UF+2*1UF+4*0.22uf+3*180PF V19 VDDCR_SOC_14 VDDCR_14 N14
+1.2VSUS W18 VDDCR_SOC_15 VDDCR_15 P7
W20 VDDCR_SOC_16 VDDCR_16 P10 C2551 C2552 C2553 C2522
Y19 P13 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6
BOTTOM SIDE DECOUPLING UNDER APU VDDIO_MEM-DDR4:6A VDDCR_SOC_17 VDDCR_17

VDDCR_18 P15
T32 VDDIO_MEM_S3_1 VDDCR_19 R8
V28 VDDIO_MEM_S3_2 VDDCR_20 R14
W28 VDDIO_MEM_S3_3 VDDCR_21 R16
W32 VDDIO_MEM_S3_4 VDDCR_22 T7
C2523 C2524 C2525 C2526 C2527 C2528 C2529 C2545 C2530 C2500 C2501 C2502 Y22 VDDIO_MEM_S3_5 VDDCR_23 T10
22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 1u/6.3V_4 1u/6.3V_4 180p/25V_2 Y25 VDDIO_MEM_S3_6 VDDCR_24 T13
Y28 VDDIO_MEM_S3_7 VDDCR_25 T15
AA20 VDDIO_MEM_S3_8 VDDCR_26 T17
AA23 VDDIO_MEM_S3_9 VDDCR_27 U14
AA26 VDDIO_MEM_S3_10 VDDCR_28 U16
AA28 VDDIO_MEM_S3_11 VDDCR_29 V13 C2503 C2504 C2505 C2506 C2507 C2508 C2489 C2490
AA32 VDDIO_MEM_S3_12 VDDCR_30 V15 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 180p/25V_2
AC20 VDDIO_MEM_S3_13 VDDCR_31 V17
AC22 VDDIO_MEM_S3_14 VDDCR_32 W7
AC25 W10
AC28
VDDIO_MEM_S3_15 VDDCR_33
W14
BOTTOM SIDE DECOUPLING UNDER APU
VDDIO_MEM_S3_16 VDDCR_34
C AD23 VDDIO_MEM_S3_17 VDDCR_35 W16 C
C2491 C2492 C2493 C2494 C2495 C2496 AD26 VDDIO_MEM_S3_18 VDDCR_36 Y8
0.22u/6.3V_2 0.22u/6.3V_2 0.22u/6.3V_2 0.22u/6.3V_2 180p/25V_2 180p/25V_2 AD28 VDDIO_MEM_S3_19 VDDCR_37 Y13
AD32 VDDIO_MEM_S3_20 VDDCR_38 Y15
AE20 VDDIO_MEM_S3_21 VDDCR_39 Y17 RR DG: 2*22UF+8*1UF+1*180PF
AE22 VDDIO_MEM_S3_22 VDDCR_40 AA7
AE25 VDDIO_MEM_S3_23 VDDCR_41 AA10
AE28 VDDIO_MEM_S3_24 VDDCR_42 AA14
AF23 AA16 VDDP +0.95V
If the VSS plane is cut to create a VDDIO_MEM_S3 plane, ceramic AF26
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDCR_43
VDDCR_44 AA18
BOTTOM SIDE DECOUPLING UNDER APU
capacitors with NP0 or C0G dielectric are connected across AF28 VDDIO_MEM_S3_27 VDDCR_45 AB13 R2409 *Short_0603
the VDDIO_MEM_S3 and VSS plane split. AF32 VDDIO_MEM_S3_28 VDDCR_46 AB15
AG20 VDDIO_MEM_S3_29 VDDCR_47 AB17 R2410 *Short_0603
AG22 VDDIO_MEM_S3_30 VDDCR_48 AB19
AG25 VDDIO_MEM_S3_31 VDDCR_49 AC14 C2497 C2480 C2481 C2482 C2483
AG28 VDDIO_MEM_S3_32 VDDCR_50 AC16 1u/6.3V_4 180p/25V_2 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
AJ20 VDDIO_MEM_S3_33 VDDCR_51 AC18
AJ23 VDDIO_MEM_S3_34 VDDCR_52 AD7
AJ26 VDDIO_MEM_S3_35 VDDCR_53 AD10
AJ28 VDDIO_MEM_S3_36 VDDCR_54 AD13
AJ32 VDDIO_MEM_S3_37 VDDCR_55 AD15
AK28 VDDIO_MEM_S3_38 VDDCR_56 AD17
AL28 VDDIO_MEM_S3_39 VDDCR_57 AD19
AL32 VDDIO_MEM_S3_40 VDDCR_58 AE8
VDDCR_59 AE14 C2488 C2464 C2465
AP12 VDDIO_AUDIO 0.2A VDDCR_60 AE16 22u/6.3V_6 22u/6.3V_6 1u/6.3V_4
+APU_VDDIO_AZ
VDDCR_61 AE18
+APU_VDD_33
AL18 VDD_33_1 0.25A VDDCR_62 AF7
AM17 VDD_33_2 VDDCR_63 AF10
VDDCR_64 AF13
AL20 VDD_18_1 2A VDDCR_65 AF15
+VDD_18
AM19 VDD_18_2 VDDCR_66 AF17
RR DG: 1*22UF+3*1UF VDDCR_67 AF19
+VDD_18_S5 AL19 VDD_18_S5_1 0.5A VDDCR_68 AG14
AM18 VDD_18_S5_2 VDDCR_69 AG16 C2534 C2535 C2536
VDDP_S5 R2411 +0.95VS5 AG18
*Short_0603
BOTTOM SIDE DECOUPLING UNDER APU AL17
VDDCR_70
AH13
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
+APU_VDD_33_S5 VDD_33_S5_1 0.25A VDDCR_71
AM16 VDD_33_S5_2 VDDCR_72 AH15
B B
VDDCR_73 AH17
+0.95VS5
AL14 VDDP_S5_1 1A VDDCR_74 AH19
C2484 C2485 C2486 C2487 AL15 VDDP_S5_2 VDDCR_75 AJ7
AM14 AJ10 VDDBT_RTC
22u/6.3V_6 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 VDDP_S5_3 VDDCR_76
VDDCR_77 AJ14
+0.95V AL13 VDDP_1 4A VDDCR_78 AJ16
AM12 VDDP_2 VDDCR_79 AJ18
AM13 VDDP_3 VDDCR_80 AK13
AN12 AK15

3
RR DG: 1*22UF+1*1UF VDDP_4 VDDCR_81
2
AN13 VDDP_5 VDDCR_82 AK17 [29]
AK19 CLR_CMOS
VDDCR_83
VDDBT_RTC AT11 VDDBT_RTC_G
+1.8V +APU_VDDIO_AZ
RR DG: 1*22UF+2*1UF

1
FP5 REV 0.90 Q2025 R2395
R2412 *Short_0402 +3V +APU_VDD_33 PART 6 OF 13 10K_5%_2
2N7002K

R2391 *Short_0402 FP5

C2466 C2467 AJ1901CUT00
1u/6.3V_4 22u/6.3V_6
C2531 C2532 C2533 +3VRTC 20MIL
1u/6.3V_4 1u/6.3V_4 22u/6.3V_6 +BAT_RTC U2021
2
R2396 470_1%_2 +VCCRTC_2
2 GND +1.5V_RTC
BOTTOM SIDE DECOUPLING UNDER APU 3 +3VRTC 3
1 VIN
BOTTOM SIDE DECOUPLING UNDER APU +3VPCU
1
RR DG: 1*22UF+2*1UF VOUT
D2021 BAT54CW-7-F
+1.8V +VDD_18 C2517 C2498 AP2138N-1.5TRG1 C2499
+3V_S5 +APU_VDD_33_S5
RR DG: 1*22UF+2*1UF 0.1u/6.3V_2 1u/6.3V_4 10u/6.3V_4

R2393 *Short_0402 R2392 *Short_0402

R2394 *Short_0402
C2537 C2538 C2539 C2509 C2510 C2511
1
2

1u/6.3V_4 1u/6.3V_4 22u/6.3V_6 1u/6.3V_4 1u/6.3V_4 22u/6.3V_6

3 4
A A
BOTTOM SIDE DECOUPLING UNDER APU BOTTOM SIDE DECOUPLING UNDER APU CN2020
50281-00201-001
Correct pin defined 9/20
+1.8V_S5 +VDD_18_S5
VDDBT_RTC
4.5uA RR DG: 1*22UF+2*1UF
R2397 1K_1%_2 +1.5V_RTC update footprint to
R2398 *Short_0402 bat-aaa-bat-046-k03-2p-smt and change pin defined
4/17
1

R2399
*0_5%_2 C2512 C2513 J1 C2514 C2515 C2516
0.22u/6.3V_2 1u/6.3V_4 *JUMP 1u/6.3V_4 1u/6.3V_4 22u/6.3V_6 Quanta Computer Inc.
2

PROJECT : Z8E
BOTTOM SIDE DECOUPLING UNDER APU Size Document Number Rev
1A
RR 6/7(POWER)
Date: Wednesday, March 18, 2020 Sheet 7 of 44
5 4 3 2 1
 5 4 3 2 1

APU GND
08
D
Vinafix.com D

U2030G U2030H U2030K

GND GND GND/RSVD
N12 K32 V8 AG8 AR5 BD16 U2030M
VSS_316 VSS_62 VSS_124 VSS_186 VSS_248 VSS_310
A3 VSS_1 VSS_63 L5 V11 VSS_125 VSS_187 AG11 AR7 VSS_249 VSS_311 BD19 CAMERAS
A5 VSS_2 VSS_64 L13 V12 VSS_126 VSS_188 AG12 AR12 VSS_250 VSS_312 BD21
A7 VSS_3 VSS_65 L15 V14 VSS_127 VSS_189 AG13 AR14 VSS_251 VSS_313 BD23 A18 CAM0_CSI2_CLOCKP CAM0_CLK B15
A10 VSS_4 VSS_66 L18 V16 VSS_128 VSS_190 AG15 AR16 VSS_252 VSS_314 BD26 C18 CAM0_CSI2_CLOCKN
A12 VSS_5 VSS_67 L20 V18 VSS_129 VSS_191 AG17 AR19 VSS_253 VSS_315 BD30 CAM0_I2C_SCL D15
A14 VSS_6 VSS_68 L25 V20 VSS_130 VSS_192 AG19 AR21 VSS_254 A15 CAM0_CSI2_DATAP0 CAM0_I2C_SDA C14
A16 VSS_7 VSS_69 L28 V22 VSS_131 VSS_193 AH14 AR26 VSS_255 C15 CAM0_CSI2_DATAN0
A19 VSS_8 VSS_70 M1 V25 VSS_132 VSS_194 AH16 AR28 VSS_256 CAM0_SHUTDOWN B13
A21 VSS_9 VSS_71 M5 W1 VSS_133 VSS_195 AH18 AR32 VSS_257 B16 CAM0_CSI2_DATAP1
A23 VSS_10 VSS_72 M12 W5 VSS_134 VSS_196 AH20 AU5 VSS_258 C16 CAM0_CSI2_DATAN1
A26 VSS_11 VSS_73 M21 W13 VSS_135 VSS_197 AJ1 AU8 VSS_259
A30 VSS_12 VSS_74 M23 W15 VSS_136 VSS_198 AJ5 AU11 VSS_260 C19 CAM0_CSI2_DATAP2
C3 VSS_13 VSS_75 M26 W17 VSS_137 VSS_199 AJ13 AU13 VSS_261 B18 CAM0_CSI2_DATAN2
C32 VSS_14 VSS_76 M28 W19 VSS_138 VSS_200 AJ15 AU15 VSS_262
D16 VSS_15 VSS_77 M32 W23 VSS_139 VSS_201 AJ17 AU18 VSS_263 B17 CAM0_CSI2_DATAP3
D18 VSS_16 VSS_78 N4 W26 VSS_140 VSS_202 AJ19 AU20 VSS_264 D17 CAM0_CSI2_DATAN3
D20 VSS_17 VSS_79 N5 Y5 VSS_141 VSS_203 AK5 AU22 VSS_265
E7 VSS_18 VSS_80 N8 Y11 VSS_142 VSS_204 AK8 AU25 VSS_266 RSVD_1 B20 D12 CAM1_CSI2_CLOCKP CAM1_CLK B10
E8 VSS_19 VSS_81 N11 Y12 VSS_143 VSS_205 AK11 AU28 VSS_267 RSVD_5 G3 B12 CAM1_CSI2_CLOCKN
C C
E10 VSS_20 VSS_82 N13 Y14 VSS_144 VSS_206 AK12 AV1 VSS_268 RSVD_7 J20 CAM1_I2C_SCL A11
E11 VSS_21 VSS_83 N15 Y16 VSS_145 VSS_207 AK14 AV5 VSS_269 RSVD_8 K3 C13 CAM1_CSI2_DATAP0 CAM1_I2C_SDA C11
E12 VSS_22 VSS_84 N17 Y18 VSS_146 VSS_208 AK16 AV7 VSS_270 RSVD_9 K6 A13 CAM1_CSI2_DATAN0
E13 VSS_23 VSS_85 N19 Y20 VSS_147 VSS_209 AK18 AV10 VSS_271 RSVD_10 K20 CAM1_SHUTDOWN D11
E14 VSS_24 VSS_86 N22 AA1 VSS_148 VSS_210 AK20 AV12 VSS_272 RSVD_11 M3 B11 CAM1_CSI2_DATAP1
E15 VSS_25 VSS_87 N25 AA5 VSS_149 VSS_211 AK22 AV14 VSS_273 RSVD_12 M6 C12 CAM1_CSI2_DATAN1 CAM_PRIV_LED D13
E16 VSS_26 VSS_88 N28 AA13 VSS_150 VSS_212 AK25 AV16 VSS_274 RSVD_13 M13 CAM_IR_ILLU D10
E18 VSS_27 VSS_89 P1 AA15 VSS_151 VSS_213 AL1 AV19 VSS_275 RSVD_22 P6 J13 RSVD_6 FP5 REV 0.90
E19 VSS_28 VSS_90 P5 AA17 VSS_152 VSS_214 AL5 AV21 VSS_276 RSVD_23 P22 PART 13 OF 13
E20 VSS_29 VSS_91 P14 AA19 VSS_153 VSS_215 AL7 AV23 VSS_277 RSVD_30 T3
E21 P16 AB14 AL10 AV26 T6 FP5
VSS_30 VSS_92 VSS_154 VSS_216 VSS_278 RSVD_31
E22 VSS_31 VSS_93 P18 AB16 VSS_155 VSS_217 AL12 AV28 VSS_279 RSVD_37 T29 AJ1901CUT00
E23 VSS_32 VSS_94 P20 AB18 VSS_156 VSS_218 AL16 AV32 VSS_280 RSVD_44 W6
E25 VSS_33 VSS_95 P23 AB20 VSS_157 VSS_219 AL23 AW5 VSS_281 RSVD_49 W21
E26 VSS_34 VSS_96 P26 AC5 VSS_158 VSS_220 AL26 AW28 VSS_282 RSVD_50 W22
E27 VSS_35 VSS_97 P28 AC8 VSS_159 VSS_221 AM5 AY6 VSS_283 RSVD_57 Y21
F5 P32 AC11 AM8 AY7 Y27 U2030L
VSS_36 VSS_98 VSS_160 VSS_222 VSS_284 RSVD_58
F28 VSS_37 VSS_99 R5 AC12 VSS_161 VSS_223 AM15 AY8 VSS_285 RSVD_59 AA3 RSVD
G1 VSS_38 VSS_100 R11 AC13 VSS_162 VSS_224 AM20 AY10 VSS_286 RSVD_60 AA6 T11 RSVD_32 RSVD_62 AA9
G5 VSS_39 VSS_101 R12 AC15 VSS_163 VSS_225 AM22 AY11 VSS_287 RSVD_69 AC29 RSVD_61 AA8
G16 VSS_40 VSS_102 R13 AC17 VSS_164 VSS_226 AM25 AY12 VSS_288 RSVD_70 AD3 AC7 RSVD_66 RSVD_65 AC6
G19 VSS_41 VSS_103 R15 AC19 VSS_165 VSS_227 AM28 AY13 VSS_289 RSVD_71 AD6
G21 VSS_42 VSS_104 R17 AD1 VSS_166 VSS_228 AN1 AY14 VSS_290 RSVD_74 AF3
B G23 VSS_43 VSS_105 R19 AD5 VSS_167 VSS_229 AN5 AY15 VSS_291 RSVD_75 AF6 Y9 RSVD_55 B
G26 VSS_44 VSS_106 R22 AD14 VSS_168 VSS_230 AN7 AY16 VSS_292 RSVD_78 AF30 Y10 RSVD_56 RSVD_72 AD11
G28 VSS_45 VSS_107 R25 AD16 VSS_169 VSS_231 AN10 AY18 VSS_293 RSVD_79 AJ6
G32 VSS_46 VSS_108 R28 AD18 VSS_170 VSS_232 AN15 AY19 VSS_294 RSVD_80 AJ24 W11 RSVD_47 RSVD_67 AC9
H5 VSS_47 VSS_109 R30 AD20 VSS_171 VSS_233 AN18 AY20 VSS_295 RSVD_81 AK23 W12 RSVD_48 RSVD_63 AA11
H13 VSS_48 VSS_110 T1 AE5 VSS_172 VSS_234 AN21 AY21 VSS_296 RSVD_82 AK27
H18 VSS_49 VSS_111 T5 AE11 VSS_173 VSS_235 AN23 AY22 VSS_297 RSVD_83 AL3 V9 RSVD_38 RSVD_33 T12
H20 VSS_50 VSS_112 T14 AE12 VSS_174 VSS_236 AN26 AY23 VSS_298 RSVD_87 AN29 V10 RSVD_39 RSVD_73 AD12
H22 VSS_51 VSS_113 T16 AE13 VSS_175 VSS_237 AN28 AY25 VSS_299 RSVD_88 AN31
H25 VSS_52 VSS_114 T18 AE15 VSS_176 VSS_238 AN32 AY26 VSS_300 RSVD_53 Y6
H28 VSS_53 VSS_115 T20 AE17 VSS_177 VSS_239 AP5 AY27 VSS_301 RSVD_54 Y7
K1 VSS_54 VSS_116 T23 AE19 VSS_178 VSS_240 AP8 BB1 VSS_302
K5 VSS_55 VSS_117 T26 AF1 VSS_179 VSS_241 AP13 BB20 VSS_303 AA12 RSVD_64 RSVD_45 W8
K16 VSS_56 VSS_118 T28 AF5 VSS_180 VSS_242 AP15 BB32 VSS_304 RSVD_14 M14 AC10 RSVD_68 RSVD_46 W9
K19 VSS_57 VSS_119 U13 AF14 VSS_181 VSS_243 AP18 BD3 VSS_305 RSVD_84 AL6
K21 VSS_58 VSS_120 U15 AF16 VSS_182 VSS_244 AP20 BD7 VSS_306 RSVD_85 AL11
K22 VSS_59 VSS_121 U17 AF18 VSS_183 VSS_245 AP25 BD10 VSS_307 RSVD_86 AN16 FP5 REV 0.90
K26 VSS_60 VSS_122 U19 AF20 VSS_184 VSS_246 AP28 BD12 VSS_308 PART 12 OF 13
K28 VSS_61 VSS_123 V5 AG5 VSS_185 VSS_247 AR1 BD14 VSS_309
FP5
FP5 REV 0.90 FP5 REV 0.90 FP5 REV 0.90
PART 7 OF 13 PART 8 OF 13 PART 11 OF 13 AJ1901CUT00
AJ1901CUT00 AJ1901CUT00 AJ1901CUT00
FP5 FP5 FP5

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
RR 7/7(GND/RSVD)
Date: Wednesday, March 18, 2020 Sheet 8 of 44
5 4 3 2 1
 5 4 3 2 1

CHA0 DDR4
[3] M_A_ALERT#
09
[3] M_A_DQ[63:0]

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D +1.2VSUS Place these Caps near SODIMM D
CN2019B
CN2019A
[3] M_A_A[13:0] M_A_A0 144 8 M_A_DQ0 111 1uF/10uF 4pcs on each side of SODIMM
M_A_A1 133 A0 DQ0 7 M_A_DQ4 2.48A 112 VDD1
M_A_A2 132 A1 DQ1 20 M_A_DQ3 117 VDD2
M_A_A3 131 A2 DQ2 21 M_A_DQ7 118 VDD3 255 +1.2VSUS
M_A_A4
M_A_A5
128
126
A3
A4
DQ3
DQ4
4
3
M_A_DQ1
M_A_DQ5
0 (0-7) 123
124
VDD4
VDD5
VDDSPD +3V
+3V
M_A_A6 127 A5 DQ5 16 M_A_DQ6 129 VDD6 257 C2375 180p/25V_2
M_A_A7 A6 DQ6 M_A_DQ2 VDD7 VPP1 +2.5V_SUS
122 17 130 259 C2322 0.1u/6.3V_2
M_A_A8 125 A7 DQ7 28 M_A_DQ8 135 VDD8 VPP2 C2405 1u/6.3V_4
M_A_A9 121 A8 DQ8 29 M_A_DQ12 136 VDD9 C2323 0.1u/6.3V_2
M_A_A10 146 A9 DQ9 41 M_A_DQ11 141 VDD10 258 C2395 1u/6.3V_4
M_A_A11 A10/AP DQ10 M_A_DQ15 VDD11 VTT +VDDQ_VTT
120 42 142
M_A_A12
M_A_A13
119
158
A11
A12
DQ11
DQ12
24
25
M_A_DQ13
M_A_DQ9
1 (8-15) 147
148
VDD12
VDD13
C2388 1u/6.3V_4

151 A13 DQ13 38 M_A_DQ14 153 VDD14 164 C2390 1u/6.3V_4 +2.5V_SUS
[3] M_A_WE# A14/WE# DQ14 M_A_DQ10 VDD15 VREF_CA +VREF_CA0
[3] M_A_CAS# 156 37 154
152 A15/CAS# DQ15 50 M_A_DQ20 159 VDD16 C2392 1u/6.3V_4 C2316 1u/6.3V_4
+1.2VSUS [3] M_A_RAS# A16/RAS# DQ16 M_A_DQ17 VDD17
49 160
TP2024 162 DQ17 62 M_A_DQ19 163 VDD18 C2377 1u/6.3V_4 C2295 0.1u/6.3V_2
TP2023 165 S2#/C0 DQ18 63 M_A_DQ23 VDD19
R2284 S3#/C1 DQ19
DQ20
46
45
M_A_DQ21
M_A_DQ16
2 (16-23) 1 2
C2406 1u/6.3V_4 C2297 0.1u/6.3V_2

DDR4 SODIMM 260 PIN

1K_1%_2
114 DQ21 58 M_A_DQ22 5 VSS1 VSS48 6 C2378 1u/6.3V_4 C2296 180p/25V_2
[3] M_A_ACT# ACT# DQ22 M_A_DQ18 VSS2 VSS49
143 59 9 10
[3] M_A_PARITY M_A_ALERT# 116 PARITY DQ23 70 M_A_DQ24 15 VSS3 VSS50 14
+1.2VSUS R2290 *1K_1%_2 C2393 10u/6.3V_4 C2315 *10u/6.3V_4
134 ALERT# DQ24 71 M_A_DQ28 19 VSS4 VSS51 18
[3] M_A_EVENT# EVENT# DQ25 M_A_DQ31 VSS5 VSS52
[3] M_A_RST# 108 83 23 22 C2379 10u/6.3V_4
RESET# DQ26 84 M_A_DQ27 27 VSS6 VSS53 26
C DQ27 66 M_A_DQ25 3 (24-31) 31 VSS7 VSS54 30 C2389 10u/6.3V_4 C

DDR4 SODIMM 260 PIN

R2283 DQ28 67 M_A_DQ29 35 VSS8 VSS55 36 +VDDQ_VTT
DQ29 79 M_A_DQ30 39 VSS9 VSS56 40 C2391 10u/6.3V_4
*0_5%_2
DQ30 80 M_A_DQ26 43 VSS10 VSS57 44 C2318 0.1u/6.3V_2
DQ31 174 M_A_DQ33 47 VSS11 VSS58 48 C2387 10u/6.3V_4
DQ32 173 M_A_DQ37 51 VSS12 VSS59 52 C2319 0.1u/6.3V_2
DQ33 187 M_A_DQ35 57 VSS13 VSS60 56 C2376 10u/6.3V_4
DQ34 186 M_A_DQ34 61 VSS14 VSS61 60 C2310 1u/6.3V_4
DQ35
DQ36
170
169
M_A_DQ36
M_A_DQ32
4 (32-39) 65
69
VSS15
VSS16
VSS62
VSS63
64
68
C2394 10u/6.3V_4
C2311 10u/6.3V_4

(260P)
DQ37 183 M_A_DQ39 73 VSS17 VSS64 72 C2396 10u/6.3V_4
DQ38 182 M_A_DQ38 77 VSS18 VSS65 78
DQ39 195 M_A_DQ41 81 VSS19 VSS66 82
150 DQ40 194 M_A_DQ45 85 VSS20 VSS67 86 +VREF_CA0
[3] M_A_BS#0 BA0 DQ41 M_A_DQ47 VSS21 VSS68
[3] M_A_BS#1 145 207 89 90
115 BA1 DQ42 208 M_A_DQ46 93 VSS22 VSS69 94 C2368 0.1u/6.3V_2
[3] M_A_BG#0
113 BG0 DQ43 191 M_A_DQ40 5 (40-47) 99 VSS23 VSS70 98
(260P)

[3] M_A_BG#1 BG1 DQ44 M_A_DQ44 VSS24 VSS71

190 103 102 C2369 1000p/25V_2
149 DQ45 203 M_A_DQ43 107 VSS25 VSS72 106
[3] M_A_CS#0 S0# DQ46 M_A_DQ42 VSS26 VSS73
[3] M_A_CS#1 157 204 167 168 C2674 *0.047u/16V_4
109 S1# DQ47 216 M_A_DQ52 171 VSS27 VSS74 172
[3] M_A_CKE0 CKE0 DQ48 M_A_DQ48 VSS28 VSS75
110 215 175 176
[3] M_A_CKE1 CKE1 DQ49 M_A_DQ55 VSS29 VSS76
228 181 180
137 DQ50 229 M_A_DQ51 185 VSS30 VSS77 184
For EMI CAP
[3]
[3]
M_A_CLKP0
M_A_CLKN0 139
138
CK0
CK0#
DQ51
DQ52
211
212
M_A_DQ53
M_A_DQ49
6 (48-55) 189
193
VSS31
VSS32
VSS78
VSS79
188
192
+1.2VSUS
[3] M_A_CLKP1 CK1 DQ53 M_A_DQ54 VSS33 VSS80
140 224 197 196 EC2008 *180p/25V_2
[3] M_A_CLKN1 CK1# DQ54 M_A_DQ50 VSS34 VSS81
225 201 202
155 DQ55 237 M_A_DQ57 205 VSS35 VSS82 206 EC2007 *180p/25V_2
[3] M_A_ODT0 ODT0 DQ56 M_A_DQ56 VSS36 VSS83
[3] M_A_ODT1 161 236 209 210
B ODT1 DQ57 249 M_A_DQ63 213 VSS37 VSS84 214 B
253 DQ58 250 M_A_DQ59 217 VSS38 VSS85 218
[5,26]
[5,26]
SMB_RUN_CLK
SMB_RUN_DAT 254 SCL
SDA
DQ59
DQ60
232
233
M_A_DQ60
M_A_DQ61
7 (56-63) 223
227
VSS39
VSS40
VSS86
VSS87
222
226
256 DQ61 245 M_A_DQ62 231 VSS41 VSS88 230
260 SA0 DQ62 246 M_A_DQ58 235 VSS42 VSS89 234
166 SA1 DQ63 239 VSS43 VSS90 238 +1.2VSUS
SA2 M_A_DQSP0 M_A_DQSP[7:0] [3] VSS44 VSS91
13 243 244
92 DQS0 34 M_A_DQSP1 247 VSS45 VSS92 248
91 CB0 DQS1 55 M_A_DQSP2 251 VSS46 VSS93 252
101 CB1 DQS2 76 M_A_DQSP3 VSS47 VSS94 R2276 +VREF_CA0
105 CB2 DQS3 179 M_A_DQSP4 1K_1%_2
88 CB3 DQS4 200 M_A_DQSP5 261
87 CB4 DQS5 221 M_A_DQSP6 GND1 262
100 CB5 DQS6 242 M_A_DQSP7 GND2 263 R2682 *0_5%_6 +VREF_CA0
CB6 DQS7 GND3 [34] +VDDQ
104 97 264
CB7 DQS8 GND4
[3] M_A_DM[7..0] M_A_DM0 M_A_DQSN0 M_A_DQSN[7:0] [3]
12 11 DDR4 STD H=4
M_A_DM1 33 DM0 DQS#0 32 M_A_DQSN1 R2270
M_A_DM2 54 DM1 DQS#1 53 M_A_DQSN2 1K_1%_2
M_A_DM3 75 DM2 DQS#2 74 M_A_DQSN3
M_A_DM4 178 DM3 DQS#3 177 M_A_DQSN4
M_A_DM5 199 DM4 DQS#4 198 M_A_DQSN5
M_A_DM6 220 DM5 DQS#5 219 M_A_DQSN6
M_A_DM7 241 DM6 DQS#6 240 M_A_DQSN7
96 DM7 DQS#7 95
DM8 DQS#8
DDR4 STD H=4

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
CHA0 DDR4 DIMM0-RVS(4.0H)
Date: Wednesday, March 18, 2020 Sheet 9 of 44
5 4 3 2 1
 5 4 3 2 1

CHA1 DDR4 U2018

M_B_A0
U2017

M_B_DQ17
P3 G2
[3] M_B_A[13:0] M_B_A0 M_B_DQ4 M_B_A1 A0 DQL0 M_B_DQ19
P3 G2 P7 F7
M_B_A1 A0 DQL0 M_B_DQ6 M_B_DQ4 [3,10] M_B_A2 A1 DQL1 M_B_DQ16
P7 F7 R3 H3
M_B_A2 A1 DQL1 M_B_DQ1 M_B_DQ6 [3,10] M_B_A3 A2 DQL2 M_B_DQ18
R3 H3 N7 H7
M_B_A3 A2 DQL2 M_B_DQ2 M_B_DQ1 [3,10] M_B_A4 A3 DQL3 M_B_DQ21 +VDDQ_VTT
N7 H7 N3 H2
M_B_A4 A3 DQL3 M_B_DQ0 M_B_DQ2 [3,10] M_B_A5 A4 DQL4 M_B_DQ23
N3 H2 P8 H8
M_B_A5 A4 DQL4 M_B_DQ7 M_B_DQ0 [3,10] M_B_A6 A5 DQL5 M_B_DQ20
P8 H8 P2 J3
M_B_A6 A5 DQL5 M_B_DQ5 M_B_DQ7 [3,10] M_B_A7 A6 DQL6 M_B_DQ22
P2 J3 R8 J7
M_B_A7 A6 DQL6 M_B_DQ3 M_B_DQ5 [3,10] M_B_A8 A7 DQL7 M_B_BS#0
R8 J7 R2 R2316 39_1%_2
M_B_A8 A7 DQL7 M_B_DQ3 [3,10] M_B_A9 A8 M_B_DQ25 M_B_BS#1
R2 R7 A3 R2334 39_1%_2
M_B_A9 R7 A8 A3 M_B_DQ12 M_B_A10 M3 A9 DQU0 B8 M_B_DQ30 M_B_BG#0
M_B_DQ12 [3,10] R2318 39_1%_2
M_B_A10 M3 A9 DQU0 B8 M_B_DQ15 M_B_A11 T2 A10/AP DQU1 C3 M_B_DQ29 M_B_CKE0
M_B_DQ15 [3,10] R2322 39_1%_2
M_B_A11 T2 A10/AP DQU1 C3 M_B_DQ13 M_B_A12 M7 A11 DQU2 C7 M_B_DQ31 M_B_CS#0
M_B_DQ13 [3,10] R2336 39_1%_2
M_B_A12 M7 A11 DQU2 C7 M_B_DQ14 M_B_A13 T8 A12/BC DQU3 C2 M_B_DQ24 M_B_A0
R2313 39_1%_2
M_B_A13 A12/BC DQU3 M_B_DQ8 M_B_DQ14 [3,10] A13 DQU4 M_B_DQ27 M_B_A1
T8 C2 C8 R2328 39_1%_2
A13 DQU4 M_B_DQ10 M_B_DQ8 [3,10] M_B_WE# DQU5 M_B_DQ28 M_B_A2
C8 M_B_DQ10 [3,10]
L2 D3 R2304 39_1%_2
M_B_WE# L2 DQU5 D3 M_B_DQ9 M_B_CAS# M8 WE_n/A14 DQU6 D7 M_B_DQ26 M_B_A3

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[3] M_B_WE# M_B_DQ9 [3,10] R2342 39_1%_2
M_B_CAS# M8 WE_n/A14 DQU6 D7 M_B_DQ11 M_B_RAS# L8 CAS_n/A15 DQU7 M_B_A4
[3] M_B_CAS# M_B_DQ11 [3,10] R2315 39_1%_2
M_B_RAS# L8 CAS_n/A15 DQU7 RAS_n/A16 G3 M_B_A5
R2347 39_1%_2 C2719 C2720 C2721 C2722 C2723 C2724
[3] M_B_RAS# RAS_n/A16 M_B_DQSP0 M_B_BS#0 DQSL_t M_B_DQSP2 [3] M_B_A6
G3 N2 F3 R2314 39_1%_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2
M_B_BS#0 DQSL_t M_B_DQSN0 M_B_DQSP0 [3] M_B_BS#1 BA0 DQSL_c M_B_DQSN2 [3] M_B_A7
D
[3] M_B_BS#0
N2 F3 M_B_DQSN0 [3]
N8 B7 M_B_DQSP3 [3] R2330 39_1%_2 D
M_B_BS#1 N8 BA0 DQSL_c B7 M_B_DQSP1 BA1 DQSU_t A7 M_B_A8
[3] M_B_BS#1 M_B_DQSP1 [3] M_B_DQSN3 [3] R2302 39_1%_2
BA1 DQSU_t A7 M_B_DQSN1 M_B_BG#0 M2 DQSU_c M_B_A9
M_B_DQSN1 [3] R2329 39_1%_2
M_B_BG#0 M2 DQSU_c BG0 E7 M_B_A10
R2317 39_1%_2
[3] M_B_BG#0 BG0 DM L_n/DBIL_n M_B_DM2 [3] M_B_A11
E7 E2 R2303 39_1%_2
DM L_n/DBIL_n M_B_DM0 [3] M_B_RST# DM U_n/DBIU_n M_B_DM3 [3] M_B_A12
E2 M_B_DM1 [3]
P1 R2343 39_1%_2
+1.2VSUS M_B_RST# P1 DM U_n/DBIU_n RESET _n N9 M_B_A13
[3] M_B_RST# R2332 39_1%_2 C2725 C2726 C2727 C2728 C2729 C2730
RESET _n N9 T EN T7 +1.2VSUS M_B_WE#
R2320 39_1%_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2
T EN T7 +1.2VSUS M_B_CS#0 L7 NC M_B_CAS#
R2335 39_1%_2
M_B_CS#0 L7 NC M_B_CKE0 K2 CS B3 M_B_RAS#
R2337 39_1%_2
[3] M_B_CS#0 M_B_CKE0 CS M_B_CLKN0 CKE VDD#B3 M_B_ODT0
R2683 [3] M_B_CKE0
K2 B3 K8 B9 R2321 39_1%_2
M_B_CLKN0 K8 CKE VDD#B3 B9 M_B_CLKP0 K7 CK_c VDD#B9 D1 M_B_ACT#
1K_1%_2 [3] M_B_CLKN0 R2319 39_1%_2
M_B_CLKP0 K7 CK_c VDD#B9 D1 CK_t VDD#D1 G7
[3] M_B_CLKP0 CK_t VDD#D1 M_B_ACT# VDD#G7 M_B_BG#1
G7 L3 J1 R2344 *39_1%_2
M_B_ACT# L3 VDD#G7 J1 M_B_ALERT# P9 ACT _n VDD#J1 J9 C2679 C2680 C2681 C2682 C2683 C2684
[3] M_B_ACT# M_B_ALERT# ACT _n VDD#J1 ALERT _n VDD#J9
P9 J9 C2352 C2380 C2431 C2412 C2678 C2381 L1 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2
[3] M_B_ALERT#
M_B_ODT0
ALERT _n VDD#J9
VDD#L1
L1 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2
M_B_ODT0
M_B1_ZQ1
K3
ODT
VDD#L1
VDD#L9
L9 SDP DNS
K3 L9 F9 R1
[3,10] M_B_ODT0 M_B1_ZQ0
M_B1_UZQ0
F9
E9
ODT
ZQ
VDD#L9
VDD#R1
R1
T9
M_B1_UZQ1 E9 ZQ
UZQ/VSS
VDD#R1
VDD#T 9
T9 DDP stuff
UZQ/VSS VDD#T 9 M_B_PARITY T3 A1
M_B_PARITY T3 A1 PAR VDDQ#A1 A9
R2338
[3] M_B_PARITY PAR VDDQ#A1 A9 VDDQ#A9 C1 M_B_CLKN0
240_1%_2 R2697 39_1%_2
VDDQ#A9 C1 VDDQ#C1 D9 M_B_CLKP0
R2339 R2698 39_1%_2
VDDQ#C1 D9 R2300 R2301 VDDQ#D9 F2 C2685 C2686 C2687 C2688
0_5%_2
SDP 0ohm R6593 VDDQ#D9
VDDQ#F2
F2 C2349 C2418 C2385 C2350 240_1%_2 0_5%_2
VDDQ#F2
VDDQ#F8
F8 0.01u/16V_2 0.01u/16V_2 0.01u/16V_2 0.01u/16V_2
F8 0.01u/16V_2 0.01u/16V_2 0.01u/16V_2 0.01u/16V_2 G1
DDP 240ohm *0_5%_2
VDDQ#F8
VDDQ#G1
G1
G9 SDP 0ohm
VDDQ#G1
VDDQ#G9
G9
J2
C2733
VDDQ#G9 VDDQ#J2 0.1u/6.3V_2
J2 J8
VDDQ#J2
VDDQ#J8
J8 DDP 240ohm DDR4 VDDQ#J8
B2
DDR4 96-BALL
96-BALL B2 VSS#B2 E1 +1.2VSUS
VSS#B2 E1 VSS#E1 G8
VSS#E1 G8 VSS#G8 K1
VSS#G8 K1 VSS#K1 K9 C2732 10u/6.3V_4
+2.5V_SUS VSS#K1 K9 +2.5V_SUS VSS#K9 N1 C2731 10u/6.3V_4
VSS#K9 N1 VSS#N1 T1 C2384 10u/6.3V_4
VSS#N1 T1 VSS#T 1 C2434 10u/6.3V_4
VSS#T 1 B1 A2 C2386 10u/6.3V_4
B1 A2 R9 VPP#B1 VSSQ#A2 A8 C2410 10u/6.3V_4
R9 VPP#B1 VSSQ#A2 A8 VPP#R9 VSSQ#A8 C9
VPP#R9 VSSQ#A8 C9 VSSQ#C9 D2
VSSQ#C9 D2 VSSQ#D2 D8
VSSQ#D2 D8 C2351 C2416 VSSQ#D8 E3
VSSQ#D8 E3 VSSQ#E3 E8 +VREF_CA1
1u/6.3V_4 1u/6.3V_4
VSSQ#E3 E8 +VREF_CA1 VSSQ#E8 F1
C2403 C2448 VSSQ#E8 F1 VSSQ#F1 H1
VSSQ#F1 H1 VSSQ#H1 H9
1u/6.3V_4 1u/6.3V_4 VSSQ#H1 VSSQ#H9
H9
C VSSQ#H9 MD@DDR4_96P M1 C
MD@DDR4_96P M1 1 VREFCA
R2684 *0_5%_2 TP9078
VREFCA M9
M9 *PAD
BG1/VSS
BG1/VSS

C2689 C2690
C2470 C2469 1000p/25V_2 0.1u/6.3V_2
1000p/25V_2 0.1u/6.3V_2

M_B_BG#1_R1 M_B_BG#1
R2687 *0_5%_2
M_B_BG#1_R0 M_B_BG#1
R2346 *0_5%_2
M_B_BG#1 [3]

R2688
R2685 0_5%_2 SDP stuff R2688 unstuff R2687
0_5%_2 SDP stuff R2685 unstuff R2346 DDP unstuff R2688 stuff R2687
DDP unstuff R2685 stuff R2346

U2014 U2013

M_B_A0 P3 G2 M_B_DQ40 M_B_A0 P3 G2 M_B_DQ48

M_B_A1 P7 A0 DQL0 F7 M_B_DQ47 M_B_A1 P7 A0 DQL0 F7 M_B_DQ51
+VREF_CA0 +VREF_CA1
M_B_A2 R3 A1 DQL1 H3 M_B_DQ41 M_B_A2 R3 A1 DQL1 H3 M_B_DQ49
M_B_A3 N7 A2 DQL2 H7 M_B_DQ46 M_B_A3 N7 A2 DQL2 H7 M_B_DQ54
M_B_A4 N3 A3 DQL3 H2 M_B_DQ44 M_B_A4 N3 A3 DQL3 H2 M_B_DQ53
M_B_A5 P8 A4 DQL4 H8 M_B_DQ42 M_B_A5 P8 A4 DQL4 H8 M_B_DQ50
R2389 *Short_0603
M_B_A6 P2 A5 DQL5 J3 M_B_DQ45 M_B_A6 P2 A5 DQL5 J3 M_B_DQ52
M_B_A7 R8 A6 DQL6 J7 M_B_DQ43 M_B_A7 R8 A6 DQL6 J7 M_B_DQ55
M_B_A8 R2 A7 DQL7 M_B_A8 R2 A7 DQL7
M_B_A9 R7 A8 A3 M_B_DQ32 M_B_A9 R7 A8 A3 M_B_DQ57
M_B_A10 M3 A9 DQU0 B8 M_B_DQ34 M_B_A10 M3 A9 DQU0 B8 M_B_DQ62
M_B_A11 T2 A10/AP DQU1 C3 M_B_DQ37 M_B_A11 T2 A10/AP DQU1 C3 M_B_DQ61
M_B_A12 M7 A11 DQU2 C7 M_B_DQ38 M_B_A12 M7 A11 DQU2 C7 M_B_DQ63
M_B_A13 T8 A12/BC DQU3 C2 M_B_DQ36 M_B_A13 T8 A12/BC DQU3 C2 M_B_DQ56
A13 DQU4 M_B_DQ39 A13 DQU4 M_B_DQ59 [9,34] +VDDQ_VTT
C8 C8
M_B_WE# DQU5 M_B_DQ33 M_B_WE# DQU5 M_B_DQ60 [3,7,9,34] +1.2VSUS
L2 D3 L2 D3
M_B_CAS# WE_n/A14 DQU6 M_B_DQ35 M_B_CAS# WE_n/A14 DQU6 M_B_DQ58 [9,34] +2.5V_SUS
M8 D7 M8 D7
M_B_RAS# L8 CAS_n/A15 DQU7 M_B_RAS# L8 CAS_n/A15 DQU7 [3] M_B_DQ[63:0]
RAS_n/A16 G3 RAS_n/A16 G3
M_B_BS#0 DQSL_t M_B_DQSP5 [3] M_B_BS#0 DQSL_t M_B_DQSP6 [3]
N2 F3 N2 F3
M_B_BS#1 BA0 DQSL_c M_B_DQSN5 [3] M_B_BS#1 BA0 DQSL_c M_B_DQSN6 [3]
B N8 B7 N8 B7 B
BA1 DQSU_t M_B_DQSP4 [3] BA1 DQSU_t M_B_DQSP7 [3]
A7 M_B_DQSN4 [3]
A7 M_B_DQSN7 [3]
M_B_BG#0 M2 DQSU_c M_B_BG#0 M2 DQSU_c
BG0 E7 BG0 E7
DM L_n/DBIL_n M_B_DM5 [3] DM L_n/DBIL_n M_B_DM6 [3]
E2 E2
M_B_RST# DM U_n/DBIU_n M_B_DM4 [3] M_B_RST# DM U_n/DBIU_n M_B_DM7 [3]
P1 P1
RESET _n N9 RESET _n N9
T EN T7 +1.2VSUS T EN T7 +1.2VSUS
M_B_CS#0 L7 NC M_B_CS#0 L7 NC
M_B_CKE0 K2 CS B3 M_B_CKE0 K2 CS B3
M_B_CLKN0 K8 CKE VDD#B3 B9 M_B_CLKN0 K8 CKE VDD#B3 B9
M_B_CLKP0 K7 CK_c VDD#B9 D1 M_B_CLKP0 K7 CK_c VDD#B9 D1
CK_t VDD#D1 G7 CK_t VDD#D1 G7
M_B_ACT# L3 VDD#G7 J1 M_B_ACT# L3 VDD#G7 J1
M_B_ALERT# P9 ACT _n VDD#J1 J9 M_B_ALERT# P9 ACT _n VDD#J1 J9
C2695 C2696 C2697 C2698 C2699 C2700 C2709 C2710 C2711 C2712 C2713 C2714
ALERT _n VDD#J9 L1 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 ALERT _n VDD#J9 L1 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2 0.22u/10V_2
M_B_ODT0 K3 VDD#L1 L9 M_B_ODT0 K3 VDD#L1 L9
[3,10] M_B_ODT0 M_B1_ZQ2 ODT VDD#L9 [3,10] M_B_ODT0 M_B1_ZQ3 ODT VDD#L9
F9 R1 F9 R1
M_B1_UZQ2 E9 ZQ VDD#R1 T9 M_B1_UZQ3 E9 ZQ VDD#R1 T9
UZQ/VSS VDD#T 9 R2693 UZQ/VSS VDD#T 9
M_B_PARITY T3 A1 M_B_PARITY T3 A1
R2689 240_1%_2
PAR VDDQ#A1 A9 PAR VDDQ#A1 A9
240_1%_2
R2690 VDDQ#A9 C1 R2694 VDDQ#A9 C1
VDDQ#C1 D9 VDDQ#C1 D9
0_5%_2 VDDQ#D9 0_5%_2 VDDQ#D9
F2 C2701 C2702 C2703 C2704 F2 C2715 C2716 C2717 C2718
VDDQ#F2 F8 0.01u/16V_2 0.01u/16V_2 0.01u/16V_2 0.01u/16V_2 VDDQ#F2 F8 0.01u/16V_2 0.01u/16V_2 0.01u/16V_2 0.01u/16V_2
VDDQ#F8 G1 VDDQ#F8 G1
SDP 0ohm VDDQ#G1 G9 VDDQ#G1 G9

DDP 240ohm
VDDQ#G9
VDDQ#J2
J2
J8
SDP 0ohm VDDQ#G9
VDDQ#J2
J2
J8
DDR4 VDDQ#J8
B2
DDP 240ohm DDR4 VDDQ#J8
B2
96-BALL 96-BALL
VSS#B2 E1 VSS#B2 E1
VSS#E1 G8 VSS#E1 G8
VSS#G8 K1 VSS#G8 K1
+2.5V_SUS VSS#K1 K9 +2.5V_SUS VSS#K1 K9
VSS#K9 N1 VSS#K9 N1
VSS#N1 T1 VSS#N1 T1
VSS#T 1 VSS#T 1
B1 A2 B1 A2
R9 VPP#B1 VSSQ#A2 A8 R9 VPP#B1 VSSQ#A2 A8
VPP#R9 VSSQ#A8 C9 VPP#R9 VSSQ#A8 C9
VSSQ#C9 D2 VSSQ#C9 D2
VSSQ#D2 D8 VSSQ#D2 D8
VSSQ#D8 E3 VSSQ#D8 E3
VSSQ#E3 E8 +VREF_CA1 VSSQ#E3 E8 +VREF_CA1
C2691 C2692 VSSQ#E8 F1 C2705 C2706 VSSQ#E8 F1
VSSQ#F1 H1 VSSQ#F1 H1
1u/6.3V_4 1u/6.3V_4 VSSQ#H1 1u/6.3V_4 1u/6.3V_4 VSSQ#H1
H9 H9
VSSQ#H9 VSSQ#H9
A MD@DDR4_96P M1 MD@DDR4_96P M1 A
VREFCA VREFCA
M9 M9
BG1/VSS BG1/VSS

C2693 C2694 C2707 C2708

1000p/25V_2 0.1u/6.3V_2 1000p/25V_2 0.1u/6.3V_2

M_B_BG#1_R2 M_B_BG#1 M_B_BG#1_R3 M_B_BG#1

R2691 *0_5%_2 R2695 *0_5%_2

SDP stuff R2692 unstuff R2691 SDP stuff R2696 unstuff R2695
R2692
DDP unstuff R2692 stuff R2691 R2696
DDP unstuff R2696 stuff R2695
Quanta Computer Inc.
0_5%_2 0_5%_2
PROJECT : Z8E
Size Document Number Rev
1A
CHA1 DDR4 MEMORY DOWN
Date: Wednesday , March 18, 2020 Sheet 10 of 44
5 4 3 2 1
 5 4 3 2 1

U2031B

A1 H2
A2 NC#A1 NC#H2 H3
A7 NC#A2 NC#H3 H12
A8 RFU#A7/NC NC#H12 H13
+3V A9 NC#A8 NC#H13 H14
U2031A A10 NC#A9 NC#H14 J1
E6 A3 A11 NC#A10 NC#J1 J2
VCC#1 DAT0 EMMC_DAT0 [5] NC#A11 NC#J2
F5 A4 A12 J3
VCC#2 DAT1 EMMC_DAT1 [5] NC#A12 NC#J3
C147 C149 J10 A5 EMMC_DAT2 [5]
A13 J12
K9 VCC#3 DAT2 B2 A14 NC#A13 NC#J12 J13
EMMC_DAT3 [5]

Vinafix.com
*[email protected]/10V_4
*[email protected]/10V_2 VCC#4 DAT3 B3 B1 NC#A14 NC#J13 J14
DAT4 EMMC_DAT4 [5] NC#B1 NC#J14
B4 EMMC_DAT5 [5] B7 K1
A6 DAT5 B5 +1.8V B8 NC#B7 NC#K1 K2
VSS#5/NC DAT6 EMMC_DAT6 [5] NC#B8 NC#K2
E7 B6 EMMC_DAT7 [5]
B9 K3
J5 VSS#1 DAT7 B10 NC#B9 NC#K3 K6
D
K8 VSS#6/NC M6 B11 NC#B10 RFU#K6/NC K7 D
VSS#4 CLK EMMC_CLK [5] NC#B11 RFU#K7/NC
G5 M5 EMMC_CMD [5] B12 K12
H10 VSS#2 CMD H5 R2714 B13 NC#B12 NC#K12 K13
+1.8V VSS#3 DS/NC EMMC_RCLK [5] NC#B13 NC#K13
B14 K14
*MMC@100K_5%_2 C1 NC#B14 NC#K14 L1
C6 K5 EMMC_RST_L_R C3 NC#C1 NC#L1 L2
M4 VCCQ#1 RSTN C5 NC#C3 NC#L2 L3
C148 C150 N4 VCCQ#2 P10 D2040 C7 NC#C5 NC#L3 L12
P5 VCCQ#3 VSF#7/NC E8 *MMC@SDM20U30-7 C8 NC#C7 NC#L12 L13
*[email protected]/10V_4
*[email protected]/10V_2 P3 VCCQ#5 VSF#6/NC G10 C9 NC#C8 NC#L13 L14
VCCQ#4 VSF#5/NC K10 2 1 C10 NC#C9 NC#L14 M1
VSF#4/NC PCIE_RST# [4,5,11,12,23,26,28,29,30] NC#C10 NC#M1
P6 C11 M2
P4 VSSQ#5 C12 NC#C11 NC#M2 M3
N5 VSSQ#4 F10 C13 NC#C12 NC#M3 M7
VSSQ#3 VSF#3/NC
NOT SURE HW RESET IS NEED. SW WILL RESET THE DEVICE UPON INIT NC#C13 NC#M7
N2 E10 C14 M8
C4 VSSQ#2 VSF#2/NC E9 D1 NC#C14 NC#M8 M9
VSSQ#1 VSF#1/NC D2 NC#D1 NC#M9 M10
EMMC_VDDI_BYP C2 D3 NC#D2 NC#M10 M11
VDDI D4 NC#D3 NC#M11 M12
*MMC@KLMBG2JETD-B041 D12 NC_Index#D4 NC#M12 M13
C146 D13 NC#D12 NC#M13 M14
*MMC@1u/6.3V_2 D14 NC#D13 NC#M14 N1
E1 NC#D14 NC#N1 N3
E2 NC#E1 NC#N3 N6
E3 NC#E2 NC#N6 N7
E5 NC#E3 NC#N7 N8
E12 RFU#E5/NC NC#N8 N9
E13 NC#E12 NC#N9 N10
E14 NC#E13 NC#N10 N11
F1 NC#E14 NC#N11 N12
F2 NC#F1 NC#N12 N13
F3 NC#F2 NC#N13 N14
F12 NC#F3 NC#N14 P1
F13 NC#F12 NC#P1 P2
F14 NC#F13 NC#P2 P7
G1 NC#F14 NC#P7/RFU P8
G2 NC#G1 NC#P8 P9
C G3 NC#G2 NC#P9 P11 C
G12 RFU#G3/NC NC#P11 P12
G13 NC#G12 NC#P12 P13
G14 NC#G13 NC#P13 P14
H1 NC#G14 NC#P14
NC#H1

*MMC@KLMBG2JETD-B041
TP2091

USB HUB *PAD

EEPROM_SDA 1
TP2089
1USB_HUB_5V

*PAD +3V_S5

nOVRP1
nOVRP2
PGANG
+3V_USB

PSELF
R2724 *HUB@0_5%_4
R2720 *HUB@0_5%_2 USB1_DM0-_HUB_R
[6] USB1_DM0-_HUB
R2721 *HUB@0_5%_2 USB1_DP0+_HUB_R
[6] USB1_DP0+_HUB
+3V +3V_USB
28
27
26
25
24
23
22
U2033
R2723 *HUB@0_5%_4
15 mil
I2C_SDA
VCC

SELFPWR
OVR#[1]
OVR#[2]
VREG

GANG
52.4mA

2
USB1_DM0-_HUB_R 1 21 +3V_USB_D R6530 +3V_USB
*HUB@0_5%_4
USB1_DP0+_HUB_R 2 DD-0 VCC_D 20 nOVRP3 C2758 C2759 C2760 C2761 C2762
3 DD+0 OVR#[3] 19 nOVRP4 *[email protected]/16V_4
*[email protected]/16V_4
*HUB@1U/6.3V_4
*HUB@1U/6.3V_4
*[email protected]/16V_4
[20] USBP8-_TS

1
DD-1 GL850G-OHY31OVR#[4]

2
4 18 EEPROM_SCL1
[20] USBP8+_TS +3V_USB DD+1 TEST RESET#_USB TP2090
5 17 C2757
6 VCC_A_5 RESET# 16 HUB_USB3_P 1 *[email protected]/16V_4
VCC_A_14

[20] USBP5-_CAM_HUB TP9085

VCC_A_9

1
7 DD-2 DD+4 15 HUB_USB3_N 1
[20] USBP5+_CAM_HUB DD+2 DD-4 TP9086
XOUT
RREF

DD+3
DD-3

GND
XIN

QFN28
GND
8
9
10
11
12
13
+3V_USB 14

29

B B
*HUB@GL852G-OHY60 GND
+3V_USB

XOUT
RREF

CARDREADER
XIN

+3V_USB

GND
[26] USBP7-_FP_HUB

2
[26] USBP7+_FP_HUB
C2763 C2764
*HUB@10u/6.3V_4*[email protected]/16V_4

1
Y2005 +3V_USB GND
4 3 XOUT +3V_USB

XIN 1 2
R6507
D8510 *HUB@100K_1%_4 nOVRP1 R566 *HUB@10K__5%_4
*HUB@12MHz *HUB@SDM20U30-7 R563 *HUB@10K_4
LCS nOVRP2
C2765 C2766 nOVRP3 R552 *HUB@10K_4
*HUB@22P/50V_4 *HUB@22P/50V_4 1 2 R2722 RESET#_USB
*HUB@0_5%_2
PSELF R556 *HUB@10K_4

nOVRP4 R551 *HUB@10K_4

GND GND C2767 R6508 EEPROM_SCL R77831 *HUB@0_5%_4
[4,5,11,12,23,26,28,29,30] PCIE_RST#
*HUB@1u/10V_4 *HUB@47K__5%_4 PGANG R559 *HUB@100K_1%_4

RREF R571 *HUB@619_1%_4

20140121:
for USB eye diagram, change R571 to 619 ohm.
GND
A A
20140117:change RESET from R/C to PLTRST# by jack discuss with vendor GND
20140123:change RESET from PLTRST# to R/C for S3 resume issue by jack's suggestion

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
eMMC
Date: Wednesday, March 18, 2020 Sheet 11 of 44
5 4 3 2 1
 1 2 3 4 5 6 7 8
U2029B
symbol2
AT41 PCIE_RX0P PCIE_TX0P AV35 PEG_RXP0_C C8134 [email protected]/6.3V_2
[2] PEG_TXP0 PEG_RXN0_C PEG_RXP0 [2]
[2] PEG_TXN0 AT40 PCIE_RX0N PCIE_TX0N AU35 C8133 [email protected]/6.3V_2 PEG_RXN0 [2]
AR41 PCIE_RX1P PCIE_TX1P AU38 PEG_RXP1_C C8127 [email protected]/6.3V_2
[2] PEG_TXP1 PEG_RXN1_C PEG_RXP1 [2]
AR40 PCIE_RX1N PCIE_TX1N AU39 C8132 [email protected]/6.3V_2
[2] PEG_TXN1 PEG_RXN1 [2]

[2] PEG_TXP2 AP41

AP40
PCIE_RX2P

PCIE_RX2N
PCIE_TX2P

PCIE_TX2N
AR37
AR38
PEG_RXP2_C
PEG_RXN2_C
C8118
C8126
[email protected]/6.3V_2
[email protected]/6.3V_2
PEG_RXP2 [2] debug port JTAG_TDO
[2] PEG_TXN2 PEG_RXN2 [2] JTAG_TDI TP8074
PEG_RXP3_C +1.8V_GFX JTAG_TMS TP8073
AM41 AN37 C8110 [email protected]/6.3V_2

Vinafix.com
PCIE_RX3P PCIE_TX3P
[2] PEG_TXP3 PEG_RXN3_C PEG_RXP3 [2] JTAG_TCK TP8076
[2] PEG_TXN3 AM40 PCIE_RX3N PCIE_TX3N AN38 C8116 [email protected]/6.3V_2 PEG_RXN3 [2] TP8075
JTAG_TESTEN
JTAG_TRSTB TP8007
AL41 PCIE_RX4P PCIE_TX4P AL37 TP8010
A AL40 PCIE_RX4N PCIE_TX4N AL38 DIECRACKMON A
BP_1 TP8067
BP_0 TP8001
AK41 PCIE_RX5P PCIE_TX5P AJ37 R2216 R2215 TP8002
AK40 PCIE_RX5N PCIE_TX5N AJ38
EV@10K_5%_2 EV@10K_5%_2 +3V_GFX
AJ41 PCIE_RX6P PCIE_TX6P AG37 U2029A
AJ40 PCIE_RX6N PCIE_TX6N AG38 symbol1
R2226 EV@33_5%_2BP_0 AA38 BP_0 JTAG_TDO AF41 JTAG_TDO
AH41 PCIE_RX7P PCIE_TX7P AE37 R2231 EV@33_5%_2BP_1 AA37 BP_1 JTAG_TDI AD40 JTAG_TDI R2600
AH40 PCIE_RX7N PCIE_TX7N AE38 JTAG_TMS AD41 JTAG_TMS
JTAG_TCK AE41 JTAG_TCK *[email protected]_1%_2

AV33 PCIE_REFCLKP PERSTB AV41 PEGX_RST#_R R8533 PEGX_RST#

*Short_0201 R8485 EV@10K_5%_2
DIECRACKMONB2 TESTEN AE40 JTAG_TESTEN
[5] CLK_PCIE_VGA_P PEGX_RST# [15] TEST6

[5] CLK_PCIE_VGA_N AU33 PCIE_REFCLKN JTAG_TRSTB AF40

AC41 PX_EN +3V_GFX
PX_EN
TP8068 JTAG
REV 0.91 JTAG_TRSTB R2599 EV@10K_1%_2R2619
R2620
*EV@1K_1%_2 EV@1K_1%_2
R2618 *EV@10K_1%_2

PCIE_ZVSS AU41 PCIE_ZVSS

REV 0.91

1
R2645
EV@200_1%_2

2
+3V_GFX
B
GPU Reset Signal B

C2655

*[email protected]/16V_4
C8155 *[email protected]/16V_4

5
[4,5,11,23,26,28,29,30] PCIE_RST# 1
4 PEGX_RST#
R8134 DGPU_HIN_RST#
*Short_0201 2
[5] VGA_RSTB
U8001
EV@TC7SH08FU(F)

3
MV R77865
EV@100K_5%_2

R8133 *EV@0_5%_2 reserve

high UMA only

DGPU_PW_CTRL#

low GPU power is control by PCH

GPUO

+3V

[6] DGPU_PW_CTRL# GPU_CLR_REQ4#

C C

R77832 DGPU_PW_CTRL#
EV@10K_5%_2 R77833 *EV@10K_5%_2
GPU CLK REQ GPU_CLR_REQ4# [5]

dGPU board ID DIS: Stuff

3
UMA: No Stuff

[5,41] R2431 *EV@0_5%_2 2 R6648

DGPU_PWREN
*Short_0201
Q2030
*EV@2N7002KTB
SVID ENABLE C2569

1
*[email protected]/6.3V_2
+3V_GFX

GPU_PCIE_CLKREQ# [15]
C96271

*[email protected]/16V_4
5

VGPU_CORE_PG 1
[39,41] VGPU_CORE_PG
4
PEGX_RST# SVID_EN [39]
2
U8023
EV@TC7SH08FU(F)
3

D R77850 EV@100K_1%_4 D

PROJECT : G3AC
Quanta Computer Inc.
Size Document Number Rev
Custom R17M-P1-70 - 1/5 (PCIE) 1A
NB5 Date: Wednesday, March 18, 2020 Sheet 12 of 44
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

[18] DQA0_[31:0] DQA1_[31:0] [18]

[18] MAA0_[8..0] MAA1_[8..0] [18]

Vinafix.com
U2029C
symbol3 U2029D
DQA0_0 L34 DQA0_0 DQA1_0 B27 DQA1_0 symbol4
DQA0_1 L37 DQA0_1 DQA1_1 A27 DQA1_1 C2 DQB0_0 DQB1_0 AH1
DQA0_2 L38 DQA0_2 DQA1_2 B26 DQA1_2 C1 DQB0_1 DQB1_1 AH2
A DQA0_3 J35 DQA0_3 DQA1_3 A26 DQA1_3 D2 DQB0_2 DQB1_2 AJ2 A
DQA0_4 G37 DQA0_4 DQA1_4 A24 DQA1_4 D1 DQB0_3 DQB1_3 AK1
DQA0_5 E38 DQA0_5 DQA1_5 B23 DQA1_5 F1 DQB0_4 DQB1_4 AL2
DQA0_6 E35 DQA0_6 DQA1_6 A23 DQA1_6 G2 DQB0_5 DQB1_5 AM1
DQA0_7 D35 DQA0_7 DQA1_7 B22 DQA1_7 DQA1_7
G1 DQB0_6 DQB1_6 AM2
DQA0_8 H41 DQA0_8 DQA1_8 B20 DQA1_8 H2 DQB0_7 DQB1_7 AN2
DQA0_9 H40 DQA0_9 DQA1_9 A20 DQA1_9 K2 DQB0_8 DQB1_8 AR1
DQA0_10 G41 DQA0_10 DQA1_10 B19 DQA1_10 K1 DQB0_9 DQB1_9 AR2
DQA0_11 G40 DQA0_11 DQA1_11 A19 DQA1_11 L2 DQB0_10 DQB1_10 AT1
DQA0_12 E40 DQA0_12 DQA1_12 B17 DQA1_12 L1 DQB0_11 DQB1_11 AT2
DQA0_13 D41 DQA0_13 DQA1_13 A16 DQA1_13 N2 DQB0_12 DQB1_12 AV2
DQA0_14 D40 DQA0_14 DQA1_14 B16 DQA1_14 P2 DQB0_13 DQB1_13 AW1
DQA0_15 C41 DQA0_15 DQA1_15 A15 DQA1_15 P1 DQB0_14 DQB1_14 AW2
DQA0_16 C40 DQA0_16 DQA1_16 B15 DQA1_16 R2 DQB0_15 DQB1_15 AY3
DQA0_17 B39 DQA0_17 DQA1_17 A14 DQA1_17 R1 DQB0_16 DQB1_16 BA3
DQA0_18 A39 DQA0_18 DQA1_18 B14 DQA1_18 T2 DQB0_17 DQB1_17 AY4
DQA0_19 B38 DQA0_19 DQA1_19 B13 DQA1_19 T1 DQB0_18 DQB1_18 BA4
DQA0_20 B36 DQA0_20 DQA1_20 A11 DQA1_20 U2 DQB0_19 DQB1_19 AY5
DQA0_21 A36 DQA0_21 DQA1_21 B11 DQA1_21 W1 DQB0_20 DQB1_20 BA7
DQA0_22 B35 DQA0_22 DQA1_22 A10 DQA1_22 W2 DQB0_21 DQB1_21 AY7
DQA0_23 A35 DQA0_23 DQA1_23 B10 DQA1_23 Y1 DQB0_22 DQB1_22 AY8
DQA0_24 B33 DQA0_24 DQA1_24 B8 DQA1_24 Y2 DQB0_23 DQB1_23 BA8
DQA0_25 B32 DQA0_25 DQA1_25 A7 DQA1_25 AB2 DQB0_24 DQB1_24 AR4
DQA0_26 A32 DQA0_26 DQA1_26 B7 DQA1_26 AC1 DQB0_25 DQB1_25 AR5
DQA0_27 B31 DQA0_27 DQA1_27 A6 DQA1_27 AC2 DQB0_26 DQB1_26 AU4
DQA0_28 A30 DQA0_28 DQA1_28 A4 DQA1_28 AD1 DQB0_27 DQB1_27 AU7
DQA0_29 B29 DQA0_29 DQA1_29 B4 DQA1_29 AF1 DQB0_28 DQB1_28 AN8
DQA0_30 B28 DQA0_30 DQA1_30 A3 DQA1_30 AF2 DQB0_29 DQB1_29 AV11
DQA0_31 A28 DQA0_31 DQA1_31 B3 DQA1_31 AG1 DQB0_30 DQB1_30 AU11
AG2 DQB0_31 DQB1_31 AP11

MAA0_0 G25 MAA0_0 MAA1_0 E15 MAA1_0

MAA0_1 H25 MAA0_1 MAA1_1 H15 MAA1_1 R5 MAB0_0 MAB1_0 AE7
MAA0_2 E27 MAA0_2 MAA1_2 G13 MAA1_2 R8 MAB0_1 MAB1_1 AE8
B MAA0_3 MAA1_3 B
D27 MAA0_3 MAA1_3 D13 N7 MAB0_2 MAB1_2 AG5
MAA0_4 D29 MAA0_4 MAA1_4 H11 MAA1_4 N4 MAB0_3 MAB1_3 AG4
MAA0_5 H27 MAA0_5 MAA1_5 H13 MAA1_5 L8 MAB0_4 MAB1_4 AJ4
MAA0_6 H23 MAA0_6 MAA1_6 H17 MAA1_6 N8 MAB0_5 MAB1_5 AG8
MAA0_7 E23 MAA0_7 MAA1_7 G17 MAA1_7 U8 MAB0_6 MAB1_6 AC8
MAA0_8 D25 MAA0_8 MAA1_8 D15 MAA1_8 U7 MAB0_7 MAB1_7 AC5
H29 MAA0_9 MAA1_9 E11 R4 MAB0_8 MAB1_8 AE4
L5 MAB0_9 MAB1_9 AJ8

WCKA0_0 D33 WCKA0_0 WCKA1_0 A22 WCKA1_0

[18] WCKA0_0 WCKA0B_0 WCKA1B_0 WCKA1_0 [18]
E33 WCKA0B_0 WCKA1B_0 B21 H1 WCKB0_0 WCKB1_0 AP1
[18] WCKA0B_0 WCKA1B_0 [18]
J2 WCKB0B_0 WCKB1B_0 AP2
WCKA0_1 A34 WCKA0_1 WCKA1_1 A8 WCKA1_1
[18] WCKA0_1 WCKA0B_1 WCKA1B_1 WCKA1_1 [18]
B34 WCKA0B_1 WCKA1B_1 B9 AB1 WCKB0_1 WCKB1_1 AN4
[18] WCKA0B_1 WCKA1B_1 [18]
AA2 WCKB0B_1 WCKB1B_1 AN5

EDCA0_0 G38 EDCA0_0 EDCA1_0 B24 EDCA1_0

[18] EDCA0_0 EDCA0_1 EDCA1_1 EDCA1_0 [18]
F41 EDCA0_1 EDCA1_1 A18 F2 EDCB0_0 EDCB1_0 AL1
[18] EDCA0_1 EDCA0_2 EDCA1_2 EDCA1_1 [18]
B37 EDCA0_2 EDCA1_2 B12 M2 EDCB0_1 EDCB1_1 AU2
[18] EDCA0_2 EDCA0_3 EDCA1_3 EDCA1_2 [18]
A31 EDCA0_3 EDCA1_3 B6 V1 EDCB0_2 EDCB1_2 BA6
[18] EDCA0_3 EDCA1_3 [18]
AD2 EDCB0_3 EDCB1_3 AV7
DDBIA0_0 J38 DDBIA0_0 DDBIA1_0 B25 DDBIA1_0
[18] DDBIA0_0 DDBIA0_1 DDBIA1_1 DDBIA1_0 [18]
F40 DDBIA0_1 DDBIA1_1 B18 E2 DDBIB0_0 DDBIB1_0 AK2
[18] DDBIA0_1 DDBIA0_2 DDBIA1_2 DDBIA1_1 [18]
A38 DDBIA0_2 DDBIA1_2 A12 M1 DDBIB0_1 DDBIB1_1 AV1
[18] DDBIA0_2 DDBIA0_3 DDBIA1_3 DDBIA1_2 [18]
B30 DDBIA0_3 DDBIA1_3 B5 V2 DDBIB0_2 DDBIB1_2 AY6
[18] DDBIA0_3 DDBIA1_3 [18]
AE2 DDBIB0_3 DDBIB1_3 AV9

ADBIA0 H21 ADBIA0 ADBIA1 H19 ADBIA1

[18] ADBIA0 ADBIA1 [18]
W8 ADBIB0 ADBIB1 AA8

CSA0B_0 H31 CSA0B_0 CSA1B_0 E7 CSA1B_0

[18] CSA0B_0 CSA1B_0 [18]
C G5 CSB0B_0 CSB1B_0 AL8 C

CASA0B D23 CASA0B CASA1B D17 CASA1B +1.35V_GFX

[18] CASA0B CASA1B [18] +1.35V_GFX
RASA0B D21 RASA0B RASA1B D19 RASA1B U4 CASB0B CASB1B AC4
[18] RASA0B RASA1B [18]
WEA0B G29 WEA0B WEA1B D11 WEA1B W4 RASB0B RASB1B AA4
[18] WEA0B WEA1B [18]
L4 WEB0B WEB1B AJ7
1

CKEA0 G21 CKEA0 CKEA1 E19 CKEA1

[18] CKEA0 CKEA1 [18]

1
R2666 W5 CKEB0 CKEB1 AA7
CLKA0 E31 CLKA0 CLKA1 D7 CLKA1 R77827
[18] CLKA0 CLKA1 [18]
CLKA0B D31 CLKA0B CLKA1B D9 CLKA1B [email protected]_1%_2 G4 CLKB0 CLKB1 AL5
[18] CLKA0B CLKA1B [18]
J4 CLKB0B CLKB1B AL4 [email protected]_1%_2
2

2
R2662 EV@120_1%_4 MEM_CALRA K15 MEM_CALRA MVREFDA K17 MVREFDA
R10 MEM_CALRB MVREFDB U10 MVREFDB
1

1
R2222 DRAM_RST_A_R L32
EV@10_1%_2 DRAM_RSTA R2665
[18] DRAM_RST_A REV 0.91 C96274 AM11 DRAM_RSTB R77828
R2223 EV@1u/6.3V_2 EV@100_1%_2 REV 0.91 C96275
[email protected]/F_2 EV@1u/6.3V_2 EV@100_1%_2
2

C2185 R2232

2
[email protected]_1%_2
EV@120P/50V_4

Need Voltage divider on MVREFDB ball for Polaris 24.

D D

PROJECT : G3AC
Quanta Computer Inc.
Size Document Number Rev
Custom R17M-P1-70 - 2/5 (Memory) 1A
NB5 Date: Wednesday, March 18, 2020 Sheet 13 of 44

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

ASIC - TMDP (E)

U2029O
symbol15
AY18
Vinafix.com
TX2P_DPE0P

TX2M_DPE0N BA18

A TX1P_DPE1P AY16 A

TX1M_DPE1N BA16

TX0P_DPE2P AY15

TX0M_DPE2N BA15

TXCEP_DPE3P AY14

TXCEM_DPE3N BA14

DDCAUX5P AU27

DDCAUX5N AV27

REV 0.91

B ASIC - TMDP (A/B) ASIC - TMDP (C/D) B

U2029G U2029H
symbol7 symbol8
TX2P_DPB0P AY32 TX2P_DPD0P AY22

TX2M_DPB0N BA32 TX2M_DPD0N BA22

TX1P_DPB1P AY31 TX1P_DPD1P AY21

TX1M_DPB1N BA31 TX1M_DPD1N BA21

TX0P_DPB2P AY30 TX0P_DPD2P AY20

TX0M_DPB2N BA30 TX0M_DPD2N BA20

TXCBP_DPB3P AY28 TXCDP_DPD3P AY19

TXCBM_DPB3N BA28 TXCDM_DPD3N BA19

AUX1P AY11

AUX1N BA11

DDCAUX3P AM21 DDC1CLK AY10

C AP21 BA10 C
DDCAUX3N DDC1DATA

TX5P_DPA0P AY36 TX5P_DPC0P AY27

TX5M_DPA0N BA36 TX5M_DPC0N BA27

TX4P_DPA1P AY35 TX4P_DPC1P AY26

TX4M_DPA1N BA35 TX4M_DPC1N BA26

TX3P_DPA2P AY34 TX3P_DPC2P AY25

TX3M_DPA2N BA34 TX3M_DPC2N BA25

TXCAP_DPA3P AY33 TXCCP_DPC3P AY24

TXCAM_DPA3N BA33 TXCCM_DPC3N BA24

D AUX2P AP19 D

AUX2N AM19
AUX_ZVSS
BA12 AUX_ZVSS

R2673 PROJECT : G3AC

EV@150_1%_2
DDCAUX4P AR23 DDC2CLK AV19 Quanta Computer Inc.
REV 0.91 DDCAUX4N AP23 DDC2DATA AU19
REV 0.91 Size Document Number Rev
A3 R17M-P1-70- 3/5 (Display) 1A
NB5 Date: Wednesday, March 18, 2020 Sheet 14 of 44

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+3V_GFX +3V_GFX
+3V_GFX
Reserve PIN
+3V_GFX
U2029E GPIO_15
R77853 *[email protected]_1%_2
GPU_PCIE_CLKREQ# AM31 symbol5 W40 GPIO_0
R8527 *EV@10K_5%_2 VDD_33 GPIO_0 R8107 R77854 [email protected]_1%_2
AA40 GPIO_1
GPIO_1
[29] DGPU_OPP# R77852 *Short_0201
R8069 VGA_ALERT
*EV@10K_5%_2 GPIO_2 AA35 GPIO_2 [email protected]_5%_2
GPIO_9_ROMSI
C2236 R77855 *[email protected]_1%_2
VGA_AC_BATT
R77861 [5,29] AC_PRESENT_EC R77851 *EV@0_5%_2R8103 *EV@0_5%_2 R77856 [email protected]_1%_2
AA34 VGA_AC_BATT
*EV@10K_1%_2 EV@1u/6.3V_2 GPIO_5_REG_HOT_AC_BATT
GPU_PCIE_CLKREQ# GPIO_6_TACH U35 GPU_GPIO6 D8001
1 2 PIN STRAPS
GPIO_8_ROMSO AP25 GPIO_8_ROMSO
AM25 GPIO_9_ROMSI TP8012
R8053 GPIO_9_ROMSI

AM27 GPIO_10_ROMSCK TP8008 EV@RB500V-40 +3V_GFX

EV@10K_1%_2
TEMP_FAIL
GPIO_10_ROMSCK

GPIO_11 W41 GPIO_11 TP8006

R8104 0 : Tx Full-swing Enable.
Y40 GPIO_12 GPIO_0

Vinafix.com
GPIO_12 *[email protected]_5%_2 U2029K R2607 *[email protected]_1%_2
Y41 GPIO_13 symbol11
GPIO_13
DBGDAT A_0
R2626 [email protected]_1%_2
A GPIO_14_HPD2 AU21 TypeC1_DDI1_HPD DBGDATA_0 L40 A
AA41 GPIO_15 TP8528 +3V_GFX L41
DBGDAT A_1
GPIO_15
U34
DBGDATA_1
M40
DBGDAT A_2 SI
GPIO_16_8P_DETECT D8509 DBGDATA_2

GPIO_17_THERMAL_INT R37 VGA_ALERT DBGDATA_3 M41 DBGDAT A_3

AV25 dGPU_DP_HPD TP8529 1 2 N40 DBGDAT A_4 GPIO_1

GPIO_18_HPD3 DBGDATA_4 R2604 *[email protected]_1%_2
+3V_GFX R38 TEMP_FAIL TP9081 N41 DBGDAT A_5
GPIO_19_CTF R12293 DBGDATA_5 R2623 *[email protected]_1%_2
AB40 GPIO_20 P40 DBGDAT A_6

SCL AC35
GPIO_20
AB41 GPIO_21_PCC EV@RB500V-40
DBGDATA_6
P41 DBGDAT A_7 1 : PCIe Gen3 Support.
R2227 [email protected]_5%_2 SCL GPIO_21 [email protected]_5%_2 DBGDATA_7

AC34 AP27 GPIO_22_ROMCSB TP8527 R40 GPIO_2

R2217 [email protected]_5%_2
SDA SDA GPIO_22_ROMCSB DBGDATA_8 R2218 [email protected]_1%_2
W37 GPIO_29 TP8013 GPU_GPIO6 R41
GPIO_29
[39] GPU_PWM_PROCHOT# R77867 *Short_0201 R12295 *EV@0_5%_2 DBGDATA_9 R2211 *[email protected]_1%_2
DGPUT_CLK DGPUT_CLK_R AW40 W38 GPIO_30 T40
DGPUT_DATA
R2644 *Short_0201
DGPUT_DATA_RAW41
SMBCLK GPIO_30
BA38 GENERICA
GPIO_30 [16]
DBGDATA_10
T41
0 : PCIe CLKREQB PM Disable.
R2643 *Short_0201 SMBDAT GENERICA DBGDATA_11

AV29 PS_1 TP8071 U40 GPIO_8_ROMSO

GENERICB DBGDATA_12 R2660 [email protected]_1%_2
GENERICC AU31 PS_2 DBGDATA_13 U41 R2661 *[email protected]_1%_2
GENERICD AV31 PS_3 DBGDATA_14 V40
AU25 HDMI_HPD_PCH V41
GENERICE_HPD4 R12296 DBGDATA_15
GPIO_SVC AU17 AV23 TP8530 GPIO_11
[39] SVI2_CLK R2243 *Short_0201 GPIO_SVC GENERICF_HPD5 R2608 [email protected]_1%_2
GPIO_SVD AV17 AM29 PS_0
[39] SVI2_DATA R2242 *Short_0201 GPIO_SVD GENERICG *[email protected]_5%_2 REV 0.91 R2627 *[email protected]_1%_2
GPIO_SVT AR17
[39] SVI2_SVT
R2241 *Short_0201 GPIO_SVT
AV21 GPU_EDP_HPD 001 : Without external ROM
AN34
HPD1
TP8531 SI GPIO_12
DDCVGACLK R2605 *[email protected]_1%_2
AP31 DDCVGADATA R2624 [email protected]_1%_2

TEST_PG R19M-P18-50 PU +3V_GFX

GPIO_13
R19M-M18-50 PD R2606 *[email protected]_1%_2
U2028 R2625 [email protected]_1%_2
GPIO_22_ROMCSB ROMCSB 1 8
C2668 *EV@1u/6.3V_2 R2669 EV@33_1%_2
AV40 GPIO_10_ROMSCK ROMSCK 6 CE# VDD
R67859 EV@1K_1%_2 CLKREQB
GPU_PCIE_CLKREQ# [12] R2657 EV@33_1%_2
R2672 *EV@1K_1%_2 TEST_PG AY13 TEST_PG WAKEB AU40 GPIO_9_ROMSI R2656 EV@33_1%_2
ROMSI 5 SCK C2663
+1.8V_GFX TEST_PG_BACO G_WAKEB GPIO_8_ROMSO SI
R2670 *EV@1K_1%_2 BA13 TEST_PG_BACO R2631 *EV@10K_1%_2 R2664 ROMSO
EV@33_1%_2 2 7 [email protected]/16V_4
SO HOLD#
3 4
1 : PCIe Tx de-emphasis EN.
C2666 *EV@1u/6.3V_2 PV: 4/28
AC40 LCD_VDDsuggest keep N.C WP# VSS GPIO_20
DIGON R2603 [email protected]_1%_2
*EV@MX25L2006EM1I-12G R2622 *[email protected]_1%_2
AC37 LCD_BLEN
TEST_PG_BACO R19M-P18-50 PU
K41
BL_ENABLE
AC38 LCD_BL_PWM 0 : Disable External BIOS ROM device
R19M-M18-50 NA RSVD#K41 BL_PWM_DIM
GPIO_22_ROMCSB
R34 RSVD#R34 R2667 *[email protected]_1%_2
HSYNC W34 HSYNC R2668 [email protected]_1%_2
B VSYNC W35 VSYNC 0 : VGA Controller Capacity EN. B
GPIO_29
R2230 R2229 R2601 R2219 [email protected]_1%_2
SWAPLOCKA AG34 R2212 *[email protected]_1%_2
SWAPLOCKB AE34 EV@10K_5%_2
EV@10K_5%_2
EV@10K_5%_2
GENLK_CLK AR29
GENLK_VSYNC AP29 R2221 *[email protected]_1%_2 HSYNC
R2214 [email protected]_1%_2
REV 0.91 00 : Special usage.
R2220 *[email protected]_1%_2 VSYNC
R2213 [email protected]_1%_2

R8118 *EV@0_5%_2 SI:0314 AMD suggest

+1.8V_GFX
AMD SI
Q2038A EV@2N7002KDW
DBGDATA_0
R2615 [email protected]_1%_2
3 4 DGPUT_DATA
[4,21,29] 2ND_MBDATA R2638 *[email protected]_1%_2
111 : No usable endpoint
R8123 *EV@0_5%_2 MLPS setting for R19M-M18-50 R2616 [email protected]_1%_2
DBGDATA_1
5

[12] PEGX_RST#
R2629 [email protected]_5%_2 R2639 *[email protected]_1%_2
R2630 [email protected]_5%_2 +3V_GFX
+3V_GFX R8122 EV@47K_1%_2 R19M-M18-50 R2613 [email protected]_1%_2 DBGDATA_2
PS_3[3:1] Vendor Type Vendor P/N R3pu R3pd
R2636 *[email protected]_1%_2
2

PS0[5:1] 11001 11001

6 1 DGPUT_CLK 000 Samsung- 2G 256Mx32 *2 K4G80325FC-HC25 NC 4.75K DBGDATA_3
[4,21,29] 2ND_MBCLK R2614 [email protected]_1%_2
PS1[5:1] 11011 11001 R2637 [email protected]_1%_2
100 Hynix- 2G 256Mx32 *2 H5GC8H24AJR-R2C 4.53K 4.99K 011 : Board ID
Q2038B EV@2N7002KDW
DBGDATA_4
PS2[5:1] 11000 11000 R2611 [email protected]_1%_2
R8128 *EV@0_5%_2 101 Micron- 2G 256Mx32 *2 MT51J256M32HF-80 :B 3.24K 5.62K R2634 [email protected]_1%_2

PS3[5:1] 11xxx 11xxx R2612 [email protected]_1%_2

DBGDATA_5

C
R2635 [email protected]_1%_2 C

DBGDATA_6
R2609 [email protected]_1%_2
+1.8V_GFX +1.8V_GFX +1.8V_GFX R2632 *[email protected]_1%_2
BIT[5:4] C ( nF) 01 : SMBUS slave address 0x41
R2610 *[email protected]_1%_2 DBGDATA_7

00 680 R2633 [email protected]_1%_2

R77817 R77819 R77822

[email protected]_1%_4 [email protected]_1%_4 *R18M-50@0_5%_4 01 82
PS_2
PS_0 PS_1
10 10

R77818 C28052 *[email protected]/16V_4 R77820 C28053 *[email protected]/16V_4 R77821 C28054 *[email protected]/16V_4 11 NC

R18M-50@2K_1%_4 [email protected]_1%_4 [email protected]_1%_4 VRAM Table of R19-P18-50
TOP B/S
Vendor Mfr. P/N SIZE
BIT[3:1] Rpu Rpd QBCON DBGDATA_[5:3]
+1.8V_GFX
AKG5QGUTL41
PS_2 000 NC 4750 Micron MT51J256M32HF-80:B 000

001 8450 2000 AKG5QGUTW34

PS_0 Hynix H5GC8H24AJR-R2C 001
rpu R77825
*[email protected]_1%_4 010 4530 2000 256Mx32
AKG5QGUT507 chekc with AMD
PS_3 Samsung K4G80325FC-HC25
PS_1 011 6980 4990 010
C
100 4530 4990 011
D rpd R77826 C28055 *[email protected]/16V_4
D
*[email protected]_1%_4
101 3240 5620

110 3400 10000

GDDR table 111 4750 NC

PROJECT : G3AC
Quanta Computer Inc.
Size Document Number Rev
Custom R17M-P1-70 - 4/5 (MISC) 1A
NB5 Date: Wednesday, March 18, 2020 Sheet 15 of 44
1 2 3 4 5 6 7 8
 5 4 3 2 1

+1.8V_GFX +1.8V_GFX
U2029J
symbol10
SI
AM13 TSVDD DPLUS N35

C8115 J8 TEMPIN0 R8047 R8046

DMINUS N34
EV@1U/6.3V_4 *[email protected]_1%_2*[email protected]_1%_2
J7 TEMPINRETURN
GPIO_28_FDO
GPIO_28_FDO U38 GPIO_28_FDO GPIO_30
[15] GPIO_30
N38 TS_A

REV 0.91

Vinafix.com R8042 R8041

*[email protected]_1%_2*[email protected]_1%_2

D D

M18:Xtal
P18:OSC

Y2004
4 2
XTALIN R77829 SI_XTALOUT 3 1 SI_XTALIN XTALOUT
*EV@0_5%_2 R77830 *EV@0_5%_2

EV@27MHZ/10ppm
C C
R2648 EV@1M_1%_2

C2657 EV@10P/50V_4 U8021

3 XOUT XIN 2 C2656 EV@10P/50V_4 +1.8V_GFX
11/05 add by AMD suggestion
U2029F 1 SI_VDD FB1041 2
VDD
symbol6 BA39 XTALIN R2652 SL_CLK_100M 4
XTALIN EV@0_5%_2 CLKOUT1 EV@BLM03AX121SN1D

5 SI_SS_SEL
SSON C2660 C96272
+1.8V_GFX [email protected]/25V_4 EV@10u/6.3V_4

VSS 6
R2650 [email protected]_1%_2
EV@Si51214-A1EAGM

R2651
XTALOUT AY39 XTALOUT *[email protected]_1%_2
TP9079

PLLCHARZ_L AV15 PLLCHARZ_L

PLLCHARZ_H AU15 PLLCHARZ_H TP8009
TP8011

REV 0.91 ANALOGIO AY38 ANALOGIO R2653 *[email protected]_1%_4

B B

A A

PROJECT : G3AC
Quanta Computer Inc.
Size Docum ent Num ber Rev
Cus tom R17M-P1-70 - 4/5 (MISC-2) 1A
NB5 Date: Wednes day, March 18, 2020 Sheet 16 of 44

5 4 3 2 1
 1 2 3 4 5 6 7 8

+VGA_CORE
+VDDCI
U2029I
N13 VDDC#0 symbol9 VDDCI#0 L13 U2029L U2029M
N15 L17

Vinafix.com
VDDC#1 VDDCI#1 symbol12 symbol13
N21 VDDC#2 VDDCI#2 L21 A2 VSS#0 VSS#58 J39 AA5 VSS#115 VSS#171 AN40
C2256 C2274 C2257 C2249 N23 VDDC#3 VDDCI#3 L25 C2254 C2281 C2258 C2272 A5 VSS#1 VSS#59 J40 AA10 VSS#116 VSS#172 AN41
EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2 N29 VDDC#4 VDDCI#4 L29 EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2 A9 VSS#2 VSS#60 J41 AA17 VSS#117 VSS#173 AP13
N31 VDDC#5 VDDCI#5 N11 A13 VSS#3 VSS#61 K21 AA19 VSS#118 VSS#174 AP17
A R13 U11 A17 K25 AA25 AR3 A
VDDC#6 VDDCI#6 VSS#4 VSS#62 VSS#119 VSS#175
R15 VDDC#7 VDDCI#7 AA11 A21 VSS#5 VSS#63 K29 AA27 VSS#120 VSS#176 AR7
R21 VDDC#8 VDDCI#8 AE11 A25 VSS#6 VSS#64 K40 AA32 VSS#121 VSS#177 AR11
R23 VDDC#9 A29 VSS#7 VSS#65 L3 AA39 VSS#122 VSS#178 AR19
C2248 C2247 C2275 R29 VDDC#10 A33 VSS#8 VSS#66 L7 AC3 VSS#123 VSS#179 AR21
EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2 R31 VDDC#11 C2239 C2282 A37 VSS#9 VSS#67 L11 AC7 VSS#124 VSS#180 AR25
U13 VDDC#12 EV@22u/6.3V_6 EV@22u/6.3V_6 A40 VSS#10 VSS#68 L15 AC11 VSS#125 VSS#181 AR27
U15 VDDC#13 B1 VSS#11 VSS#69 L19 AC17 VSS#126 VSS#182 AR31
U21 VDDC#14 B40 VSS#12 VSS#70 L23 AC19 VSS#127 VSS#183 AR35
U23 VDDC#15 B41 VSS#13 VSS#71 L27 AC25 VSS#128 VSS#184 AR39
U29 VDDC#16 C5 VSS#14 VSS#72 L31 AC27 VSS#129 VSS#185 AU1
U31 VDDC#17 C7 VSS#15 VSS#73 L35 AC39 VSS#130 VSS#186 AU3
C2265 C2264 W13 VDDC#18 C9 VSS#16 VSS#74 L39 AE1 VSS#131 VSS#187 AU9
C2250 W15 VDDC#19 C11 VSS#17 VSS#75 N1 AE3 VSS#132 VSS#188 AU23
EV@22u/6.3V_6 EV@22u/6.3V_6 EV@22u/6.3V_6 W21 VDDC#20 C13 VSS#18 VSS#76 N3 AE5 VSS#133 VSS#189 AU29
W23 VDDC#21 C15 VSS#19 VSS#77 N5 AE10 VSS#134 VSS#190 AW3
W29 VDDC#22 C17 VSS#20 VSS#78 N17 AE17 VSS#135 VSS#191 AW5
W31 VDDC#23 C19 VSS#21 VSS#79 N19 AE19 VSS#136 VSS#192 AW7
AA13 VDDC#24 C21 VSS#22 VSS#80 N25 AE25 VSS#137 VSS#193 AW9
C2251 C2279 C2262 AA15 VDDC#25 C23 VSS#23 VSS#81 N27 AE27 VSS#138 VSS#194 AW11
EV@22u/6.3V_6 EV@22u/6.3V_6 EV@22u/6.3V_6 AA21 VDDC#26 C25 VSS#24 VSS#82 N32 AE32 VSS#139 VSS#195 AW13
AA23
AA29
AA31
VDDC#27
VDDC#28
GPU SKU SELECTION C27
C29
C31
VSS#25
VSS#26
VSS#83
VSS#84
N37
N39
R3
AE35
AE39
AG3
VSS#140
VSS#141
VSS#196
VSS#197
AW15
AW17
AW19
VDDC#29 VSS#27 VSS#85 VSS#142 VSS#198
1

AC13 VDDC#30
+VGA_CORE C33 VSS#28 VSS#86 R7 AG7 VSS#143 VSS#199 AW21
C2261 C2278 + C2271 AC15 VDDC#31 C35 VSS#29 VSS#87 R11 AG11 VSS#144 VSS#200 AW23
EV@22u/6.3V_6EV@22u/6.3V_6 *EV@330U_2.5V_3528 AC21 VDDC#32 C37 VSS#30 VSS#88 R17 AG17 VSS#145 VSS#201 AW25
AC23 VDDC#33 C39 VSS#31 VSS#89 R19 AG19 VSS#146 VSS#202 AW27
2

AC29 VDDC#34 E1 VSS#32 VSS#90 R25 AG25 VSS#147 VSS#203 AW29

AC31 VDDC#35 E3 VSS#33 VSS#91 R27 AG27 VSS#148 VSS#204 AW31
AE13 VDDC#36 R2717 E4 VSS#34 VSS#92 R32 AG39 VSS#149 VSS#205 AW33
AE15 VDDC#37 [email protected]_1%_1206 E9 VSS#35 VSS#93 R35 AG40 VSS#150 VSS#206 AW35
SI:0310 add for power reguest AE21 VDDC#38 M18 E13 VSS#36 VSS#94 R39 AG41 VSS#151 VSS#207 AW37
B
AE23 VDDC#39 E17 VSS#37 VSS#95 U1 AJ1 VSS#152 VSS#208 AW39 B
AE29 VDDC#40
+VDDCI E21 VSS#38 VSS#96 U3 AJ3 VSS#153 VSS#209 AY1
AE31 VDDC#41 E25 VSS#39 VSS#97 U5 AJ5 VSS#154 VSS#210 AY2
AG13 VDDC#42 E29 VSS#40 VSS#98 U17 AJ10 VSS#155 VSS#211 AY9
AG15 VDDC#43 E39 VSS#41 VSS#99 U19 AJ11 VSS#156 VSS#212 AY12
AG21 VDDC#44 E41 VSS#42 VSS#100 U25 AJ35 VSS#157 VSS#213 AY17
AG23 VDDC#45 R2718 G3 VSS#43 VSS#101 U27 AJ39 VSS#158 VSS#214 AY23
AG29 VDDC#46 *[email protected]_1%_1206 G7 VSS#44 VSS#102 U32 AL3 VSS#159 VSS#215 AY29
AG31 VDDC#47 G11 VSS#45 VSS#103 U37 AL7 VSS#160 VSS#216 AY37
AJ13 VDDC#48 P18 G15 VSS#46 VSS#104 U39 AL10 VSS#161 VSS#217 AY40
AJ15 VDDC#49
+VDD_08 G19 VSS#47 VSS#105 W3 AL11 VSS#162 VSS#218 AY41
AJ17 VDDC#50 G23 VSS#48 VSS#106 W7 AL32 VSS#163 VSS#219 BA2
AJ19 VDDC#51 G27 VSS#49 VSS#107 W11 AL35 VSS#164 VSS#220 BA5
AJ21 VDDC#52 G31 VSS#50 VSS#108 W17 AL39 VSS#165 VSS#221 BA9
AJ23 VDDC#53 G35 VSS#51 VSS#109 W19 AN1 VSS#166 VSS#222 BA17
AJ25 VDDC#54 G39 VSS#52 VSS#110 W25 AN3 VSS#167 VSS#223 BA23
AJ27 VDDC#55 J1 VSS#53 VSS#111 W27 AN7 VSS#168 VSS#224 BA29
AJ29 VDDC#56 J3 VSS#54 VSS#112 W39 AN35 VSS#169 VSS#225 BA37
AJ31 VDDC#57 J5 VSS#55 VSS#113 AA1 AN39 VSS#170 VSS#226 BA40
AL13 VDDC#58 J34 VSS#56 VSS#114 AA3
AL15 VDDC#59 J37 VSS#57
AL17 VDDC#60 REV 0.91
AL19 VDDC#61
REV 0.91

AL21 VDDC#62
AL23 VDDC#63
AL25 VDDC#64 FB_VMEMIO C3 FB_VMEMIO
AL27 AV13 FB_VDDCI TP8000
VDDC#65 FB_VDDCI
FB_VDDC VDDCI_CORE_SENSE [39]
AL29 VDDC#66 FB_VDDC AR13
FB_VSSC VGPU_CORE_SENSE [39]
AL31 VDDC#67 FB_VSS AU13
VSS_GPU_SENSE [39]
REV 0.91

C C

+1.35V_GFX U2029N +1.8V_GFX

symbol14
K11 VMEMIO#0 VDD_18#0 AM15
K13 VMEMIO#1 VDD_18#1 AP15
K19 VMEMIO#2 VDD_18#2 AR15 C2283 C2285 C2276 C2670 C2669 C2277
C2263 C2312 C2298 C2235 K23 VMEMIO#3
EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2 K27 VMEMIO#4 EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2 EV@22u/6.3V_6 EV@10u/6.3V_4 EV@10u/6.3V_4
K31 VMEMIO#5
L10 VMEMIO#6
N10 VMEMIO#7 PV: 0425 change for +1.8V_GFX drop
W10 VMEMIO#8
C2280 C2253 C2291 C2305 AC10 VMEMIO#9
+VDD_08
EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2 AG10 VMEMIO#10
VDD_08#0 AC32
VDD_08#1 AG32
VDD_08#2 AG35
VDD_08#3 AJ32 C2237 C2289 C2287 C2290 C2288 C2238 C2286
C2306 C2304 VDD_08#4 AJ34 EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2
EV@1u/6.3V_2EV@1u/6.3V_2 VDD_08#5 AL34

VDD_08 W32

C2246 VSS AM23

C2273 VSS AM17
D EV@22u/6.3V_6 EV@22u/6.3V_6 REV 0.91
For cost effective designs where VDDCI and VDD_08 D

are supplied by one regulator, have the VDDCI and

VDD_08 balls joined on a unified power plane.

PROJECT : G3AC
Quanta Computer Inc.
Size Document Number Rev
Custom R17M-P1-70 - 5/5 (Power) 1A
NB5 Date: Wednesday, March 18, 2020 Sheet 17 of 44

1 2 3 4 5 6 7 8
 5 4 3 2 1

[13] DQA0_[31:0]
[13] DQA1_[31:0] +1.35V_GFX
+1.35V_GFX VRAM2002
VRAM2001 DQA1_23 M2 B1
DQ31__DQ7 VDDQ_B1
DQA0_30 M2 B1 DQA1_20 M4 B3
DQ31__DQ7 VDDQ_B1 DQ30__DQ6 VDDQ_B3
DQA0_31 M4 B3 [13] MAA0_[8..0] DQA1_22 N2 B12
DQ30__DQ6 VDDQ_B3 DQ29__DQ5 VDDQ_B12
DQA0_29 N2 B12 [13] MAA1_[8..0] DQA1_21 N4 B14
DQ29__DQ5 VDDQ_B12 DQ28__DQ4 VDDQ_B14
DQA0_28 N4 B14 DQA1_18 T2 D1
DQ28__DQ4 VDDQ_B14 DQ27__DQ3 VDDQ_D1
DQA0_27 T2 D1 DQA1_19 T4 D3
DQ27__DQ3 VDDQ_D1 DQ26__DQ2 VDDQ_D3
DQA0_25 T4 D3 DQA1_17 U2 D12
DQ26__DQ2 VDDQ_D3 DQ25__DQ1 VDDQ_D12
DQA0_26 U2 D12 DQA1_16 U4 D14
DQ25__DQ1 VDDQ_D12 DQ24__DQ0 VDDQ_D14
DQA0_24 U4 D14 DQA1_27 M13 E5
DQ24__DQ0 VDDQ_D14 DQ23__DQ15 VDDQ_E5

Vinafix.com
DQA0_17 M13 E5 DQA1_24 M11 E10
DQ23__DQ15 VDDQ_E5 DQ22__DQ14 VDDQ_E10
DQA0_16 M11 E10 DQA1_26 N13 F1
DQ22__DQ14 VDDQ_E10 DQ21__DQ13 VDDQ_F1
DQA0_18 N13 F1 DQA1_25 N11 F3
DQ21__DQ13 VDDQ_F1 DQ20__DQ12 VDDQ_F3
DQA0_19 N11 F3 DQA1_29 T13 F12
DQ20__DQ12 VDDQ_F3 DQ19__DQ11 VDDQ_F12
DQA0_20 T13 F12 DQA1_28 T11 F14
DQ19__DQ11 VDDQ_F12 DQ18__DQ10 VDDQ_F14
D
DQA0_22 T11 F14 DQA1_30 U13 VDDQ_G2 G2 D
DQ18__DQ10 VDDQ_F14 DQ17__DQ9
DQA0_21 U13 G2 DQA1_31 U11 G13
DQ17__DQ9 VDDQ_G2 DQ16__DQ8 VDDQ_G13
DQA0_23 U11 G13 MF = 1 DQA1_14 F13 H3
DQ16__DQ8 VDDQ_G13 DQ15__DQ23 VDDQ_H3
MF = 0 DQA0_13 F13 H3 DQA1_15 F11 H12
DQ15__DQ23 VDDQ_H3 DQ14__DQ22 VDDQ_H12
DQA0_14 F11 H12 DQA1_13 E13 K3
DQ14__DQ22 VDDQ_H12 DQ13__DQ21 VDDQ_K3
DQA0_12 E13 K3 DQA1_12 E11 K12
DQ13__DQ21 VDDQ_K3 DQ12__DQ20 VDDQ_K12
DQA0_15 E11 K12 DQA1_11 B13 L2
DQ12__DQ20 VDDQ_K12 DQ11__DQ19 VDDQ_L2
DQA0_8 B13 L2 DQA1_9 B11 L13
DQ11__DQ19 VDDQ_L2 DQ10__DQ18 VDDQ_L13
DQA0_11 B11 L13 DQA1_10 A13 M1
DQ10__DQ18 VDDQ_L13 DQ9__DQ17 VDDQ_M1
DQA0_9 A13 M1 DQA1_8 A11 M3
DQ9__DQ17 VDDQ_M1 DQ8__DQ16 VDDQ_M3
DQA0_10 A11 M3 DQA1_1 F2 M12
DQ8__DQ16 VDDQ_M3 DQ7__DQ31 VDDQ_M12
DQA0_3 F2 M12 DQA1_0 F4 M14
DQ7__DQ31 VDDQ_M12 DQ6__DQ30 VDDQ_M14
DQA0_1 F4 M14 DQA1_2 E2 N5
DQ6__DQ30 VDDQ_M14 DQ5__DQ29 VDDQ_N5
DQA0_0 E2 N5 DQA1_3 E4 N10
DQ5__DQ29 VDDQ_N5 DQ4__DQ28 VDDQ_N10
DQA0_2 E4 N10 DQA1_4 B2 P1
DQ4__DQ28 VDDQ_N10 DQ3__DQ27 VDDQ_P1
DQA0_4 B2 P1 DQA1_6 B4 P3
DQ3__DQ27 VDDQ_P1 DQ2__DQ26 VDDQ_P3
DQA0_5 B4 P3 DQA1_5 A2 P12
DQ2__DQ26 VDDQ_P3 DQ1__DQ25 VDDQ_P12
DQA0_7 A2 P12 DQA1_7 A4 P14
DQ1__DQ25 VDDQ_P12 DQ0__DQ24 VDDQ_P14
DQA0_6 A4 P14 T1
DQ0__DQ24 VDDQ_P14 VDDQ_T1
VDDQ_T1 T1 VDDQ_T3 T3
VDDQ_T3 T3 VDDQ_T12 T12
VDDQ_T12
T12 VDDQ_T14
T14
VDDQ_T14 T14 +1.35V_GFX
+1.35V_GFX MAA1_8 J5 RFU_A12_NC
MAA0_8 J5 MAA1_0 K4 C5
RFU_A12_NC A7_A8__A0_A10 VDD_C5
MAA0_7 K4 C5 MAA1_1 K5 C10
A7_A8__A0_A10 VDD_C5 A6_A11__A1_A9 VDD_C10
MAA0_6 K5 C10 MAA1_3 K10 D11
A6_A11__A1_A9 VDD_C10 A5_BA1__A3_BA3 VDD_D11
MAA0_5 K10 D11 MAA1_2 K11 G1
A5_BA1__A3_BA3 VDD_D11 A4_BA2__A2_BA0 VDD_G1
MAA0_4 K11 G1 MAA1_5 H10 G4
A4_BA2__A2_BA0 VDD_G1 A3_BA3__A5_BA1 VDD_G4
MAA0_3 H10 G4 MAA1_4 H11 G11
A3_BA3__A5_BA1 VDD_G4 A2_BA0__A4_BA2 VDD_G11
MAA0_2 H11 G11 MAA1_6 H5 G14
A2_BA0__A4_BA2 VDD_G11 A1_A9__A6_A11 VDD_G14
MAA0_1 H5 G14 MAA1_7 H4 L1
A1_A9__A6_A11 VDD_G14 A0_A10__A7_A8 VDD_L1
MAA0_0 H4 L1 L4
A0_A10__A7_A8 VDD_L1 VDD_L4
VDD_L4
L4 VDD_L11
L11
VDD_L11 L11 VDD_L14 L14
L14 WCKA1_0 D4 P11
VDD_L14 [13] WCKA1_0 WCK01__WCK23 VDD_P11
WCKA0_0 D4 P11 WCKA1B_0 D5 R5
[13] WCKA0_0 WCK01__WCK23 VDD_P11 [13] WCKA1B_0 WCK01#__WCK23# VDD_R5
WCKA0B_0 D5 R5 R10
WCK01#__WCK23# VDD_R5 VDD_R10
[13] WCKA0B_0 R10 WCKA1_1 P4
VDD_R10 [13] WCKA1_1 WCK23__WCK01
WCKA0_1 P4 WCKA1B_1 P5
[13] WCKA0_1 WCK23__WCK01 [13] WCKA1B_1 WCK23#__WCK01#
WCKA0B_1 P5 A1
WCK23#__WCK01# VSSQ_A1
[13] WCKA0B_1 A1 EDCA1_2 R2 A3
VSSQ_A1 EDC3__EDC0 VSSQ_A3
EDCA0_3 R2 A3 [13] EDCA1_2 EDCA1_3 R13 A12
EDC3__EDC0 VSSQ_A3 EDC2__EDC1 VSSQ_A12
[13] EDCA0_3 EDCA0_2 R13 A12 [13] EDCA1_3 EDCA1_1 C13 A14
EDC2__EDC1 VSSQ_A12 EDC1__EDC2 VSSQ_A14
[13] EDCA0_2 EDCA0_1 C13 A14 [13] EDCA1_1 EDCA1_0 C2 C1
EDC1__EDC2 VSSQ_A14 EDC0__EDC3 VSSQ_C1
C [13] EDCA0_1 EDCA0_0 [13] EDCA1_0 C
C2 EDC0__EDC3 VSSQ_C1 C1 VSSQ_C3 C3
[13] EDCA0_0 C3 DDBIA1_2 P2 C4
VSSQ_C3 DBI3#__DBI0# VSSQ_C4
DDBIA0_3 P2 C4 [13] DDBIA1_2 DDBIA1_3 P13 C11
DBI3#__DBI0# VSSQ_C4 DBI2#__DBI1# VSSQ_C11
[13] DDBIA0_3 DDBIA0_2 P13 C11 [13] DDBIA1_3 DDBIA1_1 D13 C12
DBI2#__DBI1# VSSQ_C11 DBI1#__DBI2# VSSQ_C12
[13] DDBIA0_2 DDBIA0_1 D13 C12 [13] DDBIA1_1 DDBIA1_0 D2 C14
DBI1#__DBI2# VSSQ_C12 DBI0#__DBI3# VSSQ_C14
[13] DDBIA0_1 DDBIA0_0 D2 C14 [13] DDBIA1_0 E1
DBI0#__DBI3# VSSQ_C14 VSSQ_E1
[13] DDBIA0_0 E1 E3
VSSQ_E1 VSSQ_E3
VSSQ_E3 E3 +1.35V_GFX VSSQ_E12 E12
+1.35V_GFX VSSQ_E12 E12 CASA1B G3 RAS#__CAS# VSSQ_E14 E14
[13] CASA1B
RASA0B G3 RAS#__CAS# VSSQ_E14 E14 RASA1B L3 CAS#__RAS# VSSQ_F5 F5
[13] RASA0B L3 F5 [13] RASA1B F10
CASA0B CAS#__RAS# VSSQ_F5 R2254 [email protected]_1%_2 VSSQ_F10
[13] CASA0B
R2239 [email protected]_1%_2 VSSQ_F10 F10 R2257 [email protected]_1%_2 VSSQ_H2 H2
R2238 [email protected]_1%_2 VSSQ_H2 H2 CKEA1 J3 CKE# VSSQ_H13 H13
J3 H13 [13] CKEA1 J11 K2
[13] CKEA0 CKEA0 CKE# VSSQ_H13 [13] CLKA1B CLKA1B CK# VSSQ_K2
CLKA0B J11 CK# VSSQ_K2 K2 CLKA1 J12 CK VSSQ_K13 K13
[13] CLKA0B J12 K13 [13] CLKA1 M5
[13] CLKA0 CLKA0 CK VSSQ_K13 VSSQ_M5
VSSQ_M5
M5 VSSQ_M10
M10
VSSQ_M10 M10 WEA1B G12 CS#__WE# VSSQ_N1 N1
CSA0B_0 G12 N1 [13] WEA1B CSA1B_0 L12 N3
[13] CSA0B_0 CS#__WE# VSSQ_N1 [13] CSA1B_0 WE#__CS# VSSQ_N3
WEA0B L12 WE#__CS# VSSQ_N3 N3 VSSQ_N12 N12
[13] WEA0B N12 N14
VSSQ_N12 VSSQ_N14
N14 R2679 EV@120_1%_4 ZQ_A1 J13 R1
VSSQ_N14 ZQ VSSQ_R1
ZQ_A0 J13 R1 SEN_A1 J10 R3
R2640 EV@120_1%_4 ZQ VSSQ_R1 R2253 EV@1K_1%_2 SEN VSSQ_R3
R2240 EV@1K_1%_2 SEN_A0 J10 R3 R4
SEN VSSQ_R3 VSSQ_R4
VSSQ_R4 R4 VSSQ_R11 R11
R11 DRAM_RST_A J2 R12
VSSQ_R11 RESET# VSSQ_R12
DRAM_RST_A J2 R12 MF_A1 J1 R14
[13] DRAM_RST_A RESET# VSSQ_R12 +1.35V_GFX R2671 EV@1K_1%_2 MF VSSQ_R14
J1 MF VSSQ_R14 R14 VSSQ_V1 U1
MF_A0 U1 U3
R2663 EV@1K_1%_2 VSSQ_V1 VSSQ_V3
VSSQ_V3 U3 VSSQ_V12 U12
VSSQ_V12 U12 VSSQ_V14 U14
VSSQ_V14 U14 A5 Vpp_NC
A5 Vpp_NC R2674 [email protected]_1%_2 U5 Vpp_NC1
U5 +1.35V_GFX B5
+1.35V_GFX R2641 [email protected]_1%_2 Vpp_NC1 R2675 [email protected]_1%_2 VSS_B5
B5 VREFD1_A1 A10 B10
R2642 [email protected]_1%_2 VSS_B5 C2671 EV@1U/6.3V_4 VREFD1 VSS_B10
C2658 EV@1U/6.3V_4 VREFD1_A0 A10 B10 U10 D10
VREFD1 VSS_B10 VREFD2 VSS_D10
U10 VREFD2 VSS_D10
D10 R2677 2.37K_1%_2 VSS_G5
G5
G5 +1.35V_GFX VREFD2_A1 G10
+1.35V_GFX R2655 [email protected]_1%_2 VSS_G5 R2678 [email protected]_1%_2 VSS_G10
VREFD2_A0 G10 H1
R2654 [email protected]_1%_2 VSS_G10 C2672 EV@1U/6.3V_4 VSS_H1
C2662 EV@1U/6.3V_4 VSS_H1 H1 VSS_H14 H14
VSS_H14 H14 VSS_K1 K1
K1 VREFC_A1 J14 K14
VSS_K1 +1.35V_GFX R2681 [email protected]_1%_2 VREFC VSS_K14
VREFC_A0 J14 K14 L5
+1.35V_GFX R2237 [email protected]_1%_2 VREFC VSS_K14 R2680 [email protected]_1%_2 VSS_L5
R2236 [email protected]_1%_2 VSS_L5 L5 C2673 EV@1U/6.3V_4 VSS_L10 L10
B C2216 EV@1U/6.3V_4 VSS_L10 L10 VSS_P10 P10 B
VSS_P10 P10 ADBIA1 J4 ABI# VSS_T5 T5
J4 T5 [13] ADBIA1 T10
ADBIA0 ABI# VSS_T5 VSS_T10
[13] ADBIA0 T10
VSS_T10

EV@GDDR5
EV@GDDR5

PV: 0422 follow AMD spec

+1.35V_GFX +1.35V_GFX

C2240 C2217 C2313 C2234 C2199 C2346 C2317 C2307 C2347 C2198
C2268 C2267
EV@10u/6.3V_4
EV@10u/6.3V_4 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2

+1.35V_GFX

C2243 C2231 C2215 C2266 C2208 C2212 C2269 C2233 C2252 C2196
DRAM SCAN PINS [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2 [email protected]/10V_2

SSH [J2] - SCAN SHIFT

SCK [G12] - SCAN CLOCK
SOUT [C2] - SCAN OUTPUT
SEN [J10] - SCAN ENABLE
SOE# [J1] - SCAN OUTPUT ENABLE

A Decoupling caps for single-sided configuration Decoupling caps for clamshell configuration Stitching caps OPTION for MEM signals that have a change of reference plane voltage. A
1 x 10uF per DRAM 1 x 10uF per 2 clamshell DRAMs Add stitching caps when required, one cap per two signals.
+1.35V_GFX 8 x 1uF per DRAM 8 x 1uF per 2 clamshell DRAMs
8 x 0.1uF per DRAM
+1.35V_GFX +1.35V_GFX

C2345 C2340 C2232 C2259 C2344 C2218 C2661 C2270 C2320

EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2
C2667 C2225 C2255 C2242 C2244 C2197 C2224 C2227 C2260 C2245 C2223 C2210 C2321 C2342 C2341 C2343 C2308 C2221 C2241
EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2
EV@10u/6.3V_4 EV@1u/6.3V_2
EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2

C2665
C2195
EV@10u/6.3V_4
C2207 C2229 C2209 C2213 C2214 C2228 C2211 C2219
EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2EV@1u/6.3V_2
PROJECT : G3AC
Quanta Computer Inc.
Size Docum ent Num ber Rev
Cus tom R17M-P1-70-GDDR5 VRAM 1/2 1A
NB5 Date: Wednes day, March 18, 2020 Sheet 18 of 44

5 4 3 2 1
 5 4 3 2 1

USB Charger to 3.0 (UBC)

+USBPWR0

24
+5VPCU
80 mils (Iout=2A)
U7 CTL1 CTL2 CTL3 ILIM_SEL
1 12 80 mils (Iout=2A)

Vinafix.com
VIN VOUT (RILIM_LO 1.2A)
ILIM_L
15 ILIM_LO (RILIM_HI 2.3A)
ILIM_HI
SDP 1 1 1 0
C328 16
ILIM_H C599 C310 C304
1u/10V_4
D
9
NC 17
R235 R223
39K_1%_2
100u/6.3V_12 470p/50V_4 0.1u/16V_4 CDP 1 1 1 1 D
20K_1%_2
13 GND#2
[6] USB_OC0# FAULT#
4 14
[29] USB_BC_ON ILIM_SEL GND#1 DCP 0 1 1 X
5 11 USBP1-_C iPAD charging current is about 2.1A so set on 2.3A
[29] USB_CHARGE_ON EN DM_IN USBP1+_C
R234 100K_5%_2 10 1.2A current limit of USB 3.0 SDP mode
6 DP_IN
[29] USB_CLT1 CTL1 USBP1-_U14
+5VPCU
R225 10K_5%_2 CTL2 7 2
R222 10K_5%_2 CTL3 8 CTL2 DM_OUT 3 USBP1+_U14
CTL3 DP_OUT

SLGC55544CVTR
RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:
1. ILIM_SEL is always set high
2. Load Detection - Port Power Management is not used
TI:AL002544001(TPS2544) 3. Mouse / Keyboard wake function is not used
If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use
Silergy: AL055544000 (SLGC55544VTR) RILIM_LO < 80.6 kΩ.
The following equation programs the typical current limit:
3/5 changoe AL055544001 (SLGC55544CVTR) for inrush crrent issue +5VPCU [21,32,33,41] (1) IOS_typ(mA) = 50,250/{RILIM_XX(KΩ)+0.1}
+5V_S5 [24,27,30,32,34,35,39] RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.
+3V [4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,33,34,35,37,41]

C C

+USBPWR0 +USBPWR1
USBP1- R251 *0_5%_2 USBP1-_C_R R211 *0_5%_2
USB 3.0 Connector (UB3) [6]
[6]
USBP1-
USBP1+
USBP1+ R252 *0_5%_2 USBP1+_C_R R218 *0_5%_2
R649 *0_5%_8
USBP1-_C R210 0_5%_2 USBP1-_C_R_N R646 *0_5%_8
USBP1+_C R217 0_5%_2 USBP1+_C_R_N
R246 0_5%_2 USBP1-_U14
+5V_S5 USBP1+_U14
R247 0_5%_2 U14
CN5 +USBPWR0
USB3.0 CONN
1 U5
1 VBUS USB30_RX1-_C 1
2
+USBPWR1 2 D- I/O 1 USB30_RX1+_C
C610 U28 C295 *1.6p/50V_4 3 10
4 3 D+ 2 I/O 6
1u/6.3V_4 Close USB3.0 4 VDD
5 1 C28066 0.33u/6.3V_2 USB30_RX1-_C 5 GND 9
IN OUT [6] USB30_RX1- USB30_RX1+_C 5 SSRX- GND_2
C28067 0.33u/6.3V_2 6 C593 3
[6] USB30_RX1+ 6 SSRX+ NC_1
2 7 8
GND C287 8 7 GND USBP1-_C_R_N 4 NC_2
USBON# 4 3 C608 C604 C612 *1.6p/50V_4 9 8 SSTX- 0.1u/16V_4 I/O 2 7 USBP1+_C_R_N
[29,30] USBON# /EN /OC 9 SSTX+ USB30_TX1-_C_R I/O 5
470p/50V_4 0.1u/16V_4 100u/6.3V_12 5

13
12
11
10

GND_1
I/O 3 6 USB30_TX1+_C_R
G524B2T11U I/O 4

13
12
11
10
[6] USB_OC1#

11
C277 0.22u/6.3V_2 USB30_TX1-_C R200 *Short_0201 USB30_TX1-_C_R
Enable: Low Active /2.5A [6] USB30_TX1-
C272 0.22u/6.3V_2 USB30_TX1+_C R198 *Short_0201 USB30_TX1+_C_R
BCD:AL002822000 (A3) [6] USB30_TX1+
USB30_ESD_AZ1065-06F.R7G
B B
GMT:AL000524007 (A3)
GMT:AL000524009 (A5) C280 C270 USB protection diodes for ESD.
*1.6p/50V_4 *1.6p/50V_4
as close as possible to USB connector pins.

R293 *Short_0201 USBP2-_C

[6] USBP2- USBP2+_C
R298 *Short_0201
[6] USBP2+ +USBPWR1
+USBPWR1
CN7 U11
USB3.0 CONN USB30_RX2-_C 1
1 I/O 1 10 USB30_RX2+_C
1 VBUS I/O 6
2 2
3 2 D- VDD 9
C368 *1.6p/50V_4
4 3 D+ 3 GND_2
C609
C28062 0.33u/6.3V_2 USB30_RX2-_C 5 4 GND NC_1 8
[6] USB30_RX2- USB30_RX2+_C 6 5 SSRX- USBP2-_C 4 NC_2
C28063 0.33u/6.3V_2 0.1u/16V_4
[6] USB30_RX2+ 6 SSRX+ I/O 2 USBP2+_C
7 7
C363 *1.6p/50V_4 8 7 GND USB30_TX2-_C_R 5 I/O 5

GND_1
9 8 SSTX- I/O 3 6 USB30_TX2+_C_R
9 SSTX+ I/O 4

13
12
11
10
13
12
11
10

11
USB30_ESD_AZ1065-06F.R7G
C351 0.22u/6.3V_2 USB30_TX2-_C R284 *Short_0201 USB30_TX2-_C_R
[6] USB30_TX2- USB30_TX2+_C USB30_TX2+_C_R
[6] USB30_TX2+
C349 0.22u/6.3V_2 R280 *Short_0201 USB protection diodes for ESD.
as close as possible to USB connector pins.
C352 C345
*1.6p/50V_4 *1.6p/50V_4

A
CAP close to different CONN A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
USB3/Charger
Date: Wednesday, March 18, 2020 Sheet 19 of 44
5 4 3 2 1
 5 4 3 2 1

+3V +5V [4,5,6,7,9,11,12,21,22,23,24,25,26,27,28,29,30,32,33,34,35,37,41]

[5,7,21,23,26,29,30,31,32,41]
[21,22,25,27,30,32,37]
[31,32,33,34,36,37,38,39,40,41]
+3V
+3VPCU
+5V
+VIN

+VIN R515
2A / 80mils
*Short_0805 +VIN_BLIGHT
+VIN_BLIGHT

25
C542
C106 C113
0.1u/16V_4 *22U/6.3V_6 C17 C526 0.1u/25V_4 eDP Conn. CN2
0.1u/16V_4
Vinafix.com 4.7u/25V_6
C527 0.01u/50V_4 196538-40041-3

42
D D

+VIN_BLIGHT 2A/80mils
C539 0.1u/16V_4 40
39
10/15 SoC side is 1.8V level C540 100p/50V_4 R34 +3VLCD_CON_R_C 38
C53 0.1u/10V_2 INT_eDP_AUXP_C *0_5%_6 37
[4] INT_EDP_AUXP +3V +3VLCD_CON_R 36
+3VLCD_CON R38 *Short_0603
C43 0.1u/10V_2 INT_eDP_AUXN_C 35
[4] INT_EDP_AUXN +3V_CCD_PWR1_C 34
R21 *1K_5%_2 BRIGHT +3V R518 0_5%_6
C538 0.1u/10V_2 INT_eDP_TXP0_C R12 *1K_5%_2 PCH_BLON_C 33
[4] INT_EDP_TXP0 CCD DMIC POWER R41 *0_5%_6 TP_PWR_C 32
INT_eDP_TXN0_C +5V 31
C537 0.1u/10V_2 R39 0_5%_2
[4] INT_EDP_TXN0
R516
TP POWER 33_5%_2
+3V 30
INT_eDP_TXP1_C [6] Board_ID6 TS_EN_R 29
[4] INT_EDP_TXP1 C536 0.1u/10V_2 C532 180p/50V_4 [29] TS_EN R33 *Short_0201
C91 180p/50V_4 VADJ1 28
C535 0.1u/10V_2 INT_eDP_TXN1_C BRIGHT R26 1K_1%_2 VADJ1 BL_ON 27
[4] INT_EDP_TXN1 ULT_EDP_HPD_R 26
[4] ULT_EDP_HPD R32 33_5%_2
C534 0.1u/10V_2 INT_eDP_TXP2_C R517 33_5%_2 25
[4] INT_EDP_TXP2 [5,6] Board_ID4 24
TP_PWR_C C541 180p/50V_4 R22 *100K_1%_2 INT_EDP_AUXP_C
C533 0.1u/10V_2 INT_eDP_TXN2_C C61 33p/50V_4 R18 *100K_1%_2 INT_EDP_AUXN_C 23
[4] INT_EDP_TXN2 +3V 22
R27
C531 0.1u/10V_2 INT_eDP_TXP3_C INT_EDP_TXP0_C 21
[4] INT_EDP_TXP3 100K_1%_2 20
C62 0.1u/25V_4 INT_EDP_TXN0_C
C530 0.1u/10V_2 INT_eDP_TXN3_C 19
[4] INT_EDP_TXN3 INT_EDP_TXP1_C 18
C67 1000p/50V_4
INT_EDP_TXN1_C 17
10/15 add , goes to SoC 16
C 15 C
INT_EDP_TXP2_C
R25 10_5%_2 BRIGHT INT_EDP_TXN2_C 14
[4] APU_DPST_PWM 13
R77848 *HUB@0_5%_2 INT_EDP_TXP3_C 12
[11] USBP5+_CAM_HUB R77849 INT_EDP_TXN3_C 11
[11] USBP5-_CAM_HUB *HUB@0_5%_2
R536 *Short_0201 DISP_ON 10
[4] APU_DISP_ON USBP5+_CAM R522 USBP5+_CAM_C 9
[6] USBP5+_CAM 0_5%_2
USBP5-_CAM R521 0_5%_2 USBP5-_CAM_C 8
[6] USBP5-_CAM 7
R520 *0_5%_2 USBP8_TS+_C 6
[11] USBP8+_TS R519 USBP8_TS-_C 5
*0_5%_2
[11] USBP8-_TS 4
L12 2 1 BLM15AG601SN1D DMIC_DAT_L_C 3
[21] DMIC_DAT_L DMIC_CLK_L_C 2
L11 2 1 BLM15AG601SN1D
[21] DMIC_CLK_L 1
+3VPCU

41
C528 C529
R23
*100K_1%_2 10P/50V_4 10P/50V_4
LCD back light +3V

LID# LID# [29,30]

1

B
R24 R13 B
10K_5%_2 10K_5%_2 D1 LID591#,EC intrnal PU
1N4148WS +3V

BL# BL_ON
2

PCH
3

C545 2.5A / 100mils +3VLCD_CON

[4] APU_LVDS_BLON R20 *Short_0201 PCH_BLON_C 5 2 2
EC_FPBACK# [29]
1u/6.3V_4 U23
[29] PCH_BLON_EC R28 *Short_0201 Q4A Q4B Q3 5 1
R19 IN OUT
2N7002KDW 2N7002KDW DDTC144EUA-7-F
4

100K_5%_2 2
EC DISP_ON 4
EN
GND

OC
3 C549 C551 C550
0.01u/50V_4 0.1u/16V_4 10U/6.3V_4
G524B1T11U

R535 R77866

100K_1%_2 100K_1%_2 +3V

A A

Enable:High Active /2.5A

GMT: AL000524004
BCD : AL022811000
EMS : AL005203000 Quanta Computer Inc.
PROJECT : Z8E
Size Document Number Rev
1A
eDP CONN/LID/CAM/D-MIC/TS
Date: Wednesday, March 18, 2020 Sheet 20 of 44
5 4 3 2 1
 5 4 3 2 1

Codec(ADO)
HP-R2

HP-L2

LINE1-VREFO-L
26
LINE1-VREFO-R

MIC2-VREFO

Vinafix.com CODEC_VREF C616

Close to codec
2.2u/6.3V_4 ADOGND
INT_AMIC-VREFO C620 10u/6.3V_4
D ADOGND D

10u/6.3V_6 C624

1u/10V_6 C615

1u/10V_6 C622
Change to 1U from Realtek's suggestion +5VA
R686 100K_5%_2
Codec PWR 1.5V(ADO)
C623 C627
+1.8VR313 *0_5%_4 0.1u/16V_4 10u/6.3V_4
+AZA_VDD
DIGITAL ANALOG
Place next to pin 26
R690
*Short_0402 L13 HCB1608KF-121T30 U30

36

35

34

33

32

31

30

29

28

27

26

25
1 2 AVDD2 ALC255-CG
+1.5V

VREF
CPVEE

LDO1-CAP
CPVDD

CBN

HP-OUT-R

LINE1-VREFO-R

MIC2-VREFO

AVSS1
HP-OUT-L

LINE1-VREFO-L

AVDD1
ADOGND

C619
10u/6.3V_4 37 24
ADOGND CBP LINE2-L
38 23
AVSS2 LINE2-R
ADOGND 39 22 LINE1-L
C629 10u/6.3V_4 LDO2-CAP LINE1-L
Place next to pin 40 Close to codec
40 21 LINE1-R R694 *0_5%_4
AVDD2 LINE1-R +5VPCU
Analog +5V_PVDD 41 20
L14 1 2 PVDD1 256@5VSTB/255@3V3STB R695 *Short_0603 R697 *Short_0402
Digital +5V L_SPK+ +3VPCU
PBY160808T-600Y-N 42 19 analog digital
SPK-L+ MIC-CAP C635 10u/6.3V_4
L_SPK- ADOGND
43 18 SLEEVE
SPK-L- MIC2-R/SLEEVE
C641 C637
R_SPK-
trace width of SLEEVE & RING2
10u/6.3V_4 0.1u/16V_4 44 17 RING2
SPK-R- MIC2-L/RING2 are required at least 40mil and
R_SPK+ 45 16 its length should be asshort as possible
SPK-R+ 256@PCBEEP/255@MONO-OUT C638 [email protected]/16V_4 PCBEEP_EC_C R707 22K_5%_2
Low is power down 46 15
amplifier output PVDD2 SPDIFO/FRONT JD/GPIO3 Placement near Audio Codec
GPIO0/DMIC-DATA

Close to codec PD# 47 GPIO1/DMIC-CLK 14 R718

PDB MIC2/LIN2 JD R715 200K_1%_4 HP_JD#
10K_1%_2
C 48 13 SENSEA C648 C

SDATA-OUT
SPDIFO/GPIO2 HP/LINE1 JD

LDO3-CAP
C650 C647 R360 *100K_1%_2 R699

SDATA-IN
+1.8V

DVDD-IO

PCBEEP
RESETB
DC DET

10u/6.3V_4 0.1u/16V_4 100p/50V_4 *Short_0201

DVDD

SYNC
49
BCLK
R734 100K_5%_2 +3V
DGND
Analog
1

10

11

12
Digital
DMIC-DATA34 R338 *0_5%_2
DMIC_DAT

DMIC_CLK

TP36
DC-DET

C659

R366 *Short_0201 D34 1N4148WS

TP41 1 2
C660 [email protected]/16V_4
+AZA_VDD ACZ_SPKR [5]
+3V R780 *Short_0603
10u/6.3V_4

R782 *Short_0201 ACZ_RST#_AUDIO [5]

1 2
PCBEEP_EC [29]
R746 *0_5%_2
2ND_MBCLK [4,15,29]
C656 C666 D35 1N4148WS
0.1u/16V_4 10u/6.3V_4 R754 *0_5%_2
2ND_MBDATA [4,15,29]
R756 *3.3K_5%_2
+3V +1.8V +1.5V
R772 *3.3K_5%_2

APU 1.8V
[20] DMIC_DAT_L
DMIC_DAT_L R745

DMIC_CLK_LR749
*Short_0201
R374 *Short_0402 Universal Audio Jack HEADPHONE/MIC/LINE combo (ADO)
Tied at one point only under [20] DMIC_CLK_L
22_5%_2 ACZ_SYNC_AUDIO [5]
the codec or near the codec
R77884 *Short_0201 DVDD_IO R373 *0_5%_4 SLEEVE/RING2 trace > 40mils
R281 *Short_0201 C663
R289 *0_5%_2 Close to codec 33p/50V_4 HP/LINE trace > 10mils
PCH_AZ_CODEC_SDIN0_R
R720
R691
*0_5%_2
*0_5%_2
R751 33_5%_2
ACZ_SDIN0 [5]
C661 C385
L/R spacing > 10mils
R275 *0_5%_2 0.1u/16V_4 10u/6.3V_4 MIC2-VREFO R260 2.2K_5%_2
BIT_CLK_AUDIO [5]
R345 *Short_0201 R420& R422 change to 62 ohm -> 3/11
C343 *1000p/50V_4 C667 *22p/50V_4 R257 2.2K_5%_2

C643 *0.1u/16V_4 Place next to pin 9 SLEEVE

ACZ_SDOUT_AUDIO [5] SLEEVE [30]
B B
R375 *Short_0201 RING2
RING2 [30]
ADOGND
HP-L2 R238 62_1%_4 HP-L3
HP-L3 [30]
Cap need near R752 *100K_1%_2 +3V
AVDD1 and HP-R2 R232 62_1%_4 HP-R3
HP-R3 [30]
AVDD2
HP_JD#
power source input HP_JD# [30]
R249 R224
LINE1-L C333 4.7u/6.3V_6 *10K_5%_2 *10K_5%_2 C340 C332 C327 C323
100p/50V_4 100p/50V_4 100p/50V_4 100p/50V_4
LINE1-VREFO-L R248 4.7K_5%_2

LINE1-VREFO-R R227 4.7K_5%_2

LINE1-R C334 4.7u/6.3V_6 ADOGND

Codec PWR 5V(ADO) Mute(ADO) APU 1.8V

+AZA_VDD +1.8V

R364
1K_5%_2
2

DIGITAL ANALOG D37

ACZ_RST#_AUDIO
PD# 2 1 3 1

+5V +5VA *RB500V-40 Q45

R355 C377 *PJA138K
1 2 *10K_5%_2 *1u/10V_4
L7 D36
HCB2012KF-220T60 2 1
AMP_MUTE# [29]
C378 C379 C375 C366
*0.1u/16V_4 *10u/6.3V_6 *10u/6.3V_6 *0.1u/16V_4 RB500V-40

A A
ADOGND
Internal Speaker 4 ohm : 40mil for each signal
5

40mil for each signal

CN11
51325-00401-001
R_SPK+ R445 *Short_0603 R_SPK+_1 1
R_SPK- R444 *Short_0603 R_SPK-_1 2
L_SPK- R443 *Short_0603 L_SPK-_1 3
L_SPK+ R442 *Short_0603 L_SPK+_1 4

C399 C398 C397 C396

Quanta Computer Inc.
1000p/50V_4 1000p/50V_4 1000p/50V_4 1000p/50V_4
PROJECT : Z8E
6

Size Document Number Rev

1A
3/24 Stuff for EMI Audio Codec/HP/SPK/Hole
Date: Wednesday, March 18, 2020 Sheet 21 of 44
5 4 3 2 1
 5 4 3 2 1

HDMI

27
Vinafix.com +3V

D HDMI_ALS_PD D
HDMI_HPD
21 20
HDMI_SDATA C560 C205 CN4
HDMI_SCLK C_TX2_HDMI+ 1
0.1u/16V_4 0.1u/16V_4 Data2+ 10444-19001
2 D2_shield
C_TX2_HDMI- 3
C_TX1_HDMI+ 4
Data2-
Data1+
5
C_TX1_HDMI- D1_shield
6
C_TX0_HDMI+ Data1-
C2744 C2745 7 Data0+
8

33
28
29
25

12
11
30

34
35
36
37
0.1u/16V_4 0.1u/16V_4
U26 C_TX0_HDMI- 9
D0_shield
C_IN_CLK 10
Data0-

From PCH

SCL_SNK
SDA_SNK
HPD_SNK
EPAD

VDD
PD#

VDDIO

THM1
THM2
THM3
THM4
CLK+
11
C_IN_CLK# CLK_shield
12
IN_CLK# C_IN_CLK#_R 10 18 INT_HDMICLK-_OUT C_IN_CLK# D5 CLK-
[4] IN_CLK# C2742 [email protected]/10V_2 R2705 *Short_0201 SSM14 spec is 40V 1A BAT54AW-L 13
IN_CLK C2743 [email protected]/10V_2 C_IN_CLK_R 9 IN_CKN OUT_CKN 19 INT_HDMICLK+_OUT R2706 *Short_0201 C_IN_CLK 1 5V_HSMBCK R163 2.2K_5%_2 14
CEC
[4] IN_CLK IN_D0# C_TX0_HDMI-_R 7 IN_CKP OUT_CKP INT_HDMITX0N_OUT C_TX0_HDMI- 5V_HSMBDT HDMI_SCLK Reserved
C2736 [email protected]/10V_2 21 R2699 *Short_0201 3 R164 2.2K_5%_2 15
[4] IN_D0# IN_D0 C_TX0_HDMI+_R 6 IN_D0N OUT_D0N INT_HDMITX0P_OUT C_TX0_HDMI+ +5V_HDMIC HDMI_SDATA DDC CLK
[4] IN_D0 C2737 [email protected]/10V_2 22 R2700 *Short_0201 2 16
IN_D1# C2738 [email protected]/10V_2 C_TX1_HDMI-_R 5 IN_D0P OUT_D0P 23 INT_HDMITX1N_OUT R2701 *Short_0201 C_TX1_HDMI- +5V C249 *10p/50V_4 17
DDC DATA
[4]
[4]
IN_D1#
IN_D1
IN_D1
IN_D2#
C2739 [email protected]/10V_2 C_TX1_HDMI+_R 4
C_TX2_HDMI-_R 2
IN_D1N
IN_D1P
PS8203 OUT_D1N
OUT_D1P
24 INT_HDMITX1P_OUT
INT_HDMITX2N_OUT
R2702 *Short_0201 C_TX1_HDMI+
C_TX2_HDMI-
Q33 +5V_HDMIC H=1.4mm(Max) C239 *10p/50V_4 18
DDC/CEC GND
+5V
[4] IN_D2# C2740 [email protected]/10V_2 26 R2703 *Short_0201 19
IN_D2 C2741 [email protected]/10V_2 C_TX2_HDMI+_R 1 IN_D2N OUT_D2N 27 INT_HDMITX2P_OUT R2704 *Short_0201 C_TX2_HDMI+ 1 +5V_HDMIC Hot Plug DET
[4] IN_D2 IN_D2P OUT_D2P VOUT

HPD_SRC
SDA_SRC
SCL_SRC

2
DCIN_EN 8 20 3 HDMI_HPD R98 HDMI_HPD_C
*Short_0201 23 22
+3V DCIN_EN CFG 17 +3V VIN C559 D24

THM5
THM6
THM7
THM8
REXT
GND

PRE
CEXT 2 *AZ5725-01F.R7G

EQ
*220p/50V_4
GND VC1 C183

1
C1104 *TVM0G5R5M220R 220p/50V_4

3
32
31
16
14

15
13

38
39
40
41
0.1u/16V_4 EQ0 R2708 4.7K_5%_2
AP2331SA-7
R107 R106 PRE R2709 4.7K_5%_2
DCIN_EN R2710 *4.7K_5%_2
2.2K_5%_2 2.2K_5%_2
HDMI_ALS_PD

INT_HDMI_AUXN
INT_HDMI_AUXP
R2711 *4.7K_5%_2

HDMI_HPD_Q
R93
EQ0
PRE *20K_1%_2
C INT_HDMI_AUXN C
[4] INT_HDMI_AUXN INT_HDMI_AUXP
[4] INT_HDMI_AUXP

checklist REV 2.0 : PD 20K

HDMI-detect [4] HDMI_HPD_Q
R104

5.9K_1%_4 10/30 change to 5.9K by FAE suggestion

+3V
EMI Solution
C_TX2_HDMI+ R595 *150_1%_2 C_TX2_HDMI-

C_TX1_HDMI+ R601 *150_1%_2 C_TX1_HDMI-

C212 C558 C210 C182 C222 C180 C181
C_TX0_HDMI+ R606 *150_1%_2 C_TX0_HDMI-
[email protected]/16V_4 [email protected]/16V_4 [email protected]/16V_4 [email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4
C_IN_CLK R589 *150_1%_2 C_IN_CLK#

ESD C_TX0_HDMI- D32 2 1 *PESD5V0H1BSF

C_TX0_HDMI+ D31 2 1 *PESD5V0H1BSF
C_TX1_HDMI- D30 2 1 *PESD5V0H1BSF
C_TX1_HDMI+ D29 2 1 *PESD5V0H1BSF
B C_TX2_HDMI- B
D28 2 1 *PESD5V0H1BSF
C_TX2_HDMI+ D27 2 1 *PESD5V0H1BSF
C_IN_CLK# D26 2 1 *PESD5V0H1BSF
C_IN_CLK D25 2 1 *PESD5V0H1BSF
HDMI_SCLK D3 2 1 *PESD5V0H1BSF
HDMI_SDATA D4 2 1 *PESD5V0H1BSF

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
HDMI/AMP HPA022642RTJR
Date: Wednesday, March 18, 2020 Sheet 22 of 44
5 4 3 2 1
 5 4 3 2 1

LAN RTL8111HSH-CG 28
For LDO mode support * Place Cc,Cd,Ce,Cf for RTL8107ESH-CG/RTL8111HSH-CG
RTL8107ESH-CG/RTL8111HSH-CG
close to each VDD10 pin-- 3, 22, 8 , 30
Stuff: La, Ca ,Cb
* Place Cg,Ch for RTL8107ESH-CG/RTL8111HSH-CG
Vinafix.com
LAN_AMBLED#
TP4
close to each VDD10 pin-- 22(reserved) LAN_LED1
TP2
LAN_LED2
D TP3 if ISOLATEB pin pull-low, D
the LAN chip will not drive it's PCI-E outputs
(excluding PCIE_WAKE# pin )
+1.05V_LAN

+3V
LAN_AMBLED#
Power trace Layout 寬 度 > 60mil +1.05V_LAN
R6 2.49K_1%_4
LAN_WLED# R31
+1.05V_LAN_REGOUT La +3V_LAN
R4 *Short_0805 1K_5%_2

LAN_LED1
LAN_LED2
XTAL2
XTAL1
ISOLATEB

RSET
PIN3 PIN8 PIN30 PIN22 PIN22 PIN22

Cc Cd Ce Cf Cg Ch R30
U1 15K_1%_4

32
31
30
29
28
27
26
25
C22 C64 C58 C65 C45 C93 C39 RTL8111HSH-CG
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 1u/6.3V_4 0.1u/16V_4

RSET

CKXTAL2
CKXTAL1
AVDD33#2

AVDD10#3

LED0
LED1/GPO
LED2
33
GND
Add 9 GND VIAs with thermal PAD
LAN_XTAL1 R16 10_5%_2 XTAL1
MDI0+ 1 24 +1.05V_LAN_REGOUT
MDIP0 REGOUT +1.05V_LAN_REGOUT
MDI0- 2 23
Y1 MDIN0 VDDREG +3V_LAN
3 22
XTAL2_R +1.05V_LAN AVDD10#1 DVDD10 +1.05V_LAN
1 3 R15 680_5%_4 XTAL2 MDI1+ 4 21 R6643 *Short_0201
2 4 5 MDIP1 LANWAKEB 20 PCIE_WAKE# [5,28]
MDI1- ISOLATEB
MDI2+ 6 MDIN1 ISOLATEB 19
MDIP2 PERSTB PCIE_RXN_LAN_L PCIE_RST# [4,5,11,12,26,28,29,30]
MDI2- 7 18 C88 0.1u/16V_4
25MHZ/30ppm 8 MDIN2 HSON 17 PCIE_RXP_LAN_L PCIE_RXN4_LAN [2]
C33 C32 +1.05V_LAN C94 0.1u/16V_4
AVDD10#2 HSOP PCIE_RXP4_LAN [2]
15p/50V_4 15p/50V_4

REFCLK_N
REFCLK_P
AVDD33#1
CLKREQB
For GbE

MDIN3
MDIP3

HSIN
HSIP
Leakage circuit (MPC) * Place RTL8111HSH-CG AL008111014
C +3V +3V For 10/100 C

9
10
11
12
13
14
15
16
* Place RTL8107ESH-CG AL008107000
+3V
CLK_PCIE_REQ4# have PU 10k. R52 R55
*10K_5%_2 10K_5%_2 MDI3+
CLK_PCIE_LANN [5]
MDI3-
2

MAIN POWER(3V_S0) CLK_PCIE_LANP [5]

PCIE_REQ_LAN#_R +3V_LAN PCIE_REQ_LAN#_R PCIE_TXN4_LAN [2]
3 1
S0 [5] PCIE_CLKREQ_LAN# PCIE_TXP4_LAN [2]

Q6
R44 2N7002K
*0_5%_2

* Place Cj and Ck, close to each VDD33 pin-- 11, 32 for

RTL8107ESH-CG/RTL8111HSH-CG RJ45
* For surge improvement, place Cm and Cn, close to each
VDD33 pin-- 11, 32(optional)
9 11
For Giga：Ub Ub CN3
2RJ1622-001111F
U21 MDI3-_1 8
MDI2+ 2 23 MDI2+_1 MDI3+_1 7
MDI2- 3 TD1+ MX1+ 22 MDI2-_1 MDI1-_1 6
+3V_LAN MDI3- 5 TD1- MX1- 20 MDI3-_1 MDI2-_1 5
MDI3+ 6 TD2+ MX2+ 19 MDI3+_1 MDI2+_1 4
MDI0- 8 TD2- MX2- 17 MDI0-_1 MDI1+_1 3
MDI0+ 9 TD3+ MX3+ 16 MDI0+_1 MDI0-_1 2
MDI1- 11 TD3- MX3- 14 MDI1-_1 MDI0+_1 1 2018/11/06
PIN11 PIN32 PIN11 PIN32 MDI1+ 12 TD4+ MX4+ 13 MDI1+_1 Need change ther footprint
TD4- MX4-
C42 C51 C30 C31 TRA_V_DAC 1 24 LAN_MCTG0 RaR11 75_1%_8
B TRA_V_DAC TCT1 MCT1 LAN_MCTG1 B
0.1u/16V_4 0.1u/16V_4 *4.7u/6.3V_4 *4.7u/6.3V_4 4 21 RbR10 75_1%_8 10 12
TRA_V_DAC 7 TCT2 MCT2 18 LAN_MCTG2 RcR8 75_1%_8
Cj Ck Cm Cn TRA_V_DAC 10 TCT3 MCT3 15 LAN_MCTG3 RdR9 75_1%_8
25 TCT4 MCT4
GND
C97 NS892407 For 10/100：Ra,Rb C525
0.01u/50V_4 For GiGA For Giga：Ra,Rb,Rc,Rd 10p/3KV_1808
BOT:GST5009B LF,DB0Z06LAN00
FCE :NS892407 ,DB0LL1LAN00

Reserve IOAC No Stuff Q2

AO3413 +3V_LAN +3V_S5

1 3 R7
+3VPCU
*2.2_1%_0805
R5
C28 100K_5%_2 C23 C25 C24 C29
2

0.1u/16V_4 10u/6.3V_6 0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4

[29] LANPWR# R14 10K_5%_2

C37
1000p/50V_4

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
LAN RTL8166EH/RTL8111HSH
Date: Wednesday, March 18, 2020 Sheet 23 of 44
5 4 3 2 1
 5 4 3 2 1

TYPE C and MUX PI2EQX632EXUBE [19,27,30,32,34,35,39] +5V_S5

29
[5,7,20,21,23,26,29,30,31,32,41] +3VPCU
[4,5,6,7,9,11,12,20,21,22,23,25,26,27,28,29,30,32,33,34,35,37,41] +3V

+1.8V +1.8V_SW +1.8V_SW

SIT-11 VBUS_EN OCP_DET

R6510 *T PC@10K_5%_2
R818 *T PC@0_5%_6

VMON
+5V_S5
+1.8V_S5 Rd
OCP_DET
R244
U2034

15
16

17
*T [email protected]_5%_2
R773 *T PC@0_5%_6 R824 R775 R2719
*T PC@10K_5%_2 *T PC@10K_5%_2 *T PC@10K_5%_4

VBUS_EN

VMON
OCP_DET
+1.8V_SW
Rc
20mil Power switch OCP pin Rc/Rd Note
C1 C2 C2769 C2768
D D

Vinafix.com
*T PC@220p/50V_4
*T PC@220p/50V_45447_CC1_CON Low Active (default) Rc/Rd mount
12
CC1 14 5447_CC2_CON
EC8 C690 C691 C692 R817 R785 CC2 High Active Rc mount,Rd don't mount
*T PC@22u/6.3V_6
*T [email protected]/16V_4
*T [email protected]/16V_4
*T [email protected]/16V_4 *T PC@10K_5%_2 *T PC@10K_5%_2 Zdiff=90ohm
Swap P/N for USB3.1 GEN2 11 USB30_T X-_T YPEC2_C USB30_T X-_T YPEC2
C2770 *T [email protected]/16V_4 For C_VBUS
SSRX/TX no via layout. C_TX2_1P/2N 10 USB30_T X+_T YPEC2_C C2771 USB30_T X+_T YPEC2
*T [email protected]/16V_4
10/30 SWAP P/N TO FOLOW OUTPUT SIDE C_TX2_1N/2P power switch OCP pin
USB3_SS0RX-_RE_C 4 24 USB30_RX-_T YPEC2_C C2772 USB30_RX-_T YPEC2
*T [email protected]/6.3V_2
USB3_SS0RX+_RE_C 5 SSRX_1P/2N C_RX2_1P/2N 1 USB30_RX+_T YPEC2_C USB30_RX+_T YPEC2 M 1_5441
C2773 *T [email protected]/6.3V_2 [29] EC_T YPEC_CHG_HI R6511 *short_0402
SSRX_1N/2P C_RX2_1N/2P
USB3_SS0T X-_RE_C 6 8 USB30_T X-_T YPEC1_C USB30_T X-_T YPEC1
*T PC@RT S5441E-GR C2774 *T [email protected]/16V_4 SIT-11 Rp configuration SIT-11
USB3_SS0T X+_RE_C 7 SSTX_1P/2N C_TX1_1P/2N 9 USB30_T X+_T YPEC1_C USB30_T X+_T YPEC1 LDO_3V3
C2775 *T [email protected]/16V_4
+1.8V_SW SSTX_1N/2P C_TX1_1N/2P
USB30_RX-_T YPEC1_C USB30_RX-_T YPEC1 M1_5441 M0_5441 Note
2 C2776 *T [email protected]/6.3V_2
C1 C_RX1_1P/2N 3 USB30_RX+_T YPEC1_C USB30_RX+_T YPEC1
Connected to USB3.1 Host C2777 *T [email protected]/6.3V_2 Rg Rp:900mA 0 1 Re/Rg mount,Re/Rh don't mount
C_RX1_1N/2P
Re

12
Zdiff=90ohm R6512 R6513 Rp:1.5A 1 0 Re/Rh mount,Rf/Rg don't mount
U2032 *T PC@10K_5%_4
*T PC@10K_5%_4
1 1 Re/Rg mount,Rf/Rh don't mount

C1
C684 *T [email protected]/16V_4
USB3_SS0T X+ 11 1 USB3_SS0T X+_RE
C2778 *T [email protected]/16V_4
USB3_SS0T X+_RE_C 25810_POL#_EC
R6514
GPIO_5441
*T PC@0_5%_2 23 need or not?
M 1_5441 M 0_5441 Rp:3.0A
[6] USB30_T X0+ AIN+ AOUT+ T P9099 M 1_5441 21 C_CONN_STAT
USB3_SS0T X- 10 2 USB3_SS0T X-_RE USB3_SS0T X-_RE_C M 0_5441 22 RP_SEL_M1
C675 *T [email protected]/16V_4 C2779 *T [email protected]/16V_4
[6] USB30_T X0- AIN- AOUT- RP_SEL_M0 USB30_RX-_T YPEC2 R6515 *T PC@220K_5%_2
9 3

VCON_IN
LDO_3V3
GND VDD(1V8) USB30_RX+_T YPEC2
R6516 R6517 *T PC@220K_5%_2
If can identify port1 or 2

EPAD
USB3_SS0RX+ USB3_SS0RX+_RE USB3_SS0RX+_RE_C

5V_IN
C700 *T [email protected]/16V_4 8 4 C2780 *T [email protected]/16V_4 *1T PC@0K_5%_4 18
[6] USB30_RX0+ BOUT+ BIN+ REXT USB30_RX-_T YPEC1
R6518 *T PC@220K_5%_2
C695 T [email protected]/16V_4 USB3_SS0RX- 7 5 USB3_SS0RX-_RE C2781 *T [email protected]/16V_4 USB3_SS0RX-_RE_C +3V
[6] USB30_RX0- BOUT- BIN- USB30_RX+_T YPEC1
C2

R6520 *T PC@220K_5%_2 25810_POL#_EC S0

25

20

19

13
+TYPEC_VBUS R6519
*PT N36001 *T [email protected]_1%_2
(to EC invert)
FVT-06 FVT-05
6

L: Port1
C2 FVT-05 C2782 H: Port2 R264
*T [email protected]/16V_4 USB3_SS0T X+_RE_C *T [email protected]_5%_2
R6521 C2783 R6522 *T PC@750K_1%_2
LDO_3V3 LDO_3V3 25810_POL#_EC
*T PC@200K_1%_2 *T [email protected]/10V_4 USB3_SS0T X-_RE_C
R6523 *short_0402 +5V_S5 R6524 *T PC@750K_1%_2
FVT-05 USB3_SS0RX+_RE_C
C R6525 *T PC@750K_1%_2 C
VM ON 11/20 change to LDO_3V3 to indicate attached state
USB3_SS0RX-_RE_C R6526 *T PC@750K_1%_2 1: Type-C is connected and under Attached.SRC state
0: Type-C is not connected and under Unattached.SRC state
R486 *T PC@0_5%_2 USBP_T YPC+_C
[6] USBP0+ R489 USBP_T YPC-_C FVT-06
[6] USBP0- *T PC@0_5%_2 R6527 C2784 C2785
*T PC@10K_1%_2 *T [email protected]/16V_4
*T PC@10u/6.3V_4

USB2.0 FVT-05
2

RV8 RV9
*T PC@PESD5V0F1BSF *T PC@PESD5V0F1BSF
1

TYPE C USB3.0 ESD +5V_S5

C459 *T PC@22u/6.3V_6

C458 *T PC@22u/6.3V_6

5447_CC1_CON T YPEC_SBU1 C710 *T PC@22u/6.3V_6

T YPEC_SBU2 C441 *T [email protected]/16V_4
5447_CC2_CON
C704 *T PC@47u/6.3V_8
D39 D19 C708 *T PC@47u/6.3V_8 +5V_S5 +T YPEC_VBUS
120mil MV-build ESD mount
C438 C711 *T PC@EGA10402V05AH_0.2p *T PC@EGA10402V05AH_0.2p C426 *T [email protected]/25V_4
*T PC@390p/50V_4 *T PC@390p/50V_4
C462 *T [email protected]/25V_4
B CN14 B
+T YPEC_VBUS
RV2
C2787 *T PC@10u/6.3V_6
USB30_RX+_T YPEC2 1 RV1
IN1 U2035
10 USB30_RX+_T YPEC2 USB30_RX+_T YPEC1 1
C2788 *T PC@10u/25V_8
USB30_RX-_T YPEC2 2 NC#4 IN1 10 USB30_RX+_T YPEC1 5 1
USB30_RX-_T YPEC2 USB30_RX-_T YPEC1 2
10/30 CHANGE TO 0 OHM BY FAE SUGGESTION C2786 *T PC@10u/6.3V_6 USB30_T X+_T YPEC1
IN2 9 NC#4 IN OUT A2 A4
3 NC#3 IN2 9 USB30_RX-_T YPEC1 2 USB30_T X-_T YPEC1 A3 SSTXp1 VBUS_1 B4
GND#1 8 3 NC#3 GND USB30_RX+_T YPEC1 SSTXn1 VBUS_3
B11 A9
USB30_T X-_T YPEC1 4 GND#2 GND#1 8 VBUS_EN R6528 *T PC@0_5%_2 VBUS_EN_EC_R 4 3 USB30_RX-_T YPEC1 B10 SSRXp1 VBUS_2 B9
IN3 7 USB30_T X-_T YPEC1 USB30_T X-_T YPEC2 4 GND#2 EN FLAG SSRXn1 VBUS_4
USB30_T X+_T YPEC1 5 NC#2 IN3 7 USB30_T X-_T YPEC2
IN4 6 USB30_T X+_T YPEC1 USB30_T X+_T YPEC2 5 NC#2 *T PC@G518A1T O1U USB30_T X+_T YPEC2 B2 A1
NC#1 IN4 6 USB30_T X+_T YPEC2 OCP_DET USB30_T X-_T YPEC2 SSTXp2 GND_1
SIT-11 B3 GND_2 A12
NC#1 USB30_RX+_T YPEC2 SSTXn2

3
A11 GND_3 B1
R6529 2 USB30_RX-_T YPEC2 SSRXp2
*T PC@M ESD3324PCR [29] EC_T ypeC_EN_R *T PC@0_5%_2 A10 GND_4 B12
SSRXn2
*T PC@M ESD3324PCR
Q2039
USBP_T YPC+_C 5
*T PC@2N7002K A6

1
USBP_T YPC-_C Dp1 GND_5
C2789 A7 6
USBP_T YPC+_C Dn1 GND_6
*T [email protected]/10V_2 FVT-01 B6 7
USBP_T YPC-_C Dp2 GND_7 8
B7 Dn2 GND_8
9
GND_9 10
5447_CC1_CON GND_10
A5 CC1
5447_CC2_CON
B5 CC2
T YPEC_SBU1 11
T P45 A8
T YPEC_SBU2 SBU1 NC_1 12
T P98 B8
D38 D41 SBU2 NC_2

*T PC@EGA10402V05AH_0.2p

*T PC@EGA10402V05AH_0.2p

*T PC@UCF3M -01N01-0P53

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Docum ent Num ber Rev
USB SW/TYPE-C RT5447 & Re-driver 1A

Date: Wednesday, M arch 18, 2020 Sheet 24 of 44

5 4 3 2 1
 5 4 3 2 1

KEYBOARD (KBC)
Touch Pad
30
Q21A
2N7002KDW

30
R450 *Short_0201 4 3 TP_SMB_CLK

30
[5] SMB_ALW_CLK
MY16
MY16 28 MY17 R469 4.7K_5%_2
28 MY17
MY16 [29] 27 MY0
Dual
MY17 [29]

5
27 MY0 26 MY1
26 MY0 [29] 25 +3V_S5 +3V_S5
MY1 MY2
25 MY1 [29] 24

2
MY2 MY3 R429 4.7K_5%_2
MY2 [29]
24
23
22
MY3
MY4
MY5
MY3
MY4
MY5
[29]
[29]
[29]
Vinafix.com 23
22
21
MY4
MY5
MY6
[5] SMB_ALW_DAT
R437 *Short_0201 1 6 TP_SMB_DATA

21 MY6 20 MY7
D MY6 [29] D
20 MY7 19 MY8 Q21B
19 MY7 [29] 18 2N7002KDW
MY8 MY9
18 MY8 [29] 17
MY9 MY10
17 MY9 [29] 16
MY10 MY11
16 MY10 [29] 15
MY11 MY12 +3V_S5 C682 0.1u/16V_4
15 MY11 [29] 14
MY12 MY13 +3V_S5 R787 4.7K_5%_2TPCLK
14 MY12 [29] 13
MY13 MY14 R784 4.7K_5%_2TPDATA
13 MY13 [29] 12
MY14 MY15
12 MY14 [29] 11
MY15 MX0 CN12

9
11 MY15 [29] 10
MX0 MX1 C681 10p/50V_4 51653-0080N-V02
10 MX0 [29] 9
MX1 MX2 R798 *Short_0201
9 MX1 [29] 8 1 2 HCB1005KF-330T30 1
MX2 MX3 [29] TPCLK L16 TPCLK-1
8 MX2 [29] 7 1 2 HCB1005KF-330T30 2
MX3 MX4 [29] TPDATA L15 TPDAT-1
7 MX3 [29] 6 3
MX4 MX5 C680 10p/50V_4
6 MX4 [29] 5 TP_SMB_DATA 4
MX5 MX6
5 MX5 [29] 4 TP_SMB_CLK 5
MX6 MX7
4 MX6 [29] 3 Q43 TP_INTH#_L 6
MX7
3 MX7 [29] 2 NBSWON# *2N7002K R796 *Short_02017
2 1 TP_INTH#_L [29] TPD_EN 8
R430 33_5%_2 NBSWON# 1 3 R820 *Short_0201
1 NBSWON# [29] TP_INTH# [5]
C439 C460

29

10
*10P/50V_4 *10P/50V_4 R795
29

FOR14@196153-28021-35 R797 R807 *Short_0201

2
TPD_INT#_EC [29]
*FOR15_17@196153-28021-35 D17 CN8 *10K_5%_2 dummy pin, please confirm need GND
CN10 AZ5725-01F.R7G 10K_5%_2
For 14"
1
1

Prevent ESD/EOS +3V_S5

For 15" D18 Layout near +3V_S5
*VPORT_0603_220K-V05 device
2

C C

MY5
MY6
MY3
C414
C415
C410
220p/25V_2
220p/25V_2
220p/25V_2
FAN check pin define
MY7 C416 220p/25V_2

MY8 C417 220p/25V_2

MY9 C419 220p/25V_2 +3V +5V +3V +5V
MY10 C418 220p/25V_2
MY11 C420 220p/25V_2

R365 R370 R371

1K_5%_2
MY1 C408 220p/25V_2 10K_5%_2 10K_5%_2
MY2 C409 220p/25V_2 FAN1

5
MY4 C411 220p/25V_2 50278-00401-001

2
MY0 C407 220p/25V_2
1
1 3 [29] FAN1_RPM FAN_PWM_C 2
MX4 C405 220p/25V_2
MX6 C402 220p/25V_2 [29] FAN_PWM 3
MX3 C404 220p/25V_2 Q16 4
30mil
MX2 C406 220p/25V_2 METR3904-G

6
MX7 C403 220p/25V_2
MX0 C412 220p/25V_2
B MX5 C401 220p/25V_2 B
MX1 C424 220p/25V_2

MY12 C421 220p/25V_2

MY13 C422 220p/25V_2
MY14 C423 220p/25V_2
MY15 C427 220p/25V_2
MY16 C400 220p/25V_2
MY17 C394 220p/25V_2

KB_BL LED (KBL@)

+5V +5V

C705 *[email protected]/6.3V_6
R827
*10K_1%_2
1

Q47
2 *KBL@DMP2130L-7
6
3

CN16
20mil 20mil
3

A A
*KBL@50505-00401-v01-4p-l
2 +5V_KB 4
[29] KB_BL_LED 3
Q44 2
*KBL@DDTC144EUA-7-F C714 C713 1
1

*[email protected]/6.3V_6 *[email protected]/50V_4

Quanta Computer Inc.

5

PROJECT : Z8E
Size Document Number Rev
1A
KB/TP/FAN
Date: Wednesday, March 18, 2020 Sheet 25 of 44
5 4 3 2 1
 5 4 3 2 1

31
TPM NPCT750
Vinafix.com
D
G-sensor (GS@) D

R2428 *TPM@10K_5%_2 PIRQA# +1.8V_TPM +1.8V_TPM_VSB

+1.8V_S5 R431 *GS@0_5%_2 +G_SEN_PW

APU_SPI_SI +3V
R448 *TPM@10K_1%_2 +1.8V_S5
U16
R452 *TPM@0_5%_6 C447 C436 1 2
R411 *TPM@10K_1%_2 SPI_TPM_CS R432 *TPM@0_5%_6 *GS@10u/6.3V_4 14 Vdd_IO NC#1 3
+1.8V_TPM *[email protected]/10V_2
VDD NC#2
OPTIONAL: +1.8V
+1.8V
Required if the Chipset
does not have an internal link HDD connector 10
ACCEL_INTA_R RES
pull-up on SPI CS# and/or R420 *TPM@0_5%_6 R453 *TPM@0_5%_6 to CPU [5] ACCEL_INT1
*GS@RB500V-40 1 2 D14
ACCEL_INT2_R
11
INT1 ADC2
15
to SATA HDD *GS@RB500V-40 1 2 D15 9
MISO signals. [27] ACCEL_INT2 INT2
R464 *GS@0_5%_2 7
C391 *TPM@10u/6.3V_6 R475 *GS@0_5%_2 G_MBDATA_R 6 SDO/SA0 5
[5,9] SMB_RUN_DAT R484 G_MBCLK_R SDA/SDI/SDO GND#1
C432 *[email protected]/10V_2 *GS@0_5%_2 4 12
[5,9] SMB_RUN_CLK SCL/SPC GND#2
C392 *[email protected]/10V_2 C446 *TPM@10u/6.3V_6 13
C413 *[email protected]/10V_2 C445 *[email protected]/10V_2 ACCEL_INT1 +G_SEN_PW 8 ADC3 16
+G_SEN_PW CS ADC1

22
8

1
G_MBDATA_R C464 *GS@33p/50V_4
ZAAR 22p

VHIO#2
VHIO#1

VSB
G_MBCLK_R C467 *GS@33p/50V_4 *GS@LIS3DHTR
TBD 30 2 C395
29 SCL/GPIO1 NC#1 3 *[email protected]/10V_2
PIRQA# R400 *TPM@0_5%_2 18 SDA/GPIO0 NC#2 5 R468 *GS@10K_1%_2 G_MBDATA_R
[5] PIRQA# PIRQ/GPIO2 NC#3 +G_SEN_PW
7 R483 *GS@10K_1%_2 G_MBCLK_R
C NC#4 9 C
APU_SPI_CLK R403 *TPM@33_5%_2APU_SPI_CLK_TPM 19 NC#5 10
[5,6,29] APU_SPI_CLK APU_SPI_SO SCLK NC#6
R417 *TPM@33_5%_2APU_SPI_SO_TPM 21 11
[5,29] APU_SPI_SO APU_SPI_SI MOSI/GPIO7 NC#7
R458 *TPM@33_5%_2APU_SPI_SI_TPM 24 12
[5,29] APU_SPI_SI SPI_TPM_CS R412 *TPM@0_5%_2 SPI_TPM_CS_TPM MISO NC#8
20 14
[5] SPI_TPM_CS SCS/GPIO5 NC#9 15
reverse DI DO 10/21 NC#11 25
6 NC#12 26
option if design PP GPIO3 NC#13
13 27
D16 1 2 *TPM@PESD5V0F1BL R423 *[email protected]_5%_2 PP 4 GPIO4 NC#14 28
PP/GPIO6 NC#15 31
D8515 NC#16 32

GND#2
GND#1
TPM_LRESET# NC#17

EPAD
[4,5,11,12,23,28,29,30] PCIE_RST# 1 2 17
PLTRST
*TPM@SDM20U30-7
+1.8V_TPM R77879 *TPM@10K_1%_2 U15

33
23
16
*TPM@NPCT750AAAYX
11/20 add follow CRB

PBA (PBA@) PBA_PWR

Change Power to +3VPCU 4/26

+3VPCU PBA_PWR
B C425 *[email protected]/16V_6 B
R422 *PBA@0_5%_2
1

R438
Q19 *PBA@0_5%_2
R418 *PBA@10K_1%_2 2 *PBA@DMP2130L-7
[29] PBA_FP_PWREN#

PBA_PWR_C
3

20mil PBA_PWR_R R804 20mil

C393 *PBA@0_5%_2

*[email protected]/50V_4
C456
C455
*[email protected]/6.3V_4
*[email protected]/50V_4

10
R77844 USBP7+_FP_R
*PBA@0_5%_2 8
[6] USBP7+_FP USBP7-_FP_R 7
[6] USBP7-_FP R77845 *PBA@0_5%_2
6
R77846 *PBA@0_5%_2 5
[11] USBP7+_FP_HUB 4
[11] USBP7-_FP_HUB R77847 *PBA@0_5%_2
3
2
1
A CN13 A

9
*PBA@196241-08021-3
USBP7-_FP_R
USBP7+_FP_R
2

EC6
*[email protected]
EC7 Quanta Computer Inc.
*[email protected]
PROJECT : Z8E
1

Size Document Number Rev

1A
TPM/G-Sensor/PBA
Date: Wednesday, March 18, 2020 Sheet 26 of 44
5 4 3 2 1
 5 4 3 2 1

SATA HDD & LED [19,24,30,32,34,35,39]

[20,21,22,25,30,32,37]
[4,5,6,7,9,11,12,20,21,22,23,24,25,26,28,29,30,32,33,34,35,37,41]
[4,5,6,7,11,23,25,28,29,32,37,38]
+5V_S5
+5V
+3V
+3V_S5 32
R834 GS_N@0_5%_2

Vinafix.com
13
R835 *GS@0_5%_2 +5V
1 ACCEL_INT2 [26]
2 +5V
3 Device sleep
D 4 DEVSLP0_R D
R837 *Short_0201 DEVSLP_HDD_C R573
5
*33K_1%_4
6 SATA_RXP0_CN R570 *0_5%_4
7 SATA_RXN0_CN
8 3 1 DEVSLP_HDD_C
9 SATA_TXN0_CN [5] DEVSLP0
10 SATA_TXP0_CN Q5403
11
R6645

2
12 2N7002K
+5V *33K_1%_4
14
12/18 flip follow CRB
51625-01201-001 C465 *10u/6.3V_4 +5V_S5 R6646 *Short_0402
HD1

C461 10u/6.3V_4

C454 0.1u/16V_4

C431 0.01u/10V_2 SATA_TXP0_IN SATA_TXP_OUT C471 0.01u/10V_2 SATA_TXP0_CN

[2] SATA_TXP0 SATA_TXN0_IN SATA_TXN_OUT SATA_TXN0_CN
C430 0.01u/10V_2 C470 0.01u/10V_2
[2] SATA_TXN0 SATA_RXN0_IN SATA_RXN_OUT SATA_RXN0_CN
[2] SATA_RXN0
C429 0.01u/10V_2 Re-Driver C469 0.01u/10V_2
C428 0.01u/10V_2 SATA_RXP0_IN SATA_RXP_OUT C468 0.01u/10V_2 SATA_RXP0_CN
[2] SATA_RXP0

C C

+3V +601_VCC

R488 *Short_0201
Near to U24 pin-10 and pin-20 as close as possible
C479 C450 C449 C476 C451 C466
10u/6.3V_4 0.1u/10V_2 0.1u/10V_2 0.1u/10V_2 0.1u/10V_2 0.1u/10V_2

SATA ODD (ODD@) SATA HDD Re-driver

20

+601_VCC
*ODD@132F18-100000-A2-R
CN15
B B
18 R471 4.7K_5%_2 EQ2 R470 *4.7K_5%_2
EC_ODD_EJ# [29]
17 R477 4.7K_5%_2 EQ1 R476 *4.7K_5%_2
16 R463 *10K_1%_2 +3V
15 +5VODD R810 *0_5%_8
+5V
14
13 C689 C688 C687 C686 C685 C683 EQ2 R466 4.7K_5%_2 DE1 R465 *4.7K_5%_2
12 H - 14dB R460 4.7K_5%_2 DE2 R461 *4.7K_5%_2
11 *[email protected]/50V_4
*[email protected]/50V_4
*[email protected]/16V_4
*[email protected]/16V_4
*ODD@10u/6.3V_6
*ODD@100u/6.3V_12 X - 0dB
10 L - 7dB
9 C699 *ODD@15p/50V_4 [5] R485 *4.7K_5%_2 DEW1
R481 4.7K_5%_2
8 ODD_PRSNT#_C ODD_PRSNT#
R812 *33_5%_2 EQ1 R436 *4.7K_5%_2 DEW2
R435 4.7K_5%_2
7 R806 *10K_1%_2 +3V C703 *ODD@180p/50V_4 H - 14dB R446 *4.7K_5%_2 EN R451 4.7K_5%_2
6 SATA_RXP1A_C C696 *[email protected]/50V_4 X - 0dB
SATA_RXN1A_C SATA_RXP1 [2] L - 7dB
5 C697 *[email protected]/50V_4
4 SATA_RXN1 [2]
3 SATA_TXP1A_C C693 *[email protected]/50V_4 DEW1
SATA_TXN1A_C SATA_TXP1 [2]
2 C694 *[email protected]/50V_4 SATA_TXN1 [2] H - Long Duration
1 X - NC (Long)

DEW1
L - Short Duration

EQ2

EQ1
DE1 +601_VCC
H - -2dB
19

X - -4dB
L - 0dB

20
19
18
17
16
DE2

VCC#2
EQ2
GND#3
EQ1
DEW1
H - -2dB 21
X - -4dB SATA_TXP0_IN 1 PPAD
L - 0dB SATA_TXN0_IN 2 RX1P 15 SATA_TXP_OUT
3 RX1N TX1P 14 SATA_TXN_OUT
DEW2 SATA_RXN0_IN 4 GND#1 TX1N 13
H - Long Duration SATA_RXP0_IN 5 TX2N GND#2 12 SATA_RXN_OUT
X - NC (Long) TX2P RX2N 11 SATA_RXP_OUT
L - Short Duration
DEW2 6 RX2P
EN 7 DEW2 22
SW7 - EN DE2 8 EN GND#4 23
H - Enabled DE1 9 DE2 GND#5 24
A L - Standby Mode 10 DE1 GND#6 25 A
+601_VCC VCC#1 GND#7 26
GND#8

U17
HDD_R@SN75LVCP601RTJR

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
HDD/ ODD
Date: Wednesday, March 18, 2020 Sheet 27 of 44
5 4 3 2 1
 5 4 3 2 1

[2] PCIE_RXN3_SSD
R852
R851
*Short_0201
*Short_0201
PCIE_RXN13_SSD_C
PCIE_RXP13_SSD_C
1
3
5
7
CN18

GND#1
GND#3
PETN3
NGFF MKEY
3.3Vaux_1
3.3Vaux_2
NC#10
2
4
6
8
100 mils
+3V_SSD 1.4A
+3V_SSD
[4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,29,30,32,33,34,35,37,41]
[20,21,22,25,27,30,32,37]
[5,7,20,21,23,26,29,30,31,32,41]
+3V
+5V
+3VPCU
33 +3V_SSD +3V
[2] PCIE_RXP3_SSD PETP3 NC#11
9 10 EC3 SSD@10u/6.3V_4R500 *Short_0805 EC4 SSD@10u/6.3V_4
11 GND#7 DAS/DSS#(I)(OD) 12
[2] PCIE_TXN3_SSD PERN3 3.3Vaux_3
13 14 C490 [email protected]/16V_2 EC5 [email protected]/16V_2
[2] PCIE_TXP3_SSD PERP3 3.3Vaux_4
15 16
R846 *Short_0201 PCIE_RXN14_SSD_C 17 GND#8 3.3Vaux_5 18 C491 *[email protected]/16V_2
[2] PCIE_RXN2_SSD

Vinafix.com
R845 *Short_0201 PCIE_RXP14_SSD_C 19 PETN2 3.3Vaux_6 20
[2] PCIE_RXP2_SSD 21 PETP2 NC#12 22 C489 *[email protected]/16V_2
23 GND#2 NC#13 24
[2] PCIE_TXN2_SSD PERN2 NC#14
[2] PCIE_TXP2_SSD
25 26
27 PERP2 NC#15 28 +3V_SSD
D
R844 *Short_0201 PCIE_RXN15_SSD_C 29 GND#9 NC#16 30 D
[2] PCIE_RXN1_SSD PCIE_RXP15_SSD_C PETN1 NC#17
R843 *Short_0201 31 32
[2] PCIE_RXP1_SSD PETP1 NC#2
33 34
35 GND#10 NC#3 36 11/20 add follow CRB
[2] PCIE_TXN1_SSD PERN1 NC#4
[2] PCIE_TXP1_SSD
37 38 R498 *Short_0201 TP9075
39 PERP1 DEVSLP 40 R77878
R850 *Short_0201 PCIE_RXN16_SSD_C 41 GND#11 NC#5 42 R501 *SSD@100K_1%_2
[2] PCIE_RXN0_SSD SATA B+/PETN0 NC#6 SSD@10K_1%_2
R849 *Short_0201 PCIE_RXP16_SSD_C 43 44
[2] PCIE_RXP0_SSD SATA B-/PETP0 NC#7 D6542
45 46
47 GND#12 NC#8 48 1 PCIE_RST#
[2] PCIE_TXN0_SSD SATA A-/PERN0 NC#9 PCIE_RST#_SSD PCIE_RST# [4,5,11,12,23,26,28,29,30]
[2] PCIE_TXP0_SSD
49 50 R497 *Short_0201 3
51 SATA A+/PERP0 PERST#/NC 52 2 R6024 *0_5%_4 PCIE_RST1#
CLK_PCIE_SSDN_C GND#13 CLKREQ#/NC SSD_PCIE_CLKREQ# [5] PCIE_RST1# [5,28]
R848 *Short_0201 53 54
[5] CLK_PCIE_SSDN CLK_PCIE_SSDP_C REFCLKN PEWAKE#/NC
R847 *Short_0201 55 56
[5] CLK_PCIE_SSDP REFCLKP NC#18 SSD@BAT54AW-L
57 58
GND#14 NC#19

+3V_SSD

67 68 +3V_WLAN_P +3V +3V_S5 +3V_WLAN_P

NC#1 SUSCLK TP49
69
R492 71 PEDET(OC-PCIE/GND-SATA) 70
GND#4 3.3Vaux_7 +3V_SSD
*SSD@10K_5%_2 73 72 R738 *Short_0805 C646 10u/6.3V_4
75 GND#5 3.3Vaux_8 74
GND#6 3.3Vaux_9 100mils R769 *0_5%_8 C715 0.1u/16V_2

76
77
78
79
[5] SSD_DET#
C707 0.1u/16V_2

76
77
78
79
SSD@NASM0-S6701-TSH4 C719 C716 C645 C644
10u/6.3V_4 0.1u/16V_2 0.1u/16V_2 *0.1u/16V_2 C717 *0.1u/16V_2

C718 *0.1u/16V_2

C PCIE_WAKE# EC9 *220p/50V_4 C

WLAN +3V_WLAN_P

CN9
NASE0-S6701-TS40

NGFF EKEY
1 2
USBP3+ 3 GND#3 3.3Vaux#1 4 +3V_WLAN_P
[6] USBP3+ USB_D+ 3.3Vaux#2 WIGIG_LED
USBP3- 5 6
+3V_WLAN_P +3V_WLAN_P [6] USBP3- USB_D- LED#1 TP83
7 8
9 GND#4 PCM_CLK 10
11 SDIO CLK(O) PCM_SYNC 12 11/20 add follow CRB
13 SDIO CMD(IO) PCM_IN 14
R816 15 SDIO DAT0(IO) PCM_OUT 16 R77877
17 SDIO DAT1(IO) LED#2 18
4.7K_5%_2 10K_1%_2
19 SDIO DAT2(IO) GND#13 20
2

SDIO DAT3(IO) UART Wake D6543

21 22
REQ_WLAN# 1 3 23 SDIO Wake(I) UART Rx 1 PCIE_RST#
PCIE_CLKREQ_WLAN# [5] SDIO Reset WLAN_RST# PCIE_RST# [4,5,11,12,23,26,28,29,30]
3
Q18 2 R6642 *0_5%_4 PCIE_RST1# PCIE_RST1# [5,28]
2N7002KTB
+3V_WLAN_P +3V_WLAN_P 32
33 UART Tx 34 BAT54AW-L
35 GND#5 UART RTS 36
[2] PCIE_TXP5_WLAN PETp0 UART CTS +3V_WLAN_P
R833
[2] PCIE_TXN5_WLAN
37 38
39 PETn0 Clink RESET 40
4.7K_5%_2 GND#6 CLink DATA
41 42 BT_EN R825 *10K_1%_2
2

[2] PCIE_RXP5_WLAN PERp0 CLink CLK RF_EN

[2] PCIE_RXN5_WLAN
43 44 R828 *10K_1%_2
MINICAR_PME# 1 3 45 PERn0 COEX3 46
PCIE_WAKE# [5,23] GND#7 COEX2
[5] CLK_PCIE_WLANP 47 48
Q46 49 REFCLKP0 COEX1 50 SUSCLK_32KHZ R802 *0_5%_2
B [5] CLK_PCIE_WLANN REFCLKN0 SUSCLK(32KHz) WLAN_RST#_R SUSCLK_WLAN [5] B
*2N7002KTB 51 52 R819 *Short_0201 WLAN_RST#
REQ_WLAN# 53 GND#8 PERST0# 54
MINICAR_PME# CLKREQ0# W_DISABLE2# BT_EN [29]
55 56
PEWake0# W_DISABLE1# LAD0_R RF_EN [29]
57 58 R830 *DBG@0_5%_2
LAD0 [5,29]
59 GND#9 NFC_I2C_SM_DATA 60 DEBUG_CLK
61 PETp1 NFC_I2C_SM_CLK 62 DEBUG_IRQ
63 PETn1 NFC_I2C_IRQ 64 LAD0_TP
GND#10 GPIO0_NFC_RESET# TP9111
65 66 LAD1
PERp1 UIM_SWP/PERST1# LAD1 [5,29]
67 68 LAD2 LAD2 [5,29] 10pF:EMI reserve
69 PERn1 UIM_POWER_SNK 70 LAD3 C701 *10p/50V_4
GND#11 UIM_POWER_SRC LAD3 [5,29]
71 72
73 Reserved1 3.3Vaux#3 74 R706 *DBG@0_2 DEBUG_CLK

GND#1
GND#2
75 Reserved2 3.3Vaux#4

NC#2
NC#1
GND#12
[5] CLK_LPC_DEBUG
[5,29] LFRAME_L

79
78
76
77
R712 *DBG@0_2 DEBUG_IRQ

FOR Debug card, MP remove them.

RDC new debug card

LAD0(58), CLK 33M(60), LFRAME#(62)

M.2 CNVI MODES

LOW-> INTEGRATED CNVI ENABLE
HIGH-> INTEGRATED CNVI DISABLE

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
HDD/WLAN
Date: Wednesday, March 18, 2020 Sheet 28 of 44
5 4 3 2 1
 5 4 3 2 1

R331 *0_5%_2 +3V_LDO_EC

+1.8V_S5
1 2 +A3VPCU

34
+3VPCU_ECPLL 1 2 TPD_INT#_EC
L10 BLM15AG121SN1D R344 0_5%_2 R309 *10K_1%_2
EC(KBC) C433 11/11 FAE L6 BLM15AG121SN1D
+3VPCU_EC +3V_S5 VSTBY _FSPI S5_ON
R333 10K_1%_2
+3VPCU

C434 0.1u/16V_4 suggestion +3V

1000p/50V_4 pin106 +3V_RTC C372 (For PLL Power) NBSWON# R362 10K_1%_2
ECAGND change to 0.1u/10V_2 DGPU_OVT#_EC
+3VPCU_EC R791 *10K_1%_2
12 mils Prevent ESD/EOS Layout near device MAINON R462 100K_5%_2
+3VPCU_EC 80PORT_DAT AC_PRESENT_EC [5,15] GPU_CHOKE_THERMAL
+3V_LDO_EC R401 2.2_5%_0603 should change to 1.8V level R325 *10K_1%_2
80PORT_DAT [30]
R402 33_5%_2 SUSON R348 100K_5%_2
BT_EN [28]

+3VPCU_EC and +3V_RTC C478 C386 C364 C365 C477 C443 C442 VRON R459 100K_5%_2
DGPU_OVT#_EC CLR_CMOS [7] C387
minimum trace width 12mils.0.1u/10V_20.1u/10V_2 0.1u/10V_2 0.1u/10V_2 0.1u/10V_2 0.1u/10V_2 0.1u/10V_2
TP9095 Prevent ESD/EOS Layout near device 180p/50V_4
EC_SPI1_SI
R698 *10K_1%_2
EC_Ty peC_CHG_HI [24]
+3V VSTBY _FSPI USBON# [19,30] EC_SPI1_SO
R77881 2.2_5%_0603 R318 33_5%_2 R700 *10K_1%_2
+3V_EC TPD_EN [25]
R794 *2.2_5%_0603
+1.8V USB_CHARGE_ON USB_BC_ON [19]
+1.8V_S5 LPCCLK_RUN_L_R USB_CHARGE_ON [19] C367
R803 *2.2_5%_0603

Vinafix.com
[5] ESPI_0 R6573 *0_5%_2 C679 180p/50V_4
[5] ESPI_1 R6574 *0_5%_2 0.1u/10V_2 U13

114
121

106

127
R6575 *0_5%_2

11
26
50
92

74

84
83
82

19
20

99
98
97
96
93
[5] ESPI_2 IT5571E-I-128/CX

3
R6576 *0_5%_2
D [5] ESPI_3 ESPI_0_R 10 110 MBCLK SM BUS PU(KBC) D

VSTBY#1
VSTBY#2
VSTBY#3
VSTBY#4
VSTBY#5

VSTBY#6

EGCLK/GPE3
EGCS#/GPE2
EGAD/GPE1

SMCLK4/L80HLAT/BAO/GPE0
SMDAT4/L80LLAT/GPE7

GPH7
ID6/GPH6
ID5/GPH5
ID4/GPH4
ID3/GPH3
CLKRUN#/GPH0/ID0
VCC

VFSPI
AVCC
ESPI_1_R 9 EIO0/LAD0/GPM0 SM CLK0/GPB3 MBCLK [31] LID#_C
add for EC mirror code C437 *180p/50V_4 111 MBDATA
ESPI_2_R 8 EIO1/LAD1/GPM1 SM DAT 0/GPB4 115 2ND_MBCLK MBDATA [31]
R77864 100K_5%_2 SM BUS 2ND_MBCLK [4,15,21]
+3V_LDO_EC ESPI_3_R 7 EIO2/LAD2/GPM2 SM CLK1/GPC1 116 2ND_MBDATA
ESPI_RESET# PLTRST#_EC EIO3/LAD3/GPM3 SM DAT 1/GPC2 EC_PECR_R 2ND_MBDATA [4,15,21] H_PROCHOT# [4]
R441 *0_5%_2 22 117 D10 +3V_LDO_EC
ESPI_RESET# ESPI_CLK_R 13 ERST#/LPCRST#/GPD2 SM CLK2/PECI/GPF6 118 LID#_C R368
R6577 *0_5%_2 33_5%_2 TP9083 TVM0G5R5M220R_22p
[5] ESPI_CLK ESPI_CS# ESPI_CS#_R ESCK/LPCCLK/GPM4 SM DAT 2/PECIRQT #/GPF7 LID# [20,30]
[5] ESPI_CS# R6578 *0_5%_2 6
ECS#/LFRAME#/GPM5 R805

3
C381 180p/50V_4 MBCLK 4.7K_5%_2 Q20
PROCHOT_EC 17 R811 4.7K_5%_2 PROCHOT_EC 2
Near EC Prevent ESD/EOS Layout near EC Battery module MBDATA
LPCPD#/GPE6
1

C440 0.1u/16V_4 2N7002K

GPU_CHOKE_THERMAL 126
R399 D13 TP9088
SERIRQ_R GA20/GPB5 PS/2
R77859 *0_5%_2 5 85 +3V_S5 R440

1
100K_5%_2 RB500V-40[5] ESPI_ALERT#
TP9082
PCH_SUSPWRDNACK 15 ALERT #/SERIRQ/GPM 6 LPC / eSPI PS2CLK0/T M B0/GPF0/CEC 86 SY S_SHDN# [4,6,32,37] TVS PN:
PLT RST #/ECSM I#/GPD4 PS2DAT 0/T M B1/GPF1 EC_FPBACK# [20] Priority1: CY000220Z00 PU at CPU side 100K_5%_2
23 89
Priority2: CY402220B00
2

[5] SIO_EXT_SCI# 14 ECSCI#/GPD3 PS2CLK2/GPF4 90 TPCLK [25] 2ND_MBCLK R315 4.7K_5%_2

WRST# GPIO
4 WRST # PS2DAT 2/GPF5 TPDATA [25] 2ND_MBDATA R314 4.7K_5%_2
[5] KBRST# KBRST #/GPB6 UMA& VGA SKU
C435 16 Need Stuff
[23] LANPWR# PWUREQ#/BBO/SM CLK2ALT /GPC7
1u/6.3V_4
IT5571 PWM 0/GPA0
PWM 1/GPA1
24
25
28 SUSLED#
PWRLED#
BATLED1#
SUSLED#
[30]
[30]
[30]
RESERVE FOR LPC CLOSE TO EC
PROCHOT_EC
ESPI_0_R
R6563 *0_5%_2 LPC_PD_L [5]
PWM 2/GPA2

[20] TS_EN
R410 33_5%_2
[25]
[5]
KB_BL_LED
DNBSWON#
113
123 CRX0/GPC0
CT X0/T M A0/GPB2 CIR LQFP PWM 3/GPA3
SM CLK5/PWM 4/GPA4
SM DAT 5/PWM 5/GPA5
29
30
31 80PORT_CLK
BATLED0#
MAINON
80PORT_CLK
[30]
[32,34,37]
[30]
ESPI_1_R
ESPI_2_R
ESPI_3_R
R6564
R6565
R6566
R6567
0_5%_2
0_5%_2
0_5%_2
0_5%_2
LAD0 [5,28]
LAD1 [5,28]
LAD2 [5,28]
HWPG(KBC)
+3V

+1.8V_S5
TS_EN_C Pin 80 EC_APWROK reserve TP ESPI_CLK_R
R6568 0_5%_2
LAD3 [5,28]
EC_Ty peC_EN PWM LPCCLK_RUN_L_R LPCCLK [5] DDR=1.5V, D1 DNP and D2 POP
C390 180p/50V_4 80 R6569 0_5%_2 R369
119 DAC4/DCD0#/GPJ4 47 SERIRQ_R LPCCLK_RUN_L [5] DDR=1.35V, D1 POP and D2 DNP
Prevent ESD/EOS Layout near device [5] R6570 0_5%_2 SERIRQ [5] 10K_5%_2
SUSB# 33 FDIO3/DSR0#/GPG6 T ACH0A/GPD6 48 FAN1_RPM [25] ESPI_CS#_R
R6571 0_5%_2 R77870
[5] EC_PWROK GINT /CT S0#/GPD5 T ACH1A/T M A1/GPD7 PLTRST#_EC LFRAME_L [5,28]
88 TP46 R6572 0_5%_2 *10K_5%_2
[20] PCH_BLON_EC TS_EN_C 81 PS2DAT 1/RT S0#/GPF3 120 LPC_RST# [5]
SUSON R336 *0_5%_2 HWPG
DAC5/RIG0#/GPJ5 GPC4 SY S_HWPG SUSON [34] [37] HWPG_1.5V
TP43 87 124
ME_WR# 109 PS2CLK1/DT R0#/GPF2 GPC6 2 *RB500V-40
TP9084 D11 1
108 T XD/SOUT 0/GPB1 [37] HWPG_1.8VS5 ESPI_RESET#
*RB500V-40 2 1 D8516
[21] AMP_MUTE# RXD/SIN0/GPB0 PCIE_RST# [4,5,11,12,23,26,28,30]
D12 1 2 *RB500V-40
dGPU_OPP# 71 107 [34] HWPG_VDDR
[15] NBSWON#
dGPU_OPP# ADC5/DCD1#/GPI5 PWRSW/GPE4 NBSWON# [25]
72 UART port 18 [5] D85141 2 *RB500V-40 R77871 0_5%_2 [4]
[31] ACIN 73 ADC6/DSR1#/GPI6 RI1#/GPD0 21 SUSC# [33] HWPG_VDDPS5 APU_RST#
WAKE UP HWPG
[31] TEMP_MBAT# 35 ADC7/CT S1#/GPI7 RI2#/GPD1 2 *RB500V-40
TP48 WLANPWR# D9 1
34 RT S1#/GPE5 [32] SY S_HWPG
[21] PCBEEP_EC 122 PWM 7/RIG1#/GPA7 112
[34] DDR4_SUSON_2V5 +1V_S5_ON FDIO2/DT R1#/SBUSY/GPG1/ID7 RING#/CK32KOUT /LPCRST #/GPB7 RSMRST# [5]
Prevent ESD/EOS Layout near device TP9087 95 D8 1 2 RB500V-40 11/15 add for ERST
EC_ODD_EJ_R# 94 CT X1/SOUT 1/GPH2/SM DAT 3/ID2 [4,5,35] VRM_PWRGD
R393 33_5%_2 Prevent ESD/EOS Layout near device
[27] EC_ODD_EJ# CRX1/SIN1/SM CLK3/GPH1/ID1
EC_SPI1_CLK EC_SPI1_CLK_ER 105
C384 180p/50V_4 R319 *Short_0201 R487 33_5%_2
EC_SPI_CS0# EC_SPI_CS0#_ER 101 FSCK RF_EN [28]
R322 *Short_0201
EC_SPI1_SI EC_SPI1_SI_ER 102 FSCE#
R321 *Short_0201 EXTERNAL SERIAL FLASH ICMNT
EC_SPI1_SO EC_SPI1_SO_ER 103 FM OSI 66 ICMNT [31]
R320 *Short_0201 C480
FM ISO ADC0/GPI0 67 C457 10u/6.3V_6 ECAGND
ADC1/GPI1 180p/50V_4
56 68
C [25] MY 16 57 KSO16/SM OSI/GPC3 ADC2/GPI2 69 IDCHG_R [31] C
[25] MY 17 KSO17/SM ISO/GPC5 ADC3/GPI3 VRON [35]
32 70
[25] FAN_PWM PWM 6/SSCK/GPA6 ADC4/GPI4 KL_NO_EC [32]
C453 100p/50V_4
S5_ON 100 +3VPCU
[32,33,37] S5_ON PTP_PWR_EN# SSCE0#/GPG2 A/D D/A
TP35 125 SPI ENABLE should change to 1.8V level
ESPI_CLK
SSCE1#/GPG0
T ACH2A/GPJ0
76
Ty peC_Strap PBA_FP_PWREN# [26]
EC ROM
36 77
[25] MY 0 37 KSO0/PD0 T ACH2B/GPJ1 78 PCH_PWROK
[25] MY 1 38 KSO1/PD1 DAC2/T ACH0B/GPJ2 79 PCH_PWROK
TP9103 R407
[25] MY 2 39 KSO2/PD2 DAC3/T ACH1B/GPJ3 USB_CLT1 [19]
[25] MY 3 100K_5%_2
R419 40 KSO3/PD3 +ECVSPI
[25] MY 4 KSO4/PD4 Ty peC_Strap
*22_5%_2 41
[25] MY 5 42 KSO5/PD5
[25] MY 6 43 KSO6/PD6 KBMX
High A5 ( w/ type C ) R358 0_5%_6
[25] MY 7 KSO7/PD7 +3V_S5
44 Low A3 ( w/o type C) R421
[25] MY 8 45 KSO8/ACK#
[25] MY 9 100K_5%_2
C389 46 KSO9/BUSY +ECVSPI
[25] MY 10 51 KSO10/PE 2 GC6FBEN_Q_EC
*10p/50V_4 [25] MY 11 KSO11/ERR# GPJ7
KSI3/SLIN#

52 128 +ECVSPI
KSI1/AFD#
KSI2/INIT#

R310 33_5%_2 TP39 R324 100K_1%_4

KSI0/STB#

[25] MY 12 53 KSO12/SLCT CLOCK GPJ6 TPD_INT#_EC [25] EC_SPI_HOLD#

R335 22_1%_4 TP9102
VCORE

[25] MY 13 KSO13
VSS#1

VSS#2
VSS#3
VSS#4
VSS#5

54
AVSS

Prevent ESD/EOS Layout near device

KSI4
KSI5
KSI6
KSI7

[25] MY 14 KSO14
55

ECROM_PWR
C371
[25] MY 15 KSO15 C370
180p/50V_4 SM BUS ARRANGEMENT TABLE R6594
TBD
0.1u/16V_2
58
59
60
61
62
63
64
65

27
49
91
104

1ECAGND 75

12

10K_1%_2
SM Bus 1 Battery
[25] MX0 U33
[25] MX1
C388 AJ089870F02 IT8987E/CX SM Bus 2 PCH/VGA/DDR
EC_SPI_CS0#
R384 0_5%_4
EC_SPI_CS0#_R 1 8
[25] MX2 CS VCC
[25] MX3 0.1u/10V_2 EC_SPI1_SO EC_SPI1_SO_R
R382 22_1%_4 2 7
[25] MX4 IO1/DO IO3/HOLD
[25] MX5 SM Bus 3 EC_SPI_WP# EC_SPI_WP#_R EC_SPI1_CLK_R EC_SPI1_CLK
L9 TP9101 R363 22_1%_4 3 6 22_1%_4 R312
[25] MX6 IO2/WP CLK
[25] MX7 BLM15AG121SN1D EC_SPI1_SI_R EC_SPI1_SI
SM Bus 4 TBD +ECVSPI 5 22_1%_4 R323
2

C374 1u/6.3V_2 R351 100K_1%_4 4 IO0/DI

GND
TP47
TP44 W25X10CLSNIG

C373
22p/50V_4
128KB EC ROM 3.3V

B B

Output for type-c Apling ridge

EC_Ty peC_EN
reset timming"Low " Active
BIOS ROM
R416 *Short_0201
EC_Ty peC_EN_R [24]

+1.8V_S5
Reset SW (FSW) [5,7,20,21,23,26,30,31,32,41] +3VPCU
[4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,30,32,33,34,35,37,41] +3V
Battery Detect Switch [4,5,6,7,11,23,25,28,32,37,38] +3V_S5
+1.8V_S5

R622 0_5%_2 +3VRTC R6535 *10K_1%_2

[5] APU_SPI_HOLD#
Reserve switch for test
(MP remove) [31] BI
2
1
4
3 R37
R6544 C2790
R6550 10K_1%_2 0.1u/16V_2
100K_5%_2 *10K_1%_2
11/29 unsutff SW1 SW3
6

Vgs = 1.5V
U2038
3

SW1 *NDT016-G1A-KKKT
2 APU_SPI_CS0# APU_SPI_CS0#_R 1 8
*T3AL-23S-Q-T/R Q7 R6532 0_5%_4
[5] APU_SPI_CS0# CS VCC
PJA138K
1 3 APU_SPI_SI APU_SPI_SI_R 2 7
NBSWON# [5,26] APU_SPI_SI R6536 22_1%_4
SW2 IO1/DO IO3/HOLD
1

APU_SPI_WP APU_SPI_WP_R APU_SPI_CLK_R APU_SPI_CLK

3
4

2 4 C112 RESET_SW R6538 22_1%_4 3 6 22_1%_4 R6533

5 [5] APU_SPI_WP IO2/WP CLK APU_SPI_CLK [5,6,26]
C676 *0.1u/25V_6
5 APU_SPI_SO_R APU_SPI_SO
0.1u/10V_2 22_1%_4 R6534
4 IO0/DI APU_SPI_SO [5,26]
GND
Reserve switch for test 6
W25Q64FWSSIG
(MP remove)
2
1

C2792
22p/50V_4
8MB 1.8V SPI ROM

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
KBC IT8987
Date: Wednesday , March 18, 2020 Sheet 29 of 44
5 4 3 2 1
 5 4 3 2 1

USB Board ADOGND

CN6
35

31
1
[21] HP-R3

Vinafix.com
2
3
[21] HP-L3 4
5
6
D 7 D
[21] RING2 8
9
10
[21] SLEEVE 11
12
[21] HP_JD# 13
[6]
[6]
USBP4-_DB
USBP4+_DB
14
15 USB2.0 DB (UB2) +5V_S5
16
17
[29] SUSLED# 18
[29] PWRLED# 19
[29] BATLED1# 20 USBPWRD2
C698 U35
[29] BATLED0# 21
22 1u/6.3V_4 Close USB3.0
+3VPCU
5 1
23 IN OUT
24 2
25 GND
USBPWRD2 26 USBON# 4 3 C672 C673 C671
27 [19,29] USBON# /EN /OC
C674 0.1U/16V_4 470p/50V_4 0.1u/16V_4 *100u/6.3V_12
C670 22U/6.3V_6 28
29 G524B2T11U
30
32 [6] USB_OC2#

CF34302D0RA-05-NH
Enable: Low Active /1.5A
GMT:AL000524009(A3 &A5)

C C

Hall Sensor For 15" DMIC CN1

20mils +3VPCU_HALL *50208-00401-V02
+3VPCU R507 2.2_5%_0603 LID#
LID# [20,29]

6
2

+3V_DMIC 4
2

D22 D21 C498 R77874 *Short_0201 DMIC_CLK_2_R

[5] DMIC_CLK_2 DMIC_DAT_2_R 3
*0.1u/6.3V_2 R77875 *Short_0201
OUTPUT
VCC

[5] DMIC_DAT_2 2
*VPORT_0603_220K-V05 *VPORT_0603_220K-V05
1

1
GND

5
S

C508 HE1
3

APX8132AI-TRG For 14"

0.1u/16V_4

+3VPCU_HALL LID#
B B

+3V R514 *Short_0201 +3V_DMIC

2

1
OUTPUT
VCC

GND
S

HE2
3

*APX8132AI-TRG
CN17
51614-00601-V01

7
1 PLTRST#
2 80PORT_CLK PCIE_RST# [4,5,11,12,23,26,28,29]
3
4
5
80PORT_DAT
+5V
80PORT_CLK [29]
80PORT_DAT [29] Debug port
6
8

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
USB DB/Hall sensor/DMIC
Date: Wednesday, March 18, 2020 Sheet 30 of 44
5 4 3 2 1
 5 4 3 2 1

Double Check ADP-IN Connector with ME

PJ6
L A NGI S
3
ADP_ID [31]
VA PQ3
AONS32306
VA2 PQ4
AONS32306 PR12
0.01_1%_0612
+VIN
PQ11
AONS32306
31

D
3 3 3

S
NI P) +(
1 5 2 2 5 5 2
5 1 1 1

0.047u/50V_6
4

0.1u/50V_4
P4SMAFJ20A

G
1

G
2

PC6
*Short_0201

PC143

*0.01u/50V_4
Vinafix.com 24780_ACN
LL E HS & GNI RPS )-(
PC8 PR19

PD2

PC91
30738-00042-001 1000p/50V_4 PC118 PC117
D *Short_0201 0.1u/50V_4 2200p/50V_4 D
PR18 24780_ACP

2
PC145 PC14
0.1u/50V_4 2200p/50V_4

PR247 PR248
4.02K_1%_4 4.02K_1%_4
PR99
*Short_0603

BAT-V
24780_ACP

24780_ACN

1
PD4 PR108
VA BAT54CW PC76 PC237 PC74 10_1%_6
0.1u/50V_4 0.1u/50V_4 0.1u/50V_4

24780_CMSRC
3
PR71 24780_ACDET
1M_5%_6

1
PU12
PR81 3 18 24780_BATDRV

ACN
ACP
CMSRC BATDRV
3

20_5%_12
2 17 24780_BATSRC +VIN
[31] ADP_ID PQ9 BATSRC
C 2N7002KW 24780_ACDRV 4 REGN6V C
PR69 PR245 ACDRV
1

1M_5%_6 866K_1%_4 24780_VCC 28

REGN6V VCC 24 PC80
ACDET=16.4V REGN 2.2u/10V_4
PC238 PC86 PC240
0.47u/25V_6 2200p/50V_4 10u/25V_8
PR75 PR246 PR254
100K_1%_4 137K_1%_4 *Short_0603
24780_ACDET 6 25 24780_BST PQ26
ACDET BTST

5
AONR32320C
PR80 *Short_0201 5 PC243 D
[29] ACIN ACOK 0.047u/50V_6
MBDATA PR253 *Short_0201 11 26 24780_DH 4 G
PR74 SDA HIDRV S
100K_1%_4 MBCLK PR255 *Short_0201 12 PR266 BAT-V
SCL

1
2
3
PL11 0.01_1%_0612
ICMNT PR249 *Short_0201 7 6.8uH/4.5A_7x7x3
[29] ICMNT IADP 27 24780_LX 1 2 BAT-V
IDCHG_R PR250 *Short_0201 8 PHASE
[29] IDCHG_R IDCHG
BQ24780S : 1 μA/W (default) TP68 PMON PR251 *Short_0201 9 PQ27
PMON

5
AONR32320C PR268
100p/50V_4

100p/50V_4
*100p/50V_4
PC77

PC73

*4.7_5%_6

PC235
D
PR270 PR271
*AMD CPU DOESN'T NEED TO REPORT PMON PR76 23 24780_DL 4 G *Short_0201 *Short_0201
*20.5K_1%_4 LODRV S

1
2
3
24780_BM# 16
+3VPCU TB_STAT 24780_SRP
PR264 10K_5%_4 PC248 PC249 PC236 PC246 PC241
PC256 24780_CMPOUT 14 0.1u/25V_4 *680p/50V_6 2200p/50V_4 22u/25V_8 22u/25V_8
0.1u/50V_4 PR265 *10K_5%_4 CMPOUT 20 PR261 24780_SRP
*Short_0201 24780_SRN
B 24780_ILIM 21 SRP B
ILIM PC253
PC258 PR98 24780_CMPIN 13 CMPIN 0.1u/25V_4

PROCHOT

BATPRES
*100p/50V_4 316K_1%_4

GND#10
GND#11
19 PR267 24780_SRN
*Short_0201

GND#8
GND#9

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
SRN
PJ11 PR97 PR85
50458-00801-V02 100K_1%_4 100K_5%_4 PC254
BAT-V 0.1u/25V_4
BQ24780SRUYR

35
36
37
38
10

15

22
29
30
31
32
33
34
10

BI [29]
PR112 *0_5%_2
8 Double Check if BI pin PU Low PC96

24780_PROCHOT
7 0.01u/50V_4
6 PR113 100_5%_4 TEMP_MBAT#
5 TEMP_MBAT# [29]
4

0_5%_2
PR88

PR86
*0_5%_2
3
2 +3VPCU
1 PR90
1M_5%_4
TEMP_MBAT#
9

PR119 PR120
100_5%_4 100_5%_4 1. PROCHOT Pin : Active Low
2. Double Check PU High with HW
REGN MAX voltage 6.5V
Double Check BATT Connector with ME V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
PR9292 *Short_0201
MBCLK [29]
CORE_PWM_PROCHOT# [4] =0.793V for 3.965A current limit
A 10/24 change netname to VRHOT A
MBDATA [29]
ILIM=0.793V
PC242 PR252 Rsr = 0.01ohm
1

*0.1u/16V_4 *100K_1%_2

PC122 PC123
*47p/50V_4 *47p/50V_4

Quanta Computer Inc.

2

PD5 PD6 +3VPCU

PDZ5.6B PDZ5.6B
PROJECT : Z8E
Size Document Number Rev
1A
Charger (BQ24780S)
Date: Wednesday, March 18, 2020 Sheet 31 of 44
5 4 3 2 1
 5 4 3 2 1

+VIN [20,31,33,34,36,37,38,39,40,41]

32
+3VPCU [5,7,20,21,23,26,29,30,31,41]
+5VPCU [19,21,33,41]
VL [37]

+5V [20,21,22,25,27,30,37]
+5V_S5 [19,24,27,30,34,35,39]
+3V [4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,33,34,35,37,41]
+VIN PJ3 PR239 PC229
+3V_S5 [4,5,6,7,11,23,25,28,29,37,38]
*Short_3720 10_1%_6 0.1u/25V_4
V3A_BOOT_R

10u/25V_8

10u/25V_8
+3VPCU

0.1u/25V_4

2200p/50V_4

0.1u/25V_4
PC245

PC221

PC244

PC239

PC233
PR258
D

Vinafix.com V3A_BOOT
*4.7_5%_6

+V3A_LX_R
3.3 Volt +/- 5%
TDC : 6A
Width : 240mil
D

PC247 FSW : 500KHZ

*680p/50V_6
To Thermal Protection (1) USM : 0.8V-1.7V
V3A_EN (2) Normal Mode : >2.3V PU11

1
PR77 RT6256BGQUF PJ2 +3VPCU
*Short_0201 PL10 *Short_3720 +3VPCU +3VPCU

VIN

BOOT
SYS_SHDN#
1uH/11A_7x7x3
[4,6,29,37] SYS_SHDN# 6 2 +V3A_LX 1 2 +V3A_OUT
PR234 10K_1%_2 PR244 EN LX#1
+3VPCU
*Short_0201

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

0.1u/16V_4
*22u/6.3V_6

*22u/6.3V_6
SYS_HWPG V3A_PWRGD 7 3

PC66

PC67

PC69

PC72
PC224

PC225

PC226
PR237 *Short_0201 PR236
[29] SYS_HWPG PGOOD LX#2
PR83 PC79 *Short_0201
10K_1%_4 0.1u/16V_4 PR230 100K_1%_2 TDC : 4.58A TDC : 3.43A
LDO=3.3V/100mA 11 10 V3A_VOUT PEAK : 6.1A PEAK : 4.6A
LDO3 VOUT Width : 200mil Width : 160mil
PR92 PC88 PC90
MAINON *0_5%_2 8 4 1u/25V_4 1u/25V_4
V3A_VOUT AGND PGND

6
VCC
PR96 +3V_S5 +3V

VIN1

VIN2
FF
3

*Short_0201 PC71
KL_NO_EC 2 0.1u/16V_4 PR110 *Short_0805 PR107 *Short_0805

12

9
[29] KL_NO_EC SYS_SHDN# V3A_VBYP
PR72 PR78
PQ12 1K_1%_4 *1K_1%_4
PR82 2N7002K PR70 PC106 PC108 13 8 PC109 PC112
1

+VCC_V3A VOUT1 OUT2

*100K_1%_2 10K_1%_4 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 10u/6.3V_6
PC227
4.7u/6.3V_4 PC234 PU7
PC70 1u/10V_4 PR260 *Short_0201 4 AOZ1331ADI 11
+5VPCU VBIAS GND1
10p/50V_4 PC251
15
GND2 PR259
C 0.1u/16V_4 *Short_0201 C
S5_ON 3 5 MAINON MAINON [29,34,37]
PR84 PR257 *Short_0201
[29,33,37] S5_ON ON1 ON2

CT1

CT2
*10K_1%_4 VCC=5V
High frequency noise eliminate circuit Power Auto Recovery (DON'T Connect to External Load) PC252 PC250

12

10
*0.1u/16V_4 *0.1u/16V_4

+3V_LDO_EC
PR68
*Short_0603
+3V_LDO_EC V3A_VBYP
PC111 PC110
1000p/50V_4 1000p/50V_4

[29] +3V_LDO_EC

+VIN PJ9010
*Short_3720

+5VPCU +5VPCU
PR115 PC116
10_1%_6 0.1u/25V_4
10u/25V_8

10u/25V_8
0.1u/25V_4

0.1u/25V_4

2200p/50V_4

V5P5A_BOOT_R
PC262

PC263

PC264

PC270

PC261

PR114 TDC : 4.54A TDC : 3.53A

*4.7_5%_6
+5VPCU PEAK : 6A PEAK : 4.7A
SYS_SHDN#
PR276 *Short_0201 5 Volt +/- 5% Width : 200mil Width : 160mil
+V5P5A_LX_R TDC : 8A PC101 PC82
Width : 320mil 1u/25V_4 1u/25V_4

6
B PR279 PC271 PC115 B
10K_1%_4 0.1u/16V_4 *680p/50V_6 FSW : 750KHZ +5V_S5 +5V

VIN1

VIN2
V5P5A_BOOT
PR121 PR111 *Short_0805 PR87 *Short_0805
MAINON *0_5%_2
PU15 +5VPCU
5

PR122 (1) USM : 0.8V-1.7V RT6258CGQUF PJ4 PC105 PC103 13 8 PC78 PC81
(2) Normal Mode : >2.3V VOUT1 OUT2
3

*Short_0201 PL13 *Short_3720 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 10u/6.3V_6

VIN

BOOT

KL_NO_EC 2 1uH/11A_7x7x3
V5P5A_EN 6 2 +V5P5A_LX 1 2 +V5P5A_OUT
PU6
PQ13 PR273 EN LX#1 PR93 *Short_0201 4 AOZ1331ADI 11
+5VPCU VBIAS GND1
PR118 2N7002K *Short_0201 3 PC93
1

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

0.1u/16V_4
*22u/6.3V_6

*22u/6.3V_6
SYS_HWPG V5P5A_PWRGD 7 LX#2 15

PC113

PC119

PC269

PC121

PC114

PC120

PC268
*100K_1%_2 PR277
PGOOD *Short_0201 GND2 PR89
PR117 0.1u/16V_4 *Short_0201
S5_ON 3 5 MAINON
*Short_0603 PR100 *Short_0201
V5P5A_VOUT ON1 ON2

CT1

CT2
VL 12 10
VL LDO5 VOUT
PC99 PC87

12

10
8 4 *0.1u/16V_4 *0.1u/16V_4
AGND PGND
LDO=5V/100mA
VCC

PC266 PC267
FF

4.7u/10V_4 0.1u/16V_4
PC98 PC92
9

11

1000p/50V_4 1000p/50V_4
+VCC_V5P5A

V5P5A_VOUT

PR278 PR274
1K_1%_4 *1K_1%_4 PC265
1u/10V_4

A PC272 A
10p/50V_4 VCC=5V
(DON'T Connect to External Load)
PR275
*10K_1%_4

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
SYSTEM 5V/3V (RT6256B/RT6258C)
Date: Wednesday, March 18, 2020 Sheet 32 of 44
5 4 3 2 1
 5 4 3 2 1

33
+VIN [20,31,32,34,36,37,38,39,40,41]
VDDP_S5 [7]
VDDP [4,7,37]
+5VPCU [19,21,32,41]
+3V [4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,34,35,37,41]

D
Vinafix.com Fsw=550KHz PC2000
*0.01u/50V_4
PJ2001 +VIN D
PR2001 *Short_3720
73.2K_1%_4
G5335-TON-1

10u/25V_8
2200p/50V_4
*0.1u/25V_4
6
PU2000

PC2001

PC2002

PC2003
7 8
VDDP_S5

TON
+5VPCU PR2002 NC V+#1 9
10_5%_4 V+#2 22 Default Setting FP5=0.95 / FP6=0.75 Volt +/- 5%
G5335-VCC-1 21 V+#3 24
VCC V+#4
FP5 FP6 TDC : 3.75A
Double Check Pull High with HW PEAK : 5A
PC2004
11.8K Ohm 5.1K Ohm
+3V 10u/6.3V_6
R1 Width : 160mil
CS31182FB18 CS25102FB02
PR2003 PC2005
2.2_5%_6 0.1u/25V_4
20 G5335-BST-1
0.95V 0.75V VDDP_S5
PR2000 BST
100K_1%_2 PR2004 25 PJ2000
*Short_0201 LX#1 10 PL2000 *Short_3720
G5335-PWRGD-1 1
LX#2 11 1uH/11A_7x7x3
[29] HWPG_VDDPS5 PGOOD LX#3 16 G5335-LX-1 1 2
+5VPCU PR2005 LX#4 17
*0_5%_2 LX#5 18
G5335-PFM-1 3 LX#6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

0.1u/16V_4
*22u/6.3V_6

*22u/6.3V_6
PFM PR2007 PR2008 10/24 change netname to follow CUP side

PC2006

PC2007

PC2008

PC2009

PC2010

PC2011

PC2012

PC2013
G5335-AGND-1
12 *4.7_5%_6 10_1%_2
G5335-EN-1 2 PGND#1 13
PR2006 EN PGND#2 14 PR9298
*Short_0201 PGND#3 15 +0.95VS5_SENSE_REMOTE *0_5%_2 CPU_VDDP_RUN_FB_H
C PGND#4 CPU_VDDP_RUN_FB_L TP2056 C
Pulse-Skipping Mode 19 TP2050
PGND#5 4 PR2015
AGND G5335-AGND-1
PC2015
R1 *0_5%_2
*680p/50V_6 PC2014 PR2010
PR2009 *1000p/50V_4 11.8K_1%_4
*Short_0402 G5335-AGND-1
G5335-SS-1 23 5 G5335-FB-1
[29,32,37] S5_ON SS FB
R2
PC2016 PC2017 G5334CQT1U
1. Follow FP6 CRB, Double Check Vsense Setting with HW
*0.047u/6.3V_2 0.047u/6.3V_2 PR2011 2. Double Check with GMT FAE
20K_1%_2 3. Double Check FP5 / FP6 Setting
G5335-AGND-1 G5335-AGND-1

G5335-AGND-1

PR2013 VFB=0.6V
*Short_0402

Vo=0.6*(R1+R2)/R2
=0.95V / 0.75V
G5335-AGND-1

VDDP_S5
B B

5
D

MAIND 4 G PQ2000
[34,37] MAIND S AONS32306

1
2
3
VDDP

PR9295
TDC : 3A 10_1%_2
PEAK : 4A PR2012
*Short_0201
Width : 120mil +0.95V_SENSE_REMOTE
APU_VDDP_RUN_FB_H [4]
APU_VDDP_RUN_FB_L [4]
PR9296
*Short_0201

G5335-AGND-1

A A
1. Follow FP6 CRB, Double Check Vsense Setting with HW
2. Double Check FP5 / FP6 Setting

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
VDDP_S5 (G5334CQT1U)
Date: Wednesday, March 18, 2020 Sheet 33 of 44
5 4 3 2 1
 5 4 3 2 1

+VIN
+1.2VSUS
[20,31,32,33,36,37,38,39,40,41]
[3,7,9,10]
+5V_S5
+3V
[19,24,27,30,32,35,39]
[4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,33,35,37,41]
34
+1.2V [37]
+2.5V_SUS
+VDDQ_VTT
[9,10]
[9,10] Vinafix.com
+VDDQ [9]
D D

+2.5V_SUS
2.5Volt +/- 5%
TDC : 0.75A
PEAK : 1A
Width : 40mil
+VIN VDDQ_PVIN
PJ1
*Short_1206 Isat=1.4A
+2.5V_SUS

PL1 +1.2VSUS
PC138
2200p/50V_4
PC10
0.1u/25V_4
PC12
10u/25V_6
PC11
10u/25V_6
PC140
10u/25V_6
4.7uH/1.08A_2.5x2.0x1.2
1 2 PR127 *Short_0805
1.2 Volt +/- 5%
TDC : 8A
PR2 PC129 PC128
Width : 320mil
*Short_0402 PR123 22u/6.3V_6 *22u/6.3V_6
*Short_0201
+5V_S5
PU1
VDDQ_PVIN 7 15 VDDQ_SW_VPP +1.2VSUS
PC2 PC3 PVIN SW_VPP
10u/10V_4 0.1u/25V_4 VDDQ_VCC 14 12 VQQD_VPPSNS
PVIN_VPP VPPSNS
PC1 1u/10V_4 PR132 PC139 Isat=25A PJ5
18 VDDQ_BOOT +VDDQ_BOOT1
*Short_1206
C BST +VDDQ_P C
13
VCC_5V 5.1_1%_6 0.1u/25V_4 PL2
Double Check Pull High with HW 0.68uH/15.5A_7x7x3
PC16 10u/6.3V_4 VDDQ_VLDOIN 1 17 VDDQ_SW 1 2
VLDOIN SW
PR131 +VDDQ_P PR6 *Short_0603
100K_1%_2 5 VDDQ_VDDQSNS PR129

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

*22u/6.3V_6
+3V VDDQSNS

PC7
PC131

PC130

PC132

PC133

PC137
*4.7_5%_6
PR128 *Short_0201 VDDQ_PG 8
[29] HWPG_VDDR VDDQ_SLP_S4 11 PGOOD PR130
PR124 *Short_0201 10 SLP_S4 2 VDDQ_VTT PR8 *Short_0603 +VDDQ_SR
[29] DDR4_SUSON_2V5 VTT_CNTL VTT +VDDQ_VTT
*Short_0201
PR126 *0_5%_2 4 VDDQ_VTTSNS

10u/6.3V_4
PC136

*10u/6.3V_4
[29] SUSON VTTSNS

PC18

PC142
*680p/50V_6
3 PR9
PR125 *Short_0201 VDDQ_VTT_CNTL 16 AGND *Short_0402 TDC : 0.45A
[29,32,37] MAINON PGND_VPP
9
PGND VTTREF
6 VDDQ_VTTREF
+VDDQ PEAK : 0.6A
PR9300
PC125 PC126 TPS51486RJER Width : 20mil 10_1%_2
*1u/10V_4 *1u/10V_4 PC15
0.47u/10V_4
PR9301
49.9_1%_2 APU_VDDIO_MEM_FB_H TP9089

B B
1. Follow FP6 CRB, Double Check Vsense Setting with HW
2. Double Check with TI FAE
3. Double Check FP5 / FP6 Setting
VTT_CNTL SLP_S4 +1.2VSUS +2.5VSUS REF VTT

S0 1 1 ON ON ON ON
+1.2VSUS
S3 0 1 ON ON ON OFF

S4/S5 0 0 OFF OFF OFF OFF

3
MAIND 2 PQ9056
[33,37] MAIND *AOSS32334C

1
+1.2V

TDC : 0.23A
A
PEAK : 0.3A A
Width : 20mil

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
DDR4_+1.2VSUS (TPS51486R)
Date: Wednesday, March 18, 2020 Sheet 34 of 44
5 4 3 2 1
 5 4 3 2 1

35
3662AC_VCC +5V_S5
+VDDCR_SOC [7,36] PR6001
+VCC_CORE [7,36] 4.7_5%_4
+5V_S5
PR6002
*Short_0402 +VIN
PC6001 3622AC_PVCC
+5V_S5 [19,24,27,30,32,34,39]
2.2u/10V_4 PR6003

2.2u/10V_4
+1.8V [4,5,6,7,11,21,24,26,29,37]
4.7_5%_4

PC6002
Vinafix.com
+3V [4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,33,34,37,41]

D PC6003 D
0.1u/25V_4
PR6004 PR6005

17

34

28
1.47K_1%_4 28K_1%_4
VREF_PINSET_CPU 3662ACSET1 13 PR6008

VCC

PVCC

VIN
SET1 1_5%_6
PR6009 PR6010 31 3662NBUGATENB
590_1%_4 4.53K_1%_4
f=400KHz UGATE_NB 3662AC_NB_HG1 [36]

3662ACNBISENP [36]
3662AC_TSEN_NB 23 3662ACNBISENN [36]
VREF_PINSET_CPU PR6011 PR6006 PR6012 *Short_0201 PR6013 PR6014
237K_1%_4 19.1K_1%_4 60.4K_1%_4 TSEN_NB 30 3662NBBOOTNB *Short_0603
BOOT_NB PR6015
PUT COLSE TO
VDDCR_SOC PC6004 3.74K_1%_4
PR6016 PR6017 1 2 HOT SPOT 0.1u/25V_4
10K_1%_4 14K_1%_4 PR6018 100K_NTC_4_1% PC6005
32 3662AC_NB_LX1 0.1u/16V_4
PHASE_NB 3662AC_NB_LX1 [36]
PR6019 PR6020 PR6021 *Short_0201 PR6022 3662AC_TSEN 12 33 3662AC_NB_LG1
VREF_PINSET_CPU TSEN LGATE_NB 3662AC_NB_LG1 [36]
6.04K_1%_4 60.4K_1%_4 60.4K_1%_4
PUT COLSE TO PR6023
VDDCR_CPU 25 3662AC_ISENP_NB 1.43K_1%_4 PC6006
PR6024 PR6007 1 2 HOT SPOT ISENP_NB 0.1u/6.3V_2
11K_1%_4 22.6K_1%_4 PR6025 100K_NTC_4_1% 24
ISENN_NB
27 3662ACCOMP_NB PC6007 82p/50V_4 PC6008 150p/50V_4
PR6028 COMP_NB
*Short_0402 PR6026 24.9K_1%_4 PR6027 10K_1%_4
3662AC_EN 29 PR6029 100_1%_4
[29] VRON EN 3662ACFB_NB LL~2.1m +VDDCR_SOC
26 Double Check Vsense Setting
FB_NB with HW
Vih=2V
C PC6000 PR6030 *Short_0201 [4]
C
Double Check EN Sequence with HW *1000p/25V_2 PR6031 CPU_VDDNB_RUN_FB_H
1_5%_6 PR6032
37 3662AC_HG1 3662AC_RGND CPU_VDDNB_RUN_FB_L
*Short_0201
UGATE1 3662AC_CPU_HG1 [36] TP9093
PR2033 38 3662AC_BOOT1
*10K_1%_2 BOOT1 PR6033 10/24 change netname to follow mb side
PR6034 2.2_5%_6 3662AC_VDDIO 22 *Short_0603 PC6009
+1.8V +1.8V VDDIO 3662AC_CPU_LX1
36 0.1u/25V_4 3662AC_CPU_LX1 [36]
PHASE1 PR6035 *1K_1%_4 3662AC_CPUISEN2N
PC6010 35 3662AC_CPU_LG1
LGATE1 3662AC_CPU_LG1 [36]
10/24 change netname to follow CUP side 1u/6.3V_4
9 3662AC_ISEN1P_CPU PR6036 3.74K_1%_4
3662AC_PWROK ISEN1P 3662AC_CPUISEN1P [36]
PR6037 *Short_0201 18
[4] APU_PWRGD_SVID_REG PWROK
3662AC_CPUISEN1N [36]
PC9173 *10p/50V_4 PU6000 PC6012
RT3662AMGQW 0.1u/6.3V_2 PR6038 PC6011
PR6039 *Short_0201 3662AC_SVC 19 1.43K_1%_4 0.1u/16V_4
[4] APU_SVC SVC
PC9174 *10p/50V_4 10 3662AC_ISEN1N_CPU PR6040 1_1%_4
ISEN1N
PR6041 *Short_0201 3662AC_SVD 20 1 3662AC_HG2 PR6042
[4] APU_SVD SVD UGATE2 3662AC_CPU_HG2 [36]
1_5%_6 3662AC_CPUISEN2P [36]
PC9175 *10p/50V_4
2 3662AC_BOOT2
3662AC_SVT BOOT2 3662AC_CPUISEN2N [36]
PR6044 *Short_0201 21 PR6043 PR6045
[4] APU_SVT SVT *Short_0603 PC6013 3.74K_1%_4
0.1u/25V_4
40 3662AC_CPU_LX2 PC6014
PHASE2 3662AC_CPU_LX2 [36]
0.1u/16V_4
Double Check Pull High with HW 39 3662AC_CPU_LG2 PR6047
B LGATE2 3662AC_CPU_LG2 [36] B
1_1%_4
[4,5,29] VRM_PWRGD 3662AC_ISEN2P_CPU 3662AC_ISEN1N_CPU
7
PR6049 *Short_0201 3662AC_PGOOD 3 ISEN2P PR6046
+3V PGOOD 1.43K_1%_4
PR6048
10K_1%_2 PC6015 82p/50V_4 PC6016 150p/50V_4 PR6050 *1K_1%_4 3662AC_CPUISEN1N

PR6051 *Short_0201 3662AC_VRHOT 11

[4] CORE_PWM_PROCHOT# VRHOT_L 3662ACCOMP_CPU
5 PR6052 54.9K_1%_4 PR6053 10K_1%_4
COMP +VCC_CORE
PUT COLSE TO
VDDCR_CPU CHOKE PR6054 LL~0.7m
1K_1%_4
PHASE 1 3662AC_IMON_CPU 14
IMON 6 3662ACFB_CPU PR6055
Ispike~80A FB 100_1%_4 Double Check Vsense Setting
Vset1 474mV
2

PC6017 PR6056 with HW

PR6057 *100p/50V_4 VREF_PINSET_CPU *Short_0402
8 VSEN_CPU PR6000 *Short_0201
Delta Vset1 348mV 100K_NTC_4_1%
15 VSEN CPU_VDD0_RUN_FB_H [4]
PR6058 VREF_PINSET PC6018
IMON_NB
1

10.2K_1%_4 *82p/50V_4
Vtsen 1074mV PR6060 4 3662AC_RGND PR6061 *Short_0201
GND

RGND CPU_VDD0_RUN_FB_L [4]

PR6059 3.9_1%_4
10K_1%_4
Vtsen_NB 274mV PR6062 10/24 change netname to follow mb side
16.5K_1%_4

16

41

16.2K_1%_4 PR6064
PR6063

100_1%_4
PC6019
3662AC_IMON_NB
1

0.47uF/6.3V_2
A A
PR6065
100K_NTC_4_1%
2

Ispike~30A

PUT COLSE TO PR6066

VDDCR_SOC
13K_1%_4 PC6020
*100p/50V_4
Quanta Computer Inc.
CHOKE
PROJECT : Z8E
Size Document Number Rev
1A
VCORE (RT3662AMGQW)
Date: Wednesday, March 18, 2020 Sheet 35 of 44
5 4 3 2 1
 5 4 3 2 1

36
+VIN [20,31,32,33,34,37,38,39,40,41]
+VCC_CORE [7,35] +VIN
+VDDCR_SOC [7,35]

*15u/25V_7343H1.9
10u/25V_8

10u/25V_8

2200p/50V_4
*10u/25V_8

0.1u/25V_4
PC6021

PC6022

PC6023

PC6024

PC6025

PC6026
+

3
4
9
D1
Vinafix.com
PQ6001
AOE6932
Isat=42.5A +VCC_CORE AMD Dali FP5(15W)
D 1 G1 DCR(Typ)=1.9 mohm D
[35] 3662AC_CPU_HG1 PL6001
D2/S1 5 0.15uH/22A_7x7x3
2 S1/D2 6 3662AC_CPU_LX1 1 2 VDDCR_VDD
7
Countinue current:35A

330u/2V_7343H1.9

330u/2V_7343H1.9

330u/2V_7343H1.9

*330u/2V_7343H1.9
Don't Connect Pin2 to Phase PR6067
*2.2_5%_6
Peak current:45A

PC6027

PC6028

PC6029

PC6030
+ + + +
PR6068 PR6069
8 G2 *Short_0201 *Short_0201
OCP minimum:80A
[35] 3662AC_CPU_LG1
S2 LL= -0.7mV/A
PC6031

10
*2200p/50V_4

L/S RDSon(MAX)=1.8 mohm 3662AC_CPUISEN1P

[35] 3662AC_CPU_LX1
[35] 3662AC_CPUISEN1P
3662AC_CPUISEN1N
AMD Renoir FP6(15W)
[35] 3662AC_CPUISEN1N

VDDCR_VDD
Countinue current:33A
+VIN Peak current:50A
OCP minimum:80A
LL= -0.7mV/A

10u/25V_8

10u/25V_8

2200p/50V_4

0.1u/25V_4
*10u/25V_8
PC6032

PC6033

PC6034

PC6035

PC6036
3
4
9

D1 PQ6002
AOE6932
Isat=42.5A
C 1 G1 DCR(Typ)=1.9 mohm +VCC_CORE
C
[35] 3662AC_CPU_HG2 PL6002
D2/S1 5 0.15uH/22A_7x7x3
2 S1/D2 6 3662AC_CPU_LX2 1 2
7

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6
*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6
Don't Connect Pin2 to Phase PR6070

PC6037

PC6038

PC6039

PC6040

PC6041

PC6042

PC6043

PC6044

PC6045

PC6046
*2.2_5%_6
PR6071 PR6072
8 G2 *Short_0201 *Short_0201
[35] 3662AC_CPU_LG2
S2
PC6047
10

*2200p/50V_4

L/S RDSon(MAX)=1.8 mohm

[35] 3662AC_CPUISEN2P
3662AC_CPUISEN2P 3*330uF/9m+35*22uF/0603 (total with EE)
3662AC_CPUISEN2N
[35] 3662AC_CPU_LX2 [35] 3662AC_CPUISEN2N

AMD Dali FP5(15W) AMD Renoir FP6(15W)

B B
VDDCR_SOC VDDCR_SOC
Countinue current:10A Countinue current:13A
+VIN
Peak current:13A Peak current:17A
OCP minimum:30A OCP minimum:30A
10u/25V_8

10u/25V_8

2200p/50V_4

0.1u/25V_4

LL= -2.1mV/A LL= -2.1mV/A

*10u/25V_8
PC6048

PC6049

PC6050

PC6051

PC6052
5

D PQ6003
G AONS36380
4
[35] 3662AC_NB_HG1 S
Isat=42.5A +VDDCR_SOC
DCR(Typ)=1.9 mohm
1
2
3

PL6000
0.15uH/22A_7x7x3
3662AC_NB_LX1 1 2
330u/2V_7343H1.9

*330u/2V_7343H1.9
[35] 3662AC_NB_LX1

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6
5

PR6073
PC6053

PC6054

PC6055

PC6056

PC6057

PC6058

PC6059

PC6060

PC6061

PC6062

PC6063

PC6064
+ +
D PQ6000 *2.2_5%_6
AONS36312 PR6074 PR6075
4 G *Short_0201 *Short_0201
[35] 3662AC_NB_LG1 S
1
2
3

PC6065
*2200p/50V_4

1*330uF/9m+20*22uF/0603 (total with EE)

L/S RDSon(MAX)=2.6 mohm 3662ACNBISENP
[35] 3662ACNBISENP
A A
3662ACNBISENN
[35] 3662ACNBISENN

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
VCORE (RT3662ACGQW)
Date: Wednesday, March 18, 2020 Sheet 36 of 44
5 4 3 2 1
 5 4 3 2 1

+3V_S5
+1.8V_S5
+1.8V
+1.5V
+1.2V
[4,5,6,7,11,23,25,28,29,32,38]
[4,5,6,7,24,26,29]
[4,5,6,7,11,21,24,26,29,35]
[21]
[34]
VL
+VIN
+3V
+5V
VDDP
[32]
[20,31,32,33,34,36,38,39,40,41]
[4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,33,34,35,41]
[20,21,22,25,27,30,32]
[4,7,33]
37
D +1.8V_S5 D

1.8 Volt +/- 5%

Vinafix.com TDC : 3A
PEAK : 4A +1.5V
Width : 160mil PR9282
*Short_0603
1.5Volt +/- 5%
Double Check PU high with HW Double Check PU high with HW +3V_S5
TDC : 0.08A
+1.8V_S5 +1.8V_S5 PEAK : 0.1A
+3V
PC551 PR551
+3V PC9164
4.7u/6.3V_4
Width : 20mil
*2200p/50V_6 *2.2_5%_6
PJ7004
PR9283 *Short_3720 PR6416 +1.5V
100K_1%_2 PU3004 100K_1%_2 PU3003 PJ7002

4
3
PR9290 PL551 PR284 JW5222RSOTB_TRPBF PL14 *Short_3720
*Short_0201 1uH/3.35A_2.5x2.0x1.2 *Short_0201 2.2uH/1.67A_2.5x2.0x1.2

VIN
5213PG_1.8V 2 6 5213LX_1.8V 1 2 MAIND 2 [29] HWPG_1.5V 5 3 JW5222LX1.5V 1 2
PQ9014
[29] HWPG_1.8VS5 POK SW 5213FB_1.8V_S AOSS32334C POK SW
PR569 PR6417

22u/6.3V_6

22u/6.3V_6
0.1u/6.3V_2

*22u/6.3V_6
3 5 *Short_0201 *Short_0402 PR6414

PC561

PC562

PC563

PC9163
+3V_S5 VIN NC 1 2
MAINON *Short_0201

10u/6.3V_6

10u/6.3V_6

0.1u/16V_4
PC574 PR568 EN GND
R1

PC6230

PC9132

PC6231
PJ7005 1 5213FB_1.8V *22p/50V_4 20K_1%_2

FB
10u/6.3V_4
0.01u/50V_4

4 FB +1.8V
*Short_3720 PC6229
PC572

PC571

8 PGND 0.47u/6.3V_4 PC9162

SGND 5213EN_1.8V

6
9 7 *22p/50V_4
C
EPAD EN TDC : 1.88A C

*0.1u/6.3V_2
PR567 PEAK : 2.5A

PC581
JW5213DFND_TRPBF R2 10K_1%_4 R1
Vo=0.6*(R1+R2)/R2 Width : 100mil
=1.8V PR6418
22.6K_1%_4
R2 PR283
15K_1%_2 Vo=(0.6(R1+R2)/R2)
PR566
*Short_0402
=1.504V
S5_ON [29,32,33]

Thermal Protection
B Need fine tune B

PR191
for thermal protect point
150_5%_4 Note placement position +VIN +3V +5V +1.8V +1.2V VDDP +VIN
VL
TEMP=80'C

PC164 PR9284 PR102 PR216 PR9285 PR9311 PR9286 PR9289

0.1u/16V_4 1M_5%_6 22_5%_8 *220_5%_8 22_5%_8 22_5%_8 22_5%_8 1M_5%_6
5

PR193
*Short_0201 MAINON_ON_G MAIND
VCC

3 SYS_SHDN# PQ8 MAIND [33,34]

OT SYS_SHDN# [4,6,29,32]
DDTC144EUA-7-F

3
PU9006

3
PR194 TMP708AIDBVR PR9288
25.5K_1%_4 2 1M_5%_6 2 2 2 2 2 2
1 [29,32,34] MAINON PC104
SET
HYST
GND

PQ9013 PQ35 PQ7 PQ9057 PQ10 PQ9015 *2200p/50V_4

2N7002K *2N7002K 2N7002K 2N7002K 2N7002K 2N7002K

1
1
PR9287
Rset(Kohm)=0.0012T*T-0.9308T+96.147 *100K_1%_6
2

=29.363 K ohm HYST=VCC for 10

degree Hys.
HYST=GND for 30
degree Hys.

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Docum ent Num ber Rev
1A
+1.8V_S5/+1.5V/Thermal
Date: Wednes day, March 18, 2020 Sheet 37 of 44
5 4 3 2 1
 5 4 3 2 1

Design Reserved
Vinafix.com
D D

Double Check +3V_GFX +VDD_08

PU high with HW 0.95 Volt +/- 5%
TDC : 2A
PR9103
SP@100K_1%_2 PU9007
PEAK : 4A +VDD_08
PR9104 PL9006 Width : 160mil
*Short_0201 SP@1uH/3.35A_2.5x2.0x1.2
[39] VDD08_PG
5213PG_VDD08 2 6 5213LX_VDD08 1 2 +VDDCI (R19M-M18-50)_18W
POK SW
PR9108

*22u/6.3V_6
SP@22u/6.3V_6

SP@22u/6.3V_6
[email protected]/6.3V_2
3 5 *Short_0201

PC9185

PC9186

PC9187

PC9188
+3V_S5 VIN NC PC9189 PR9106 VDD_08
*22p/50V_4 [email protected]_1%_4
[email protected]/50V_4

SP@10u/6.3V_4
1 5213FB_VDD08
PC9190

PC9191

4 FB Vo = 0.95V (Fix)
8 PGND R1
9 SGND 7 5213EN_VDD08
EPAD EN Vo=0.6*(R1+R2)/R2 TDC：2A
R2
C SP@JW5213DFND_TRPBF PR9107
=0.95V EDC：3A C
PC9192 SP@20K_1%_4
*0.1u/6.3V_2 OCP：16A
PR9105
*Short_0201
+1.8V_GFX_PG [39,41]
R19M-P18-50 no stuff: +VDDCI (R19M-P18-50) _18W
PR9103,PR9104,PC9190,PC9191,PU9007,PL9006,PR9106,PR9107,PR9105,PC9185,PC9186,PC9187
R19M-P18-50 stuff:
PJ9000,PC9046,PC9045,PC9043,PC9042,PQ9002,PL9002,PR9072,PR9073,PC9047,PC9049 VDDCI + VDD_08 (merged)
+VIN
Vo = 0.875V (Fix)
TDC：8A
*SP@10u/25V_8

*SP@10u/25V_8

*SP@10u/25V_8

*SP@2200p/50V_4

*[email protected]/25V_4
EDC：12A
PC9042

PC9043

PC9044

PC9045

PC9046
B OCP：16A B
2

PQ9002
D1
D1
D1

*SP@AONY36354 Isat=22A
DCR(Typ)=9 mohm +VDDCI
1 G1 PL9002
[39] 3662AM_HG1_VDDCI *SP@1uH/11A_7x7x3
S1/D2 9 3662AM_LX1_VDDCI 1 2

*SP@330u/2V_7343H1.9
*[email protected]/16V_4
8 G2 PR9071
[39] 3662AM_LG1_VDDCI *[email protected]_5%_6 +

PC9047

PC9049
PR9072 PR9073
*Short_0201 *Short_0201
S2
S2
S2
7
6
5

PC9050
*SP@2200p/50V_4

A
L/S RDSon(MAX)=3.5 mohm A

[39] 3662AM_LX1_VDDCI 3662AM_VDDCI_ISENP

[39] 3662AM_VDDCI_ISENP
3662AM_VDDCI_ISENN
Quanta Computer Inc.
[39] 3662AM_VDDCI_ISENN
PROJECT :
Size Document Number Rev
1A
LED Panel (TPS61087)
Date: Wednesday, March 18, 2020 Sheet 38 of 44
5 4 3 2 1
 5 4 3 2 1

3662AM_VCC_GPU +5V_S5

39
+VIN_GPU [40]
+VGA_CORE [17,40] PR9001
+VDD_08 [17,38] [email protected]_5%_4
+5V_S5
PR9002
*Short_0402 +VIN_GPU
+5V_S5 [19,24,27,30,32,34,35] 3622AM_PVCC_GPU
+1.8V_GFX [12,15,16,17,41] PC9001
[email protected]/10V_4 PR9003

[email protected]/10V_4
+3V [4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,33,34,35,37,41]
[email protected]_5%_4

PC9002
R19M-P18-50 no stuff:
PR9100,PR9101,PR77865

. R19M-P18-50 stuff:
Vinafix.com PC9003
[email protected]/25V_4
PR9004 PR9005

17

34

28
PR9029,PR9102,PR9006,PR9010,PC9004,PR9011,PC9005,PR9022,PC9007,PC9008,PR9026,PR9027,
D PR9064,PR9061,PR9057,PR9063,PR9008,PR9017,PR9018,PR9009,PR9019,PR9013,PR9012 EV@487_1%_4 EV@105K_1%_4 D
3662AM_SET1_GPU 13 PR9006 for +VDDCI

VCC

PVCC

VIN
VREF_PINSET_GPU SET1 *SP@1_5%_6
PR9007 PR9016 31 3662AM_UGATE_VDDCI
f=400KHz UGATE_NB 3662AM_HG1_VDDCI [38]
EV@140_1%_4 [email protected]_1%_4
3662AM_VDDCI_ISENP [38]
3662AM_TSEN_VDDCI 23 3662AM_VDDCI_ISENN [38]
VREF_PINSET_GPU PR9008 PR9017 PR9009
*SP@237K_1%_4 *[email protected]_1%_4 *[email protected]_1%_4 TSEN_NB 30 3662AM_BOOT_VDDCI
PR9018 PUT COLSE TO
BOOT_NB PR9010 PR9011
*SP@0_5%_2 VDDCI HOT *Short_0603 PC9004 *[email protected]_1%_4
PR9012 PR9013 1 2 SPOT *[email protected]/25V_4
*SP@10K_1%_4 *SP@14K_1%_4 PR9019 *SP@100K_NTC_4_1% PC9005
32 3662AM_LX1_VDDCI *[email protected]/6.3V_2
PHASE_NB 3662AM_LX1_VDDCI [38]
PR9014 PR9020 PR9021 3662AM_TSEN_GPU 12 33 3662AM_LG1_VDDCI
VREF_PINSET_GPU TSEN LGATE_NB 3662AM_LG1_VDDCI [38]
[email protected]_1%_4 [email protected]_1%_4 [email protected]_1%_4
PR9015 PUT COLSE TO PR9100 SP@10K_1%_2 +5V_S5 PR9022
*Short_0201 VGA_CORE HOT 25 3662AM_ISENP_VDDCI *[email protected]_1%_4 PC9006
PR9023 PR9024 1 2 SPOT ISENP_NB PR9101 SP@10K_1%_2 [email protected]/6.3V_2
+5V_S5
EV@11K_1%_4 [email protected]_1%_4 PR9025 EV@100K_NTC_4_1% 24 PR9102 *SP@0_5%_2
ISENN_NB
27 3662AM_COMP_VDDCI PC9007 *SP@82p/50V_4 PC9008 *SP@150p/50V_4
PR77865 SP@0_5%_4 COMP_NB
[38] VDD08_PG +VDDCI
PR9026 *[email protected]_1%_4 PR9027 *SP@10K_1%_4
PR9029 *SP@0_5%_4 3662AM_EN_GPU 29
[38,41] +1.8V_GFX_PG EN 3662AM_FB_VDDCI
LL~0m
26 PR9304 *53.6K_1%_4
PC9009 FB_NB
Vih=2V
*EV@1000p/50V_4 PR9028
Double Check EN Sequence with HW PR9030 EV@100_1%_4
EV@1_5%_6 Double Check Vsense Setting with HW
Double Check VDDIO Pin Pull High Sequence with HW 37 3662AM_UGATE1_GPU
UGATE1 3662AM_HG1_GPU [40]
Double Check SVC/SVD Pull High (*MUST earlier than EN pin) PR77849 *Short_0201
(same as VDDIO pin) PR9032 38 3662AM_BOOT1_GPU VDDCI_CORE_SENSE [17]
[email protected]_5%_6 BOOT1 PR9031
+1.8V_GFX 3662AM_VDDIO_GPU 22 *Short_0603 PC9010 for +VGA_CORE PH1
+1.8V_GFX VDDIO 3662AM_LX1_GPU
36 [email protected]/25V_4
3662AM_LX1_GPU [40]
PHASE1 PR9000 *EV@1K_1%_4 3662AM_GPU_ISEN2N
C C
PC9011 35 3662AM_LG1_GPU
LGATE1 3662AM_LG1_GPU [40]
PR9310 10/24 change netname to follow mb side EV@1u/6.3V_2
*Short_0402 9 3662AM_ISEN1P_GPU PR9033 [email protected]_1%_4
SVID_EN ISEN1P 3662AM_GPU_ISEN1P [40]
[12] SVID_EN PR9034 *Short_0201 3662AM_PWROK_GPU18
PWROK
3662AM_GPU_ISEN1N [40]
PC9176 *EV@10p/50V_4 PU9000 PC9013
EV@RT3662AMGQW [email protected]/6.3V_2 PR9035 PC9012
SVI2_CLK PR9036 *Short_0201 3662AM_SVC_GPU 19 PR9037 [email protected]_1%_4 [email protected]/16V_4
[15] SVI2_CLK SVC
PR9308 PR9309 EV@1_1%_4
EV@10K_1%_4 *EV@10K_1%_4 PC9177 *EV@10p/50V_4 10 3662AM_ISEN1N_GPU
ISEN1N
SVI2_CLK SVI2_DATA SVI2_DATA PR9038 *Short_0201 3662AM_SVD_GPU 20 1 3662AM_UGATE2_GPU PR9039
[15] SVI2_DATA SVD UGATE2 3662AM_HG2_GPU [40]
EV@1_5%_6 3662AM_GPU_ISEN2P [40]
PC9178 *EV@10p/25V_2
PR9305 PR9306 2 3662AM_BOOT2_GPU
SVI2_SVT BOOT2 3662AM_GPU_ISEN2N [40]
*EV@10K_1%_4 EV@10K_1%_4 PR9041 *Short_0201 3662AM_SVT_GPU 21 PR9040 for +VGA_CORE PH2 PR9042
[15] SVI2_SVT SVT *Short_0603 PC9014 [email protected]_1%_4
[email protected]/25V_4
40 3662AM_LX2_GPU PC9015
PHASE2 3662AM_LX2_GPU [40]
[email protected]/16V_4
Double Check Pull High with HW (+3V or +3V_GFX??) 39 3662AM_LG2_GPU PR9045
Set VBOOT=0.9V LGATE2 3662AM_LG2_GPU [40]
EV@1_1%_4
Pre-PWROK Output Voltage [12,41] VGPU_CORE_PG 3662AM_ISEN2P_GPU 3662AM_ISEN1N_GPU
7
PR9046 *Short_0201 3662AM_PGOOD_GPU 3 ISEN2P PR9044
+3V_GFX PGOOD [email protected]_1%_4
PR9043
SVC SVD V EV@10K_1%_2 PC9016 EV@82p/50V_4 PC9017 EV@150p/50V_4 PR9047 *EV@1K_1%_4 3662AM_GPU_ISEN1N
change to GFX PR77866
*EV@10K_1%_2
0 0 1.1
+3V_GFX PR9048 *Short_0201 3662AM_VRHOT_GPU 11
VRHOT_L 5 3662AM_COMP_GPU PR9049 EV@34K_1%_4 PR9050 EV@10K_1%_4
COMP +VGA_CORE
0 1 1.0 [15] GPU_PWM_PROCHOT# PUT COLSE TO
VGA_CORE CHOKEPR9051 (1) R19M-P18-50, LL~0.6m : 56.2K CS35622FB10
(2) R19M-M18-50, LL~1m : 34K (default) CS33402FB18
EV@1K_1%_4
PHASE 1 3662AM_IMON_GPU 14
1 0 0.9 Ispike~90A
IMON 6 3662AM_FB_GPU PR9052
FB EV@100_1%_4
B B
2

PC9018 PR9053 Double Check Vsense Setting with HW

1 1 0.8 PR9054 *EV@100p/50V_4 VREF_PINSET_GPU *Short_0402
8 3662AM_VSEN_GPU PR9055 *Short_0201
EV@100K_NTC_4_1%
15 VSEN VGPU_CORE_SENSE [17]
PR9056 VREF_PINSET PC9019
IMON_NB
1

EV@11K_1%_4 *EV@82p/50V_4
PR9058 4 3662AM_RGND_GPU PR9059 *Short_0201
GND

RGND VSS_GPU_SENSE [17]

PR9057 [email protected]_1%_4
*[email protected]_1%_4
PR9060
*SP@13K_1%_4

3662AM_IMON_VDDCI 16

41

[email protected]_1%_4 PR9062
PR9061

EV@100_1%_4
PC9000
Vset1 474mV
1

[email protected]/6.3V_2

PR9063
Delta Vset1 1250mV *SP@100K_NTC_4_1%
2

Ispike~16A
Vtsen 1074mV
PUT COLSE TO PR9064
Vtsen_NB 274mV VDDCI CHOKE *[email protected]_1%_4 PC9020
*EV@100p/50V_4
+VIN +VGA_CORE +VDD_08

PR77861 PR77860 PR77863

EV@1M_5%_6 EV@22_5%_8 EV@22_5%_8

PR77862
3

3
A *Short_0402 A
3662AM_EN_GPU 2 2 2
PR77859 PQ9067 PQ9069
EV@1M_5%_6 EV@2N7002K EV@2N7002K
PQ9068
1

1
EV@2N7002K

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
VGACORE1 (RT3662AMGQW)
Date: Wednesday, March 18, 2020 Sheet 39 of 2
5 4 3 2 1
 5 4 3 2 1

40
+VIN [20,31,32,33,34,36,37,38,39,41]
+VGA_CORE [17,39] PJ9001
+VIN_GPU *Short_3720 +VIN
+VDD_08 [17,38,39]
+VIN_GPU [39]

EV@15u/25V_7343H1.9
EV@10u/25V_8

EV@10u/25V_8

EV@2200p/50V_4
*EV@10u/25V_8

[email protected]/25V_4
PC9021

PC9022

PC9023

PC9024

PC9025

PC9026
+

D
Vinafix.com +VGA_CORE(R19M-P18-50) _18W
D

3
4
9
D1 PQ9000
EV@AOE6932
Isat=40A VDDC
+VGA_CORE
DCR(Typ)=2.5 mohm
1 G1
[39] 3662AM_HG1_GPU
PL9001
D2/S1 5 [email protected]/23A_7x7x3 TDC：22A
2 S1/D2 6 3662AM_LX1_GPU 1 2

EV@330u/2V_7343H1.9
7 EDC：60A

[email protected]/16V_4

EV@22u/6.3V_6
OCP：90A

PC9027

PC9029

PC9028
Don't Connect Pin2 to Phase PR9065 +
*[email protected]_5%_6
PR9066 PR9067 LL=-0.6m
8 G2 *Short_0201 *Short_0201
[39] 3662AM_LG1_GPU
S2
PC9031

10
*EV@2200p/50V_4

C C
L/S RDSon(MAX)=1.8 mohm 3662AM_GPU_ISEN1P +VGA_CORE(R19M-M18-50)_18W
[39] 3662AM_GPU_ISEN1P
[39] 3662AM_LX1_GPU 3662AM_GPU_ISEN1N
[39] 3662AM_GPU_ISEN1N
VDDC + VDDCI (merged)

TDC：25A
+VIN_GPU EDC：60A
OCP：90A

EV@10u/25V_8

EV@10u/25V_8

EV@2200p/50V_4
*EV@10u/25V_8

[email protected]/25V_4
LL=-1m

PC9032

PC9033

PC9034

PC9035

PC9036
3
4
9

D1 PQ9001
EV@AOE6932
Isat=40A
B
DCR(Typ)=2.5 mohm +VGA_CORE B
1 G1
[39] 3662AM_HG2_GPU PL9000
D2/S1 5 [email protected]/23A_7x7x3
2 S1/D2 6 3662AM_LX2_GPU 1 2

EV@330u/2V_7343H1.9

*EV@330u/2V_7343H1.9
7

[email protected]/16V_4

EV@22u/6.3V_6
PC9038

PC9040

PC9039

PC9037
Don't Connect Pin2 to Phase PR9068 + +
*[email protected]_5%_6
PR9070 PR9069
8 G2 *Short_0201 *Short_0201
[39] 3662AM_LG2_GPU
S2
PC9041
10

*EV@2200p/50V_4

L/S RDSon(MAX)=1.8 mohm 3662AM_GPU_ISEN2P

[39] 3662AM_GPU_ISEN2P
3662AM_GPU_ISEN2N
[39] 3662AM_LX2_GPU [39] 3662AM_GPU_ISEN2N

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Document Number Rev
1A
VGACORE2 (RT3662AMGQW)
Date: Wednesday, March 18, 2020 Sheet 40 of 2
5 4 3 2 1
 5 4 3 2 1

41
+3V [4,5,6,7,9,11,12,20,21,22,23,24,25,26,27,28,29,30,32,33,34,35,37]
+3V_GFX [12,15,38,39]

+3VPCU [5,7,20,21,23,26,29,30,31,32]
+1.8V_GFX [12,15,16,17,39]
+5VPCU [19,21,32,33,41]

PQ9003
EV@AO3413 +3VPCU

+3V
PC9091
1 3
Vinafix.com
+3V_GFX TDC : 10mA
PEAK : 20mA PR156
*[email protected]/16V_4 PC9092
Width : 20mil *Short_0805 TDC : 1.13A

2
D [email protected]/16V_4 D
+3V_GFX PC5357 PEAK : 1.5A
EV@10u/6.3V_6
PR9132 PR77864 Width : 60mil
EV@100K_1%_4 *Short_0402
+3V PC135 PU9 +1.8V_GFX
[email protected]/16V_4 EV@UP8801SSW8
PR77846 3.3V_PU9 3 5
VIN NC
*EV@0_5%_4
PR9133 DGPU_PWREN_R 8801EN 2 6 1.8V_PU9 PR77848 *Short_0805
VEN VO
*EV@10K_1%_4 Vih=1.4V
PR9134 4 PR159
+5VPCU VPP 7

3
EV@20K_1%_2 PC9182 [email protected]_1%_4 PC9181 PC9183 PC5359

GND#2
GND#1
DGPU_PWREN_R 2 [email protected]/16V_4 ADJ EV@10u/6.3V_4 *EV@10u/6.3V_4 [email protected]/16V_4
[5,12] DGPU_PWREN 1
PQ9006 PC9179 Rg
EV@2N7002K EV@1u/6.3V_4 POK
Rh
PR9136 PC9094

1
9 8
*EV@100K_1%_6 [email protected]/10V_4 PR160
EV@10K_1%_4

PR161
*Short_0402 Vout = (1+Rg/Rh)*0.8
Double Check EN Sequence with HW
[38,39] +1.8V_GFX_PG =1.816V
PR77847
+3V_GFX EV@100K_1%_4

+VIN +1.8V_GFX
change to GFX
+VIN +3V_GFX Double Check Pull High with HW
PR77857 PR77855
EV@1M_5%_6 EV@22_5%_8
PR9128 PR9129
EV@1M_5%_6 EV@22_5%_8

PR77858

3
*Short_0402
PR77835 8801EN 2 2
3

C
*Short_0402 PR77854 PQ9065 C
DGPU_PWREN_R 2 2 EV@1M_5%_6 EV@2N7002K
PR9135 PQ9008 PQ9066

1
EV@1M_5%_6 EV@2N7002K EV@2N7002K
PQ9007
1

EV@2N7002K

+VIN [20,31,32,33,34,36,37,38,39,40]
+1.35V_GFX [13,17,18]
+5VPCU [19,21,32,33,41] Fsw=550KHz PC9067
*[email protected]/50V_4 PJ9007
*Short_3720 +VIN
PR9120
EV@105K_1%_4
G5335-TON

EV@10u/25V_8
EV@2200p/50V_4
*[email protected]/25V_4
6

PU9005

PC9075

PC9065

PC9080
+5VPCU 7 8
+1.35V_GFX
TON

NC V+#1 9
PR9121
V+#2
EV@10_5%_4
G5335-VCC 21 V+#3
22
24
1.35 Volt +/- 3%
VCC V+#4 TDC : 4.5A
Double Check Pull High with HW
PC9074
PEAK : 6A
+3V_GFX EV@10u/6.3V_6 Width : 200mil
PR9137 PC9072
[email protected]_5%_6 [email protected]/25V_4
20 G5335-BST +1.35V_GFX
BST
PR9122 PJ9008
EV@100K_1%_2 25 *Short_3720
LX#1 10 PL9005
PR9119 *Short_0201 G5335-PWRGD 1 LX#2 11 EV@1uH/11A_7x7x3
B [5] DGPU_PWROK PGOOD LX#3 16 G5335-LX 1 2 B
+5VPCU PR9124 LX#4 17
11/13 change to DGPU_PWROK *EV@0_5%_2 LX#5 18
EV@22u/6.3V_6

EV@22u/6.3V_6

EV@22u/6.3V_6

EV@22u/6.3V_6

EV@22u/6.3V_6

[email protected]/16V_4
*EV@22u/6.3V_6

*EV@22u/6.3V_6
G5335-PFM 3 LX#6
PFM PR9123
PC9073

PC9070

PC9069

PC9076

PC9079

PC9066

PC9071

PC9078
PR9116 *Short_0201 12 *[email protected]_5%_6
G5335-AGND 2 PGND#1 13
G5335-EN
EN PGND#2 14 R1
PGND#3 15
PGND#4 19
Pulse-Skipping Mode PGND#5
PR9125 PC9095
4 [email protected]_1%_4 *EV@1000p/50V_4
AGND G5335-AGND
PC9068
*EV@680p/50V_6
PR9118
*Short_0402
G5335-SS 23 5 G5335-FB
[12,39] VGPU_CORE_PG SS FB
R2 Vo=0.8*(R1+R2)/R2
PC9096 PC9077 EV@G5335QT2U PR9126
=1.357V
*[email protected]/6.3V_2 [email protected]/6.3V_2 [email protected]_1%_2

Double Check EN Sequence with HW

G5335-AGND G5335-AGND

G5335-AGND

PR9117 VFB=0.8V
*Short_0402

G5335-AGND

+VIN +1.35V_GFX

PR77852 PR77851
EV@1M_5%_6 EV@22_5%_8
A A

PR77853
3

*Short_0402
G5335-EN 2 2
PR77850 PQ9062
EV@1M_5%_6 EV@2N7002K
PQ9063
1

EV@2N7002K

Quanta Computer Inc.

PROJECT : Z8E
Size Docum ent Num ber Rev
1A
GPU_POWER
Date: Wednes day, March 18, 2020 Sheet 41 of 44
5 4 3 2 1
 5 4 3 2 1

45
HOLE22 HOLE8 HOLE26
*HG-Z8E-EDADOC-1 *HG-Z8E-EDADOC-3 *SPAD-RE3_5X5_0 remove HOLE12 as Z8E
7
8
Vinafix.com
6
5
9 4
D D
10
Hole

1
2
3

1
HOLE24 HOLE25 HOLE14 HOLE19 HOLE17
HOLE2 HOLE13 *2D-BARCODE-8X8-S *2D-BARCODE-6X6-S *H-TC154IC154BC237D154PT-1 *H-TC154IC154BC237D154PT-1 *H-TC154IC154BC237D154PT-1
*SPAD-RE5_98X2_0 *SPAD-A3A5-EDADOC-1

1
1

C C

HOLE21
h-davidoff-1
HOLE23 HOLE16
*H-DAVIDOFF-1-1 *hg-c354i158d118p2 HOLE18
7 6 7 6 HOLE5 *HG-C276D126P2 HOLE3
8 5 8 5 HOLE11 *spad-re209x315np 7 6 *h-s157d157n
9 4 9 4 *hg-o335x315d252x232p2 8 5
1

7 6 9 4
8 5
1
2
3

1
2
3
9 4

1
2
3
WiFi Nut

1
1
2
3
B B

HOLE6 HOLE7 HOLE10 HOLE15

HOLE20 *spad-c354np *spad-c354np EV@O-Z8E-1P2 EV@O-Z8E-1P2
*h-c75d75n
1

1
1

A A
Quanta Computer Inc.
PROJECT : Z8E
Size Document Number Rev
1A
Hole
Date: Wednesday, March 18, 2020 Sheet 42 of 44
5 4 3 2 1
 5 4 3 2 1

+5VPCU TDC : 8A USB 3.0 port*1 with USB Charger

46
+5V_S5 PEAK : 5.5A USB 3.0 port*2, USB2.0*1 : 2.5A
TypeC*1 : 3A
S5_ON PANEL_LED_EN
VA JW7110DFNC_TRPBF

BQ24780SRUYR +VIN RT6258CGQUF PU6002

PU6003
PU1 SYS_SHDN#
+5V PEAK : 4.7A Realtek ALC255 : 1A
p37 SATA HDD & ODD*1pcs : 2.5A
p37
MAINON
BAT-V

p36
Vinafix.com VL

D Touch Pad D
WIFI TDC : 0.98A
TDC : 6A +3V_S5 PEAK : 7A EC G9661MF11U +2.5V_SUS
+3VPCU
PU14 p39 MAIND
S5_ON JW7110DFNC_TRPBF DDR4_SUSON_2V5
PU6001
RT6256BGQUF TDC : 2.48A
PU6000 JW5213DFND_TRPBF +1.8V_S5 AO3404
MAINON
+3V +1.8V PEAK : 0.4A
SYS_SHDN# p37 PEAK : 4.36A S5_ON PU3004 p43 MAIND PQ9 p43
p37
NGFF SSD *1pcs : 2A

AO3404 +1V8_GFX_MAIN TDC : 0.9A

3V_LDO EC 1V8_MAIN_EN
PQ9 p46

+1V8_AON TDC : 0.75A

DGPU_PWR_EN

JW5222RSOTB_TRPBF
MAINON
PU3003 p43 +1.5V TDC : 0.39A
TDC : 8.09A
G5335QT2U +1V_S5 AON7408
+1V_S5_ON
PU16
PQ35
+VCCIO PEAK : 4.8A
MAIND p38

p38

AO3404
SUSD PQ11
+1V_SUS PEAK : 0.25A
p38
C C

TDC : 5.57A
+1.2VSUS
G9336ADJTP1U
GPU_PWR_GD PU9003
+1.03_GFX TDC : 0.9A
p46
S3/MAINON G5416QS1U
S5/SUSON_R PU26 TDC : 0.45A
+VDDQ_VTT
+2.5V_SUS TDC : 0.98A

+VDDQ TDC : 0.38A

p39

+VIN_VCC_CORE RT9610CGQW
+VCC_CORE Icc Max：70A
3602_DRON PU7002

p41

+VIN_VCC_CORE RT9610CGQW
+VCC_CORE Icc Max：70A
3602_DRON PU7001

B B
p41

+VIN_VCCGT RT9610CGQW
3602_DRON PU7003 +VCCGT Icc Max：31A

p42

+VIN_VCCSA RT9610CGQW
3602_DRON PU7004 +VCCSA Icc Max：6A

p42

+VIN_VGPU_CORE RT8813DGQW
EDP-P:60.3A
1V8_MAIN_EN PU9000 +VGPU_CORE

p44

A A

G5335QT2U
FBVDDQ_EN PU9004 +1.35V_GFX EDP-P:7.4A

p45

Quanta Computer Inc.

PROJECT : Z8E
Size Docum ent Num ber Rev
Power Tree 1A
Date: Wednes day, March 18, 2020 Sheet 43 of 44

5 4 3 2 1
 5 4 3 2 1

Stage
A
Date
20191005 1. first released
CHANGE LIST
47
Vinafix.com
D D

C
MP C

B B

A A

Quanta Computer Inc.

PROJECT : Z8E
Size Docum ent Num ber Rev
Change List_1 1A

Date: Wednesday, M arch 18, 2020 Sheet 44 of 44

5 4 3 2 1