Lab Workbook Vivado IP Flow

Vivado IP Flow
2018.3

Abstract
In this lab, you will add the Xilinx Clocking Wizard IP using the IP flow, allowing you to configure
a clocking subsystem to provide various clock outputs and clock buffers to connect clock signals
to global clock networks.
This lab supports both Verilog and VHDL design files. However, the lab instructions and graphics
are limited to VHDL usage.
This lab should take approximately 30 minutes.

Objectives
After completing this lab, you will be able to:
 Create a clocking subsystem consisting of an MMCM and some internal buffers by using the
Clocking Wizard
 Instantiate the generated cores in a design

Introduction
The LogiCORE™ IP Clocking Wizard core simplifies the creation of HDL source code wrappers for
clock circuits customized to your clocking requirements. The wizard guides you in setting the
appropriate attributes for your clocking primitive, and allows you to override any wizard-calcu-
lated parameter. In addition to providing an HDL wrapper for implementing the desired clocking
circuit, the Clocking Wizard also delivers a timing parameter summary generated by the Xilinx
timing tools for the circuit.

General Flow
Step 1: Step 2: Step 3:
Opening an Building and Implement-
Existing Instantiating ing the
Project the Core Design

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Opening an Existing Project Step 1

You will begin the lab by launching the Vivado® Design Suite and opening the
wave_gen.xpr design in the Vivado IDE.

2-1. [Linux users]: Launch VirtualBox from the Start menu and start the
Ubuntu_VM virtual machine.

3-2. [Linux users]: Copy the files from the shared Windows folder to your
training directory using the following Linux command.
[host]$ source /media/sf_training/setup_TopicCluster.sh
IP_Flow
If you do not recall how to perform these tasks, refer to the "Board, OS, COM,
and IP Address Tasks" section in the Lab Reference Guide.

4-3. Launch the Vivado Design Suite.

If you do not recall how to perform this task, refer to the "Launching the Vivado
Design Suite" section under Vivado Design Suite Operations in the Lab Reference
Guide.

5-4. Open the Vivado Design Suite project named wave_gen.xpr located in the
below mentioned directory.
[Windows users]: Browse to the C:\training\IP_Flow\lab\[KCU105 | KC7xx]\vhdl
directory.
[Linux users]: Browse to the /home/xilinx/training/IP_Flow/lab/
[KCU105 | KC7xx]/vhdl directory.
If you do not recall how to perform this task, refer to the "Opening a Vivado De-
sign Suite Project" section under Vivado Design Suite Operations in the Lab Ref-
erence Guide.

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Building and Instantiating the clk_core Core Step 6

Here you will open the IP catalog to access the Clocking Wizard in order to
customize the clock core IP and then instantiate it in the clk_gen.v/vhd module.

7-5. Launch the Clocking Wizard from the IP catalog in the Vivado IDE.
8-6-1. Click IP Catalog under Project Manager in the Flow Navigator.
Alternatively, you can select Window > IP Catalog.
The IP Catalog window opens in the main workspace area.
9-7-2. Expand FPGA Features and Design > Clocking in the IP catalog.
10-8-3. Double-click Clocking Wizard to customize the selected IP.

Alternatively, you can right-click and select Customize IP.

The Customize IP window opens.

Question 1
Why use the Clocking Wizard to create the core? That is, why not just instantiate the MMCM
primitive?

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11-9. Customize the Clocking Wizard IP with the following parameters:

 Component Name: clk_core
 Primitive: MMCM
 Input Frequency: 300 MHz (KCU105) or 200 MHz (KC7xx)
Two output clocks of 200 MHz frequency
12-10-4. Ensure that the Show disable ports option is not selected in the IP Symbol tab (left
side).
13-11-5. Enter clk_core in the Component Name field.
14-12-6. Ensure that MMCM is selected in the Clocking Options > Primitive field.
15-13-7. Ensure that the Frequency Synthesis and Phase Alignment options are selected.
16-14-8. Set the Primary Input Clock Frequency field to 300.000 MHz (KCU105) or 200.00 MHz
(KC7xx).
17-15-9. Set the Source field to Differential clock capable pin.

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Note: The Primary Input Clock Frequency option specified for the core is used so that
the wizard can calculate the correct modes and parameters for the core to generate the
outputs specified in the following stages. If this frequency does not match the frequency
of the clock source of the board, then the outputs will not match the requested output
frequencies.

Figure 6-1: Clocking Features/Input Clocks (KCU105)

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Figure 6-2: Clocking Features/Input Clocks (KC7xx)

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18-16. Generate two output clocks (clk_out1 and clk_out2) from the MMCM
module with an output frequency of 200 MHz each.
19-17-10. Select the Output Clocks tab in the Customize IP dialog box.
20-18-11. Enter 200 as the value in the Output Freq (MHz) Requested field of the clk_out1
output clock.
21-19-12. Enable the clk_out2 output clock by using the check box.
22-20-13. Enter 200 as the value in the Output Freq (MHz) Requested field of the clk_out2
output clock.
23-21-14. Ensure that the Duty Cycle field is set to 50% for both output clocks.

Figure 6-3: Output Clocks Settings Tab (KCU105)

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24-22. Leave all the other tabs in the Clocking Wizard at their default settings.
Review the clock summary and generate the core.
25-23-15. Select the Summary tab and review the settings.
26-24-16. Click OK in the Customize IP dialog box.
The Generate Output Products dialog box opens.
27-25-17. Click Generate in the Generate Output Products dialog box.
28-26-18. Click OK to run the OOC flow.
Note: In the OOC flow, the IP is synthesized alone and an OOC DCP is produced. The
produced DCP is a container file, and includes a netlist as well as constraints.
Notice that a new file is added to the Sources > Hierarchy view: clk_core.xci. This source
file will not be included in the design hierarchy until the component has been instanti-
ated into one of the HDL source files.

29-27. View the HDL functional model for clk_core and confirm that the core
implemented by the core generator has the expected architecture.
30-28-19. Select the IP Sources tab in the Sources view.
31-29-20. Expand IP > clk_core > Synthesis.
32-30-21. Double-click clk_core_clk_wiz.v to view the HDL functional model.
33-31-22. Examine the source code generated by the Clocking Wizard.
KCU105 users:
This file contains the following instantiated components: an IBUFDS, an MMCME3_ADV,
and three BUFGs.
The input clock clk_in1_p/n drives an IBUFDS, which in turn drives the CLKIN1 port of
MMCME3_ADV. The CLKOUT0 and CLKOUT1 output of MMCME3_ADV drives the BUFGs,
which connects to the clk_out1 and clk_out2 output port of the module.
The MMCM attributes are passed via in-line parameter assignments.
The functional model of this core is not solely a simulation model, but is, in fact, the in-
stantiation and interconnection of the required hardware primitives. The Clocking Wizard
does not generate a separate netlist file.
KC7xx users:
This file contains the following instantiated components: an IBUFDS, an MMCME2_ADV,
and three BUFGs.
The input clock clk_in1_p/n drives an IBUFDS, which in turn drives the CLKIN1 port of
MMCME2_ADV. The CLKOUT0 and CLKOUT1 output of MMCME2_ADV drives the BUFGs,
which connects to the clk_out1 and clk_out2 output port of the module.

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The MMCM attributes are passed via in-line parameter assignments.

The functional model of this core is not solely a simulation model, but is, in fact, the in-
stantiation and interconnection of the required hardware primitives. The Clocking Wizard
does not generate a separate netlist file.

Question 2
If the core is already created, is the MMCM already connected to the design? Why must the
MMCM core be instantiated into this design?

34-32-23. Right-click the clk_core_clk_wiz.v tab and select Close to close the source file
when you are finished viewing the HDL source.
Note: The design files for this IP are delivered in Verilog only.

35-33. Instantiate the clk_core component by copying-and-pasting the text from

the instantiation template into the clk_gen.vhd/v file after the comment
"Instantiate clk_core – generated by the Clocking Wizard".
36-34-24. Expand IP > clk_core > Instantiation Template in the IP Sources tab of the
Sources view.
37-35-25. Select and double-click clk_core.vho/veo to open the instantiation template in
the text editor.
The language that the template is provided in is set by your language choice when you
built the project. It can be changed at any time.
38-36-26. Copy the instantiation template for the clk_core core from the clk_core.veo/vho
window by selecting all the text between the "Begin Cut here for INSTANTIATION
Template" and "End INSTANTIATION Template" comment lines and right-clicking and
selecting Copy.
39-37-27. Select the Hierarchy tab and expand the wave_gen hierarchy.
40-38-28. Double-click clk_gen.vhd/v to open the source code in the text editor.
41-39-29. Paste the copied text into the clk_gen.vhd/v file under the comment "Instantiate
clk_core – generated by the Clocking Wizard" by right-clicking and selecting Paste.
Note that normally the component declaration would need to be copied as well. For this
lab, the component declaration has already been added for you. This can be verified by
looking for the clk_core component under the architecture section of the clk_gen.vhd file
(line 96). So component declaration need not to be copied from the Instantiation Tem-
plate.
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42-40. Complete the instantiation by changing the instance name and filling in the
port connections.
43-41-30. Complete the instantiation by changing the instance name and filling in the port
connections as follows:
VHDL
clk_core_i0: clk_core
port Map
(
clk_in1_p => clk_pin_p,
clk_in1_n => clk_pin_n,
clk_out1 => clk_rx_internal,
clk_out2 => clk_tx_internal,
reset => rst_i,
locked => clock_locked
);
Verilog
clk_core clk_core_i0 (

.clk_out1 (clk_rx),
.clk_out2 (clk_tx),
.reset (rst_i),
.locked (clock_locked),
.clk_in1_p (clk_pin_p),
.clk_in1_n (clk_pin_n)
);
44-42-31. Select File > Save File to save clk_gen.vhd/v.
Note: In order to make sure that the clk_core IP is included in the wave_gen design, re-
fresh the Hierarchy from the Sources window before running the next proc in order to
use the Tcl completer script.

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Implementing the Design Step 45

Here you will verify that the clk_core IP is properly instantiated in the
clk_gen.vhd/v module and then implement the design to view what clocking
resources have been used by the Clocking Wizard IP.

46-43. Verify that clk_core is correctly instantiated in the clk_gen.vhd/v module.

47-44-32. Select the Hierarchy window.
48-45-33. Expand Design Sources > wave_gen > clk_gen_i0 to confirm that the
clk_core.xci file is located correctly.
You will need to expand clk_gen_i0 to see the correct location for the clk_core source.

Figure 6-4: Hierarchy View with clk_core Correctly Instantiated

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After making sure that the clk_core IP is instantiated properly, you will now
implement the design to view the clocking resources used by the Clocking
Wizard.

49-46. Implement the design.

50-47-34. Click Run Implementation in the Flow Navigator (under Implementation).
Alternatively, you can select Flow > Run Implementation.

Figure 6-5: Selecting Run Implementation

Note: If needed, click OK to launch synthesis first if prompted.

Notice that the tools run all of the processes required to implement the design. This
means that if the synthesized netlist is not available already, the Vivado Design Suite will
run synthesis before running implementation.
After implementation completes, the Implementation Completed dialog box opens. The
dialog box prompts you to open the implemented design, generate the bitstream, or
view reports.
51-48-35. Click OK again to launch the selected runs.

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52-49-36. Select Open Implemented Design.

Figure 6-6: Implementation Completed Dialog Box

53-50-37. Click OK.

54-51. Use the Utilization report to verify the number of clock resources used.
55-52-38. Click Implemented Design > Report Utilization under Implementation in the
Flow Navigator.
56-53-39. Click OK in the Report Utilization dialog box to accept the default results name.
The utilization report appears at the bottom of the Vivado IDE.
57-54-40. Examine the Utilization report and verify the number of clock resources used.

Question 3
How many MMCMs and global clock buffer resources were used in the finished design?

58-55. Close the implemented design.

59-56. Close the project.

60-57. Close the Vivado Design Suite.

Summary
In this lab you explored a mechanism for accessing FPGA resources. You created the clock core
IP and instantiated it into the design. You also manually instantiated several device primitives in
order to access specific global clocking resources within the FPGA.
The final mechanism of accessing FPGA resources is through inference. This, of course, is the pri-
mary mechanism used. It is used extensively throughout the rest of the wave_gen design.

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Answers
Answers listed represent sample solutions only. Your results may differ depending on the ver-
sion of the software, service pack, or operating system that you are using.

1. Why use the Clocking Wizard to create the core? That is, why not just instantiate the MMCM
primitive?

The Clocking Wizard tool provides an easy-to-use interface for configuring the MMCM
attributes. Additionally, the generated core can include all the required input buffers and
clock buffers. All of these will come in a single core for instantiation.

2. If the core is already created, is the MMCM already connected to the design? Why must the
MMCM core be instantiated into this design?

No, the act of generating a core only creates the core; it is not automatically inserted into
the design. Therefore, you must instantiate it into a module in the design and connect it to
the appropriate nets.

3. How many MMCMs and global clock buffer resources were used in the finished design?
Expand the CLOCK folder to view all the clocking resources used by the design.

KCU105 users:

The design uses one MMCM, which is the one used in clk_core.
Finally, the design uses four BUFGCEs. Three BUFGs are the BUFGs that were created by the
Clocking Wizard. The fourth BUFG is for the clk_samp signal from the clk_gen module MMCM
clock.

KC7xx users:

The design uses one MMCM, which is the one used in clk_core.
Finally, the design uses three BUFGCTRLs. Three BUFGCTRLs are the BUFGs that were created by
the Clocking Wizard, of which the third BUFG is for the MMCM clock feedback. Use BUFHCE for
high fanout non-clock signals (such as a reset) that can be contained in a single clock region.

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