0% found this document useful (0 votes)
15K views4 pages

Arm Based Mcus

ARM is a 32-bit RISC architecture used in many commercial applications like mobile phones, games consoles, and handheld devices. It provides high performance with low power consumption due to its architectural simplicity which allows for small, low-power implementations. The ARM architecture uses a load/store design, uniform 32-bit instructions, and supports features like conditional execution and autoincrement/autodecrement addressing modes. It operates in different privilege modes including user, supervisor, fast interrupt request, and system modes.

Uploaded by

Dragos Craciun
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
15K views4 pages

Arm Based Mcus

ARM is a 32-bit RISC architecture used in many commercial applications like mobile phones, games consoles, and handheld devices. It provides high performance with low power consumption due to its architectural simplicity which allows for small, low-power implementations. The ARM architecture uses a load/store design, uniform 32-bit instructions, and supports features like conditional execution and autoincrement/autodecrement addressing modes. It operates in different privilege modes including user, supervisor, fast interrupt request, and system modes.

Uploaded by

Dragos Craciun
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
You are on page 1/ 4

ARM- Advanced Risc machine

Arm will be used for commercial purpose

Ex: video games, modems, mobile phone, handycams, etc

Features: architectural simplicity, it allow very small implementations=> very low power consumption

RISC-> competitive , easy to develop, cheap compared to CISC

-pointing the way to future

ARM architectural:

Risc architecture-> large uniform registered file

 Load/store arhitectures

 Simple addressing modes

 Uniform and fixed length instruction fields

Enhanced + RISC= ARM

 Each instruction controle the ALU & Shifter

 Autoincrement & autodecrement addressing modes

 Multiple load/store, conditional execution

Results ARM:

-high performance, lost code size

-low power consumption, low silicon area

ARM architecture

-based on Berkeley RISC machine

-fixed length instructions

-pipelines

-load/store architecture

->ARM is a 32-bit architecture

->when used in relation to the ARM

-bytes= 8-bits

-word= 32-bits0

-half word= 16-bits

-> most ARM implements 2 instruction sets


-32 bit ARM instruction set

- 16 bit Thumb instruction set

-> Jazzle instr set used for the concepts that are implemented using Java

ARM Register organization

Used to store info

- In arm, there are 13 general purpose reg(r0-r12)

3 special purpose registers(r13, r14, r15) used to perform specific task

16-reg impartit in general purpose and special purpose

R13- stack pointer

R14- link register

R15- program counter

CPRSR( current program status REG)- 32 bit size

Mode-> total 7 modes can support ARM: user, FIQ, IRQ, Abort mode, supervisor mode, undefined
mode, system

ARM MODES OF OPERATION

 Arm support two types of modes: (is a not) non/privileged mode


(powerful mode, got wide lvl of access permission

ARM poate fi de 32/64 bit risc


Privileged mode- read and write access of CPSR

Non-privileged mode- read acces of CPSR( control field)

User mode

- Non privileged mode

- Most of the task are executed in this mode

- Memory access is restricted

- Hardware device cannot read directly

Fast Interrupt request Mode( FIQ)

-privileged mode

- this mode is a entered whenever high priority intrerrupts is raised

- handle the peripherials that issue fast interrupts. Ex: floppy disc,handling data,serial port

Interrupt mode( IRQ)

-privileged mode

-entered when a low priority interrupt is raised

Ex: keyboard, hard disk, floppy


Supervisor Mode( SVC)

-privileged mode

-additional privileges-> greatear control to the processor

-processor enters this mode on rest

-mode can be entered if a software interrupt is executed

-an Operating system kernel operates

-read i/o module

Undefined mode( Undef)

- Handle undefined instructions

Abort mode

-mode is entered whenever any attempt to access memory fails

System mode

-privileged mode

-special version of user mode

-full read

-version 4

You might also like