a Quad, 12-Bit DAC

Voltage Output with Readback

DAC8412/DAC8413
FEATURES FUNCTIONAL BLOCK DIAGRAM
+5 V to ⴞ15 V Operation VLOGIC VDD VREFH
Unipolar or Bipolar Operation
True Voltage Output DATA
12
I/O INPUT OUTPUT
I/O PORT REG A DAC A VOUTA
Double-Buffered Inputs REG A

Reset to Min (DAC8413) or Center Scale (DAC8412) DGND

INPUT OUTPUT
Fast Bus Access Time REG B REG B DAC B VOUTB
A0
Readback
A1 CONTROL INPUT OUTPUT
REG C REG C DAC C VOUTC
LOGIC
APPLICATIONS R/W
Automatic Test Equipment CS INPUT OUTPUT
REG D REG D DAC D VOUTD
Digitally Controlled Calibration
Servo Controls RESET
Process Control Equipment LDAC

VREFL VSS

GENERAL DESCRIPTION Digital controls allow the user to load or read back data from any
The DAC8412 and DAC8413 are quad, 12-bit voltage output DAC, load any DAC and transfer data to all DACs at one time.
DACs with readback capability. Built using a complementary An active low RESET loads all DAC output registers to mid-
BiCMOS process, these monolithic DACs offer the user very scale for the DAC8412 and zero scale for the DAC8413.
high package density.
The DAC8412/DAC8413 are available in 28-lead plastic DIP,
Output voltage swing is set by the two reference inputs VREFH PLCC and LCC packages. They can be operated from a wide
and VREFL. By setting the VREFL input to 0 V and VREFH to a variety of supply and reference voltages with supplies ranging
positive voltage, the DAC will provide a unipolar positive output from single +5 V to ±15 V, and references from +2.5 V to ± 10 V.
range. A similar configuration with VREFH at 0 V and VREFL at Power dissipation is less than 330 mW with ± 15 V supplies and
a negative voltage will provide a unipolar negative output range. only 60 mW with a +5 V supply.
Bipolar outputs are configured by connecting both VREFH and
VREFL to nonzero voltages. This method of setting output voltage For MIL-STD-883 applications, contact your local ADI sales
range has advantages over other bipolar offsetting methods because office for the DAC8412/DAC8413/883 data sheet which specifies
it is not dependent on internal and external resistors with different operation over the –55°C to +125°C temperature range. All
temperature coefficients. 883 parts are also available on Standard Military Drawings
5962-91 76401MXA through 76404M3A.

0.500

0.375 +125ⴗC

+25ⴗC
0.250
LINEARITY ERROR – LSB

0.125

0
–55ⴗC
–0.125
VDD = +15V
–0.250 VSS = –15V
VREFH = +10V
–0.375 VREFL = –10V
TA = –55ⴗC, +25ⴗC, +125ⴗC
–0.500
0 512 1024 1536 2046 2548 2560 3072 4096
DIGITAL INPUT CODE – Decimal

Figure 1. INL vs. Code Over Temperature

REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
DAC8412/DAC8413–SPECIFICATIONS
(@ V = +15.0 V, V = –15.0 V, V = +5.0 V, VREFH = +10.0 V, VREFL = –10.0 V,
DD SS LOGIC
ELECTRICAL CHARACTERISTICS –40ⴗC ≤ T ≤ +85ⴗC unless otherwise noted. See Note 1 for supply variations.)
A

Parameter Symbol Conditions Min Typ Max Units

Integral Nonlinearity Error INL E Grade 0.25 ± 0.5 LSB
INL F Grade ±1 LSB
Differential Nonlinearity Error DNL Monotonic Over Temperature –1 LSB
Min-Scale Error VZSE RL = 2 kΩ ±2 LSB
Full-Scale Error VFSE RL = 2 kΩ ±2 LSB
Min-Scale Tempco TCVZSE RL = 2 kΩ 15 ppm/°C
Full-Scale Tempco TCVFSE RL = 2 kΩ 20 ppm/°C
Linearity Matching Adjacent DAC Matching ±1 LSB
REFERENCE
Positive Reference Input Voltage Range Note 2 VREFL + 2.5 VDD – 2.5 V
Negative Reference Input Voltage Range Note 2 –10 VREFH – 2.5 V
Reference High Input Current IREFH –2.75 +1.5 +2.75 mA
Reference Low Input Current IREFL 0 +2 +2.75 mA
Large Signal Bandwidth BW –3 dB, VREFH = 0 V to +10 V p-p 160 kHz
AMPLIFIER CHARACTERISTICS
Output Current IOUT RL = 2 kΩ, CL = 100 pF –5 +5 mA
Settling Time tS to 0.01%, 10 V Step, RL = 1 kΩ 10 µs
Slew Rate SR 10% to 90% 2.2 V/µs
Analog Crosstalk 72 dB
LOGIC CHARACTERISTICS
Logic Input High Voltage VINH TA = +25°C 2.4 V
Logic Input Low Voltage VINL TA = +25°C 0.8 V
Logic Output High Voltage VOH IOH = +0.4 mA 2.4 V
Logic Output Low Voltage VOL IOL = –1.6 mA 0.4 V
Logic Input Current IIN 1 µA
Input Capacitance CIN 8 pF
Digital Feedthrough3 VREFH = +2.5 V, VREFL = 0 V 5 nV-s
LOGIC TIMING CHARACTERISTICS 3 Note 4
Chip Select Write Pulsewidth tWCS 80 ns
Write Setup tWS tWCS = 80 ns 0 ns
Write Hold tWH tWCS = 80 ns 0 ns
Address Setup tAS 0 ns
Address Hold tAH 0 ns
Load Setup tLS 70 ns
Load Hold tLH 30 ns
Write Data Setup tWDS tWCS = 80 ns 20 ns
Write Data Hold tWDH tWCS = 80 ns 0 ns
Load Data Pulsewidth tLDW 170 ns
Reset Pulsewidth tRESET 140 ns
Chip Select Read Pulsewidth tRCS 130 ns
Read Data Hold tRDH tRCS = 130 ns 0 ns
Read Data Setup tRDS tRCS = 130 ns 0 ns
Data to Hi Z tDZ CL = 10 pF 200 ns
Chip Select to Data tCSD CL = 100 pF 160 ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSS 14.25 V ≤ VDD ≤ 15.75 V 150 ppm/V
Positive Supply Current IDD VREFH = +2.5 V 8.5 12 mA
Negative Supply Current ISS –10 –6.5 mA
Power Dissipation PDISS 330 mW
NOTES
1
All supplies can be varied ± 5%, and operation is guaranteed. Device is tested with nominal supplies.
2
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
3
All parameters are guaranteed by design.
4
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.

–2– REV. D
 DAC8412/DAC8413
(@ VDD = VLOGIC = +5.0 V ⴞ 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, and VSS = –5.0 V ⴞ 5%,
ELECTRICAL CHARACTERISTICS VREFL = –2.5 V, –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted. See Note 1 for supply variations.)
Parameter Symbol Conditions Min Typ Max Units
Integral Nonlinearity Error INL E Grade 1/2 ±1 LSB
INL F Grade ±2 LSB
INL VSS = 0.0 V; E Grade2 ±2 LSB
INL VSS = 0.0 V; F Grade2 ±4 LSB
Differential Nonlinearity Error DNL Monotonic Over Temperature –1 LSB
Min-Scale Error VZSE VSS = –5.0 V ±4 LSB
Full-Scale Error VFSE VSS = –5.0 V ±4 LSB
Min-Scale Error VZSE VSS = 0.0 V ±8 LSB
Full-Scale Error VFSE VSS = 0.0 V ±8 LSB
Min-Scale Tempco TCVZSE 100 ppm/°C
Full-Scale Tempco TCVFSE 100 ppm/°C
Linearity Matching Adjacent DAC Matching ±1 LSB
REFERENCE
Positive Reference Input Voltage Range Note 3 VREFL + 2.5 VDD – 2.5 V
Negative Reference Input Voltage Range VSS = 0.0 V 0 VREFH – 2.5 V
VSS = –5.0 V –2.5 VREFH – 2.5 V
Reference High Input Current IREFH Code 000H –1.0 +1.0 mA
Large Signal Bandwidth BW –3 dB, VREFH = 0 V to 2.5 V p-p 450 kHz
AMPLIFIER CHARACTERISTICS
Output Current IOUT RL = 2 kΩ, CL = 100 pF –1.25 +1.25 mA
Settling Time tS to 0.01%, 2.5 V Step, RL = 1 kΩ 7 µs
Slew Rate SR 10% to 90% 2.2 V/µs
LOGIC CHARACTERISTICS
Logic Input High Voltage VINH TA = +25°C 2.4 V
Logic Input Low Voltage VINL TA = +25°C 0.8 V
Logic Output High Voltage VOH IOH = +0.4 mA 2.4 V
Logic Output Low Voltage VOL IOL = –1.6 mA 0.45 V
Logic Input Current IIN 1 µA
Input Capacitance CIN 8 pF
LOGIC TIMING CHARACTERISTICS 4 Note 5
Chip Select Write Pulsewidth tWCS 150 ns
Write Setup tWS tWCS = 150 ns 0 ns
Write Hold tWH tWCS = 150 ns 0 ns
Address Setup tAS 0 ns
Address Hold tAH 0 ns
Load Setup tLS 70 ns
Load Hold tLH 50 ns
Write Data Setup tWDS tWCS = 150 ns 20 ns
Write Data Hold tWDH tWCS = 150 ns 0 ns
Load Data Pulsewidth tLDW 180 ns
Reset Pulsewidth tRESET 150 ns
Chip Select Read Pulsewidth tRCS 170 ns
Read Data Hold tRDH tRCS = 170 ns 20 ns
Read Data Setup tRDS tRCS = 170 ns 0 ns
Data to Hi Z tDZ CL = 10 pF 200 ns
Chip Select to Data tCSD CL = 100 pF 320 ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSS 100 ppm/V
Positive Supply Current IDD 7 12 mA
Negative Supply Current ISS VSS = –5.0 V –10 mA
Power Dissipation PDISS VSS = 0 V 60 mW
VSS = –5 V 110 mW
NOTES
1
All supplies can be varied ± 5%, and operation is guaranteed. Device is tested with V DD = +4.75 V.
2
For single supply operation only (V REFL = 0.0 V, VSS = 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002 H).
3
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4
All parameters are guaranteed by design.
5
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
REV. D –3–
DAC8412/DAC8413
t RCS 80ns
CS
CS
t RDS t RDH
tWS tWH
R/W

t AS t AH R/W

A0/A1 tAS
ADDRESS ADDRESS ADDRESS ADDRESS
t DZ ADDRESS
ONE TWO THREE FOUR
DATA HI-Z HI -Z
OUT DATA VALID tLS tLH
t CSD
LDAC
Figure 2. Data Output (Read Timing)
tLDW
tWDS tWDH

t WCS DATA IN DATA1 DATA2 DATA3 DATA4

VALID VALID VALID VALID
CS

t WS t WH Figure 5. Double Buffer Mode

R/W

t AS t AH VDD
VREFH
A0/A1 VREFL

+ + R2 R2 R1
t LH t LDW C1 D1
t LS C1 C1 +
D1
LDAC D1 C2
VREFH VREFL

t WDS t WDH N/C VOUTB VOUTC N/C R3 R3 R3

N/C VOUTA VOUTD N/C C2
DATA IN C2
VSS VDD
t RESET DGND VLOGIC
C2
RESET RESET CS
LDAC A0
Figure 3. Data WRITE (Input and Output Registers) Timing DB0 A1
DB1 R/W
DB2 DB11
80ns R6
DB3 DB10
CS DB9
DB4
R5 R4 R4
tWS tWH R1 DB5 DB8
DB6 DB7 *
R/W ONCE PER PORT

tAS DGND +
D1 C1
ADDRESS ADDRESS ADDRESS ADDRESS VSS
ADDRESS
ONE TWO THREE FOUR
VDD = +15V, VSS = –15V, VREFH = +10V, VREFL = 0V
tLS tLH R1 = 10⍀, R2 = 100⍀, R3 = 5k⍀, R4 = 10k⍀, R5 = 100k⍀,
R6 = 47⍀ FOR LCC, R6 = 100⍀ FOR DIP
C1 = 4.7␮F (ONCE PER PORT), C2 = 0.01␮F (EACH DEVICE)
LDAC D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT)

tWDS tWDH Figure 6. Burn-In Diagram

DATA1 DATA2 DATA3 DATA4
DATA IN
VALID VALID VALID VALID

Figure 4. Single Buffer Mode

–4– REV. D
 DAC8412/DAC8413
ABSOLUTE MAXIMUM RATINGS Thermal Resistance
(TA = +25°C unless otherwise noted)
Package Type ␪JA* ␪JC Units
VSS to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V
VSS to VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V 28-Lead Plastic DIP (P) 48 22 °C/W
VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7.0 V 28-Lead Hermetic Leadless Chip Carrier (TC) 70 28 °C/W
VSS to VREFL . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +VSS–2.0 V 28-Lead Plastic Leaded Chip Carrier (PC) 63 25 °C/W
VREFH to VDD . . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V *θJA is specified for worst-case mounting conditions, i. e., θJA is specified for device
VREFH to VREFL . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, VSS–VDD in socket.
Current into Any Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . ± 15 mA
Digital Input Voltage to DGND . . . . . –0.3 V, VLOGIC +0.3 V
Digital Output Voltage to DGND . . . . . . . . . . –0.3 V, +7.0 V
Operating Temperature Range
ET, FT, EP, FP, FPC . . . . . . . . . . . . . . . . –40°C to +85°C
AT, BT, BTC . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation Package . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C

ORDERING INFORMATION 1, 2

INL Military3 Temperature Extended Industrial3 Temperature Package Package

(LSB) –55ⴗC to +125ⴗC –40ⴗC to +85ⴗC Description Option
±1 DAC8412FPC PLCC P-28A
± 1.5 DAC8412BTC/883 LCC E-28A
0.5 DAC8412EP Plastic DIP N-28
±1 DAC8412FP Plastic DIP N-28
±1 DAC8413FPC PLCC P-28A
± 1.5 DAC8413BTC/883 LCC E-28A
± 0.5 DAC8413EP Plastic DIP N-28
±1 DAC8413FP Plastic DIP N-28
NOTES
1
Die Size 0.225 × 0.165 inches, 37,125 sq. mils (5.715 × 4.191 mm, 23.95 sq. mm). Substrate should be connected to V DD; Transistor Count = 2595.
2
Burn-in is available on extended industrial temperature range parts in cerdip.
3
A complete /883 data sheet is available. For availability and burn-in information, contact your local sales office.

CAUTION
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only; functional operation at or above this specification is not implied.
Exposure to the above maximum rating conditions for extended periods may affect
device reliability. WARNING!
2. Digital inputs and outputs are protected, however, permanent damage may occur on unprotected units
from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until ESD SENSITIVE DEVICE
ready to use. Use proper antistatic handling procedures.
3. Remove power before inserting or removing units from their sockets.
4. Analog outputs are protected from short circuit to ground or either supply.

REV. D –5–
DAC8412/DAC8413
PIN FUNCTION DESCRIPTIONS PIN CONFIGURATIONS

Pin Name Description Plastic DIP

1 VREFH High-Side DAC Reference Input
VREFH 1 28 VREFL
2 VOUTB DAC B Output
VOUTB 2 27 VOUTC
3 VOUTA DAC A Output
VOUTA 3 26 VOUTD
4 VSS Lower-Rail Power Supply VSS 4 25 VDD
5 DGND Digital Ground DGND 5 DAC8412 24 VLOGIC
6 RESET Reset Input and Output Registers to all 0s, RESET 6
DAC8413
23 CS
Enabled at Active Low TOP VIEW
LDAC 7 (NOT TO SCALE)
22 A0
7 LDAC Load Data to DAC, Enabled at Active Low DB0 (LSB) 8 21 A1
8 DB0 Data Bit 0, LSB DB1 9 20 R/W
9 DB1 Data Bit 1 DB2 10 19 DB11 (MSB)

10 DB2 Data Bit 2 DB3 11 18 DB10

11 DB3 Data Bit 3 DB4 12 17 DB9

12 DB4 Data Bit 4 DB5 13 16 DB8

DB6 14 15 DB7
13 DB5 Data Bit 5
14 DB6 Data Bit 6
15 DB7 Data Bit 7
16 DB8 Data Bit 8 PLCC
17 DB9 Data Bit 9

VOUTA

VOUTB

VOUTC

VOUTD
VREFH

VREFL
VSS
18 DB10 Data Bit 10
19 DB11 Data Bit 11, MSB 4 3 2 1 28 27 26

20 R/W Active Low to Write Data to DAC. Active

DGND 5 25 VDD
High to Readback Previous Data at Data Bit
Pins with VLOGIC Connected to +5 V RESET 6 24 VLOGIC

LDAC 7 23 CS
21 A1 Address Bit 1 DAC8412PC
DB0 (LSB) 8 DAC8413PC 22 A0
22 A0 Address Bit 0
DB1 9 21 A1
23 CS Chip Select, Enabled at Active Low
DB2 10 TOP VIEW 20 R/W
24 VLOGIC Voltage Supply for Readback Function. Can DB3 11
(NOT TO SCALE)
19 DB11 (MSB)
be Open Circuit If Not Used
25 VDD Upper-Rail Power Supply 12 13 14 15 16 17 18 DB10
DB4
DB5

DB6

DB7
DB8

DB9

26 VOUTD DAC D Output

27 VOUTC DAC C Output
28 VREFL Low-Side DAC Reference Input
LCC
VOUTA

VOUTB

VOUTC
VOUTD
VREFH
VREFL
VSS

4 3 2 1 28 27 26
DGND 5 25 VDD

RESET 6 24 VLOGIC

LDAC 7 23 CS
DAC8412TC
DB0 (LSB) 8 DAC8413TC 22 A0

DB1 9 21 A1

DB2 10 TOP VIEW 20 R/W

(NOT TO SCALE)
DB3 11 19 DB11 (MSB)
12 13 14 15 16 17 18
DB4
DB5

DB6

DB7
DB8
DB9

DB10

–6– REV. D
 Typical Performance Characteristics– DAC8412/DAC8413
VDD = +5V

MAXIMUM LINEARITY ERROR – LSB

MAXIMUM LINEARITY ERROR – LSB
MAXIMUM LINEARITY ERROR – LSB

VSS = 0V
+2
VREFL = 0V
+1 TA = +25ⴗC 0.3

+1

0 0 0.2

VDD = +15V
VDD = +15V –1
VSS = –15V
–1 VSS = –15V 0.1
VREFL = 0V
VREFL = –10.0V –2 TA = +25ⴗC
TA = +25ⴗC

6 7 8 9 10 11 12 1 2 3 6 8 10 12
VREFH – Volts VREFH – Volts VREFH – Volts

Figure 7. DNL vs. VREFH Figure 8. DNL vs. VREFH Figure 9. INL vs. VREFH

0.4 0.3
VDD = +15V
MAXIMUM LINEARITY ERROR – LSB

VSS = –15V X+3␴

ZERO-SCALE ERROR – LSB

VREFH = +10V 0.1
FULL-SCALE ERROR – LSB

0.2
+1 VREFL = –10V
X
0 –0.1

0
X+3␴ X–3␴
–0.2 –0.3

–1 VDD = +5V X VDD = +15V

VSS = 0V –0.4 –0.5 VSS = –15V
VREFL = 0V VREFH = +10V
TA = +25ⴗC X–3␴ VREFL = –10V
–0.6 –0.7
1 2 3 0 200 400 600 800 1000 0 200 400 600 800 1000
VREFH – Volts T = HOURS OF OPERATION AT +125ⴗC T = HOURS OF OPERATION AT +125ⴗC

Figure 10. INL vs. VREFH Figure 11. Full-Scale Error vs. Figure 12. Zero-Scale Error vs.
Time Accelerated by Burn-In Time Accelerated by Burn-In

0.2 0.3
VDD = +15V VDD = +15V
VSS = –15V VSS = –15V
FULL-SCALE ERROR – LSB

ZERO-SCALE ERROR – LSB

VREFH = +10V VREFH = +10V

0 VREFL = –10V 0.1 VREFL = –10V

DAC A
–0.2 –0.1 DAC C
DAC A DAC D DAC D

DAC B
DAC B
–0.4 –0.3
DAC C

–0.6 –0.5
–75 0 75 150 –75 0 75 150
TEMPERATURE – ⴗC TEMPERATURE – ⴗC

Figure 13. Full-Scale Error vs. Figure 14. Zero-Scale Error vs.
Temperature Temperature

REV. D –7–
DAC8412/DAC8413
0.37500 0.500

0.26125 0.375

0.18750 0.250
LINEARITY ERROR – LSB

LINEARITY ERROR – LSB

0.08375 0.125

0 0

–0.09375 –0.125
VDD = +15V
–0.18750 –0.250 VSS = –15V
VREFH = +10V VREFH = +10V
–0.23125 VREFL = 0V –0.375 VREFL = –10V
TA = +25ⴗC TA = –55ⴗC, +25ⴗC, +125ⴗC
–0.37500 –0.500
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096
DIGITAL INPUT CODE – Decimal DIGITAL INPUT CODE – Decimal

Figure 15. Channel-to-Channel Matching Figure 18. INL vs. Code

(VSUPPLY = ± 15 V)

1.00 2.0
VDD = +15V
VDD = +5.0V VSS = –15V
0.75 VSS = 0V VREFH = +10V
VREFH = +2.5V 1.5 VREFL = –10V
0.50 TA = +25ⴗC TA = +25ⴗC
LINEARITY ERROR – LSB

0.25
1.0
IVREFH – mA

0.5
–0.25

–0.50
0
–0.75

–1.00 –0.5
0 512 1024 1536 2048 2560 3072 3584 4096 0 511 1023 1535 2047 2559 3071 3583 4095
DIGITAL INPUT CODE – Decimal DIGITAL INPUT CODE – Decimal

Figure 16. Channel-to-Channel Matching Figure 19. IVREFH vs. Code

(VSUPPLY = +5 V/GND)

13
VDD = +15V
VSS = –15V
VREFL = –10V

10
IDD – mA

4
–7 –3 1 5 9 13
VREFH – Volts

Figure 17. IDD vs. VREFH All DACs High

–8– REV. D
 DAC8412/DAC8413
32.5mV 15.5mV 10V
VDD = +15V
+5V 0
INPUT VSS = –15V
INPUT
0 –5V VREFH = +10V
VREFL = –10V
TA = +25ⴗC
1V/ VDD = +15V
5mV/DIV 1 LSB ERROR BAND 2mV/DIV DIV
V VSS = –15V
5 5 V EA
VREFH = +10V
DIV DIV
VREFL = –10V
TRIG'D TRIG'D TRIG'D TA = +25ⴗC
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = +25ⴗC
–17.5mV –4.5mV 0V
–1.96␮s 2␮s/DIV 18.04␮s –1.96␮s 2␮s/DIV 18.04␮s –580ns 1␮s/DIV 9.42␮s

Figure 20. Settling Time (Positive) Figure 21. Settling Time (Negative) Figure 22. Positive Slew Rate

10V 1.0 12
VDD = +15V VDD = +15V
VSS = –15V VSS = –15V
0.8 10
VREFH = +10V VREFH = +10V

FULL SCALE VOLTAGE – V

VREFL = –10V VREFL = –10V
0.6 TA = +25ⴗC 8 TA = +25ⴗC
1V/ VDD = +15V
INL – LSB

DIV
VSS = –15V
EA 0.4 6
VREFH = +10V
VREFL = –10V
TRIG'D TA = +25ⴗC
0.2 4

0.0 2

0V –0.2 0
–580ns 1␮s/DIV 9.42␮s 0.01 0.10 1.00 10.0 100 0.01 0.10 1.00 10.0 100
LOAD RESISTANCE – K⍀ LOAD RESISTANCE – K⍀

Figure 23. Negative Slew Rate Figure 24. DAC 8412 INL vs. Load Figure 25. DAC 8412 Output Swing
Resistance vs. Load Resistance

10 100

+PSRR
POWER SUPPLY REJECTION – dB
POWER SUPPLY CURRENT – mA

6 IDD 80
VDD = +15V
0 VSS = –15V –PSRR
–10 2 60
GAIN – dB

+PSRR:
VDD = +15V VDD = +15Vⴞ1Vp
–30 –2 40
VSS = –15V VSS = –15V
VREFH = 0 ⴞ100mV –PSRR:
VREFL = –10V ISS VDD = +15V
–50 –6 20 VSS = –15Vⴞ1V
DATA BITS = +5V
200mV p-p VREFH = 10V
ALL DATA 0
–10 0
0 10 100 1k 10k 100k 1M 10M –75 0 75 150 10 100 1k 10k 100k 1M
FREQUENCY – Hz TEMPERATURE – ⴗC FREQUENCY – Hz

Figure 26. Small Signal Response Figure 27. Power Supply Current vs. Figure 28. PSRR vs. Frequency
Temperature

REV. D –9–
DAC8412/DAC8413
10.0 0
VDD = +15V
VDD = +15V
VSS = –15V 30
VSS = –15V
VREFH = +10V +ISC
VREFH = +10V
1.00 VREFL = –10V 20
NOISE DENSITY – ␮V

VREFL = –10V CH1 MEAN

TA = +25ⴗC
TA = +25ⴗC 66.19␮V
10
DATA = 000H

IOUT – mA
1 VDD = +15V
0.10 VSS = –15V
0
VREFH = +10V
VREFL = –10V
–10
TA = +25ⴗC
–ISC
0.01 –20

–30
20uV/DIV M 200␮s A CH1 12.9mV
0.001 0
1 10 100 1000 10000 –25 –20 –15 –10 –5 0 5 10 15 20 25
NOISE FREQUENCY – Hz VOUT – Volts

Figure 29. DAC8412 Noise Figure 30. IOUT vs. VOUT Figure 31. Broadband Noise
Frequency vs. Noise Density

25 10␮s
VDD = +15V +ISC
20
VSS = 0V 1V 4␮s
15 VREFH = +10V
VREFL = 0V GLITCH AT DAC OUTPUT
10 TA = +25ⴗC
DATA = 800H
5
IOUT – mA

0
2
–5

–10
1
–15 –ISC
DEGLITCHER OUTPUT
–20 1V

–25 CH2 1.86V

–6 –4 –2 0 2 4 6
VOUT – Volts

Figure 32. IOUT vs. VOUT Figure 33. Glitch and Deglitched Results

OPERATION precision instrumentation control, a deglitcher circuit can be

Introduction implemented with a standard sample-and-hold circuit. (See
The DAC8412 and DAC8413 are quad, voltage output, 12-bit Figure 34.) When CS is enabled by synchronizing the hold
parallel input DACs featuring a 12-bit data bus with readback period to be longer than the glitch tradition, the output voltage
capability. The only differences between the DAC8412 and can be smoothed with minimum disturbance. A quad sample-
DAC8413 are the reset functions. The DAC8412 resets to mid- and-hold amplifier, SMP04, has been used to illustrate the
scale (code 800H) and the DAC8413 resets to minimum scale deglitching result. (See Figure 33.)
(code 000H).
The ability to operate from a single +5 V supply is a unique fea- DACOUT
DACOUT'
ture of these DACs.
S/H
Operation of the DAC8412 and DAC8413 can be viewed by
dividing the system into three separate functional groups: the
digital I/O and logic, the digital to analog converters and the output
amplifiers. DACOUT

DACs
Each DAC is a voltage switched, high impedance (R = 50 kΩ), CS

R-2R ladder configuration. Each 2R resistor is driven by a pair of

switches that connect the resistor to either VREFH or VREFL. S/H H S H S

Glitch
DACOUT'
Worst-case glitch occurs at the transition between half-scale
digital code 1000 0000 0000 to half-scale minus 1 LSB, 0111
1111 1111. It can be measured at about 2 V µs. (See Figure 33.) Figure 34. Deglitcher Circuit
For demanding applications such as waveform generation or

–10– REV. D
 DAC8412/DAC8413
Reference Inputs The R/W input, when enabled by CS, controls the writing to and
All four DACs share common reference high (VREFH) and refer- reading from the input register.
ence low (VREFL) inputs. The voltages applied to these reference Coding
inputs set the output high and low voltage limits of all four of Both the DAC8412 and DAC8413 use binary coding. The out-
the DACs. Each reference input has voltage restrictions with put voltage can be calculated by:
respect to the other reference and to the power supplies. The
VREFL can be set at any voltage between VSS and VREFH – 2.5 V, (VREF H _ VREFL ) × N
VOUT = VREFL +
and VREFH can be set to any value between +VDD – 2.5 V and 4096
VREFL + 2.5 V. Note that because of these restrictions the
where N is the digital code in decimal.
DAC8412 references cannot be inverted (i.e., VREFL cannot be
greater than VREFH).
RESET
It is important to note that the DAC8412’s VREFH input both The RESET function can be used either at power-up or at any
sinks and sources current. Also the input current of both VREFH time during the DAC’s operation. The RESET function is inde-
and VREFL are code dependent. Many references have limited pendent of CS. This pin is active LOW and sets the DAC output
current sinking capability and must be buffered with an ampli- registers to either center code for the DAC8412, or zero code
fier to drive VREFH. The VREFL has no such special requirements. for the DAC8413. The reset to center code is most useful when
It is recommended that the reference inputs be bypassed with the DAC is configured for bipolar references and an output of
0.2 µF capacitors when operating with ± 10 V references. This zero volts after reset is desired.
limits the reference bandwidth. Supplies
Digital I/O Supplies required are VSS, VDD and VLOGIC. The VSS supply can
See Table I for digital control logic truth table. Digital I/O consists be set between –15 V and 0 V. VDD is the positive supply; its op-
of a 12-bit bidirectional data bus, two registers select inputs, A0 erating range is between +5 V and +15 V.
and A1, a R/W input, a RESET input, a Chip Select (CS), and VLOGIC is the digital output supply voltage for the readback
a Load DAC (LDAC) input. Control of the DACs and bus function. It is normally connected to +5 V. This pin is a logic
direction is determined by these inputs as shown in Table I. reference input only. It does not supply current to the device.
Digital data bits are labeled with the MSB defined as data bit If you are not using the readback function, VLOGIC can be left open-
“11” and the LSB as data bit “0.” All digital pins are TTL/ circuit. While VLOGIC does not supply current to the DAC8412,
CMOS compatible. it does supply currents to the digital outputs when readback
See Figure 35 for a simplified I/O logic diagram. The register is used.
select inputs A0 and A1 select individual DAC registers “A” Amplifiers
(binary code 00) through “D” (binary code 11). Decoding of Unlike many voltage output DACs, the DAC8412 features buff-
the registers is enabled by the CS input. When CS is high no ered voltage outputs. Each output is capable of both sourcing
decoding takes place, and neither the writing nor the reading of and sinking 5 mA at ± 10 volts, eliminating the need for external
the input registers is enabled. The loading of the second bank of amplifiers when driving 500 pF or smaller capacitive load in
registers is controlled by the asynchronous LDAC input. By tak- most applications. These amplifiers are short-circuit protected.
ing LDAC low while CS is enabled, all output registers can be
updated simultaneously. Note that the tLDW required pulsewidth
for updating all DACs is a minimum of 170 ns.

Table I. DAC8412/DAC8413 Logic Table

A1 A0 R/W CS RS LDAC INPUT REG OUTPUT REG MODE DAC

L L L L H L WRITE WRITE Transparent A
L H L L H L WRITE WRITE Transparent B
H L L L H L WRITE WRITE Transparent C
H H L L H L WRITE WRITE Transparent D
L L L L H H WRITE HOLD WRITE INPUT A
L H L L H H WRITE HOLD WRITE INPUT B
H L L L H H WRITE HOLD WRITE INPUT C
H H L L H H WRITE HOLD WRITE INPUT D
L L H L H H READ HOLD READ INPUT A
L H H L H H READ HOLD READ INPUT B
H L H L H H READ HOLD READ INPUT C
H H H L H H READ HOLD READ INPUT D
X X X H H L HOLD Update all output registers All
X X X H H H HOLD HOLD HOLD All
X X X X L X *All registers reset to mid/zero-scale All
X X X H g X *All registers latched to mid/zero-scale All
*DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don’t Care. Input and Output registers are transparent when
asserted.

REV. D –11–
DAC8412/DAC8413
VREFH VDD VSS

RDDACA WRDB0
CS
DAC A
WRDB1 VOUTA
WRDACA
WRDB2

WRDB3
A0 RDDACB
WRDB4 DAC B
OUTPUT VOUTB
WRDACB WRDB5 REGISTER
INPUT
A1 REGISTER WRDB6
RDDACC
WRDB7
DAC C
WRDB8 VOUTC
WRDACC
R/W
WRDB9
RDDACD WRDB10
DAC D
WRDB11 VOUTD
WRDACD

DB11..DB0 VREFL
VLOGIC
LDAC
RESET

READOUTBAR

READBACKDATAIN_DB11 READBACKDATAIN_DB10

READBACK
DATAOUT_DB11

READOUT

DGND
Figure 35. Simplified I/O Logic Diagram

Careful attention to grounding is important to accurate opera- +15V

tion of the DAC8412. This is not because the DAC8412 is 39k⍀
more sensitive than other 12-bit DACs, but because with four +15V
outputs and two references there is greater potential for ground
loops. Since the DAC8412 has no analog ground, the ground VDD
must be specified with respect to the reference. BALANCE
6.2⍀
VREFH
100k⍀
Reference Configurations 0.2␮F
AD688 FOR ⴞ10V DAC8412
Output voltage ranges can be configured as either unipolar or AD588 FOR ⴞ 5V OR 0.1␮F
bipolar, and within these choices a wide variety of options exists. GAIN DAC8413 //10␮F
100k⍀
The unipolar configuration can be either positive or negative 6.2⍀
voltage output, and the bipolar configuration can be either sym- VREFL

metrical or nonsymmetrical. 0.2␮F

VSS

+15V 1␮F
+15V –15V
+ ⴞ5 OR ⴞ10V OPERATION

INPUT OP-400
OP400
VREFH VDD Figure 37. Symmetrical Bipolar Operation
OUTPUT
0.2␮F
DAC8412
Figure 37 (Symmetrical Bipolar Operation) shows the DAC8412
REF10
TRIM OR 0.1␮F configured for ± 10 V operation. Note: See the AD688 data
DAC8413 //10␮F
10k⍀ sheet for a full explanation of reference operation. Adjustments may
VREFL not be required for many applications since the AD688 is a very
VSS high accuracy reference. However if additional adjustments are
+10V OPERATION
required, adjust the DAC8412 full scale first. Begin by loading
the digital full-scale code (FFFH), and then adjust the Gain
–15V
Adjust potentiometer to attain a DAC output voltage of 9.9976 V.
Figure 36. Unipolar +10 V Operation Then, adjust the Balance Adjust to set the center scale output
voltage to 0.000 V.

–12– REV. D
 DAC8412/DAC8413
The 0.2 µF bypass capacitors shown at the reference inputs Figure 38 shows the DAC8412 configured for –10 V to 0 V
in Figure 37 should be used whenever ± 10 V references are operation. A REF08 with a –10 V output is connected directly
used. Applications with single references or references to ± 5 V to VREFL for the reference voltage.
may not require the 0.2 µF bypassing. The 6.2 Ω resistor in series Single +5 V Supply Operation
with the output of the reference amplifier is to keep the amplifier For operation with a +5 V supply, the reference voltage should be
from oscillating with the capacitive load. We have found that this is set between 1.0 V and +2.5 V for optimum linearity. Figure
large enough to stabilize this circuit. Larger resistor values are 39 shows a REF43 used to supply a +2.5 V reference voltage.
acceptable, provided that the drop across the resistor doesn’t The headroom of the reference and DAC are both sufficient to
exceed a VBE. Assuming a minimum VBE of 0.6 V and a maxi- support a +5 V supply with ± 5% tolerance. VDD and VLOGIC
mum current of 2.75 mA, then the resistor should be under should be connected to the same supply. Separate bypassing
200 Ω for the loading of a single DAC8412. to each pin should also be used.
Using two separate references is not recommended. Having two
references could cause different drifts with time and tempera- +5V
ture; whereas with a single reference, most drifts will track.
10␮F 0.01␮F
Unipolar positive full-scale operation can usually be set with a
reference with the correct output voltage. This is preferable to INPUT
VDD
using a reference and dividing down to the required value. For a OUTPUT VREFH
10 V full-scale output, the circuit can be configured as shown REF43 0.2␮F DAC8412
in Figure 38. In this configuration the full-scale value is set first TRIM
10k⍀
OR 0.1␮F
DAC8413 //10␮F
by adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.
GND VREFL
10k⍀
VSS

VREFH VDD ZERO TO +2.5V OPERATION

TRIM SINGLE +5V SUPPLY

OUTPUT DAC8412
REF08 0.1␮F
GND
0.2␮F
OR //10␮F Figure 39. +5 V Single Supply Operation
DAC8413
VREFL
0.01␮F
VSS
10␮F
ZERO TO –10V OPERATION
–15V

Figure 38. Unipolar –10 V Operation

REV. D –13–
DAC8412/DAC8413
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

28-Position Leadless Chip Carrier

(TC Suffix)

C1544a–2–3/00 (rev. D)
0.300 (7.62)
0.075 BSC
0.458 (11.63) 0.100 (2.54)
(1.91) 0.150
0.442 (11.23) 0.064 (1.63) REF (3.51) 0.015 (0.38)
SQ BSC MIN
0.095 (2.41) 26 4
0.075 (1.90) 25 28 5
0.028 (0.71)
1
0.458 0.022 (0.56)
TOP (11.63) 0.011 (0.28) BOTTOM
VIEW MAX 0.007 (0.18) VIEW 0.050
SQ R TYP (1.27)
BSC
0.075 19 11
(1.91) 18 12
REF 45ⴗ TYP
0.200
0.088 (2.24) 0.055 (1.40) (5.08)
0.054 (1.37) 0.045 (1.14) BSC

28-Lead PLCC (P-28A)

(PC Suffix)
0.180 (4.57)
0.048 (1.21) 0.165 (4.19)
0.042 (1.07) 0.056 (1.42) 0.025 (0.63)
0.042 (1.07) 0.015 (0.38)
0.048 (1.21)
4 26
0.042 (1.07) 5 PIN 1 25 0.021 (0.53)
IDENTIFIER
0.013 (0.33)
0.050 0.430 (10.92)
TOP VIEW
(PINS DOWN) (1.27) 0.390 (9.91)
BSC 0.032 (0.81)
11 19
0.026 (0.66)
12 18
0.020 0.040 (1.01)
(0.50) 0.456 (11.58)
SQ 0.025 (0.64)
R 0.450 (11.43)
0.495 (12.57) 0.110 (2.79)
SQ 0.085 (2.16)
0.485 (12.32)

28-Lead Epoxy DIP (N-28)

(P Suffix)
1.565 (39.70)
1.380 (35.10)
28 15

0.580 (14.73)
0.485 (12.32)
1 14

PIN 1
PRINTED IN U.S.A.
0.060 (1.52) 0.625 (15.87)
0.015 (0.38) 0.600 (15.24)
0.250 0.195 (4.95)
(6.35) 0.125 (3.18)
MAX 0.150
(3.81)
MIN
0.200 (5.05) 0.015 (0.381)
0.022 (0.558) 0.100 0.070 SEATING
0.125 (3.18) (2.54) (1.77) PLANE 0.008 (0.204)
0.014 (0.356)
BSC MAX

–14– REV. D