Module 3 VLSI Design (18EC72)

Module 5
SYLLABUS:
Semiconductor Memories: Introduction, Dynamic Random Access Memory (DRAM) and
Static Random Access Memory (SRAM), (10.1 to 10.3 of TEXT 1)
Testing and Verification: Introduction, Logic Verification Principles, Manufacturing Test
Principles, Design for testability (15.1, 15.3, 15.5 15.6.1 to 15.6.3 of TEXT 2).

Table of Contents
5.1. Semiconductor Memories - Introduction ........................................................................... 2
5.2. Dynamic Read-Write Memory (DRAM) Circuits .............................................................. 4
5.2.1. Three-Transistor DRAM Cell...................................................................................................... 5
5.2.1.1. Write "1" operation ........................................................................................................... 6
5.2.1.2. Read "1" operation ............................................................................................................ 7
5.2.1.3. Write "0" operation ........................................................................................................... 8
5.2.1.4. Read "0" operation ............................................................................................................ 8
5.2.2. One-Transistor DRAM Cell ........................................................................................................ 8
5.2.2.1. Write Operation: ................................................................................................................ 9
5.2.2.2. Read Operation: ................................................................................................................. 9
5.3. Static Read-Write Memory (SRAM) Circuits .................................................................... 9
5.3.1. Full CMOS SRAM Cell .............................................................................................................. 10
5.3.1.1. Read “0” operation: ......................................................................................................... 11
5.3.1.2. Write “0” operation: ........................................................................................................ 12
5.4. Testing and Verification – Introduction ............................................................................ 13
5.5. Logic Verification Principles ............................................................................................ 15
5.6. Manufacturing Test Principles .......................................................................................... 16
5.6.1. Fault Models ........................................................................................................................... 16
5.6.1.1. Stuck-At Faults ................................................................................................................. 16
5.6.1.2. Short-Circuit and Open-Circuit Faults .............................................................................. 17
5.6.2. Observability ........................................................................................................................... 17
5.6.3. Controllability.......................................................................................................................... 18
5.6.4. Fault Coverage ........................................................................................................................ 18
5.6.5. Automatic Test Pattern Generation (ATPG)............................................................................ 18

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5.6.6. Delay Fault Testing .................................................................................................................. 19

5.7. Design for Testability ....................................................................................................... 19
5.7.1. Ad Hoc Testing ........................................................................................................................ 20
5.7.2. Scan Design ............................................................................................................................. 20
5.7.3. Built-In Self-Test (BIST)............................................................................................................ 22
5.8. Question Bank ................................................................................................................... 24

TEXT, REFERENCE & ADDITIONAL REFERENCE BOOKS

Book Title/Authors/Publication /Web links/Channel

“CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang &
T-1.
Yosuf Leblebici, Third Edition, Tata McGraw-Hill.

“CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste,

T-2.
and David Money Harris4th Edition, Pearson Education.

5.1. Semiconductor Memories - Introduction

Semiconductor memory arrays capable of storing large quantities of digital information are essential
to all digital systems.
• The area efficiency of the memory array, i.e., the number of stored data bits per unit area, is one
of the key design criteria that determine the overall storage capacity and, hence, the memory cost
per bit.
• Another important issue is the memory access time, i.e., the time required to store and/or retrieve
a particular data bit in the memory array, which determines the memory speed.
• Finally, the static and dynamic power consumption of the memory array is a significant factor to
be considered in the design.
Memory circuits are generally classified as:
• Read-Only Memory (ROM) that allow only the retrieval of previously stored data and do not
permit modifications of the stored information contents during normal operation. ROMs are non-
volatile memories, i.e., the data storage function is not lost even when the power supply voltage is
off. Depending on the type of data storage (data write) method, ROMs are classified as mask-
programmed ROMs, Programmable ROMs (PROM), Erasable PROMs (EPROM), and
Electrically Erasable PROMs (EEPROM).

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Fig 5.1. Overview of semiconductor memory types

• Read-write (R/W) memory circuits, permit the modification (writing) of data bits stored in the
memory array, as well as their retrieval (reading) on demand. This requires that the data storage
function be volatile, i.e., the stored data are lost when the power supply voltage is turned off. The
read-write memory circuit is commonly called Random Access Memory (RAM), as any cell in
the R/W memory array can be accessed with nearly equal access time. Based on the operation
type of individual data storage cells, RAMs are classified into two main categories: Static RAMs
(SRAM) and Dynamic RAMs (DRAM).
Fig 5.1 shows an overview of the different memory types and their classifications.
A typical memory array organization is shown in Fig. 5.2. The data storage structure, or core, consists
of individual memory cells arranged in an array of horizontal rows and vertical columns. Each cell is
capable of storing one bit of binary information. Also, each memory cell shares a common connection
with the other cells in the same row, and another common connection with the other cells in the same
column. In this structure, there are 2N rows, also called word lines, and 2M columns, also called bit
lines. Thus, the total number of memory cells in this array is 2N x 2M.

Fig 5.2. Typical random-access memory array organization.

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To access a particular memory cell, i.e., a particular data bit in this array, the corresponding
bit line and the corresponding word line must be activated (selected). The row and column
selection operations are accomplished by row and column decoders, respectively. The row
decoder circuit selects one out of 2N word lines according to an N-bit row address, while the
column decoder circuit selects one out of 2M bit lines according to an M-bit column address.
Once a memory cell or a group of memory cells are selected in this fashion, a data read
and/or a data write operation may be performed on the selected single bit or multiple bits on a
particular row. The column decoder circuit serves the double duties of selecting the particular
columns and routing the corresponding data content in a selected row to the output.

5.2. Dynamic Read-Write Memory (DRAM) Circuits

In a dynamic RAM cell, binary data is stored simply as charge in a capacitor, where the
presence or absence of stored charge determines the value of the stored bit. The data stored as
charge in a capacitor cannot be retained indefinitely, because the leakage currents eventually
remove or modify the stored charge. Thus, all dynamic memory cells require a periodic
refreshing of the stored data, so that unwanted modifications due to leakage are prevented
before they occur.
Unlike SRAM cell, the DRAM cell access circuitry is very simple but it also requires access
devices, for "read" and "write" operations. In addition, it also requires additional peripheral
circuitry for scheduling and performing the periodic data refresh operations. The hardware
overhead of the refresh circuitry, however, does not overshadow the area advantages gained
by the small cell size.
Fig 5.3 shows the historical evolution of the DRAM cell. The four-transistor cell shown in
Fig. 5.3(a) is the simplest dynamic memory cells. The cell has two storage nodes, i.e., the
parasitic oxide and diffusion capacitances. Since no current path is provided to the storage
nodes for restoring the charge being lost to leakage, the cell must be refreshed periodically.
The three-transistor DRAM cell shown in Fig. 5.3(b) utilizes a single transistor as the storage
device and one transistor each for the "read" and "write" access switches. The cell has two
control and two I/O lines. Its separate read and write select lines make it relatively fast, but
the four lines with their additional contacts tend to increase the cell area.
The one-transistor DRAM cell shown in Fig. 5.3(c) is widely used dynamic RAM cell in
high-density DRAM arrays. With only one transistor and one capacitor, it has the lowest

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component count and, hence, the smallest silicon area of all the dynamic memory cells. The
cell has one read-write control line (word line) and one I/O line (bit line).

Fig 5.3. Various configurations of the dynamic RAM cell. (a) Four-transistor DRAM cell
with two storage nodes. (b) Three-transistor DRAM cell with two bit lines and two word lines. (c)
One-transistor DRAM cell with one bit line and one word line.
5.2.1. Three-Transistor DRAM Cell
The circuit diagram of a typical three-transistor dynamic RAM cell is shown in Fig. 5.4 as
well as the column pull-up (precharge) transistors and the column read/write circuitry. Here,
the binary information is stored in the form of charge in the parasitic node capacitance Cl.
The storage transistor M2 is turned on or off depending on the charge stored in C1, and the
pass transistors Ml and M3 act as access switches for data read and write operations. The cell
has two separate bit lines for "data read" and "data write," and two separate word lines to
control the access transistors.
The operation of the three-transistor DRAM cell and its peripheral circuitry is based on a
two-phase non-overlapping clock scheme. The precharge events are driven by 𝞥1, whereas

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the "read" and "write" events are driven by 𝞥2. Every "data read" and "data write" operation
is preceded by a precharge cycle, which is initiated with the precharge signal PC going high.
During the precharge cycle, the column pull-up transistors are activated, and the
corresponding column capacitances C2 and C3 are charged up to logic-high level. All "data
read" and "data write" operations are performed during the active 𝞥2 phase, i.e., when PC is
low.

Fig 5.4 Three-transistor DRAM cell with the pull-up and read/write circuitry.
Fig 5.5 depicts the typical voltage waveforms associated with the 3-T DRAM cell during a
sequence of four consecutive operations: write " 1," read "1," write "0," and read "0." The
four precharge cycles shown in Fig. 5.4 are numbered 1, 3,5, and 7, respectively. During this,
the two column capacitances C2 and C3 are charged. These capacitances are larger than the
internal storage capacitance C1.
5.2.1.1. Write "1" operation
✓ For the write "1" operation, ̅̅̅̅̅̅̅̅
𝐷𝐴𝑇𝐴 is at the logic ‘0’, because the data to be written onto
the DRAM cell is logic "1." Consequently, the "data write" transistor is turned off, and
the voltage level on column Din remains high.
✓ Now the "write select" signal WS is pulled high during the active phase of 𝞥2. As a
result, the write access transistor Ml is turned on.

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✓ With Ml conducting, the charge on C2 is now shared with Cl. Since the capacitance C2 is
very large compared to C1, the storage node capacitance Cl attains approximately the
same logic-high level as the column capacitance C2 at the end of the charge-sharing
process.
5.2.1.2. Read "1" operation
✓ After the write "1" operation is completed, the write access transistor MI is turned off.
With the storage capacitance C1 charged-up to a logic-high level, transistor M2 is now
conducting.
✓ In order to read this stored "1," the "read select" signal RS must be pulled high during the
active phase of 𝞥2, following a precharge cycle.
✓ As the read access transistor M3 turns on, M2 and M3 create a conducting path between
the "data read" column capacitance C3 and the ground.
✓ The capacitance C3 discharges through M2 and M3, and the falling column voltage is
interpreted by the "data read" circuitry as a stored logic "1."

Fig 5.5 Typical voltage waveforms associated with the 3-T DRAM cell during four
consecutive operations: write "1," read "1," write "0," and read "O."’

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5.2.1.3. Write "0" operation

̅̅̅̅̅̅̅̅ is at the logic “1”, because the data to be written onto
✓ For the write "0" operation, 𝐷𝐴𝑇𝐴
the DRAM cell is a logic "0." Consequently, the data write transistor is turned on, and the
voltage level on column Din is pulled to logic "0."
✓ Now, the "write select" signal WS is pulled high during the active phase of 𝞥2. As a
result, the write access transistor Ml is turned on. The voltage level on C2, as well as that
on the storage node Cl, is pulled to logic "0" through MI and the data write transistor.
✓ Thus, at the end of the write "0" sequence, the storage capacitance C1 contains a very low
charge, and the transistor M2 is turned off since its gate voltage is approximately equal to
zero.
5.2.1.4. Read "0" operation
✓ In order to read this stored "0," the "read select" signal RS must be pulled high during the
active phase of 𝞥2, following a precharge cycle. The read access transistor M3 turns on,
but since M2 is off, there is no conducting path between the column capacitance C3 and
the ground.
✓ Consequently, C3 does not discharge, and the logic-high level on the Dout column is
interpreted by the data read circuitry as a stored "0" bit.

5.2.2. One-Transistor DRAM Cell

The one-transistor (1-T) DRAM cell consists of one storage capacitor and one access
transistor is shown in Fig. 5.6. Cl represents the storage capacitor and C2 represents the much
larger parasitic column capacitance. Binary data are stored as the presence or absence of
charge in the storage capacitor.

Fig 5.6. (a) Typical one-transistor (1-T) DRAM cell with its access lines

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5.2.2.1. Write Operation:

✓ For the write "1" operation, the bit line (D) is raised to logic " 1 " by the write circuitry,
while the selected word line is pulled high by the row address decoder.
✓ The access transistor Ml turns on, allowing the storage capacitor C to charge up to a
logic-high level.
✓ For the write "0" operation, the bit line (D) is pulled to logic "0" and the word line is
pulled high by the row address decoder.
✓ In this case, the storage capacitor C discharges through the' access transistor, resulting in
a stored "0" bit.
5.2.2.2. Read Operation:
✓ In order to read stored data out of a 1T DRAM cell, on the other hand, we have to
build a fairly elaborate read-refresh circuit. The reason for this is the fact that the "data
read" operation on the one-transistor DRAM cell is by necessity a "destructive readout."
This means that the stored data must be destroyed or lost during the read operation.
✓ The read operation starts with precharging the column capacitance C.
✓ Then, 'the word line is pulled high in order to activate the access transistor Ml.
✓ Charge sharing between C1 and C2 occurs and, depending on the amount of stored charge
on C1, the column voltage either increases or decreases slightly.
✓ This charge sharing inevitably destroys the stored charge on C1. Hence, we also have to
refresh data every time we perform a "data read" operation.

5.3. Static Read-Write Memory (SRAM) Circuits

The memory circuit is said to be static if the stored data can be retained indefinitely (as long
as a sufficient power supply voltage is provided), without any need for a periodic refresh
operation.
The 1-bit memory cell in static RAM arrays, consists of a simple latch circuit with two stable
operating points (states). The states of the two-inverter latch circuit, is interpreted either as a
logic "0" or as a logic " 1." To access (read and write) the data contained in the memory cell
via the bit line, one switch each controlled by the corresponding word line is used. (Fig.
5.7(a)).
Fig 5.7(b) shows the generic structure of the MOS static RAM cell, consisting of two cross-
coupled inverters and two access transistors. The load devices may be polysilicon resistors
(Fig. 5.7(c)), depletion-type nMOS transistors, or pMOS transistors, depending on the type of

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the memory cell. The pass gates acting as data access switches are enhancement-type nMOS
transistors.
The six-transistor depletion-load nMOS SRAM cell shown in Fig. 5.6(d) can be easily implemented
with one polysilicon and one metal layer, and the cell size tends to be relatively small, especially with
the use of buried metal-diffusion contacts.
The full CMOS SRAM cell shown in Fig. 5.6(e) achieves the lowest static power dissipation among
the various circuit configurations.

Fig 5.7. Various configurations of the static RAM cell. (a) Symbolic representation of the
two-inverter latch circuit with access switches. (b) Generic circuit topology of the MOS static
RAM cell. (c) Resistive-load SRAM cell. (d) Depletion-load nMOS SRAM cell. (e) Full CMOS
SRAM cell.

5.3.1. Full CMOS SRAM Cell

The circuit structure of the full CMOS static RAM cell is shown in Fig. 5.8, along with the
pMOS column pull-up transistors on the complementary bit lines. The memory cell consists
of a simple CMOS latch and two complementary access transistors (M3 and M4). The cell
will preserve one of its two possible stable states, as long as the power supply is available.
The access transistors are turned on whenever a word line is activated for read or write
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operation, connecting the cell to the complementary bit-line columns. The most important
advantage of this circuit topology is that the static power dissipation is even smaller;
essentially, it is limited by the leakage current of the pMOS transistors.

Fig 5.8. Circuit topology of the CMOS SRAM cell.

CMOS SRAM Cell Design Strategy

5.3.1.1. Read “0” operation:

Consider the data read operation first, assuming that a logic "0" is stored in the cell. The
voltage levels in the CMOS SRAM cell at the beginning of the "read" operation are depicted
in Fig. 5.9. Here, the transistors M2 and M5 are turned off, while the transistors Ml and M6

Fig 5.9. Voltage levels in the SRAM cell at the beginning of the "read" operation

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in the linear mode. Thus, the internal node voltages are V1 = 0 and V2 = VDD before the cell
access (or pass) transistors M3 and M4 are turned on.
After the pass transistors M3 and M4 are turned on by the row selection circuitry, the voltage
level of column C’ will not show any significant variation since no current will flow through
M4. On the other half of the cell, however, M3 and Ml will conduct a nonzero current and the
voltage level of column C will begin to drop slightly. The data read circuitry is responsible
for detecting this small voltage drop and amplifying it as a stored "0. "
5.3.1.2. Write “0” operation:
Consider the write "0" operation, assuming that a logic "1" is stored in the SRAM cell
initially. Fig 5.10 shows the voltage levels in the CMOS SRAM cell at the beginning of the
data-write operation. The transistors M1 and M6 are turned off, while the transistors M2 and
M5 operate in the linear mode. Thus, the internal node voltages are V = VDD and V2= 0 V
before the cell access (or pass) transistors M3 and M4 are turned on.

Fig 5.10 Voltage levels in the SRAM cell at the beginning of the "write" operation.

The column voltage VC is forced to logic "0" level by the data-write circuitry. Once the pass
transistors M3 and M4 are turned on by the row selection circuitry, the node voltage V2
remains below the threshold voltage of Ml, since M2 and M4 are designed accordingly.
Consequently, the voltage level at node (2) would not be sufficient to turn on Ml. To change
the stored information, i.e., to force V1 to 0 V and V2 to VDD, the node voltage V1 must be
reduced below the threshold voltage of M2, so that M2 turns off first. When V1 = VTh, the
transistor M3 operates in the linear region while M5 operates in saturation. M3 and M5 are
designed such that, the transistor M2 will be forced into cut-off mode during the write "0"

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operation. This will guarantee that Ml subsequently turns on, changing the stored
information.
5.4. Testing and Verification – Introduction
➢ Testing is an organized process to verify the behavior, performance, and reliability of
a device or system against designed specifications.
➢ It ensures a device or system to be as defect-free as possible.
➢ Testing a die (chip) can occur at the following levels
i. Wafer level
ii. Packaged chip level
iii. Board level
iv. System level
v. Field level
➢ By detecting a malfunctioning chip early, the manufacturing cost can be kept low. For
instance, the approximate cost to a company of detecting a fault at the various levels
is at least
i. Wafer $0.01–$0.10
ii. Packaged chip $0.10–$1
iii. Board $1–$10
iv. System $10–$100
v. Field $100–$1000
➢ Obviously, if faults can be detected at the wafer level, the cost of manufacturing is
lower.

Logic Verification
➢ In the design of integrated circuits, at all levels of abstraction, verification tools
compare the design at different levels to make sure that in the synthesis process, the
designers or optimization tools have not introduced errors, particularly logic errors.
➢ Due to the high complexity of VLSI design and the complexity of synthesis tools,
logic verification has become increasingly important.
➢ Logic verification detects any discrepancy in the function implemented by the two
compared logic designs.

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Fig. 5.11: Functional equivalence at various levels of abstraction

➢ Fig.5.11 shows the functional equivalence at various levels of abstraction.
➢ To check the functional equivalence simulations on the two descriptions of the chip
(e.g., one at the gate level and one at a functional level) is done and outputs are
compared for all the applied inputs.
➢ Verification tools are used to check the functional equivalence. These tools verify that
a lower-level implementation is equivalent to a higher-level one.
➢ Verification tools can be a
i. Formal verification tools: such as mathematical models, Boolean
equivalence, Binary Decision Diagrams (BDDs)
ii. Simulation tools
• A simulator uses mathematical models to represent the behavior of circuit
components.
• For a given specific input signals, the simulator solves for the signals
inside the circuit.

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• Simulators come in a wide variety depending on the level of accuracy and

the simulation speed desired.
a. circuit simulation
b. switch-level simulation
c. logic simulation
d. functional simulation
➢ The behavioral specification might be a verbal description, a plain language textual
specification, a description in some high level computer language such as C, or a
hardware description language such as VHDL or Verilog, or simply a table of inputs
and required outputs.
➢ RTL converts the HDL into a set of registers and combinational logic. The
combinational logic is optimized using algebraic and/or Boolean techniques
➢ Structural specification converts the combinational logic into switch level.
➢ Physical specification converts the switch level into layer specifications.

5.5. Logic Verification Principles

5.5.1. Testbenches and Harnesses
➢ A verification test bench or harness is a piece of HDL code that is placed as a wrapper
around a core piece of HDL to apply and check test vectors.
➢ In the simplest test bench, input vectors are applied to the module under test and at
each cycle, the outputs are examined to determine whether they comply with a
predefined expected data set.
➢ The expected outputs can be derived from the golden model and saved as a file or the
value can be computed on the fly.
➢ Simulators usually provide settable break points and single or multiple stepping
abilities to allow the designer to step through a test sequence while debugging
discrepancies.
5.5.2. Regression Testing
➢ Regression testing involves performing a set of simulations to automatically verify
that no functionality has changed inadvertently (accidentally) in a module or set of
modules.
➢ During a design, it is common practice to run a regression test after design activities
have concluded to check the bug.

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➢ High-level language scripts are frequently used when running large testbenches,
especially for regression testing.
5.5.3. Version Control
➢ Combined with regression testing is the use of versioning, that is, the orderly
management of different design iterations. Unix/Linux tools such as CVS or
Subversion are useful for this.
5.5.4. Bug Tracking
➢ Bug-tracking systems such as the Unix/Linux based GNATS allow the management
of a wide variety of bugs.
➢ In these systems, each bug is entered and the location, nature, and severity of the bug
noted.
➢ The bug discoverer is noted, along with the perceived person responsible for fixing
the bug.

5.6. Manufacturing Test Principles

➢ Manufacturing tests verify that every gate and register in the chip functions correctly.
These tests are used after the chip is manufactured to verify that the silicon is intact.
5.6.1. Fault Models
➢ To deal with the existence of good and bad parts, it is necessary to propose a fault
model; i.e., a model for how faults occur and their impact on circuits.
➢ Types of fault models
i. Stuck-At model
ii. Short Circuit / Open Circuit model
5.6.1.1. Stuck-At Faults
➢ In the Stuck-At model, a faulty gate input is modeled as a stuck at zero (Stuck-At-0,
S-A-0) or stuck at one (Stuck-At-l, S-A-l) as shown in fig.5.12.
➢ These faults most frequently occur due to gate oxide shorts (the nMOS gate to GND
or the pMOS gate to VDD) or metal-to-metal shorts.

Fig.5.12: Stuck at faults

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5.6.1.2. Short-Circuit and Open-Circuit Faults

➢ In open-circuit fault a single transistor is permanently stuck in the open state and in
short circuit fault a single transistor is permanently shorted irrespective of its gate
voltage.

Fig.5.13: Bridge faults

➢ Two bridging or shorted faults are shown in fig.5.13. The short S1 results in an S-A-0
fault at input A, while short S2 modifies the function of the gate.
➢ Fig.5.14 shows a 2-input NOR gate in which one of the nMOS transistor A is stuck
open, then the function displayed by the gate will be
Z = ̅̅̅̅̅̅̅
A+B+B ̅Z ′
where Z' is the previous state of the gate.

Fig.5.14: Open faults

➢ Stuck open fault converts a combinational circuit into a sequential circuit.
5.6.2. Observability
➢ Observability is the ability to observe, either directly or indirectly, the state of any
node in the circuit.
➢ Observability is relevant when you want to measure the output of a gate within a
larger circuit to check that it operates correctly.

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➢ Given the limited number of nodes that can be directly observed, it is the aim of good
chip designers to have easily observed gate outputs.
➢ Ideally, chip designers should be able to observe directly or with moderate indirection
(i.e., with a wait of few cycles) of every gate output within an integrated circuit.
5.6.3. Controllability
➢ Controllability is the ability to set (to 1) and reset (to 0) every internal node of the
circuit.
➢ Controllability is important when assessing the degree of difficulty of testing a
particular signal within a circuit.
➢ It should be the aim of good chip designers to make all nodes easily controllable.
➢ An easily controllable node would be directly settable via an input pad.
➢ A node with little controllability, such as the most significant bit of a counter, might
require many hundreds or thousands of cycles to get it to the right state.
➢ For example, making all flip-flops resettable via a global reset signal is one step
toward good controllability.
5.6.4. Fault Coverage
➢ Fault coverage tells what percentage of the chip’s internal nodes was checked for a set
of test vectors.
➢ To detect fault, each circuit node is taken in sequence and held to 0 (S-A-0).
➢ The circuit is simulated with the test vectors and the outputs are compared with a
known good machine with no nodes artificially set to 0.
➢ If a difference is detected between the faulty machine and the good machine, the fault
is marked as detected and the simulation is stopped.
➢ This is repeated by setting the node to 1 (S-A-1). In turn, every node is stuck
(artificially) at 1 and 0 sequentially.
➢ The fault coverage of a set of test vectors is the percentage of the total nodes that can
be detected as faulty when the vectors are applied.
➢ To achieve world-class quality levels, circuits are required to have in excess of 98.5%
fault coverage.
5.6.5. Automatic Test Pattern Generation (ATPG)
➢ Manufacturing test ideally would check every node in the circuit to prove it is not
stuck.

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➢ Sequence of test vectors should be applied to the circuit to prove each node is not
stuck.
➢ Generation of test vector (test pattern) is tedious, hence Automatic Test Pattern
Generation (ATPG) tools are used
➢ Automatic Test Pattern Generation, or ATPG, generates the vectors or input patterns
automatically which are required to check a device for faults.
➢ The vectors are sequentially applied to the device under test and the device's response
to each set of inputs is compared with the expected response from a good circuit.
➢ An 'error' in the response of the device means that it is faulty.
➢ The effectiveness of the ATPG is measured primarily by the fault coverage achieved
and by the number of patterns generated.
5.6.6. Delay Fault Testing
➢ Delay fault increases the input to output delay of one logic gate, at a time but the
functionality of the circuit is untouched.
➢ For ex, consider an inverter gate composed of paralleled nMOS and pMOS transistors
as shown in fig.5.15

Fig.5.15: Delay fault

➢ If an open circuit occurs in one of the nMOS transistor source connections to GND,
then the gate would still function but with increased fall time propagation delay (tpdf).
➢ The fault now becomes sequential as the detection of the fault depends on the
previous state of the gate.

5.7. Design for Testability

➢ Design for testability (DFT) refers to those design techniques that make the task of
subsequent testing easier. There is definitely no single methodology that solves all
testing problems. There also is no single DFT technique, which is effective for all
kinds of circuits.

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Module 3 VLSI Design (18EC72)

➢ The keys to designing circuits that are testable are controllability and observability.
➢ Good observability and controllability reduce the cost of manufacturing testing
because they allow high fault coverage with relatively few test vectors.
➢ Main approaches of Design for Testability (DFT) are
1. Ad hoc testing
2. Scan-based approaches
3. Built-in self-test (BIST)

5.7.1. Ad Hoc Testing

➢ Ad-hoc testing is useful only for small designs where scan, ATPG, and BIST are not
available.
➢ Common techniques used for ad hoc testing are
1. Partitioning large sequential circuits
2. Adding test points
3. Adding multiplexers
4. Providing for easy state reset
➢ Large circuits should be partitioned into smaller sub-circuits to reduce test costs. One
of the most important steps in designing a testable chip is to first partition the chip in
an appropriate way such that for each functional module there is an effective (DFT)
technique to test it. Partitioning must be done at every level of the design process,
from architecture to circuit, whether testing is considered or not. Partitioning can be
functional (according to functional module boundaries) or physical (based on circuit
topology).
➢ Test access points must be inserted to enhance controllability & observability of the
circuit.
➢ Multiplexers can be used to provide alternative signal paths during testing.
➢ Any design should always have a method of resetting the internal state of the chip
within a single cycle or at most a few cycles. A power-on reset mechanism
controllable from primary inputs is the most effective and widely used approach.

5.7.2. Scan Design

➢ The scan-design strategy for testing provides observability and controllability at each
register.

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➢ The registers operate either in normal mode or scan mode.

➢ In normal mode, registers behave as expected. In scan mode, registers are connected
to form a giant shift register called a scan chain spanning the whole chip.

Fig.5.16: Scan based testing

➢ By applying N clock pulses in scan mode, all N bits of state in the system can be
shifted out and new N bits of state can be shifted in. Therefore, scan mode gives easy
observability and controllability of every register in the system.
➢ Scan based testing is as shown in fig.5.16. The scan register is a D flip-flop preceded
by a multiplexer.
➢ When the SCAN signal is deasserted, the register behaves as a conventional register,
storing data on the D input.
➢ When SCAN is asserted, the data is loaded from the SI pin, which is connected in
shift register fashion to the previous register Q output in the scan chain.
➢ Test generation for this type of test architecture can be highly automated. ATPG
techniques can be used for the combinational blocks.
➢ The prime disadvantage is the area and delay impact of the extra multiplexer in the
scan register.

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5.7.3. Built-In Self-Test (BIST)

➢ Built-in Self-test allow the circuit to be self-testable
➢ These techniques add area to the chip for the test logic, but reduce the test time
required and thus can lower the overall system cost.
➢ One method of testing a module is to use signature analysis or cyclic redundancy
checking. This involves using a pseudo-random sequence generator (PRSG) to
produce the input signals for a section of combinational circuitry and a signature
analyzer to observe the output signals.
➢ A PRSG of length n is constructed from a linear feedback shift register (LFSR),
which in turn is made of n flip-flops connected in a serial fashion, as shown in
fig.5.17 (a).
➢ The XOR of particular outputs are fed back to the input of the LFSR.
➢ On reset the registers must be initialized to a non zero value.
➢ An n-bit LFSR will cycle through 2n – 1 states before repeating the sequence.
➢ The inputs fed to the XOR are described by a characteristic polynomial indicating
which bits are fed back.
➢ In the fig.5.17 (a) inputs are fed to the XOR after 1st and 3rd bits hence the
characteristic polynomial 1 + x + x3.
➢ A complete feedback shift register (CFSR), shown in fig.5.17 (b), includes the zero
state that may be required in some test situations.

Fig.5.17: Pseudo-random sequence generator

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Module 3 VLSI Design (18EC72)

➢ An n-bit LFSR is converted to an n-bit CFSR by adding an n – 1 input NOR gate

connected to all bits except the last bit.
➢ When in state 0…01, the next state is 0…00. When in state 0…00, the next state is
10…0. Otherwise, the sequence is the same.
➢ A signature analyzer receives successive outputs of a combinational logic block and
produces a syndrome that is a function of these outputs.
➢ The syndrome is reset to 0, and then XORed with the output on each cycle. The
syndrome is swizzled each cycle so that a fault in one bit is unlikely to cancel itself
out.
➢ At the end of a test sequence, the LFSR contains the syndrome that is a function of all
previous outputs. This can be compared with the correct syndrome to determine
whether the circuit is good or bad.
Built-In Logic Block Observation (BILBO)
➢ The essence of BIST is to have internal capability for generation of tests and for
compression of the results.
➢ Instead of using separate circuits for these two functions, it is possible to design a
single circuit that serves both purposes known as the built-in logic block observation
(BILBO) as shown in the fig.5.18.

Fig.5.18: Built-In Logic Block Observation

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➢ The 3-bit BILBO register shown in fig.5.18 is a scannable, resettable register that also
can serve as a pattern generator and signature analyzer.
➢ The BILBO circuit has four modes of operation, which are controlled by the mode
bits C[1:0].
➢ In the reset mode (10), all the flip-flops are synchronously initialized to 0.
➢ In normal mode (11), the flip-flops behave normally with their D input and Q output.
➢ In scan mode (00), the flip-flops are configured as a 3-bit shift register between SI and
SO.
➢ In test mode (01), the register behaves as a pseudo-random sequence generator or
signature analyzer.
➢ If all the D inputs are held low, the Q outputs loop through a pseudo-random bit
sequence, which can serve as the input to the combinational logic.

Verification v/s Testing

Verification Testing
Testing verifies correctness of manufactured
Verification verifies correctness of design
hardware
Verification is performed by simulation, Testing is a two-part process:
hardware emulation, or formal methods i. Test generation
ii. Test application
Verification is performed once prior to Testing is performed on every manufactured
manufacturing. device.
Verification is responsible for quality of
Testing is responsible for quality of devices.
design.

5.8. Question Bank

1. Explain the read and write operation in 3 transistor dynamic RAM cell.
2. Demonstrate write operation & read operation for six transistor static CMOS memory
cell.
3. Design Various configurations of the static RAM cell.
4. Explain the general structure of memory array organization.
5. Write a note on historical evolution of DRAM cell.
6. Explain the operation of one-transistor DRAM cell.
7. Write a note on SRAM read/write circuits.
8. Explain full CMOS SRAM cell with necessary circuit topology.
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9. Explain different levels of logical verification

10. Explain following with neat circuit diagram
a) Stuck-At Faults b) Short-Circuit and Open-Circuit Faults iii) ATPG
11. Explain any two fault models in combinational circuits.
12. What is fault model? Explain stuck-at model with examples.
13. Write short notes on i) Observability ii) Controllability iii) Fault Coverage
14. Explain the Built-in Self-test.
15. Explain scan based and parallel scan testing with example.
16. Mention the approaches used in design for testability. Explain scan based testing
using necessary diagrams.
17. Draw t4he circuit of 3-bit BIST register and explain.

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