Basics of Differential Amplifier 1.1 Introduction The operational amplifier, most commonly referred as ‘op-amp’ was introduced in 1940s. The first operational amplifier was designed in 1948 using vacuum tubes. In those days, it was used in the analog computers to perform a variety of mathematical operations such as addition, subtraction, multiplication etc. Due to its use in performing mathematical operations it has been given a name operational amplifier. Due to the use of vacuum tubes, the early op-amps were bulky, power consuming and expensive. Robert J. Widlar at Fairchild brought out the popular 741 integrated circuit (IC) op-amp between 1964 to 1968. The IC version of op-amp uses BJTs and FETs which are fabricated along with the other supporting components, on a single semiconductor chip or wafer which is of a pinhead size. With the help of IC op-amp, the circuit design becomes very simple. The variety of useful circuits can be built without the necessity of knowing about the complex internal circuitry. Moreover, IC op-amps are inexpensive, take up less space and consume less power. The IC op-amp has become an integral part of almost every electronic circuit which uses linear integrated circuit. The modern linear IC op-amp works at lower voltages. It is so low in cost that millions are now in use, annually. Key Point : Because of their low cost, small size, versatility, flexibility, and dependability, op-amps are used in the fields of process control, communications, computers, power and signal sources, displays and measuring systems. The op-amp is basically an excellent high gain d.c. amplifier. The differential amplifier is the basic building block of IC op-amp. Thus let us study the differential amplifier and the supporting circuits. 1.2 Basics of Differential Amplifier Key Point: The differential amplifier amplifies the difference between two uput voltage signals, Hence it is also called difference amplifier. : Consider an ideal differential amplifier shown in the Fig. 11. y f V, and V2 are the two input signals while V, i - a ‘ois the single t. Each signal is Measured with respect to the ground. Ble ended output, Bach 8 (1-4)a In an ideal differential amplifier, the output voltage V, is proportional to the difference between the two input signals. Hence we can write, veg Vo & (Vi - V2) 0) Fig. 1.1 Ideal differential amplifier 1.2.1 Differential Gain Ag From the equation (1) we can write, Vo = Aa (Vi - V2) 1) where Ag is the constant of proportionality. The Aq is the gain with which differentia amplifier amplifies the difference between two input signals. Hence it is called differential gain of the differential amplifier. Thus, Aq = differential gain The difference between the two inputs (V; - V2) is generally called difference voltage and denoted as Vy. Vo = Aa Va 8 Hence the differential gain can be expressed as, Vv. Aa= <2. 4 Vy eld Generally the differential gain is expressed in its decibel (dB) value as, Aa = 20 Logio (Aa) in dB -(5) 1.2.2 Common Mode Gain Ac If we apply two input volta i i amples se yo et vole which are equal in all the respects to the differentia cally the output voltage V, = (V, - V2) Ay, must be zero. But the output voltage of the . Practical differential amplifier not only depends on thi the average common level of the two inputs. Suct ‘an average level of the two input signals is called common mode signal denoted as V.Linear IC Applications: 1-3 Basics of Differentiat Amplifier a ee ition Practically, the differential amplifier produces the output voltage proportional to such ‘common mode signal, also. Key Point : The gain with which it amplifies the common mode signal to produce the output is called common mode gain of the differential amplifier denoted as Ac. Vo = AcVe 7) Thus there exists some finite output for V, = V; due to such common mode gain Ag, in case of practical differential amplifiers. So the total output of any differential amplifier can be expressed as, vi Ad Va+Ac Ve --(8) This shows that if one input is + 25 Vand other is -25 uV then the output of the amplifier will not be same, with the inputs as 600 uV and 650 pV, though the difference between the two sets of the inputs is 50 ,V. Key Point : For an ideal differential amplifier, the differential gain Ay must be infinite while the common mode gain. must be zero. This ensures zero output for V; = V2. But due to mismatch in the intemal circuitry, there is some output available for Vi= V2 and gain A. is not practically zero. The value of such common mode gain A, is very very small while the value of the differential gain Aq is always very large. At this stage, we can define one important parameter of the differential amplifier known as common mode rejection ratio (CMRR). 1.2.3 Common Mode Rejection Ratio (CMRR) When the same voltage is applied to both the inputs, the differential amplifier is said to be operated in a common mode configuration. Many disturbance signals, noise signals appear as a common input signal to both the input terminals of the differential amplifier Such a common signal should be rejected by the differential’ amplifier, The ability of a differential amplifier to reject a common mode signal is expressed by a ‘atio called common mode rejection ratio denoted as CMRR. It is defined as the ratio of the differential voltage gain Ay to common mode voltage gain A, (9) hed Pa + Ideally the common mode voltage gain is zero, hence the ideal value of CMRR ifiite, For a practical differential amplifier Ay is large and A, is small hence the value of RR is also very large.Many a times, CMRR is also expressed in dB, as +(10) i f CMRR as below : The output voltage can be expressed in terms of a. Vo = Aa VatAcVe=Aa va [tea Ve -(11) This equation explains that as CMRR is practically very large, though both V. and V, components are present, the output is mostly ia to the difference signal only. The common mode component is greatly rejected. | 1.2.4 Features of Differential Amplifier The various features of a differential amplifier are - 1. High differential voltage gain. 2. Low common mode gain. 3. High CMRR 4. Two input terminals. 5. High input impedance. 6. Large bandwidth. 7. Low offset voltages and currents. 8. Low output impedance. mi Example 1.1: Determine the output voltage of a differential amplifier for the input voltages of 300 uV and 240 wV. The differential eai Ree of the CMR is i) 100 and ii) 108. iferential gain of the amplifier is 5000 and the valu: Solution :Linear 1C Appleations 1-5 of Differential Amplifier = Ad CMRR = $4 _ 5000 oo = Ac = 50 Vo = AgVa+AVe = 5000 x 60 + 50x 270 = 313500 nV = 313.5 mV ii) CMRR = 10° Aa CMRR A 10 AaVa + AcVe = 5000 x 60 + 0.05 x 270 = 300013.5 uV = 300.0135 mV Ideally A, must be zero and output should be only AyVy which is 5000 x 60%10-° ie 300mv. Key Point : It cart be seen that higher the onlue of CMRR, the output is almost proportional to the difference voltage Vz, rejecting the common mode signal Vo 1.3 Transistorised Differential Amplifier The transistorised differential amplifier basically uses the emitter biased circuits which are identical in characteristics. Such two identical emitter biased circuits are shown in the Fig. 13. The two transistors Q: and Qz have exactly matched characteristics. The two collector resistances Rc, and Rez are equal while the two emitter resistances Rr) and Rea are also equal. Thus Rey = Rez and Re = Rez The magnitudes of + Vcc and - Vig are also same. The differential amplifier can be oblained by using such two emitter biased circuits. This is achieved by connecting emitter © of Q to the emitter Ey of Qo. Due to this, Rey appears in parallel with Ry and the Combination can be replaced by a single resistance denoted as Rg. The base By of Qi is Connected to the input 1 which is Vs, while the base By of Qy is connected to the input 2 which is Vso. The supply voltages are measured with respect to ground. The balanced Cutput is taken between the collector Ci of Qi and the collector C2 of Q2. Such an ee called emitter coupled differential amplifier. The two collector resistances are can be denoted as Rc.Linear IC Applications Veo Cy By & “Vee Fig. 1.3 Emitter biased circuits The output can be taken between two collectors or in between one of the two collectors and the ground. When the output is taken between the two collectors, none of them is grounded then it is called balanced output, double ended outut or floating When the output is taken between any of the collectors and the ground, it is called The complete circuit diagram of such a basic dual input, balanced output differential Vee Res Cy B, a a, g Rey we “ee output. unbalanced output or single ended output. amplifier is shown in the Fig. 1.4. bey Fig. 1.4 Dual input, batanced Output differential amplifi ierLinear IC Application Amplifier As the output is taken between two output terminals, none of them is grounded, it is called balanced output differential amplifier. Let us study the circuit operation in the two modes namely i) Differential mode operation ii) Common mode operation. 1.3.1 Differential Mode Operation In the differential mode, the two input signals are different from each other. Consider the two input signals which are same in magnitude but 180° out of phase. These signals, with opposite phase can be obtained from the center tap transformer The circuit used in differential mode operation is shown in the Fig. 1.5. Vee Assume that the sine wave on the base of Q) is positive Sai Center tap wanstormer going while on the base of Qs © is negative going. With a ‘Source Positive going signal on the Fig 1.5 Differential mode operation base of Qi, an amplified negative going signal develops on the collector of Q). Due to positive going signal, current through Rg also increases and hence a positive going wave is developed across Rg. Due to négative going signal on the base of Qo, an amplified positive going signal develops on the collector of Q3. And a negative going signal develops across Re, because of emitter follower action of Qo. So signal voltages across Re, due to the effect of Qi and Q2 are equal in magnitude and 180° out of phase, due to matched pair of transistors. Hence these two signals cancel each other and there is no signal across the emitter resistance. Hence there is no a.c. signal Current flowing through the emitter resistance. Hence Re in this case does not introduce Negative feedback. ile V. is the output taken across collector of Qy and collector of Q2. The two Sutputs on collector 1 and 2 are equal in magnitude but opposite in polarity. And V. is the difference between these two signals, eg. + 10 - (-10) = + 20. Hence the difference Sutput V, is twice as large as the signal voltage from either collector to ground172 Sern Nose Creation are derived from the same \n this mode, the signals applied to the base of Qh and va recat deat anes Source. So the two signals are equal in magnitude as well as in pI is shown in the Fig. 1.6. Voc Fig. 1.6 Common mode operation In phase signal voltages at the bases of Q: and Qz causes in phase signal appear across Re, which ad voltages tc Id together. Hence Re carries a signal current and Provides « ial amplifier. actoss the two collectors of Q; and Qo. the two collector voltages, which are Thus the difference output V, Now the output voltage is the diffe equal and also same in phase, eg. (10) - (10) = is almost zero, negligibly small. Ideally it should be zero. 1.4 Types of Differential Amplifiers The differential amy in four configurations : plifiet, in the difference amplifier Stage in the op-amp, can be used ') Dual input, balanced output differential amplifier. ii) Dual input, unbalanced output differential a mplifier iii) Single input, balanced output differential amplifier. 'v) Single input, unbalanced output differential The differential amplifier uses two transistors in common emitter configuration. If output is taken between the two collectors t it is called balanced output or double ended output. While if the output is taken between One collector with Tespect to ground it amplifier, isLinear IC Applications 1-9 Basics of Differential Amplifier —_—_— ee called unbalanced output or single ended output. If the signal is given to both the input terminals it is called dual input, while if the signal is given to only one input terminal and other terminal is grounded it is called single input or single ended input. Out of these four configurations the dual input, balanced output is the basic differential amplifier configuration. This is shown in the Fig. 1.7 (a). The dual input, unbalanced output differential amplifier is shown in the Fig. 1.7 (b). The single input, balanced output differential amplifier is shown in the Fig. 1.7 (c) and the single input, unbalanced output differential amplifier is shown in the Fig. 1.7 (d). Voc Veg (a) Dual input balanced output (b) Dual input unbalanced output Veg {c) Single input balanced output (d) Single input unbalanced output Fig. 1.7 we= | Digeweatiat | ATP Ampligiot | — Te Bo high | gain In amplizer, amplaie the dlagrience- petueen oF spit 0 - Very and. Weng: pe output \ottage v Vp = Very - Ving - “the oligerorctio ampligrer consists ¥ ‘Y’ oc these’ WICLtTOns: \ Ara nl reds baséd, or the re F inputs app lied. the, YP és taken “1D puad. input ‘baleantack euleputs gg \ampligier & dual wnpul unbalanced cutpint cliy amp oy ) > J 9 ae tee tar ated ep \ ) Single input unbolanad' eulpeak- chy > dual tape patanced a dipertl enlganmt is the basic diyen ential ampliprer __ cimait fer which, we can oexcve the "emnaining "3 digguntiat” amplipon \ conpg erations, | Ty tte cincuit uses v2! input signals ard the output ts measwod between two cotlectits, thon the “conpigura. bin tS culedl \‘duakinpet balan (ad output clipgprantio£ arnpligs or", because both collectiils ay at the Same de potential with saspect to ground: -7 DC Analysts; the dc equivalent cimeuit can be obtained gon the basic olippential amplifO7 cincutt, simply 4 making input Signals Vin, > Ving 2d. to. dc eguiiualent eke’ 1s Shown below Be tiec Figs De equivahnt cht a dual op balanced 0 4 5 We oentin! bee -; | Lak the Up % trransistt! @ 612 base arryg “ku : : (St ; emitter lap g tansised? @, V _ Rindg = Vge!~ atgRe > ~ VEE + Rin Tg - VE ~ 27 RE +UEE =O 9D | \ We Kroc, that, Ip = Tetle | Here ‘the, \Tg\ és) Smau.\ comparaal, tD Fe, Here 6 can. be nagtected. wt (,, ) Ay Dp ee Te we Know that, Bye Tet, fae= FEfrp ooh LF 0 dotexmine the pena point Valens, CTee, Nera) pil to cliygesen bal anipliper, Sintee, both the emitten - base sections oe ily ample fer ow oe coe nead)to euueeaen int ona. sectién, ue cperating PP fog (4 » pe emansisi? a, tat! gin be eset p61 Qy pe substituting 69¢a) In | (e700), we get - Rin [e/a = oo - QT eRe + Vee = O re 1B , mete Vpe - YEE- «4 “ee - VBI Tp = BE ES Rin +2Re Pe. she value. % fr? Rin: Hence the. ¢g becomes te = Veg — Vpe ORE \ Vee = 0-6 461 silean transistdl 2 Od fil Geuranium tnanséstél & slectiog tho proper value 4 Re, we Can Staak V5) aol value somitten cworent, Te 561 a. knowin’ value 4 HEE: Myb ys) eT oe RY QRe To datermme the collectit- to- emitter voltae Vavvasvy vo tay ah freee , the ‘cotlecté.," ' \\ Vee. Applying Kul at Vez Vee- Tek| a the collect’! - tP- emetter ~Uoltage, \ MW ce = Ue - YE «| a) veel eRe tig)” ad > vet Tee +Vpe| = Veeq .-74) | Hen ie pi en the transistils, we can deter mine . the ea, ord Vea, ky, oy 45s ca) £ CH), 8 Pte, en T= Fog t tee hoy the) pe analy sts 5 9s aw, a to al ffir Gnpiqurations , (bgcause the Same. 3 used pf) all the “4” “enpperatian. aig “7 Byuisalent a fila ‘transesegt is BE oc ° B we 27 Peproninate. exe at transis 8 BE ic “7 Ae Analysis: — A, / a 9 piper ec sis te dive the erpriassins pal he étage in i a ~ é b Me diperentign ampl sith |MA ) set the de voltages +Vec = -UEE = 0 2 substitute he sna signal T- equivalent models pl the tlansistils. as shaun in the pig etme @ m4 k ie Vo I ae aL , <_ in - Ye tie - Rin Cie +e’) . + J+ Ring T2R + eh te, c Re i + Viny 3 @ Sing vs VW Figt- Ac equivalent cKt % a dual input balanced output digerential amplaren Applying KUL fal the Leapts) & copa) Viny = Rin, tb, +3e te, + RE Cie, + ley) Ja) | Ving + Ring Eby +e ie, + RE Cle, tie) 7 ~) we Know that, the amplig: catien forced, Pye Be “lip ip = tc /Pac - we Krom thet, fe = intic | fe = ic Cho) 4Tbe ie = ‘e/ Pate. Sustitute the Value 4% ip in eg5cn¢ (2) be, + He toy + Re Cie, +(e) > 03) ac Ving = = ty t Mele, + Re Cie, + te) 7 cy) aL \ Ow, Met ac emitter resistance - Vr. = 26m Te Pac = arnpli¢i catien pact tdnh tn, Ring = input swsistanies ee, leg = emitter Coownts Re = emitter Swsistance Veny Wing = input voltage Leo10s pave ent Rin Bae Rano fy lalues oe vew Sau *. Thuy on naplected - hence ¢9's (3) & CH) Lecomes Vinj = ete; + RE es tig) 15) Ving > Tele t RE Geytiay 5 ( viny = Clic, + Re ie, TWH Ving = ke ce, + Get RE) te 5 cg)‘ é we ane 7 To fink the, Values te, | tey, ing the Clamen's mule “eg (set RE) Re te, - y Re rete | | He Ving Vin} Re , Ving et Re) ie) os (let RE) Re Re Cetke)|,’ ie) * Certo) tiny - Fee og (Me + RE? — Ke let RE) Viny ‘ RE Ving je. 2 @etfE) Xe Re Clete) . Cle +€E) Ving - RE Vin, “oy le. = OT Qetke)®— keON The ouput Voltage, Mo = Nop — Vey I ~ Ke igg — CR ‘cy = Re key Ke leg Re Lie, - ica) Vo = Re Cley~ bey) Cv ieZie) Substitute the Values q te 3 ity: in (0, Ue get Mo = Re Cie, ~ieg = Re [eee ete ei NE 2 2 (et RE) es Re ‘(Cet Rey* ee =, Cle tRE)Viny ae Ving — Cet RE Nang 4 Re | Clete P— & «eet Re) CVin, — Ving) tRe CViny ~ Ving) Sy ae 2 Rk [Pentre CWiny ~ ving] 00 “ete = Re [Stee CViny —Ving). (eS CUiny ~ Vina) Me lef 2REF | Yo= Se (Win - vi f) = CVin, Ving) | rc), ie observe that, the amplifies the oiperance Win, & Ying Fran the. egcil), we diygron tial amplepior , petweon bud input signals i Wet is defined as the Matic the, input Uoltages 7 voltage gain Ay)s gp tre ouput woreage Fnem eg CH, Nol Up = RE Win, - We a ing 9) Vint -Vin2.= Ug Vin Win EE fe NS T whore Viny - Ving = Vid. Fig afpe op cate Sons who: 50m Age “oo = & ke Vid = dipountial 4p Votta Ved. %e. FoL= ogyerartiah voltae. “7 input sistanter— FE iS aap as tli equivalent mosistane that would be, maasuredwhew te, : Get RE) Viny — Ke ving. (Setkey— OF Ving Bat Cle# RE) Win ~ RECO (et ke) RE a VK Pac Van Pac Cet RE) YA Coet RE) WA) (ste RE) (e+ 2RENe) Rue Rt Pac Cre + 2kNe) (mete) R= faemeCtet AE) et RE- Generaliy, Rer? Me, which implies that (let 2RE) =2Re & CetkE) = ke1 hy 2 Paete CoR) tbo =0- whore, loa 3 “ea Bac \ Rig. = | Ming Pac ins ie, lhe whore ten 2" (ae tee) ving RE Vin, etme Re Ryo! | Ving Pac Urb +! 2% Re) . (let RE) Vinge Re ©),’ wW Rig = Wika Pac Melt Re) Cle + RE) waxy ' whore Jet Re = Re 4 Cet 2RE) = ake 1 MS Rip Pac! Me CORE) Roca y . Rig = fac ne ste ip sassores,7 Output rusiStante (Ko)i— Tt is olyinodl ag ‘te uivalent nesistance that would be moasloud a eithon q the ouput teuminal. with rwspect to the Pow: ‘ | “7 Dual Input unbalanced oust diperentas Fa: Dual 7 chon the Tan ho ony $e kg gu orca opt = DC StS! — the dt sis 1 Similan to the dual input balanted output digerentiaL amplgier waste > ME MBE 2Re + Rin/py,Vee = WeeQ > Vect+ Vee - Te Ke. 7 AC qralysiss— Fig: Ac equivalent CKE % dual input unbalarted output digesrentiaL ampligien Peni, Ku Bl the Lope § loopen, Viny = Rin eb, +7¢ le, +Re Cle, +t fey 30) Ving’ > Ring ba t Neleg t Ue, t te) -7@) Apter fol Simpl ging ii eq's cg 2), Vin, = Cet Red te + Re bey —> G) Ving. = Re te, + CletRe) iey 7 C4) Apter, Solu ing the. q's C3) & cH), we get 36) oo 2 2 (PletREY - Re-eow : , _ Gerke) tng = EN 5c) (met RE)? - te “the ‘cutput voltage Takth ocrmss tel collectél cy, because ae is a dunk pe nietan cod cutpur dipeuntiol amplisier, whe output voltage, Uo = Yay! PR . Vo = ~Keie, C. ip Mie) Substitute the Value ig in vo, we gel \ Vo = -Re leg 2h | (et Rey — Re = re C%et RE) Ving . we (einen Cet RE) Vina nb+ are ke + fe KEI’ No = ; Re Van, — Cle + RES Ving| c : Tp Le FARE) “| , Greneralng, Re>> ne; here Cle thE) BE Re | Cetake) me 2K.. 2Viny — Re Ving ogg eta stat 27 e RE = Re ae 7] 2% ’ td \ ane | ~7 voltage gain chads - Pan | equation ¢#) Vo = RE cviny - Ving) ale Agi vi Qesniy ye Ke, ' ! Ven,- Ving ae . 24, . SEs Heap Vid; Dtv0 7 Suput sesistance: — yw " Ry = Re i i 1 an desisega@ as) mecasemed at collects! with ee to ground. i3 equal to Wee ering Yt the collecim mesesea?\ R,4 ) iw"7 Singl input balanced gutput dijerantot amplipny, | igi eingla input balanced. euiput diyprontial emplizior 7 De Analysis; — Te= Ips Mee ~ Vee = BRE + Rin, Pole Vee = VeeQ = Vect+ VBE - RePili nnn Pa AC eypilent Ciclo a ge tnput balantwd ouput’ a i | amplprer. 4 ry KUL rl the tegp ch) & | foop ey my Min. = Rint) +ele, + Relée, = te) 7) Vin = Rinib, t ele, + rele, -7 @) we knour that, lo = iptic ic Cp 20) ® u we know that, fae = tefip Pac = te fiz, Cu esle) ” ip Vig! Pac. Substitute the Value Hi, in eg. 0) & @). Vay = oe de, + Ne te) + Rp cle; - Q)A® he aVin > Rin ig, + mee) + ee Vy | Pac Rin | Pac Value és Leng Small - Thonapa,, te can be raglected y hence eg's (3) G4) beconey Vin = 3p te, + amgklle, - te) 7 05) | Vin = Sete; + Ye tey. > Vin = (optRe)ie; - Re ley 707) Vin ome ie, +%¢ te a) “TT find. the Values % ie, | Tey we ow using the cnamen's mule. (etke) Re] fies] _ c Me I [a] Mi Vin ~RE UD He fe, =, ———__—_ Grete) -Re Te Je = MeVin, + Re Vin . Nee tRe) +R_ere. ‘ey 2 (Fle +RE) Win = _ me CNet 2K) C4)7 | | ee \ , CetRE) Vin (le). Vip tep iS (CetRe) -Re Fe. Te = GletRe)vin - He Vin Qlet RE) He + ReENe , ~ RE Vin ie = = 7 (10) ; le (let 2Re) : Wy the culput Voltage, Vo = Veg Vey = Releg ~ (Re te) 2 Re Cle + key) Moi* Re Cle tie) Cpe) & phaay tho Values % 1% ey ty Yorne gee Ah = R, Cie, tie) | 2 Re [Muef Renin 3 pre an %e Cle F2RE) Meret ake, t Vin Cle t RE + RED Fe x @ Cle tQRE)vy 2, (Cet 28) =) 0- g.| ——— [ Te Cle T2RE) i Gerenaliy RE? Me) NetaRe = Ae Ww: & SRE ) | ° Ne (ORE) I | Vo = Re Vin —7 Ci) Je ~7 Voltage pain (Ay); pram e401), Yo= Ke vin Me A= Mo 2 Vin ne. Ad= Re 7 me = input Rosistan(a *— 4 culpur \RoSistance 2—(7 Single input untalented cuiput diyprentia denpliens— yyy : ia pel gp OD nine SpbSIOS. ' ) y i ' » Mey oe Jes Xa = Vee - Vee ORE + Rin i Pac Veen Veg = ec tUBE- rR.Vo = Roles CX 2 te) Oo. = ie, - Re Vin we Know that, tey = moet) . PRENin eT [ota He. \ Neto Pare Re>. . Generaty Yo: 8 [RE Min Ip 2 BE ne QE)= C!) 3 vortage punt: - Fem the @C0, Vo = = Vin At= Vo = Re Vin axe 7 pur wwsistances — “7 cutpur swsistante ;— waeAMPLIFIER CIRCUIT CONFIGURATIONS Osta 4-1 PROPERTIES OF THE DIFFERENTIAL \ Vote nan | joltaee redietance | TABLE Configuration Ry = ate Rat he | 1 Deal inp ele seemrat | Ru * Beste om d io . apart Mert none ; Stead Ra eke Stdlovipat Rete UR 4 Sings not, RokFor the differential amplifier shown in Fig. 1.15, cak ul fea and Vero. ti) Voltage gain. im > Example 1.4 : jy Operating pom Le. i) Imput and outpttt im Assume [b= 100. pedance. Woo = 12V 3.3 kQ 1502 Vs1 -12V Fig. 1.15 Solution : As hj, is not given, use r parameters to obtain voltage gain. Re = 3.3 kQ, Rs = 1509, Re = 8.2 kQ, Voc = 12 V = Vee, B= 100 i) ln = R Moe = 2-07 __. 0.688 mA a8 3 . +2ReE FO 218.2104 Icq = Tr = 0.688 mA Veg = Veo + Vee —IcgRe = 12+0.7 -0.688« 1073 x 33x10? = 10.4296 V ii) For voltage gain, 1. = ZmA 1 26x103 re = —26x108 TaRaIp > = 37-79060 Ri 3. 3 Ag = Re, 33x10 Te 37,7908 = 87:32 As the configuration is dual input balanced output. R, iit) 2reB = 2% 37.7906 100 = 7.558 k0d . Ro = Re =331Q "Linear IC Applications 1-23 Basics of Differential Amplifier 1.8 Methods of Improving CMRR As seen earlier, in the Ex. 1.1, higher the value of CMRR, better is the performance of differential amplifier. Hence in practice the efforts are always to improve the CMRR of the differential amplifier. Alongwith the basic circuit, various other circuits are used to improve the performance of differential amplifier 1.8.1 Effect of Re To improve the CMRR, the common mode gain A. must be reduced. The common mode gain Ac approaches zero as Rr tends to infinity. This is because Ry; introduces a negative feedback in the common mode operation which reduces the common mode gain Ac. Thus higher the value of Rg, lesser is the value of A, and higher is the value of CMRR. The differential gain Ag is not dependent on Ry. But practically Re can not be selected very high due to certain limitations such as, 1. Large Re needs higher biasing voltage to set the operating Q point of the transistors. 2. This increases the overall chip area. Hence practically instead of increasing Re various other methods are used which provide effect of increased Re without any limitations. Such two methods are - 1. Constant current bias method. 2. Use of current mirror circuit. The other method used to increase Aq to improve CMRR is called use of an active load. Let us discuss these methods in detail 1.9 Differential Amplifier with Constant Current Source Without physically increasing the value of Re, the Ry: is replaced by a transistor operated at a constant current. Such a constant currrent source circuit gives the effect of a very high resistance without affecting the Q point values of the differential amplifier. The differential amplifier using constant current bias circuit instead of Re is shown in the Fig. 1.16. The transistor used is Q; and the values of Rj, R2 and Ry are selected so as to give the same operating point values for the two transistors Q and Qo.| -y constan ean’ tiboent BRAS 5 = MER: Brthinhos tise ¢ vega end fo atte) o4Ucce aL Ring Za \\ Veny @) @ we 6 - Veg Ny See ie ett BES nase pig ee cwount bias the cienenbiaL amplipren 2s tasically a cembination ‘a tu emittttn ~ccupled. transiseris, 6 prtopen pprctiohing % the vamplipien, gt, 8 ‘egsential “thatthe tnansistfis: am leeey biased: athe? nece. dic. basing 2 protec. iby the adpply Sobre EE end te” emitter |io ence OO nesista RE} it 1S doSimable that the. operating *\ escent point 2emains Stabk, and this a que : . Ee the. emitter uworent Tp eM ans uines . i itude. this can be achieved ed in magne unchang by anconpos a a Constant cwurent ‘bias as | shown in the above ry the. constant cucwnt bias is basically a tnansistd! cotth popen bingy coorargertent , Cove ceed tp the Caumen emitter polnt as shown ir che ig. zt can be shown -that this supplies a constant emitter upount to the transistBIs 68 Ag" Fuém the. pipe, ERE * Gavrent, T)37 Veg oe j re = MV VEE } Vel P| oy res yy eg + VEE a Patben R3, Emitter vo age, F %,) Vez = Yes - Vee3—70 i ~ -uce. [Ro Voltage. ak He base, § Gs, Vag = cMEE Eval 703) Pa s5). YA Anagte syess poten tia divéde’ “rele. °) substitute Vag 1 eg@). (Mey. Vg3\* YBES ae Veg. [Ree | = Vgese we, evr Vee eel Substituta te value 5 Veg Ir YW ' ‘ Vez + VEE = El Ip, = E3, % “Vee (Ro + Y -y; ee IEE ~VpBe3 ‘a2 yoy Taba ut yoy Rit Re , tes = Tes = Nhl og eS sity) Rg Ce tee (am the Fig Te, = Teg 3 ysince tho trunsistls, @, {Gg ane symmetrical and thew ’s Cqumt divisien gy wevent i Vee ~ VEE Fee wat Vge3 Tp, > Tet = eg — ARE \) \ ay eee Oe ages) Th te -eltoue’” ope NEE’ Vibes ts OF Pa Sliten -transistt), Ry Ro ond, Re ae. Win 699 yreed magnituch. ; a i a Hence the: emitter cwwents\' Te) od TE2 aon % constant: ipaghitieles The: transiste! @ g at / ver| lies constant biasing cuvunts to the tran f sistdts @) % 42° This Stabiluses the operating points g | beth tnansestéis 4) ard a. } stant eovent hi | 7 constas bias wlth canpensating i guodles~ 8 Tempered compensate cancun Sure she stability § the asc operating point on ‘tf poten arnprroued. 4 neplating the xaSo- abt ay He abe ip ty des Ps Pa os shown In the bbolowe “0% se bald 6 -VEE 4 congosetl cies Pig: constant cunnent bias, corthpron the obeve pip, THE WOenE divides at Py cvoant Fas FGM tate ent ¥ and. uroent Fp Selig oh we diodes - rhe diodes Di 42 PHEYEES Any thorural ig ae _eporation point % O3 ard. en8ures that its emitter woant eae itude , een cohen changes “temperate. ohn the. fig) M+VEE + V8ES + VER en the temmpenatune; inowases, the base- en, in, they vortoge G 3, Wwe Veea cacmwases, This hag the eeee ioe Sg the Voltage dnop Qur0ss Re wee emitter cwoeat! Tea tends to nowase, thoeby disturb de dee, bas 5 @2: But this » 4 appcetuely pontented fy the, diodes: Dy arf. Dy j vr ' The ‘Curvuont , fy + Sgt Zab pm tn magnitude, an inowasé! 1 Fine dagnease % Tes: this my ebraceepins ea" Thus - ! “Y CK) due to towase\ kempbratioe, ‘ae. which wat puuents the oni oy the. | qporatirg ot «quiescent py:Prom the pip, the value g Tez depends 4 upon “he meseStd1s “Re ard Rp, the bias level can be changed, by \anyying ,F Ry: | enittey Teg 2\\ : Nea ~ GEE), uvvant, Re ' Jeg = Mes t MEE ay ey Re Emitter vote 5 a3, Veg = VB3 - VeeEZ 502) vee at te bdse G92, Veg = Wy VEE) eupsti tute ” the idle” t ‘Ug3 wn “ Vea 7; V83 - VBER 1 Veg 2 2M VEE, «eg 36H) Substitute the Value 3 Mgs' ew Th!) area FE Bol ts Re \va La) row 3 2p Ve Upes tue a jer yg Fe Teg = 2Vp - “BER. Vp - Ve@EZ = Teg +. — OF 2 = ; = > 6 Re RE RE a | = Oct Re a 7,15) who eS YBEB* Woz Tea: (milter wownt % the tnansistf Vp = Voltage’ Sarge awisss te diodes D,6 p, \VBE3 = ‘base - emibter woltege % tuarsisit g, Re = emitter Jwsistunce. “thowssie, fem, the. YS)» te level F Tes, can te pitad by choosing RE Satta gritos To obbain, the, Value. Ry pier the. i. Ry = es, Qo ( aN uk a 4 yy ee ' From #903)" UB3 Olp-VEE | Roz Vee~9vp pode ey i obs) Pe eB Fay ee TO, select , the assumptibn' cs nade that” 7 >TE3 (Re EE= te [™ vo= otv ‘ TER) : - pe. 72> 73], ‘516m eg'cs) SG Ce) \ Re = pt and Ro 2 Vee - "4 Teg Tes anataenatter wont Tez ow % Canstank magnitooe Th t7an- sist] Gq, Supplies constant bias covonts ® the sransistil @ § 43- this stabilises the openatig * the transistdls A) & %: points Cunnent E2018! CRETE: COOTER SORE Ty. J on.n) (GRE: an, Ks ee pry thas pel the toransists a, and My % te. clipgerentiat amptigor may a qhas ‘intuit provides thoural stabilihy operating point. (0 Pada tapas” balanced ccubput ctype ad. ample sing can camblint ident’ c2neae 25 shown ‘inl jig’ elon’ aro yoy yp oahy ; In a cwvrent maven? eincuit, tha! ecrspest taper 2s tha. Vinnisona) tage. tha, Preeti Cement that rads that the \QuEPtoe pam. 2S ,Gpuat to the Unpat) MONE) .03, F ‘ Turia. | ypoant Tift . Norvor Tevet > Zsenk - Feég:. flock dagrany -| Ff al ip talancd. 9p cipemogi al ay cwoent misvigl ceuit, whe “yp & Op caer: oh "pe eon be. prdved. a5 pollens Fyn si Foo the pe, othe tansestls,.az and ay. ap identical haliing uot bese Cnittey voleapes, CMee), equal base cwounts' ard eguel cotlects! ewvents - bet Vee3 = Veey 5 xf) Ae anal ba = Tey: wes} oo f erynpplin g keh & the. Junction olenoted as Pp, 5 Ips Toy tL, afew I. = ,Te3t Tey | { Fg > Feyt Ipgt Cgy Ty > Fey # OTB Li Tyg .> Tey] Tyg = Fey t &I gy) 9 c1) we Know that, Tre = Igtle Te = I [Ip £6) Pc Kpow that , B= Fc] Fe 7a = Fe. B- SN - Fey = sar psorplitaien Substitute the value $F Ipq in act) paces B=) Ty 't ‘sz Ry = 74 + 2 Tey » We 5 Rail tal. 30. Raa P! is" quvte large in, ransistits ne 70D: ‘a (ean, be, regpates: Nout =e beconies . 2 Tomi Fide Cusrter > Zea][Pata] 7 © mom the above €963), the owlput Cpoant >| equal to input vant Tg: & mus tabi lises the operating points. pt te toansisthis 4, & 9 Apply ing KL to the base - emitter Loop g ¢, “WEE = -Iyh —Veex “VEE ToRy = +Veeg ‘ FoR, 2 NEE —Vpe3 Frm the Above’ 24%), VEE, Ro ano. on pret itede. the tmansigtf? 2! supplies‘ canstat cuvent to the tPANSESEBIE 1, & Og » Which stobi- (igs the operating, fuses % oe, tnansésté] a94) . PS é€-sectew pry dt1.9.3 Constant Current Bias using Zener From junction of emitters of Q, & Qy Vee Fig. 1.18 Constant current bias using zener Circuit Analysis : The voltage at the base of transistor Q3 is Ve =. -Vec + Wz Now Ve = Vb ~ Vae The zener diode is often used in practice in place of the two diodes. Then problem of __ temperature dependent characteristics of | the transistor can be solved by using zener diode. This is because zeners are available over a wide range of voltages and can have a matching temperature coefficient of voltage to those of transistors. Constant current bias circuit using zener is shown in the Fig. 1.18 .- (11)Ve = — Vee + Vz - Vor _ (12) And ly = JE a Vee ) 3 eg = Nett Me = Vor + Ver BOS TRS Ie = (13) While the value of Rj is selected in such a way that zener diode always conducts in Teverse region. It can be calculated as - (14) The common mode gain is almost zero, providing very large value of CMRR, with a constant current bias, To offer extremely large resistance under a.c. conditions, a simple circuit of constant current source, with less number of components is now a days used This circuit is called current mirror or current repeater circuit.Be eg | In electaientcs, De coupli galso Called dimect "coupli FW \canect wrod coyact 61 conductive oh l 2s a wy y inteicanne ct. ing ‘two cibeuits, Such ‘Hat, in adldi'tren to trang exting the. AC signal (81 ingfmation) tho prse St augoy /porousdles ‘Oc ‘bias to ‘the next: Thus, there 1S NO need. pol a De blocking capati ty tp be used. tn Bidex -t0 tnterrcomact: tho cinuits , wd this methoa. #5 ao Kner, as DC coupling Ne DE ROapG. abies” bath Ac and. De Signals. zt denectly emnects the Comp ahorttogether: without any crupling copacitts | ’ | in coupling Ss usd ina oven, eaten | ow 8S & Need p81 a eidlo bandleoialth, 3 won DC ~ Unbalanied code. i Used. Both intexa- as must have tha same ground potential On the same board. a1 system . ! ) . This Coupling 1 Used by aaa i | cinmits Ke Ic- op- Amps, sine lage couple | capatitfis can nat be fabricated en- chip. Some | distwte circuits ceuuh as power emplizers) S20 employ oliniace coupling tp - seduce the cast and inpnove vow pepe peypeimance \ awd Adwan tages‘ 1) Simple boand aasign 2) wey Gook Low fog response ~ disadvantages '~ ty canoput powes supply Aesign.inplixten Stages’ —\ [> cascante eaypsantine aiptpen Sp etce eee + Fa: cascaded Apprentia amplzien yA The diggerential ampliyier, tohich tan amples the alipppoance Petceen the! Palleyitiing od. fun- werting teuninals, -and the. output is, tector, acmoss the colleus! teyrinals Cc, % Cy ine Calteol dual input balanced. output dipper ents igor. with a@ site stage, the vottage : quarlable 2 Umited. when Lange voltage gos ane neoded /*t iS . Conmen practe ty arrange| | j EN Several Steges in: caseddle, Such that, the output — * one stage pours the input to the next Stage. the overou vottape\ pain g Seuenal stapes in cascade és geen ty the product o the individual Stage Gees: A ‘boo - stage cascaded clipgerorctial ampli — fier tS Bhown in the above fig. Te is san fim the pig ts that te. pense stope és a duh input balanted output aipgerntial amplifier, because | the amplijred output, Yor 75 ebtainid between Ht | COLLECTS Cy Gp, and thes | amplizredt output drives the second Stage THe Second St ss @ dual input unbalantad output dipgeremtiat -armpliyior, aT ard the rept 13 taken across the collects” Leumi: rab fy gd the ground. It is evident’ that, the - ampligied output 5 the pirse stage £5) gen thom amplipred. , and. tha ouera ‘voltage gent the cascade annaggemint ¢ on) the, total Gen nooded , several Stages ray thus be Cascada. FR the poitper functioning 5 the Cascooled set, that the. tnansé~ sifig used in te dierent tages. ano Pxgperty. ere r Aprikods anal cxclag cua le “dec biasing ’ the tnansistéls ¢é providedf \| i | { vel toonslaté! ; Chevel shigton), — taanstere want an op- Amp to qperate, down tp ace, coupling copacitt] % used. Because F dime 6 de coupling the de uel Wises prim =) . eho. “inerwase in oc “level tends to shige the cporating point % tha noxt Stare. This Limits output wot tage swing and distiit the oub- put Signal, sot reduie Oe de tauel to EO0,ue louel transiatii, ue t which te qyue- one stage zs shigted beyde et zs ov par 2270 input Signal Ww the simplest type % a wwe translata ig Shown in pigorbeoee which & ASSAY emitter poilower. with .( shit the ‘dic Voltage letet. ef intearredigns, Ste peeing ve pat voltage , Vo 6 ‘4 appyog KUL ts “Wye My; Vee. wis ; WY Von en VE ind: my ow Vee’? 2084 Be sb-ob "hus by oy the. ‘towel sanstat he abc ia, bin, re paght aan fy! wa heheapoy Cetin spowy 4 th ag this Shige i tnguggi creat, the adput can be wake | af a Junction g 12 mwSiSts RiE RH as iy F shown in nape +Vec lige! “Lover towmastats | &y Opplyy iG KL tp the -base.- emittey cop pnangistty IN eG Mo = Wie Mee ~ Fale)Wee Vi vee + hI} ©) pra) the p62), Vo tan bax Varted ty. we haut, Vp = TR, = Ro Ci VBE) We ny RItRy Prem the eg(3), Vo can be Varied by vaxying Rand Ro andl by property choosing the mmsisttis, Vp can be made to 0. However, the. arvrargerrunt tr the fpr hag the disadvantage that. the, input Signal also gets td the frotee? attenuated by i fal! Gi) A’ modified versien i the level trranslat? kt, tonich | Uses a” constant Gwbwnt § Sowie is ‘Shou in ff below. wh aT Bb 1 Fig@):teued transett) using VEE | \\ Constant wboent bias CKtthe censcant | dbvent! axrdice \iconstitutes g constétnt’ -cupobrit \to the, ) ) banststd, ay cu Fie ‘he Pa, Be vent). a Vwi Vez Vee vBer pba the MeeAstone Meumont | bias» Cnc e Br Aer oppling RDL; bf “~VEEtAYD = 0 ZT, > Wp - WEES. ay Ry 2) Mee 2D BAC AN ARSE yee ar | Soave the core OE hex vatiengir,£ Rpt en ctoert cece By 'suitdkte ‘seliction) yy” Values. a, Id Re Are Rg, % can be (fade to 0° Poh Wtraneky w An. Umpotoued version oy te uel thanslazd! ywtiSing . eovent ymirnbt. 7s, shawn 02 p96) belay, |—- = she wwownt mirng cincuit, whith Supplies a constant uvvent the tnansista’ @, From the DR Vo = G- Wwe -~ TR Flom the Usvent mini nuit, a C." Ofp wevent = Ye event) et opplycra ‘KVL, FR -VEEtVBE= 0 ‘Tp = VEE - VBE —~ WeE-OF ve Rg POUVE Th Complete douvtion LR fron ees miner mec %4 Selecting suitable Values a Ry Ry he Voltage, Vo can be | mace to 2; ay,1.12 Methods of Realizing High Input Resistance The various methods of realizing the high input resistance for the differential amplifier ci are, 1) Use of Darlington pair. 2) Use of FET _3) Use of swamping resistors.1.13 FET Differential Amplifiers Uptil now we have seen the various differential amplifier configurations using, BJTs But if very high input impedance is required then FETs can be used in the differential amplifier configurations instead of BJTs. Due to FET, high input resistance of the order of 10° -10"° is possible. This reduces the input bias current to the order of 10°? to 10-2 A The limitations of using FETs in the differential amplifier are low voltage gain and higher offset voltage compared to BJT differential amplifier. In the ac. analysis of FET differential amplifiers the only replacements required in the expressions derived earlier for BJT differential amplifiers are, Re—>Rp and Te 7e Thus the voltage gain of JFET dual input balanced output differential amplifier is, R Ag = —2=gmRp (rn) The Fig. 1.26 shows basic JFET used as an amplifier. This acts like common emitter BIT amplifier providing a phase shift of 180° between input and output. - (1) Thus differential amplifier circuit can be obtained using JFETs instead of basic two BJTs Qi and Q2 while other circuits using BJTs as it is. The Fig. 1.27 shows JFET dual input balanced output differential amplifier using JFETs intend of BJTs and a constant current bias circuit using BJT. The supply Vcc is now called ‘Dp while Re gets replaced by Rp.JFET Fig. 1.26 JFET as an amplifier *VYoo “ee Fig. 1.27 JFET dual input balanced output differential amplifier - = ---aded Niffereantial Amnlifiar Ctanae prea meer ee fogpegee4.12.3 Use of Swamping Resistors To achieve fee pie Tesistance, external resistances Rj: are connected in series with each emitter of each transistor of a differential amplifier. Such resistances are called swamping resistors. ances are cae The differential amplifier using swamping resistors is shown in the Fig. 1.24 Fig, 1.24 Differential amplifier with swamping resistors ‘The various effects of swamping resistances on the performance of the differential amplifier are, 1. Increase in the input resistance. 2. Minimization of changes in the transistor parameters due to th temperature. 3. Reduction in the differential gain. 4. Increase in the linearity range of the differentia! amplifier. e factors likeIC Applications 1-34 D.C. Analysis Due to Rg, there are few changes in the d.c. analysis of differential amplifier. The emitter current in each transistor can be determined by applying KVL to base-emitter loop of Qi. For the d.c. analysis i = Yip = 0 V. Assuming Rs) = Rs2 = Rs, we can write, - IRs - Voce - IeRe - 2 eRe + Vee = 0 (I) The values of Ip, le and Ip are same for Q, and Q2 as they are matched. Now [eee Nee IpRe - 2 1gRe + Vee = 0 - Vee ~ Vor we Q) 2Re+Re + hie As BS is very small, as he is large, the equation can be modified as, fe Vee — Vee le = gReaee “Ie 7G While the equation for the collector-emitter loop remains same as before which is +Vai ver le Ri The expressions are valid for remaining three configurations of differential amplifier. AC. Analysis| When external resistors R¢ are added to each emitter lead, the new voltage gain and new input resistance can be obtained for any configuration simply by replacing r, by (r, + Ré). For instance, the voltage gain of the dual-input, bal- anced-output differential amplifier of Figure 1-12 becomes =e _Re_ ul Aa oa + RE (1-35) and the new input resistance becomes Ri = Ra = 2Baclte + Ri) (1-36) Keep in mind that the output resistance with or without Rz is the same [see Equation (1-17)]. That is, . Rot = Roz = Re Thus the use of Ré reduces the voltage gain but increases the input resistance, as can be seen from Equations (1-35) and (1-36), respectively.rawie 1a Configuration Circuit Aq voltage R, Output gain Resistance Dual input Me Re 2Rs thy) Re Balanced Output Rs + Dual Input Ne Re 2(Ry +hy) Unbalanced 2Rs+ Ne) . * Output alLinear 1C Applications 1-19 Basics of Differential Amplifier Single Input wie former | s* Pe Balanced Output Nt Re 2(Ry +h) R Single Input Unbalanced ZUR = Fe) Outputeapaanail Example 1.3 : The Fig. 1.14 shows dual input, balanced output differential amplifier configuration. Assuming silicon transistors with hie = 2.8 IQ calculate i) Operating point values ii) Differential gain iii) Common mode gain iv) CMRR 2) Output if Vay = 70 mV peak to peak at 1kHz Vt) Tp2 oP Rascstarcos and Vsq = 40 mV peak to peak at 7 kHz Veg = +15 ye = 100 Re=6.8k2 Veg = ~15V ' Fig. 1.14Solution : As the transistors are silicon, Vin = 0.7V i) Operating point values are Igg and Ver Now kes keg = Now Ne = Nero = ii) Differential gain Aa = iii) Common mode gain Ag = iv) CMRR = ie. MRR = ¥) Output voltage v= Now VW = vs Vy = Ver = Var, Rs” B hye = 100 15-0.7 100 * 6.8.x 103 + 2% 68% 103 +755 2Rp += = 1.051 mA Ip = 1.051 mA 1.051 mA Nec + Vaz = IeRe = 15 + 0.7 ~ 1.051 x 103 x 47 «103 10.758 V 10.758 V hieRe _ 100% 47x10 Rs +h ~ 100+28% 105 162.068 hfe Re 2Re (+ hae)+Rs the (100 x 47 x 103 2%'68x 1037 +100) +100 + 28x 103 0.3414 Aa 162.068 Te! ne = 474.652 20 log (474.652) = 53,527 dB Aa t AN, Nb ~ Veo.= 70 - 40 = Mi +a _ 70440 ~~~ = 3 = 55 mV peak to peak 162.068 x mia 4.86204 + 0.0187 = 4.88 V peak to peak 30 mV peak to peak. +55x 103 « 0.3414 wy) Ry: 2CRsthie) > S.8ke Ro: Re = We tkhe