NAME:MUHAMMAD NEHAL KHAN

SEAT #:EP-1850081

SEC: A

ASSEMBLY LANGUAGE

SUBMITTED TO:

SIR KHALID AHMED KHANZADA

ASSIGNMENT# 1

Question 1:Draw the block diagram of three

bus architecture and label each block of it.
Question 2:What are the advantages of having wider
address and data bus? Give examples of each bus.
Advantages of wider data bus:
• A data bus that consists of 8 bits, can transfer 1 byte of data
per read/write operation.
• A data bus that consists of 16 bits, can transfer 2 bytes of
data per read/write operation. Example:
Data stored in memory address 4 (11111111 00000000), each
bit of the data must be transferred on a different wire of the
data bus.
Advantages of wider address bus:
• An address bus that consists of 8 wires (= bits), can convey
28(= 256) different addresses.
• An address bus that consists of 16 wires (= bits), can
convey 216 (= 64K) different addresses.
• An address bus that consists of 24 wires (= bits), can
convey 224 (= 16M) different addresses.
Question 3:Is data bus bidirectional? If so justify your
answer (hint: fetch, decode and extension)
It is a group of conducting wires which carries Data only.Data
bus is bidirectional because data flow in both directions, from
microprocessor to memory or Input/Output devices and from
memory or Input/Output devices to microprocessor.
Length of Data Bus of 8085 microprocessor is 8 Bit (That is,
two Hexadecimal Digits), ranging from 00 H to FF H. (H
denotes Hexadecimal).
When it is write operation, the processor will put the data (to
be written) on the data bus, when it is read operation, the
memory controller will get the data from specific memory
block and put it into the data bus.
The width of the data bus is directly related to the largest
number that the bus can carry, such as an 8 bit bus can
represent 2 to the power of 8 unique values, this equates to
the number 0 to 255.A 16 bit bus can carry 0 to 65535.
Question 4:What is the function of EU and BIU in a
microprocessor? Also list the registers of 8086;
Execution unit gives instructions to BIU stating from where to
fetch the data and then decode and execute those
instructions. Its function is to control operations on data
using the instruction decoder & ALU. EU has no direct
connection with system buses as shown in the above figure, it
performs operations over data through BIU.
The 8086 has eight more or less general 16-
bit registers (including the stack pointer but excluding the
instruction pointer, flag register and segment registers). Four
of them, AX, BX, CX, DX, can also be accessed as twice as
many 8-bit registers (see figure) while the other four, SI, DI,
BP, SP, are 16-bit only.

Question 5:Differentiate between real and protected

mode of a microprocessor;
The main difference is the mode the CPU is in. In protected
mode the OS can use features like paging and virtual
memory. Also, real mode code is never in 32 bits whereas
protected mode code can be 16 bits or 32 bits. Every x86
CPU starts in real mode and the OS must switch to protected
mode.
Question 6:How multitasking is achieved using protected
mode of a micro-processer?
The 80386+ provides many new features to overcome the
deficiencies of 8086 which has almost no support for memory
protection, virtual memory, multitasking, or memory above
640K - and still remain compatible with the 8086 family. The
386 has all the features of the 8086 and 286, with many more
enhancements. As in the earlier processors, there is the real
mode. Like the 286, the 386 can operate in protected mode.
However, the protected mode on 386 is vastly different
internally. Protected mode on the 386 offers the programmer
better protection and more memory than on the 286. The
purpose of protected mode is not to protect your program.
The purpose is to protect everyone else (including the
operating system) from your program
The 386 has special provisions to save the current processor
state and switch to a new task (known as context switch). A
single instruction can switch contexts rapidly. This has
important ramifications for operating systems and real-time
processing. The 386 also supports nested tasks. A task can
return to its original task using a back-link.
Question 7:What is the concept of VM (Virtual Memory),
Cache memory and FPU (Floating point unit) of a
microprocessor?
Virtual Memory: is a computer concept where the main
memory is broken up into a series of individual pages. Those
pages can be moved in memory as a unit, or they can even be
moved to secondary storage to make room in main memory
for new data.
Cache memory: is an extremely fast memory type that acts as
a buffer between RAM and the CPU. It holds frequently
requested data and instructions so that they are immediately
available to the CPU when needed. Cache memory is used to
reduce the average time to access data from the Main
memory.
FPU: A floating-point unit (FPU, colloquially a math
coprocessor) is a part of a computer system specially
designed to carry out operations on floating-point numbers.
Typical operations are addition, subtraction, multiplication,
division, and square root.
Question 8:Define super scalar architecture of a Pentium
processor.
The Pentium has what is known as a “superscalar pipelined
architecture.” Superscalar means that the CPU can execute
two (or more) instructions per cycle. (To be more precise:
The Pentium can generate the results of two instructions in a
single clock cycle.) A pipelined architecture refers to a CPU
that executes each portion of an instruction in different
stages. When a stage is completed, another instruction
begins executing in the first stage while the previous
instruction moves to the second stage. The 80486 and
Pentium have five-stage pipelines. The Pentium has two
pipelines, named the U pipe and the V pipe.
At some points in the pipeline some instructions may prevent
other instructions from advancing in the pipeline because of
conflicts in register usage or address generation.
Question 9:How can you distinguish core i3, i5 from 80486
series of processors?
Intel Core i3 processors are where the Core lineup starts for
each generation. In general, Core i3 processors have lower
core counts than higher-grade CPUs. This used to mean that
Core i3’s started with dual-core processors, but for recent
generations, that core count has gone up to four on the
desktop. Those earlier dual-core Core i3’s also tended to
have four threads, also known as Hyper-Threading. Intel has
elected not to double the thread count in recent Core i3
generations; instead, it’s building CPUs with four cores and
four threads.Core i3 processors also have lower cache sizes
(onboard memory). They handle less RAM than other Core
processors and have varying clock speeds. At this writing,
the ninth-generation, Core i3 desktop processors have a top
clock speed of 4.6 GHz; however, that’s only the higher-
end Core i3-9350K.A step up from Core i3 is the Core i5. This
is often where bargain-hunting PC gamers look for solid deals
on processors. An i5 typically lacks Hyper-Threading, but it
has more cores (currently, six, rather than four) than Core i3.
The i5 parts also generally have higher clock speeds, a larger
cache, and can handle more memory. The integrated
graphics are also a bit better.
Question 10:Differentiate between register and memory
of a microprocessor system;
S.NO. Register Memory
1. Registers hold the Memory holds the
operands or instructions and the
instruction that CPU is data that the currently
currently processing. executing program in
CPU requires.
2. Register holds the Memory of the
small amount of data computer can range
around 32-bits to 64- from some GB to TB.
bits.
3. CPU can operate on CPU accesses memory
register contents at the at the slower rate than
rate of more than one register.
operation in one clock
cycle.
4. Types are Accumulator Type of memory are
register, Program RAM, etc.
counter, Instruction
register, Address
register, etc.
5. Registers can be Memory is almost not
control i.e. you can controllable.
store and retrieve
information from them.
6. Registers are faster RAM is much slower
than memory. than registers.
Question 11:What is the clock period of a clock frequency
of 1 Ghz?
It is the reciprocal of the clock frequency.
For example, a 1 GHz processor has a cycle time of 1.0 ns

Question 12:
Suppose memory bytes 0-4 have the following contents
Address Contents

0 01101010

1 11011101

2 00010001

3 11111111

4 01010101

Assume that a word is 2 bytes; what are the contents in (Hex)

- the word of memory of address 2?

- the word of memory of address 3?

- what is bit 7 of byte 2?

Answers:
- 2 bytes are represented in hex in
format 0xNNNN where N is a hex
number - Address 2 in hex is 0x0011
- Address 3 in hex is 0x00FF
- Bit 7 of byte 2 is 0
Question 13:Convert FAE2CH into binary and decimal
system.
FAE2CH into binary system:
(FAE2CH)16=(11111010111000101100)2
FAE2CH into decimal system:
(FAE2CH)16=(1027628)10
=(15 x 164)+(10 x 164)+(14 x 164)+(2 x 164)+(12 x 164)
=(1027628)10

Question 14:Add FEFFEh to FBCADh .

FEFFE + FBCAD = 1FACAB

Question 15:What is the maximum un-signed integer of a

16-bit register?
The maximum un-signed integer of a 16-bit register is 65535.

Question 16:Why four bits of 8086 address bus are

grounded ?
The data bus in the 8086 is 16 bits in size, while the address
bus is 20 (16bits would only address 64KB of memory, an
extra 4 bits allows to address the total of 1MB, this is done
trough segmentation of the memory).
To form a multiplexed of data bus and address bus, four bits
of 8086 address bus are grounded.
Question 17:Determine the physical address of a memory
location given by 0A51h:CD90h.
The physical address of a memory location given by
0A51h:CD90h is 7500h 3.

Question 18:What is the size DB, DW, DD, DQ and DT?

DB = Define Byte size (8 bits)variables
DW = Define Word size (16 bits) variables
DD = Define Double word size (32 bits) variables
DQ = Define Quad word size (64 bits) variables

Question 19:How the multiple definition is implemented in

assembly give example of it .
Assembler gives an error on duplicate definition and
prevents the program from running, an
example would be like this

.model small
.stack 100h .data
msg1 db "Hellow $" msg1
db "Hellow $"
.code
Here msg1 is declared multiple times hence the assembler
would give duplicate error message.
Question 20:How the assembler assign contiguous
memory space for variables? Give example using symbol
table?

Allocating Memory for Integer Variables:

1. Intel x86 CPU performs operations on different sizes of
data.
2. An integer is a whole number with no fractional part.
3. In assembler, the variables are created by data allocation
directives.
4. Assembler declaration of integer variable assigns a
label to a memory space allocated for the integer.
5. DB is directive for bite-sized memory allocation
6. 77h is initializer specifying initial value.

example using symbol table:

• For multiple data directives Assembler builds a symbol
table
• Both offset (in bytes) and label refer to the
allocated storage space in memory: • ; label
memory
• ; name offset
• .DATA; -------- -------
• value DW 0; value 0
Question 21:What is addressing mode? List all
addressing mode with example?

Addressing modes are an aspect of the instruction set

architecture in most central processing unit (CPU) designs. The
various addressing modes that are defined in a given instruction
set architecture define how the machine language instructions in
that architecture identify the operand(s) of each instruction. An
addressing mode specifies how to calculate the effective memory
address of an operand by using information held
in registers and/or constants contained within a machine
instruction or elsewhere. In computer programming, addressing
modes are primarily of interest to those who write in assembly
languages and to compiler writers. For a related concept
see orthogonal instruction set which deals with the ability of any
instruction to use any addressing mode.

Addressing Example
Meaning When used
modes Instruction
Register Add R4,R3 R4 <- R4 + R3 When a value is in a register

Immediate Add R4, #3 R4 <- R4 + 3 For constants

Add R4,
Displacement R4 <- R4 + M[100+R1] Accessing local variables
100(R1)

Register Accessing using a pointer or a

Add R4,(R1) R4 <- R4 + M[R1]
deffered computed address

Useful in array addressing:

Add R3, (R1 +
Indexed R3 <- R3 + M[R1+R2] R1 - base of array
R2)
R2 - index amount
 Add R1,
Direct R1 <- R1 + M[1001] Useful in accessing static data
(1001)

Memory If R3 is the address of a pointer p,

Add R1, @(R3) R1 <- R1 + M[M[R3]]
deferred then mode yields *p

Useful for stepping through arrays in

Auto- R1 <- R1 +M[R2] a loop.
Add R1, (R2)+
increment R2 <- R2 + d R2 - start of array
d - size of an element

Same as autoincrement.
Auto- R2 <-R2-d
Add R1,-(R2) Both can also be used to implement a
decrement R1 <- R1 + M[R2]
stack as push and pop

Used to index arrays. May be applied

Add R1, R1<-
Scaled to any base addressing mode in some
100(R2)[R3] R1+M[100+R2+R3*d]
machines.
Question 22:List illegal operations for MOV and ADD
instructions

General Rules:

- Both Operands must be of same size

MOV AX,BL (Illegal)
MOV AL,BL (Legal)

- Both Operands cannot be memory operands

simultaneously
MOV i,j (Illegal)
MOV AL,i (Legal)

- First Operand cannot be an immediate value

ADD 2,AX (Illegal)
ADD AX,2 (Legal)
Question 23:Differentiate between conditional and
unconditional jump instruction with examples
Conditional Jump

If some specified condition is satisfied in conditional jump, the

control flow is transferred to a target instruction. There are
numerous conditional jump instructions depending upon the
condition and data. Conditional Jump Instructions are an
important aspect of the decision making process in
programming. These Instruction test for a certain condition
(e.g., Zero or Carry Flag) and alter the program sequence
when the condition is met. The conditional Jump instruction
check the flag conditions and make decisions to change or
not to change the sequence of the program.
In conditional jump instruction, status conditions at the time
of jump instruction execution decide whether or not the jump
will occur.
For example, in a loop:
ldi r16,10
loop:
<do something>
dec r16
brne loop ; conditional jump
Unconditional jump

In unconditional jump instruction, as the instruction is

executed, the jump always ready to takes pace to change the
execution sequence.
This is performed by the JMP instruction. Conditional
execution often involves a transfer of control to the address
of an instruction that does not follow the currently executing
instruction. Transfer of control may be forward, to execute a
new set of instructions or backward, to re-execute the same
steps.
·
The assembler determines the smallest encoding possible for
the direct unconditional jump.
·
We introduce a new instruction called JMP. It is the
unconditional jump
·
that executes regardless of the state of all flags. So we write
an unconditional
·
jump as the very first instruction of our program and jump to
the next
·
instruction that follows our data declarations.
Question 24:Differentiate between SUB and CMP
instruction give example of CMP instruction
CMP :
Format :
CMP destination, source
Compare the numerical value of the destination with the
source and set flags appropriately. This comparison is
carried out in the form of a subtraction to determine which of
the operands has a greater value. After a CMP instruction,
OF, SF, ZF and CF are set appropriately. For example, if the
operands have equal values, then ZF if set.
These flags can then be interpreted by the various conditional
JUMP instructions and decisions can be taken on that basis.
The CMP instruction does not modify the destination field
SUB:
Format :
SUB destination, source
The legal operands combinations are the same as for
addition.
SUBtracts the source value from the destination. Operation is
almost identical to addition, except that the CF flag is used as
a borrow in the case of the SBB (subtract with borrow)
instruction. The logic of the SUB instruction is:
destination = destination - source
and the logic of the SBB instruction is:
destination = destination - source - carry

Question 25:Give implementation of ‘and’ and ‘xor’

logical instructions
The AND Instruction:
The AND instruction is used for supporting logical
expressions by performing bitwise AND operation.
The bitwise AND operation returns 1, if the matching bits
from both the operands are 1, otherwise it returns 0. For
example:
Operand1: 0101
Operand2: 0011
----------------------------
After AND -> Operand1: 0001

The XOR Instruction:

The XOR instruction implements the bitwise XOR operation.
The XOR operation sets the resultant bit to 1, if and only if the
bits from the operands are different. If the bits from the
operands are same (both 0 or both 1), the resultant bit is
cleared to 0.
For example:
Operand1: 0101
Operand2: 0011
----------------------------
After XOR -> Operand1: 0110
Question 26:What is the draw back of shift instruction and
how it is resolve in rotate instruction? Illustrate your
concept with example
Shift instructions allow the bits of a register or memory byte
to be shifted one-bit place to the left or to the right. There are
two types of shift instructions — logical and
arithmetic. Logical shifts consider the contents of the
register or memory byte to be just a bit pattern when the shift
is made.
Rotate instructions are similar to shift instructions, except
that rotate instructions are circular, with the bits shifted out
one end returning on the other end. Rotates can be to the left
or right. Rotates can also employ an extend bit for multi-
precision rotates.
Question 27:What is the advantage of macros in assembly
language give the example of it?
Advantages of using Macros:
A macro is an automated method of using a Geographical
Information System. Commands and parameters are entered
into a text file to produce a desired outcome.
The advantages of using macros include:-
Efficiency and Accuracy: A process can be repeated many
times without the need to re-enter commands and parameters
into instruction input fields. The result is an increased in
efficiency and accuracy. The efficiency comes from the
saving in operators time while the accuracy is the result of
the avoidance of repetitive operations which results in miss
keyed, double entry or missed entry of required data.
Repeatability: Operations may be repeated many times with
variations in particular parameters. An example of this is the
exercise performed at GBRMPA by Mick Hartcher to
determine which areas of the marine park could be at risk
from catamarans, sailboards and other small craft. When
updated information became available, after he had left that
organisation, another operator could have used a macro of
his work, to input the new data into the parameter, which
contained the range of these craft.
Sandra Sherriff could set up a macro, which could be used to
identify all underground services. Staff not trained in GIS
could, by entering one simple parameter, which contains the
reference details of the land under consideration, produce a
map of these services and hence avoid damage when
excavations are proposed.
Decisions could be made to determine a best result, given a
set of options, which could be input as parameter changes
into a macro. Or a macro could be used with a different set of
input files so as to achieve Consistency between successive
operations.
Verification: The macro can be stored with the hard copy of
the resultant files for future examination, particularly when
there is some doubt cast on the validity of derived data.
Speed: An experienced operator can write a macro file in a
shorter time than it takes to call various entry screens wait for
them to open, enter date in a variety of fields and wait for the
processing of that data. With a macro entries are performed
contemporaneously with no need to wait between entries, the
processing of the macro occurs contiguously with respect to
time and at the end of the entry process, by which time the
operator has finished their work and is available to start the
next task.
Question 28:Write the sequence of operation perform
during POST( power on self test) of a PC?
A power-on self-test (POST) is a process performed
by firmware or software routines immediately after a
computer or other digital electronic device is powered on.
This article mainly deals with POSTs on personal computers,
but many other embedded systems such as those in major
appliances, avionics, communications, or medical equipment
also have self-test routines which are automatically invoked
at power-on.
The results of the POST may be displayed on a panel that is
part of the device, output to an external device, or stored for
future retrieval by a diagnostic tool. Since a self-test might
detect that the system's usual human-readable display is non-
functional, an indicator lamp or a speaker may be provided to
show error codes as a sequence of flashes or beeps. In
addition to running tests, the POST process may also set the
initial state of the device from firmware.
In the case of a computer, the POST routines are part of a
device's pre-boot sequence; if they complete successfully,
the bootstrap loader code is invoked to load an operating
system.
Question 29:Perform the 2’s complement addition of
decimal number:-
+16 + (-08)

First, we have to convert 16 and 8 to binary

16 = 10000
8 = 1000
Now taking 1’s compliment of both
10000 = 01111
1000 = 0111
Now taking 2’s 01111 = 10000
0111 = 1000
Now adding 2’s compliment 10000 + 1000 = 11000
discarding
first carry as the positive number is bigger, we get 1000
Converting 1000 in decimal gives 8 which is the correct
answer.
Question 30:Describe the sequence of signals that
occurs on the address bus, the control bus and the data bus
when a simple microcomputer fetches an instruction;
A bus is a pathway for digital signals to rapidly move data.
There are three internal buses associated with processors:
the data bus, address bus, and control bus. Together, these
three make up the “system bus.” The system bus is an
internal bus, intended to connect the processor with internal
hardware devices, and is also called the “local” bus, Front
Side Bus, or is sometimes loosely referred to as the “memory
bus.”
Data moving in and out of the data bus is bi-directional, since
the processor reads and writes data, however, the others are
uni-directional, since the processor always determines when
and what it will read from or write to. The address bus carries
addressing signals from the processor to memory, I/O (or
peripherals), and other addressable devices around the
processor. Control signals move out of the processor, but not
in to it.
 Figure 1: Internal system bus.
By W Nowicki – Own work, based on a diagram in The
Essentials of Computer Organization and Architecture By
Linda Null, Julia Lobur. CC BY-SA 3.0
The data bus “width” of an MCU is typically 8-, 16-, 32- or 64-
bits, although MCUs of just a 4-bit data bus or greater than
64-bit width are possible. The width of the data bus reflects
the maximum amount of data that can be processed and
delivered at one time. A 64-bit processor has a 64-bit data
bus and can communicate 64-bits of data at a time, and
whether the data is read or written is determined by the
control bus. The physical location of the data in memory is
carried by the address bus. An internal hardware component,
having received the address from the address bus and about
to receive the data, enables a buffer to allow the flow of
signals to or from the location that was designated by the
address bus. The address bus carries only the information
regarding the address, and is synchronized with the data bus
to accomplish read/write tasks from the processor. The
address bus is only as wide as is necessary to address all
memory in the system.
Other communication buses also communicate with the
processor but are external to the system, such as Universal
Serial Bus, RS-232, Controller Area Network (CAN), eSATA,
and others. External peripherals may be set up to use the
internal bus, and this was common with computers that used
“expansion cards” to connect products to the internal bus.
However, with one card per device this became untenable for
the long term, and other bus communication systems such as
USB were developed.
A system bus can be “extended” to communicate with other
computers via a chassis called a backplane. Internal buses
have very rapid throughput and low latency. Several
computers can be rack-mounted in a single backplane for
very fast communication between computers.