Project Report: EEE458 VLSI II Group No: 01

Project Topic: Design of a 4 bit Incrementer/Decrementer

Submitted By:
Anik Saha (0906001)
Anupam Golder (0906004)
Table of Contents:

Topic Page No.

Project Abstract 1
Introduction 1
Task 1: Specification, architectural design and functional verification 2
Task 2: Gate level schematic design 4
Task 3: Transistor or switch level design and cell layout 7
Task 4: Top level layout placement and routing and LVS 17
Task 5: Complete chip layout with IO pad placement, clearing all DRC errors 22
and tape out
Possible future improvement 32
Conclusion 32
List of Figures:

Figure Name Page No.

Functional verification of 4 bit incrementer’s Verilog description 3
1 bit incrementer cell 4
1 bit incrementer/decrementer from Pucknell’s book 5
Modified 1 bit incrementer/decrementer 5
Cascading of 1 bit designs to form a 4 bit design 6
Inverter (a) Schematic (b) Layout (c) Symbol 7
Rule checking for Inverter (a) DRC check (b) LVS check 8
ADE L Simulation result for inverter (NOT gate) 8
2 input NAND gate (a) Schematic (b) Layout (c) Symbol 9
Rule checking for 2 input NAND (a) DRC check (b) LVS check 10
ADE L Simulation result for 2 input NAND 10
2 input XOR gate (a) Schematic (b) Layout (c) Symbol 11
Rule checking for 2 input XOR (a) DRC check (b) LVS check 12
ADE L Simulation result for 2 input XOR 13
Design of D flip-flop used in our design 13
Operation of D flip-flop used in our design 13
D Flip-flop (a) Schematic (b) Layout (c) Symbol 15
Rule checking for flip-flop (a) DRC check (b) LVS check 15
ADE L Simulation result for D flip-flop 16
1 bit Incrementer/Decrementer (a) Schematic (b) Layout (c) Symbol 18
Rule checking for 1 bit Incrementer/Decrementer (a) DRC check (b) LVS 18
check
4 bit Incrementer/Decrementer (a) Schematic (b) Layout (c) Symbol 19
Rule checking for 4 bit Incrementer/Decrementer (a) DRC check (b) LVS 20
check
ADE L Simulation result for 4 bit Incrementer/Decrementer demonstrating 20
increment and decrement operation
Cell height consistency 21
ESD Protection (a) Schematic (b) Layout 22
Rule checking for ESD Protection (a) DRC check (b) LVS check 23
Bondpad Layout 24
Schematic view of the chip with I/O pad 24
Layout view of the chip with I/O pad 25
Different portions of layout shown 25
Pin diagram of the final chip 25
Rule checking for final chip (a) DRC check (b) LVS check 26
av_extracted view of final chip layout 27
Simulated waveforms when clock frequency is 50 MHz 27
Power calculation for the final chip 29
Simulated waveform from av_extracted view when clock frequency is 50 MHz 30
Power calculation for the final chip 31
List of Tables:

Topic Page No
Truth table for binary 1 bit incrementer/decrementer 4
Number of Transistors used 21
Measure of delays and rise time and fall time from schematic simulation with 28
IO pad
Measure of delays and rise time and fall time from av_extracted simulation 30
with IO pad
Dependency of power dissipation on clock frequency 32
 Page |1

Project Abstract

The objective of this lab project is to design a medium scale integration chip from concept to
layout including the placement of the I/O pads and preparation of a GDS file of the layout
after clearing all the design rule check and verification. The design to be pursued is that of a 4
bit incrementer/decrementer, but the design is general in that the standard cell envisaged can
be cascaded at will to n-bits. So, the design is basically a modular design.

Introduction

A modular 1 bit incrementer/decrementer has been designed and then 4 bit

incrementer/decrementer chip has been completed with I/O pad and ESD protection. The
project is divided into 5 tasks which are explained in different sub-sections. The tasks have
been performed one after another to the placement of IO pad in final circuit and tape out.
 Page |2

Task1
Specification, architectural design and functional verification
This is a high-level description of the design implemented. Verilog has been used to describe
the architecture and to verify the system level functionality including data flow using NCSim
and SimVision in Cadence.

Design Specification:
 4 bit Incrementer / Decrementer

 Synchronous +ve edge clock operation

 Synchronous Clear capability

 Enabler option (Cin)

 Sequential addition/subtraction logic

 Cascading option (Cout)

Verilog code for functional verification:

module incdec (clk, reset, incdec, cin, Q, c3);

input clk, reset, incdec, cin;

output reg [3:0] Q;

output reg c3;

always @(posedge clk)

if (~reset)

{c3, Q[3:0]} <= 5'b0 ;

else if (incdec)

{c3, Q[3:0]} <= {c3, Q[3:0]} + cin ;

else

{c3, Q[3:0]} <= {c3, Q[3:0]} - cin ;

endmodule
 Page |3

Code for testbench:

module stimulus;
reg clk, reset, incdec, cin;
wire cout;
wire [3:0] Q;
incdec in1(clk, reset, incdec, cin, Q, cout);
initial
begin
clk = 1'b0;
forever begin #5 clk = ~clk; end
end
initial
begin
$shm_open("shm.db",1); // Opens a waveform database
$shm_probe("AS"); // Saves all signals to database
#300 $finish;
#400 $shm_close(); // Closes the waveform database
end

initial // Stimulate the Input Signals

begin
cin<=1;
end

initial
begin
#0 incdec<=1; #100 incdec<=0;
end

initial
begin
#0 reset=1; #30 reset=0; #40 reset=1; #250 reset=0;
#280 reset=1;
end
endmodule //stimulus

Waveforms generated in functional simulation:

Fig. 1. Functional verification of 4 bit incrementer’s Verilog description (the figure shows
reset,increment and decrement operation)
 Page |4

Task 2
Gate level schematic design
Each sub-block of the system has been designed in gate level at this stage. Schematic
structure of each component has been detailed. It also includes the Boolean expressions used.

Truth Table for Sequential Design:

Inputs Outputs
clk Ci Qn-1 Qn Ci+1
0 0 0 0 0
1 0 0 0 0
0 1 0 0 0
1 1 0 1 0
0 0 1 0 0
1 0 1 1 0
0 1 1 0 0
1 1 1 0 1
Table 1: Truth table for binary 1 bit incrementer/decrementer

The truth table for binary 1 bit incrementer is shown in the table, where Ci is the carry bit
from the previous stage, clk is the clock input, Ci+1 is the carry bit output, and Qn is the stage
output and Qn-1 is the state of the output prior to clocking.

Fig. 2 bit incrementer cell

The logic expressions for the incrementer are as follows:

Qn  Ci  Qn 1.............(1)
Ci 1  Ci .Qn 1...............(2)

The n stages are isolated by the clock signal clk, and it will be seen that the truth table
assumes positive-edge clocking. A reset signal should also be provided for the incrementer so
that it can start from zero at any time.

For the incrementer to operate as a decrementer an additional function that needs to be

implemented is as follows:

Ci 1  Ci .Qn 1................(3)
 Page |5

Design provided in Pucknell’s book

An incrementer/decrementer cell realized by direct implementation of expressions stated
above is shown in Fig.

Fig. 3. 1 bit incrementer/decrementer from Pucknell’s book

The cell uses its current input and the carry in from the previous stage as another input. The current
state and the carryout are modified according to the two inputs on clocking.

Modified Design:

Fig. 4. Modified 1 bit incrementer/decrementer

 Page |6

Here, the two passgates and the inverter are replaced by an XOR gate.

Features of modified design:

 Lowered type of gates (only 4 types of cells required)

 Addition of reset

Explanation of operation of the modified design:

The 1 bit incrementer/decrementer cell contains three inverters, two 2-input XOR gates, two
2-input NAND gates and 1 D-flipflop. Fig. depicts the schematic diagram of the gate level
design of the cell. Instance U28 in Fig. performs the operation of eqn. 1. Instance U27 adds
the reset capability so that the incrementer can start from 0 at any instant of time. The
inverters (U30 and U32), the XOR gate (U29) and the NAND gate (U31) combinedly
generate Ci+1. Inside the flip-flop, the clock is inverted to provide both clk and clk .

Fig. shows cascaded 1 bit cells to form a 4 bit incrementer/decrementer. In our design, MR
(reset) is active low.

Fig. 5 Cascading of 1 bit designs to form a 4 bit design

Cin of first stage basically works as an enabler. Setting it to 0 will stop the
increment/decrement operation and freeze it. Cout of the last stage basically offers cascading
option to another incrementer/decrementer.
 Page |7

Task3
Transistor or switch level design and cell layout
The gate level design has been converted in static CMOS gates (complex or standard gate)
and sequential Circuits. Storing the gates in working library, schematic, symbol and layout
view of each gate has been created and cell level simulation (schematic based, for functional
verification), DRC and LVS have been performed.

(a) Inverter (NOT gate):

(a) (b) (c)

Fig. 6. Inverter (a) Schematic (b) Layout (c) Symbol

Transistor widths:

240n for nMOS and 480n for pMOS considering a mobility ratio of the two to be of 2.
 Page |8

(a)

(b)

Fig. 7. Rule checking for Inverter (a) DRC check (b) LVS check

Simulation Results from SchematicView:

Fig. 8. ADE L Simulation result for inverter (NOT gate)

 Page |9

(b) 2 input NAND (NAND2X1):

(a) (b) (c)

Fig. 9. 2 input NAND gate (a) Schematic (b) Layout (c) Symbol

NAND gate has been designed using CMOS logic.

Transistor widths: 240n for NMOS, 480n for pMOS

(a)
 P a g e | 10

(b)

Fig. 10. Rule checking for 2 input NAND (a) DRC check (b) LVS check

Simulation Results from SchematicView:

Fig. 11. ADE L Simulation result for 2 input NAND

 P a g e | 11

(c) 2 input XOR (XOR2X1):

(a)

(b)

(c)

Fig. 12. 2 input XOR gate (a) Schematic (b) Layout (c) Symbol

Transistor widths: 240n for nMOS and 480n for pMOS

 P a g e | 12

(a)

(b)

Fig. 13. Rule checking for 2 input XOR (a) DRC check (b) LVS check

XOR gate has been designed as compact XOR using transmission gates as the on with CMOS
logic would require 12 transistors instead of 6 as used in this case. It show better performance
in terms of delay compared to CMOS PUN-PDN based design or pass transistor based
design.
 P a g e | 13

Simulation Results from Schematic View:

Fig. 14. ADE L Simulation result for 2 input XOR

(d) D Flip-flop:

Fig. 15. Design of D flip-flop used in our design

(a)

(b)

Fig. 16. Operation of D flip-flop used in our design

 P a g e | 14

By combining two level-sensitive latches, one positive-sensitive and one negative sensitive,
an edge-triggered flip-flop can be formed.The first latch stage is the master and the second
latch state is the slave. While CLK is low, the master negative-level-sensitive latch output
QM follows the D input while the slave positive-level-sensitive latch holds the previous
value. When the clock transitions from 0 to1, the master latch becomes opaque and holds the
D value at the time of the clock transition.

The slave latch becomes transparent, passing the stored master value QM to the output of the
slave latch(Q).The D input is blocked from affecting the output because the master is
disconnected from the D input. When the clock transitions from1 to 0, the slave latch holds
its value and the master starts sampling the input again.

(a)

(b)
 P a g e | 15

(c)

Fig. 17. D Flip-flop (a) Schematic (b) Layout (c) Symbol

(a)

(b)

Fig. 18. Rule checking for flip-flop (a) DRC check (b) LVS check
 P a g e | 16

Simulation Results from Schematic View:

Fig. 19. ADE L Simulation result for D flip-flop

Transistor widths in D flip-flop:

In transmission gate: 240n for pMOS and 120n for nMOS

In normal inverters: 240n for nMOS and 480n for pMOS

In tri-state inverters: 120n for NMOS and 240n for pMOS

This design is superior to that of a NAND gate based flip-flop in that this requires lesser
number of transistors.
 P a g e | 17

Task4
Top level layout placement and routing and LVS
This is the incorporation cells along with interconnect to realize the function of the circuit
according to the architecture. A layout versus schematic check has been performed and
matched between layout and schematic.

1 bit Incrementer/Decrementer:

(a)

(b)
 P a g e | 18

(c)

Fig. 20. 1 bit Incrementer/Decrementer (a) Schematic (b) Layout (c) Symbol

(a)

(b)

Fig. 21. Rule checking for 1 bit Incrementer/Decrementer (a) DRC check (b) LVS check
 P a g e | 19

4 bit Incrementer/Decrementer:

(a)

(b)

(c)

Fig. 22. 4 bit Incrementer/Decrementer (a) Schematic (b) Layout (c) Symbol
 P a g e | 20

(a)

(b)

Fig. 23. Rule checking for 4 bit Incrementer/Decrementer (a) DRC check (b) LVS check

Simulation Results from Schemactic View:

Fig. 24. ADE L Simulation result for 4 bit Incrementer/Decrementer demonstrating increment and
decrement operation
 P a g e | 21

Statistics:
Number of Transistors used:
Blocks Number of Transistors
NOT 2
NAND2X1 4
XOR2X1 6
DFF 18
Table 2: Number of Transistors used

Number of transistors per leaf cell: 44

Total number of transistors in a 4 bit design is hence 176.

Some Features of our work:

1. INVERTER (NOT) and NAND gate (NAND2X1) are designed in such a way so that the
effective worst case rise and fall resistance are equal to those of a unit inverter.

2. Layouts of cells designed in our project have same height, only widths vary. This helps in
easy routing of power lines (VDD and GND) and input and output signals when cells are
cascaded to form a 1 bit design, but only at the expense of increased leaf cell size because the
cell having the highest height determines the cell height of other cells which could be made of
smaller height.

Fig. 25 Cell height consistency

Some Layout parameters:

- 2 Metal layer Used (Metal 1 and Metal 2).

- Poly layer is used only for routing signal wires.

 P a g e | 22

Task5
Complete chip layout with I/O pad placement, clearing all DRC errors
and tape out
At this stage the I/O pad has been placed around the edge of the chips. The final chip has
been cleared for DRC and LVS. Finally, tape out has been performed.

ESD Protection:

(a)

(b)

Fig. 26. ESD Protection (a) Schematic (b) Layout

 P a g e | 23

(a)

(b)

Fig. 27. Rule checking for ESD Protection (a) DRC check (b) LVS check

Bond PAD:
- Must have all metal layers used in drawing layout. (Here, we have used 3 metal layers)
- Must have via layers in between metal layers. (Here, we have used 2 via layers)
- Size 70u x 70u (minimum size can be found in gpdk090_DRM.pdf)
- Slots can be used, but avoided here.
- Metal bar sizes = 12u x 70u
- Spacing between metal bars =2.5 um
 P a g e | 24

Fig. 28. Bondpad Layout

Final Chip with I/O Pad:

Fig. 29. Schematic view of the chip with I/O pad

 P a g e | 25

Fig. 30. Layout view of the chip with I/O pad

Fig. 31.Different portions of layout shown

Pin Diagram:

Fig. 32. Pin diagram of the final chip

 P a g e | 26

(a)

(b)

Fig. 33. Rule checking for final chip (a) DRC check (b) LVS check
 P a g e | 27

Av_extracted view of final chip:

Fig. 34. av_extracted view of final chip layout

Final Chip Simulation:

Simulation from Schematic:

Clock Signal specs:

Rise time = Fall time = 1 ns, Period = 20 ns, Pulse width = 9 ns

Simulated waveforms:

Fig. 35. simulated waveform when clock frequency is 50 MHz

 P a g e | 28

Circuit Inventory:

Clock to Q Rise time (ns) Fall time (ns)

propagation delay
(ns)
For Q0 0.17474 0.30 0.24
For Q1 0.17804 0.31 0.23
For Q2 0.1819 0.33 0.25
For Q3 0.1858 0.34 0.23

Table 3: Measure of delays and rise time and fall time from schematic simulation with IO pad

So these times are almost same for all Q signals. So, later we will determine this for Q0 only.

Power Calculation:

(a)

(b)
 P a g e | 29

(c)

Fig. 36. Power calculation for the final chip

Average power dissipation = 13.35 µW

Maximum instantaneous power dissipation = 798.6 µW

Simulation from av_extracted view:

Clock Signal specs: Rise time = Fall time = 1 ns, Period = 20 ns, Pulse width = 9 ns

Simulated waveforms:

(a)
 P a g e | 30

(b)

(c)

Fig. 37 Simulated waveform from av_extracted view when clock frequency is 50 MHz

As seen from the waveforms, delay has increased from the delay observed from schematic
based simulation due to inclusion of bondpad and parasitic resistances and capacitances.

Circuit Inventory:

Clock to Q Rise time (ns) Fall time (ns)

propagation delay
(ns)
For Q0 1.4634 3.2 2.53

Table 4 : Measure of delays and rise time and fall time from av_extracted simulation with IO
pad

So these times are almost same for all Q signals. So, later we will determine this for Q0 only.
 P a g e | 31

Power Calculation:

(a)

(b)

(c)

Fig. 38. Power calculation for the final chip

Average power dissipation = 44.41 µW

Maximum instantaneous power dissipation = 959.5 µW

 P a g e | 32

Dependency of power dissipation on clock frequency:

Clock Frequency Average power Maximum instantaneous power
dissipation (µW) dissipation (µW)
50 MHz 44.41 959.5
100 MHz 82.75 1.08033
Table 5: Dependency of power dissipation on clock frequency

Increasing clock frequency increases dynamic power dissipation. Also, after av_extractaction,
parasitic resistors and capacitors increase both power consumption and delay.

Final Chip Performance:

Chip Dimension without I/O Pad: 36.56 µm ×31.09 µm

Final Chip Dimension: 660 µm ×660 µm
Average Power Consumption: 44.41 µW (at 50 MHz)
Frequency Support: up 100 MHz

Possible Future Improvement

Due to time limitation, chip area could not be minimized. The only protection used in the
chip is the ESD protection. More protection schemes like the guard ring may have been
deployed. Also schimtt trigger and buffer can be used for boosting weak input and output
signals.

Conclusion
The 4 bit incrementer/decrementer design has been a success. All the basic gates and
complex designs have performed as per expectation as verified in ADE L. Although, the chip
is not a highly optimized one, it shows reasonable delay, very small power consumption and
high frequency (~MHz) operation.