STF 15 NM 65 N
STF 15 NM 65 N
Features
Order code VDSS @Tjmax RDS(on) max. ID
3
STF15NM65N
1
2 710 V 0.38 Ω 12 A
STFI15NM65N
TO-220FP 1
2
3
2
• 100% avalanche tested
I PAKFP
(TO-281) • Low input capacitance and gate charge
• Low gate input resistance
Applications
• Switching applications
Figure 1. Internal schematic diagram
Description
' These devices are N-channel Power MOSFETs
developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFETs associates a vertical structure to the
company’s strip layout to yield one of the world’s
* lowest on-resistance and gate charge. It is
therefore suitable for the most demanding high
efficiency converters.
6
$0Y
STF15NM65N TO-220FP
15NM65N Tube
STFI15NM65N I2PAKFP (TO-281)
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 I2PAKFP (TO-281) package information . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1 Electrical ratings
2 Electrical characteristics
Table 6. Dynamic
Symbol Parameter Test conditions Min. Typ. Ma. Unit
is
10 ea )
ar S(on
s 10µs
hi
t R
D
in x
n ma
io
r at by 100µs
pe ed
O mit
1 Li 1ms
Tj=150°C 10ms
Tc=25°C
0.1 Single pulse
0.01
0.1 1 10 100 VDS(V)
15 15
10 10
5V
5 5
0 0
0 2 4 6 8 10 12 14 16 18 20 22 VDS(V) 0 2 4 6 8 10 VGS(V)
0.335
0.330
0 2 4 6 8 10 12 ID(A)
4JQ&
1.10 ID=250µA
1000 Ciss
1.00
100
Coss 0.90
10
Crss 0.80
1
0.1 1 10 100 VDS(V)
0.70
-50 -25 0 25 50 75 100 TJ(°C)
0.9 0.4
0.7 0.2
0.5 0
-50 -25 0 25 50 75 100 TJ(°C) 0 2 4 6 8 10 12 ISD(A)
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
-50 -25 0 25 50 75 100 TJ(°C)
3 Test circuits
Figure 12. Switching times test circuit for Figure 13. Gate charge test circuit
resistive load
VDD
12V 47kΩ
1kΩ
100nF
RL 2200 3.3
μF μF
VDD IG=CONST
VD Vi=20V=VGMAX 100Ω D.U.T.
VGS 2200
RG D.U.T. μF 2.7kΩ VG
PW
47kΩ
PW 1kΩ
AM01468v1 AM01469v1
Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test circuit
switching and diode recovery times
L
A A A
D
FAST L=100μH VD
G D.U.T. DIODE 2200 3.3
μF μF VDD
S B 3.3 1000
B B μF μF
25 Ω VDD ID
D
RG S
Vi D.U.T.
Pw
AM01470v1 AM01471v1
Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform
V(BR)DSS ton toff
tr tdoff tf
VD tdon
90% 90%
IDM
10%
ID 10% VDS
0
4 Package information
7012510_Rev_K_B
A 4.4 4.6
B 2.5 2.7
D 2.5 2.75
E 0.45 0.7
F 0.75 1
F1 1.15 1.70
F2 1.15 1.70
G 4.95 5.2
G1 2.4 2.7
H 10 10.4
L2 16
L3 28.6 30.6
L4 9.8 10.6
L5 2.9 3.6
L6 15.9 16.4
L7 9 9.3
Dia 3 3.2
5HY&
A 4.40 4.60
B 2.50 2.70
D 2.50 2.75
D1 0.65 0.85
E 0.45 0.70
F 0.75 1.00
F1 1.20
G 4.95 5.20
H 10.00 10.40
L1 21.00 23.00
L2 13.20 14.10
L3 10.55 10.85
L4 2.70 3.20
L5 0.85 1.25
L6 7.50 7.60 7.70
5 Revision history
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